High electron mobility transistor chip and preparation method thereof
By setting a composite barrier layer between SiN and single crystal BN between the high-resistance layer and the channel layer of the HEMT chip, the problem of doped elements is solved and the dynamic characteristics and reliability of the chip are improved.
Patent Information
- Application Number
- CN202510305331.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-14
- Publication Date
- 2025-07-25
AI Technical Summary
The memory effects of C-doping and Fe-doping in existing HEMT chips cause doping elements to diffuse into the channel layer in the epitaxial layer, affecting dynamic characteristics.
A composite barrier layer is provided between the high-resistance layer and the channel layer. The composite barrier layer is composed of a SiN layer and a single crystal BN layer. The SiN layer prevents the diffusion of doped elements, and the single crystal BN layer alleviates the stress and dislocation defects caused by lattice mismatch.
It improves the dynamic characteristics and reliability of the HEMT chip, reduces vertical leakage, and improves the performance and crystal quality of two-dimensional electronic gas.
Smart Images
Figure CN120379301A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a high electron mobility transistor chip and a preparation method thereof. Background Art
[0002] HEMT (High Electron Mobility Transistor) is a heterojunction field effect transistor, which is widely used in fields such as aerospace, communication technology, automotive electronics, and switching power supplies. In particular, it has received extensive attention in the fields of high power and high frequency applications. The HEMT chip is the basis for preparing electronic power devices.
[0003] In the related art, the HEMT chip mainly includes a substrate and an epitaxial layer grown on the substrate. In order to reduce the leakage that may occur in the HEMT chip, a high-resistance layer is provided between the substrate and the epitaxial layer. The high-resistance layer is a C-doped GaN layer or an Fe-doped GaN layer.
[0004] However, due to the memory effect of C doping and Fe doping, the doping elements will diffuse into the channel layer in the epitaxial layer, affecting the dynamic characteristics of the HEMT chip. Summary of the Invention
[0005] Embodiments of the present disclosure provide a high electron mobility transistor chip and a preparation method thereof, which can improve the dynamic characteristics of the high electron mobility transistor chip. The technical solution is as follows:
[0006] On the one hand, embodiments of the present disclosure provide a high electron mobility transistor chip, including a high-resistance layer, a composite barrier layer, and an epitaxial layer stacked in sequence;
[0007] The high-resistance layer is a C-doped GaN layer;
[0008] The composite barrier layer includes a first barrier layer and a second barrier layer stacked. The first barrier layer is a SiN layer, and the second barrier layer is a single-crystal BN layer;
[0009] The epitaxial layer includes a channel layer, a barrier layer, and a cap layer stacked in sequence.
[0010] In an implementation manner of the present disclosure, the thickness of the first barrier layer is 5-10 nm;
[0011] The thickness of the second barrier layer is 1-3 nm.
[0012] In an implementation manner of the present disclosure, the high electron mobility transistor chip further includes a substrate and a buffer layer;
[0013] The substrate and the buffer layer are both located on the side of the high-resistance layer facing away from the composite barrier layer, and the buffer layer is located between the substrate and the high-resistance layer, and the buffer layer is a GaN layer.
[0014] In one implementation of the present disclosure, the channel layer is a GaN layer, and the barrier layer is an AlGaN layer;
[0015] The epitaxial layer further includes an insertion layer;
[0016] The insertion layer is located between the channel layer and the barrier layer, and the insertion layer is an AlN layer.
[0017] On the other hand, an embodiment of the present disclosure provides a method for manufacturing a high electron mobility transistor chip. The manufacturing method is used to manufacture the high electron mobility transistor chip as described in the above aspect. The manufacturing method includes:
[0018] Manufacture a high-resistance layer, and the high-resistance layer is a C-doped GaN layer;
[0019] Manufacture a first barrier layer on one side of the high-resistance layer, and the first barrier layer is a SiN layer;
[0020] Manufacture a second barrier layer on one side of the first barrier layer, and the second barrier layer is a single-crystalline BN layer;
[0021] Manufacture an epitaxial layer on one side of the second barrier layer, and the epitaxial layer includes a channel layer, a barrier layer, and a capping layer stacked in sequence.
[0022] In one implementation of the present disclosure, manufacturing the high-resistance layer includes:
[0023] Set the growth temperature to 1020 - 1090 °C;
[0024] Introduce trimethylgallium gas at a flow rate of 450 - 550 sccm, introduce NH3 at a flow rate of 30 - 40 slm, and introduce C3H8 at a flow rate of 750 - 900 sccm respectively;
[0025] Perform growth for 14 - 15 minutes to grow the high-resistance layer.
[0026] In one implementation of the present disclosure, manufacturing the first barrier layer on one side of the high-resistance layer includes:
[0027] Set the growth temperature to 950 - 1100 °C and set the growth pressure to 150 - 300 mbar;
[0028] Introduce NH3 and silane at a flow rate of 100 - 500 sccm, and the gas atmosphere is a nitrogen atmosphere;
[0029] Grow the first barrier layer.
[0030] In one implementation of the present disclosure, preparing a second barrier layer on one side of the first barrier layer includes:
[0031] Introduce NH3 and a metal-organic boron source;
[0032] Adjust the flow rates of NH3 and the metal-organic boron source such that the molar ratio of NH3 to the metal-organic boron source is 1500 - 6000;
[0033] Grow the second barrier layer.
[0034] In one implementation of the present disclosure, before preparing the high-resistance layer, the preparation method further includes:
[0035] Provide a substrate and place the substrate in a reaction chamber;
[0036] Set the pressure to 50 - 100 torr;
[0037] Introduce hydrogen and set the temperature to 1000 - 1100 °C;
[0038] Perform baking for 5 - 15 min;
[0039] Under the condition that the gas atmosphere is a hydrogen atmosphere, introduce NH3 for 1 - 10 min to nitride the surface of the substrate.
[0040] In one implementation of the present disclosure, after nitriding the surface of the substrate, the preparation method further includes:
[0041] Keep the pressure, temperature, and gas flow rate in the reaction chamber unchanged, introduce TMGa at a flow rate of 15 - 20 sccm, and introduce NH3 at a flow rate of 20 - 30 slm;
[0042] Grow the buffer layer.
[0043] The beneficial effects brought by the technical solutions provided in the embodiments of the present disclosure at least include:
[0044] The high electron mobility transistor chip provided by the embodiments of the present disclosure is provided with a composite barrier layer between the high-resistance layer and the channel layer. The composite barrier layer includes a first barrier layer and a second barrier layer stacked on top of each other. Among them, the first barrier layer is a SiN layer. Due to its dense structure, the SiN layer has a very strong shielding ability, can effectively prevent the diffusion of doping elements in the high-resistance layer, and improve the performance of the two-dimensional electron gas in the high electron mobility transistor chip. The second barrier layer is a single-crystalline BN layer. The single-crystalline BN layer can relieve the stress and dislocation defect problems caused by the lattice mismatch between the first barrier layer and the channel layer, thereby facilitating the improvement of the crystal quality of the channel layer. Moreover, the presence of the single-crystalline BN layer can also solve the grain boundary problem caused by directly epitaxially growing the channel layer on the amorphous first barrier layer. In addition, the single-crystalline BN layer has high resistivity, which is beneficial to reducing the vertical leakage of the high electron mobility transistor chip and improving the reliability of the high electron mobility transistor chip.
[0045] That is to say, by setting a composite barrier layer between the high-resistance layer and the channel layer, the dynamic characteristics of the high electron mobility transistor chip can be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0047] Figure 1 is a schematic structural diagram of a high electron mobility transistor provided by the embodiments of the present disclosure;
[0048] Figure 2 is a flowchart of a preparation method of a high electron mobility transistor provided by the embodiments of the present disclosure;
[0049] Figure 3 is a flowchart of another preparation method of a high electron mobility transistor provided by the embodiments of the present disclosure.
[0050] Reference Numerals in the Drawings:
[0051] 10. High-resistance layer;
[0052] 20. Composite barrier layer;
[0053] 210. First barrier layer; 220. Second barrier layer;
[0054] 30. Epitaxial layer;
[0055] 310. Channel layer; 320. Barrier layer; 330. Capping layer; 340. Insertion layer;
[0056] 40. Substrate;
[0057] 50. Buffer layer. Detailed implementation manner
[0058] To make the purpose, technical solution and advantages of the present disclosure clearer, the embodiments of the present disclosure will be further described in detail below in conjunction with the accompanying drawings.
[0059] As a representative of the third-generation semiconductor materials, GaN is an important semiconductor material that emerged after Si and GaAs materials. Due to its excellent properties such as large bandgap width, high critical field strength, high carrier saturation velocity, and high temperature and radiation resistance, it has received extensive attention.
[0060] The GaN-based high electron mobility transistor forms a two-dimensional electron gas (2DEG) with high concentration and high mobility at the heterojunction to generate a conductive channel, thereby realizing the conduction of the device. Due to its excellent properties such as high thermal conductivity, low on-resistance, and tolerance to high-frequency and high-voltage conditions, the GaN-based high electron mobility transistor has become a research hotspot in the fields of high-frequency and high-power devices and switching devices in recent years.
[0061] In the related art, in order to ensure the reliability of the high electron mobility transistor chip, a high-resistance layer is provided. The first type of high-resistance layer is to introduce a high density of edge dislocations, and the second type of high-resistance layer is to dope GaN. For example, when the high electron mobility transistor chip is applied to a power device, C-doped GaN is used as the high-resistance layer to reduce the leakage current of the device, and when applied to a radio frequency device, Fe-doped GaN is used as the high-resistance layer to reduce the leakage current of the device.
[0062] For the first type, the high dislocation density introduced by the intrinsic dislocation technology may reduce the reliability of the AlGaN / GaN high electron mobility transistor chip, and the intrinsic dislocations will capture charges under high voltage, resulting in the current collapse effect.
[0063] For the second type, due to the memory effect of C doping and Fe doping, the doped elements will diffuse into the channel layer of the epitaxial layer, affecting the dynamic characteristics of the high electron mobility transistor chip.
[0064] To solve the above technical problems, the embodiments of the present disclosure provide a high electron mobility transistor. Figure 1 For the structural schematic diagram of the high electron mobility transistor, in combination with Figure 1, in this embodiment, the high electron mobility transistor includes a high-resistance layer 10, a composite barrier layer 20, and an epitaxial layer 30 stacked in sequence. The high-resistance layer 10 is a C-doped GaN layer. The composite barrier layer 20 includes a first barrier layer 210 and a second barrier layer 220 stacked thereon. The first barrier layer 210 is a SiN layer, and the second barrier layer 220 is a single-crystalline BN layer. The epitaxial layer 30 includes a channel layer 310, a barrier layer 320, and a cap layer 330 stacked in sequence.
[0065] For the high electron mobility transistor chip provided by the embodiment of the present disclosure, a composite barrier layer 20 is disposed between the high-resistance layer 10 and the channel layer 310. The composite barrier layer 20 includes a first barrier layer 210 and a second barrier layer 220 stacked thereon. Among them, the first barrier layer 210 is a SiN layer. Due to its dense structure, the SiN layer has a strong shielding ability, can effectively prevent the diffusion of doping elements in the high-resistance layer 10, and improve the performance of the two-dimensional electron gas in the high electron mobility transistor chip. The second barrier layer 220 is a single-crystalline BN layer. The single-crystalline BN layer can relieve the stress and dislocation defect problems caused by the lattice mismatch between the first barrier layer 210 and the channel layer 310, thereby facilitating the improvement of the crystal quality of the channel layer 310. Moreover, the presence of the single-crystalline BN layer can also solve the grain boundary problem caused by directly epitaxially growing the channel layer 310 on the amorphous first barrier layer 210. In addition, the single-crystalline BN layer has high resistivity, which is beneficial to reducing the vertical leakage current of the high electron mobility transistor chip and improving the reliability of the high electron mobility transistor chip.
[0066] That is to say, by disposing the composite barrier layer 20 between the high-resistance layer 10 and the channel layer 310, the dynamic characteristics of the high electron mobility transistor chip can be effectively improved.
[0067] Continue to refer to Figure 1 , in this embodiment, the composite barrier layer 20 is composed of a first barrier layer 210 and a second barrier layer 220. Among them, the thickness of the first barrier layer 210 is 5-10 nm, and the thickness of the second barrier layer 220 is 1-3 nm.
[0068] In the above implementation, the thicknesses of the first barrier layer 210 and the second barrier layer 220 are designed to be the above values. On the one hand, it can ensure that the functionality of the two will not be affected due to too small thickness, and on the other hand, it can also ensure that the preparation efficiency of the two will not be affected due to too large thickness.
[0069] Exemplarily, in this embodiment, the thickness of the first barrier layer 210 is 7 nm, and the thickness of the second barrier layer 220 is 2 nm.
[0070] As described above, the second barrier layer 220 is a single-crystalline BN layer, and the single-crystalline BN layer utilizes the principle of van der Waals epitaxy to achieve its effect. In this embodiment, the number of the second barrier layers 220 can be multiple layers, and the multiple second barrier layers 220 are stacked together. In this way, compared with a single-layer single-crystalline BN layer, the multiple single-crystalline BN layers can better shield the influence of SiN in the first barrier layer 210 on the crystal orientation of GaN in the epitaxial layer 30.
[0071] Continuing to refer to Figure 1 , in this embodiment, the channel layer 310 is a GaN layer, the barrier layer 320 is an AlGaN layer, and the cap layer 330 is a GaN layer.
[0072] Exemplarily, the thickness of the channel layer 310 is 250 - 300 nm, the thickness of the barrier layer 320 is 15 - 35 nm, and the thickness of the cap layer 330 is 1 - 2 nm.
[0073] In the above implementation, an AlGaN / GaN heterojunction is formed between the channel layer 310 and the barrier layer 320. Due to the influence of surface traps, if the barrier layer 320 is thinner, the electric field strength of the barrier layer 320 is greater, the current collapse is more serious, and the saturated output power is lower. If the barrier layer 320 is thicker, the barrier layer 320 will increase the parasitic effect and reduce the small-signal gain characteristic. Therefore, designing the barrier layer 320 to the above thickness can ensure better reliability.
[0074] In this embodiment, the epitaxial layer 30 further includes an insertion layer 340, and the insertion layer 340 is located between the channel layer 310 and the barrier layer 320, and the insertion layer 340 is an AlN layer.
[0075] In the above implementation, an insertion layer 340 is provided between the channel layer 310 and the barrier layer 320. Under the polarization effect, the insertion layer 340 can increase the effective conduction band offset between the barrier layer 320 and the channel layer 310. In this way, on the one hand, a deeper and narrower quantum well can be formed, which is beneficial to increasing the channel electron density. On the other hand, it can also suppress the alloy disorder scattering suffered by the two-dimensional electron gas infiltrating into the barrier layer 320 and improve the channel electron mobility. In addition, the insertion layer 340 also reduces the forward current of the Schottky gate, enables the high electron mobility transistor chip to work at a higher gate voltage, and improves the leakage current.
[0076] Continuing to refer to Figure 1 , the high electron mobility transistor chip further includes a substrate 40 and a buffer layer 50.
[0077] Both the substrate 40 and the buffer layer 50 are located on the side of the high-resistance layer 10 opposite to the composite barrier layer 20, and the buffer layer 50 is located between the substrate 40 and the high-resistance layer 10, and the buffer layer 50 is a GaN layer.
[0078] In the above implementation, the substrate 40 provides a stable foundation for epitaxial growth to ensure the reliability of the growth of the high-resistance layer 10, the composite barrier layer 20, the epitaxial layer 30, etc. The buffer layer 50 is disposed between the substrate 40 and the high-resistance layer 10, and can effectively alleviate part of the lattice mismatch problem. In addition, the buffer layer 50 also has a certain high resistance, reducing the background carrier concentration to reduce the drain current collapse caused by the trap effect of the buffer layer 50.
[0079] Figure 2 A method for manufacturing a high electron mobility transistor chip provided by an embodiment of the present disclosure is shown in Figure 2 and the manufacturing method includes:
[0080] Step 201: Prepare the high-resistance layer 10, and the high-resistance layer 10 is a C-doped GaN layer.
[0081] Step 202: Prepare a first barrier layer 210 on one side of the high-resistance layer 10, and the first barrier layer 210 is a SiN layer.
[0082] Step 203: Prepare a second barrier layer 220 on one side of the first barrier layer 210, and the second barrier layer 220 is a single-crystal BN layer.
[0083] Step 204: Prepare an epitaxial layer 30 on one side of the second barrier layer 220, and the epitaxial layer 30 includes a channel layer 310, a barrier layer 320, and a cap layer 330 that are sequentially stacked.
[0084] When manufacturing a high electron mobility transistor chip by the manufacturing method provided by the embodiment of the present disclosure, a composite barrier layer 20 is disposed between the high-resistance layer 10 and the channel layer 310, and the composite barrier layer 20 includes a stacked first barrier layer 210 and second barrier layer 220. Among them, the first barrier layer 210 is a SiN layer. Since the SiN layer has a dense structure, its shielding ability is very strong, and it can effectively prevent the diffusion of doping elements in the high-resistance layer 10, improving the performance of the two-dimensional electron gas in the high electron mobility transistor chip. The second barrier layer 220 is a single-crystal BN layer, and the single-crystal BN layer can alleviate the stress and dislocation defect problems caused by lattice mismatch between the first barrier layer 210 and the channel layer 310, thereby being beneficial to improving the crystal quality of the channel layer 310. Moreover, the presence of the single-crystal BN layer can also solve the grain boundary problem caused by directly epitaxially growing the channel layer 310 on the amorphous first barrier layer 210. In addition, the single-crystal BN layer has a high resistance, which is beneficial to reducing the vertical leakage of the high electron mobility transistor chip and improving the reliability of the high electron mobility transistor chip.
[0085] That is to say, by disposing the composite barrier layer 20 between the high-resistance layer 10 and the channel layer 310, the dynamic characteristics of the high electron mobility transistor chip can be effectively improved.
[0086] Figure 3 Another preparation method of a high electron mobility transistor chip provided by an embodiment of the present disclosure is shown in Figure 3 , and the preparation method includes:
[0087] Step 301: Provide a substrate 40 and place the substrate 40 in a reaction chamber.
[0088] Exemplarily, the material of the substrate 40 is sapphire, SiC, Si, GaN, etc. In this embodiment, the material of the substrate 40 is sapphire.
[0089] Exemplarily, the reaction chamber is a reaction chamber of an MOCVD (Metal Organic Chemical Vapor Deposition) device.
[0090] After step 301, nitridation treatment is performed on the surface of the substrate 40. The nitridation treatment includes the following steps:
[0091] First, set the pressure of the reaction chamber to 50-100 torr.
[0092] Then, introduce hydrogen and set the temperature of the reaction chamber to 1000-1100 °C.
[0093] Next, perform baking for 5-15 min.
[0094] Finally, in the case where the gas atmosphere is a hydrogen atmosphere, introduce NH3 for 1-10 min to complete the nitridation treatment of the surface of the substrate 40.
[0095] Step 302: Prepare a buffer layer 50 on one side of the substrate 40.
[0096] Exemplarily, in step 302, keep the pressure, temperature and gas flow rate in the reaction chamber unchanged, introduce TMGa at a flow rate of 15-20 sccm, and introduce NH3 at a flow rate of 20-30 slm.
[0097] Step 303: Prepare a high-resistance layer 10 on one side of the buffer layer 50, and the high-resistance layer 10 is a C-doped GaN layer.
[0098] Exemplarily, step 303 includes the following steps:
[0099] First, set the growth temperature to 1020-1090 °C.
[0100] Then, introduce trimethylgallium gas at a flow rate of 450-550 sccm, introduce NH3 at a flow rate of 30-40 slm, and introduce C3H8 at a flow rate of 750-900 sccm respectively.
[0101] Finally, a growth is performed for 14 to 15 minutes to grow the high-resistance layer 10.
[0102] Step 304: Prepare a first barrier layer 210 on one side of the high-resistance layer 10. The first barrier layer 210 is a SiN layer.
[0103] Exemplarily, step 304 includes the following steps:
[0104] First, set the growth temperature to 950 to 1100 °C and set the growth pressure to 150 to 300 mbar.
[0105] Then, introduce NH3 and silane at a flow rate of 100 to 500 sccm, and the gas atmosphere is a nitrogen atmosphere.
[0106] Finally, through growth, the first barrier layer 210 is obtained.
[0107] Step 305: Prepare a second barrier layer 220 on one side of the first barrier layer 210. The second barrier layer 220 is a single-crystalline BN layer.
[0108] Exemplarily, step 305 includes the following steps:
[0109] First, introduce NH3 and a metal-organic boron source.
[0110] Then, adjust the flow rates of NH3 and the metal-organic boron source so that the molar ratio of NH3 to the metal-organic boron source is 1500 to 6000.
[0111] Finally, through growth, the second barrier layer 220 is obtained.
[0112] Through step 304 and step 305, a composite barrier layer 20 can be prepared on the side of the high-resistance layer 10 facing away from the substrate 40.
[0113] Step 306: Prepare an epitaxial layer 30 on one side of the second barrier layer 220. The epitaxial layer 30 includes a channel layer 310, a barrier layer 320, and a cap layer 330 stacked in sequence.
[0114] Exemplarily, step 306 includes the following steps:
[0115] Step 3061: Prepare the channel layer 310.
[0116] First, set the growth temperature to 1020 to 1090 °C and set the pressure of the reaction chamber to 150 Torr.
[0117] Next, introduce trimethylgallium gas at a flow rate of 200 to 300 sccm and introduce NH3 at a flow rate of 55 to 65 slm.
[0118] Finally, grow for 5 - 7 minutes to grow the channel layer 310. The thickness of the channel layer 310 is 250 - 300 nm.
[0119] Step 3062: Prepare the insertion layer 340.
[0120] First, set the growth temperature to 980 - 1050 °C.
[0121] Then, introduce trimethylaluminum gas at a flow rate of 35 - 40 sccm and introduce NH3 at a flow rate of 10 - 12 slm.
[0122] Finally, grow for 1 minute to grow the insertion layer 340. The thickness of the insertion layer 340 is 1 - 2 nm.
[0123] Step 3063: Prepare the barrier layer 320.
[0124] First, set the growth temperature to 980 - 1050 °C.
[0125] Then, introduce trimethylaluminum gas at a flow rate of 35 - 40 sccm, introduce trimethylgallium gas at a flow rate of 25 - 30 sccm, and introduce NH3 at a flow rate of 10 - 12 slm.
[0126] Finally, grow for 5 minutes to grow the barrier layer 320. The thickness of the barrier layer 320 is 20 nm.
[0127] Step 3064: Prepare the capping layer 330.
[0128] First, set the growth temperature to 980 - 1050 °C.
[0129] Then, introduce NH3 at a flow rate of 10 - 12 slm and introduce trimethylgallium gas at a flow rate of 25 - 30 sccm.
[0130] Finally, grow for 30 s to grow the capping layer 330. The thickness of the capping layer 330 is 1 - 2 nm.
[0131] Unless otherwise defined, technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second", "third" and similar terms used in the specification and claims of this patent application of the disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, terms such as "a" or "an" do not denote a quantity limitation, but mean that there is at least one. Terms such as "comprising" or "including" mean that the elements or items appearing before "comprising" or "including" cover the elements or items listed after "comprising" or "including" and their equivalents, and do not exclude other elements or items. Terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper", "lower", "left", "right", "top", "bottom" are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationships may also change accordingly.
[0132] As mentioned above, there is no formal restriction on this disclosure. Although this disclosure has been disclosed through examples as above, it is not intended to limit this disclosure. Any person skilled in the art, without departing from the scope of the technical solution of this disclosure, may make some modifications or refinements to the equivalent embodiments by using the technical content disclosed above. However, as long as the content does not depart from the technical solution of this disclosure, any simple modifications, equivalent changes and refinements made to the above embodiments based on the technical essence of this disclosure still fall within the scope of the technical solution of this disclosure.
Claims
1. A high electron mobility transistor chip, characterized in that, It includes a high-resistance layer (10), a composite barrier layer (20), and an epitaxial layer (30) stacked in sequence; The high-resistance layer (10) is a C-doped GaN layer; The composite barrier layer (20) includes a first barrier layer (210) and a second barrier layer (220) stacked. The first barrier layer (210) is a SiN layer, and the second barrier layer (220) is a single-crystalline BN layer; The epitaxial layer (30) includes a channel layer (310), a barrier layer (320), and a cap layer (330) stacked in sequence.
2. The high electron mobility transistor chip according to claim 1, wherein The thickness of the first barrier layer (210) is 5 - 10 nm; The thickness of the second barrier layer (220) is 1 - 3 nm.
3. The high electron mobility transistor chip according to claim 1, characterized in that, The high electron mobility transistor chip further includes a substrate (40) and a buffer layer (50); Both the substrate (40) and the buffer layer (50) are located on the side of the high-resistance layer (10) facing away from the composite barrier layer (20), and the buffer layer (50) is located between the substrate (40) and the high-resistance layer (10). The buffer layer (50) is a GaN layer.
4. The high electron mobility transistor chip according to claim 1, characterized in that, The channel layer (310) is a GaN layer, and the barrier layer (320) is an AlGaN layer; The epitaxial layer (30) further includes an insertion layer (340); The insertion layer (340) is located between the channel layer (310) and the barrier layer (320), and the insertion layer (340) is an AlN layer.
5. A method for fabricating a high electron mobility transistor chip, characterized in that, The preparation method is used to prepare the high electron mobility transistor chip as described in claim 1. The preparation method includes: Preparing the high-resistance layer (10), where the high-resistance layer (10) is a C-doped GaN layer; Preparing the first barrier layer (210) on one side of the high-resistance layer (10), where the first barrier layer (210) is a SiN layer; Preparing the second barrier layer (220) on one side of the first barrier layer (210), where the second barrier layer (220) is a single-crystalline BN layer; Preparing the epitaxial layer (30) on one side of the second barrier layer (220), where the epitaxial layer (30) includes a channel layer (310), a barrier layer (320), and a cap layer (330) stacked in sequence.
6. The preparation method according to claim 5, characterized in that, Preparing the high-resistance layer (10) includes: Setting the growth temperature to 1020 - 1090 °C; Introducing trimethylgallium gas at a flow rate of 450 - 550 sccm, NH3 at a flow rate of 30 - 40 slm, and C3H8 at a flow rate of 750 - 900 sccm respectively; Performing growth for 14 - 15 minutes to grow the high-resistance layer (10).
7. The preparation method according to claim 5, characterized in that, Preparing the first barrier layer (210) on one side of the high-resistance layer (10) includes: Setting the growth temperature to 950 - 1100 °C and the growth pressure to 150 - 300 mbar; Introducing NH3 and silane at a flow rate of 100 - 500 sccm, and the gas atmosphere is a nitrogen atmosphere; Growing to obtain the first barrier layer (210).
8. The preparation method according to claim 5, characterized in that Preparing the second barrier layer (220) on one side of the first barrier layer (210) includes: Introducing NH3 and a metal-organic boron source; Adjusting the flow rates of NH3 and the metal-organic boron source so that the molar ratio of NH3 to the metal-organic boron source is 1500 - 6000; The second blocking layer (220) is grown.
9. The preparation method according to claim 5, characterized in that, Before preparing the high-resistance layer (10), the preparation method further includes: providing a substrate (40) and placing the substrate (40) into a reaction chamber; setting the pressure to 50-100 torr; introducing hydrogen and setting the temperature to 1000-1100 °C; performing baking for 5-15 min; under the condition that the gas atmosphere is a hydrogen atmosphere, introducing NH3 for 1-10 min to nitride the surface of the substrate (40).
10. The preparation method according to claim 9, characterized in that, After nitriding the surface of the substrate (40), the preparation method further includes: keeping the pressure, temperature and gas flow rate in the reaction chamber unchanged, introducing TMGa at a flow rate of 15-20 sccm, and introducing NH3 at a flow rate of 20-30 slm; growing the buffer layer (50).