Semiconductor chip, manufacturing method and application thereof

Abstract

The application discloses a semiconductor chip, which comprises a semiconductor stack arranged on a substrate, the semiconductor stack is provided with a functional area, and a protection structure is arranged on the semiconductor stack, the protection structure is arranged at the periphery of the functional area in a top view, the protection structure comprises at least two metal layers, each metal layer comprises at least one metal segment, the metal segments of the upper metal layer are partially arranged on the lower metal layer, the projection shape of the protection structure in the direction from the semiconductor stack to the substrate is a first closed figure, and the projection shape of each metal layer in the direction from the semiconductor stack to the substrate is a non-closed figure. The semiconductor chip of the application can eliminate the sudden charge transfer phenomenon generated between two objects with different charges through contact or proximity in the chip manufacturing process, form a charge release path, prevent the semiconductor stack from being damaged in the chip manufacturing process, and increase the proportion of good products of the semiconductor chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a semiconductor chip applied in the field of radio frequency. BACKGROUND

[0002] With the development of semiconductor technology, the size of circuit is getting smaller and smaller, and the miniaturization degree of electronic device is getting higher and higher, so that the elements on the chip are very sensitive to the electric charge generated by the outside world. Even a small amount of electric charge accumulation or sudden electric charge transfer will cause permanent damage to the microstructure inside the semiconductor chip.

[0003] In the process of semiconductor chip, usually including cleaning, film forming, etching, stripping photoresist, depositing metal film, stripping metal and other process, the phenomenon of sudden electric charge transfer between two charged different objects by contact or proximity will be formed, which will cause permanent damage to the epitaxial layer of the semiconductor chip. The existing technology usually improves the production equipment or machine to solve the problem, but still cannot avoid the influence of sudden electric charge transfer on the wafer in the process. For example, in the etching process, the solution sprayed on the surface of the wafer contacts the surface of the wafer and generates arc discharge phenomenon. In the process of cleaning the wafer, the wafer rotates, and then water is sprayed on the surface of the wafer, which uses the transverse force between the rotating wafer and the vertically sprayed water beam to remove the impurities on the surface of the wafer, which also causes electric charge accumulation. The wafer residual charge may cause damage to the semiconductor chip in the further process.

[0004] In addition, in the process of wafer cutting, semiconductor chip packaging or semiconductor chip use, the existing semiconductor chip usually uses transistors, diodes or capacitors to form a protection circuit to form an effective charge release path. However, the protection circuit not only has a complex structure, but also occupies additional area on the semiconductor chip, which increases the manufacturing cost. SUMMARY

[0005] The present application aims to overcome the shortcomings of the prior art and provide an improved semiconductor chip, manufacturing method and application.

[0006] In order to achieve the above purpose, the technical scheme of the present application is as follows:

[0007] The present application provides a semiconductor chip, which comprises a substrate and a semiconductor stack stacked on the substrate, wherein the semiconductor stack is provided with a functional area, the functional area is formed with a semiconductor element, the functional area comprises a device area and a pad area arranged outside the device area; the pad area is provided with at least one pad; and the device area is provided with at least one electrode.

[0008] The semiconductor stack is provided with a protection structure, which, as viewed from the top, is arranged in a non-functional area outside the functional area of the semiconductor stack; the protection structure comprises at least two metal layers; each metal layer comprises at least one metal segment; the metal segments of the upper metal layer are partially arranged on the lower metal layer; the protection structure has a first closed figure in the projection shape from the semiconductor stack to the substrate, and each metal layer has a non-closed figure in the projection shape from the semiconductor stack to the substrate.

[0009] In an embodiment of the present application, the protection structure comprises a top metal layer, which, as viewed from the top, is not connected with the pad.

[0010] In an embodiment of the present application, a connecting metal segment is further included; the protection structure comprises a top metal layer; the pad area comprises at least a first pad, and the connecting metal segment is used to electrically connect the first pad with the protection structure. The first pad is at the same potential as the ground terminal of the semiconductor chip.

[0011] In an embodiment of the present application, a dielectric layer is arranged on the connecting metal segment. The connecting metal segment is formed in the same layer as at least one metal layer of the protection structure except the top metal layer.

[0012] Further, the top metal layer has an extension towards the inside, one end of the connecting metal segment is connected with the extension, and the other end is connected with the first pad.

[0013] Further, the dielectric layer on the connecting metal segment is provided with a first via hole and a second via hole, one end of the connecting metal segment is electrically connected with the top metal layer of the protection structure through the first via hole, and the other end of the connecting metal segment is electrically connected with the first pad through the second via hole.

[0014] In an embodiment of the present application, the semiconductor stack further comprises a first ion implantation area, and the protection structure comprises a first metal layer, which is arranged on the first ion implantation area.

[0015] In an embodiment of the present application, the first ion implantation area is provided with a groove, and the first metal layer is arranged on the groove of the first ion implantation area.

[0016] In an embodiment of the present application, the device area of the functional area of the semiconductor stack is provided with a second ion implantation area; the second ion implantation area and the first ion implantation area are formed through an ion implantation process.

[0017] Further, in the present application, the functional region includes a device region and a pad region arranged outside the device region; the pad region is provided with at least one pad; the device region is provided with at least one electrode; from a top view, the electrode of the functional region and the pad of the pad region are projected in a second pattern in a direction from the semiconductor stack to the substrate, and the second pattern is located in the first closed pattern.

[0018] In an embodiment of the present application, the semiconductor stack is further provided with an isolation region, and the protection structure includes a first metal layer arranged on the isolation region. The isolation region is formed by an ion implantation process.

[0019] In some embodiments of the present application, a back metal layer arranged on the back of the substrate is further included; and the protection structure is electrically connected to the back metal layer.

[0020] In some embodiments of the present application, the semiconductor stack is further provided with a first isolation region and a second isolation region; from a top view, the pad region is arranged on the first isolation region; and the second isolation region is located at the periphery of the protection structure.

[0021] In an embodiment of the present application, from a top view, the protection structure has a projected perimeter L in a direction from the semiconductor stack to the substrate; and the i-th metal layer of the protection structure has a projected perimeter L in the direction from the semiconductor stack to the substrate. Mi , i is a natural number greater than or equal to 1; 1>L Mi / L≥0.5. When the first metal layer is composed of at least two metal segments, the shortest distance between any two adjacent metal segments is greater than or equal to 2 µm. When the first metal layer is composed of one metal segment, the shortest distance between the head end and the tail end of the metal segment of the first metal layer is greater than or equal to 2 µm. The thickness of the first metal layer is d1; the shortest distance between any two adjacent metal segments of the first metal layer or the shortest distance between the head end and the tail end of the metal segment of the first metal layer is e1, e1≥10×d1.

[0022] In an embodiment of the present application, the device region of the semiconductor chip is provided with a HEMT device; the semiconductor chip includes a back metal layer arranged on the back of the substrate, and the protection structure is electrically connected to the back metal layer; the protection structure includes a first metal layer and a top metal layer; the HEMT device includes a source electrode, a drain electrode and a gate electrode; the source electrode includes a source electrode contact layer and a source metal layer arranged on the source electrode contact layer; the drain electrode includes a drain electrode contact layer and a drain metal layer arranged on the drain electrode contact layer; the first metal layer, the source electrode contact layer and the drain metal layer are arranged in the same layer; and the top metal layer, the source metal layer and the drain metal layer are arranged in the same layer.

[0023] In an embodiment of the present application, the HEMT device further comprises a field plate electrode; the protection structure further comprises an intermediate metal layer; the intermediate metal layer is arranged between the first metal layer and the top metal layer; the intermediate metal layer is arranged in the same layer as the field plate electrode, that is, the intermediate metal layer and the field plate electrode are formed by the same metal deposition step.

[0024] Correspondingly, the present application further provides a manufacturing method of a semiconductor chip, forming a semiconductor stack on a substrate; and dividing the semiconductor stack into a functional region; the functional region comprises a device region and a pad region outside the device region; forming a protection structure on the semiconductor stack outside the functional region synchronously with a plurality of metal deposition process steps for forming at least one electrode and at least one pad in the functional region; the protection structure comprises at least two metal layers; each metal layer comprises at least one metal segment; the upper metal layer is partially arranged on the lower metal layer; the projection shape of the protection structure from the semiconductor stack to the substrate is a first closed figure, and the projection shape of each metal layer from the semiconductor stack to the substrate is a non-closed figure; as viewed from the top, the projection shape of the electrode and the pad of the functional region from the semiconductor stack to the substrate is a second figure, and the second figure is located in the first closed figure.

[0025] Correspondingly, the present application further provides an electronic device comprising the above semiconductor chip.

[0026] Compared with the prior art, the present application has the following advantages:

[0027] The protection structure of the semiconductor chip of the present application comprises at least two metal layers; each metal layer comprises at least one metal segment; the upper metal layer is partially arranged on the lower metal layer; the protection structure formed on the semiconductor stack outside the functional region is formed synchronously with a plurality of metal deposition process steps for forming at least one electrode and at least one pad in the functional region; each metal layer can eliminate the sudden charge transfer phenomenon between two charged objects with different charges generated by contact or proximity in the process, form a charge release path, prevent damage to the semiconductor stack in the process, and increase the proportion of good products in the semiconductor chip. Each metal layer has a non-closed figure in the projection shape from the semiconductor stack to the substrate; the electrode of the semiconductor chip and the metal layer of the protection structure are prepared by a photolithography process; after the wafer deposition metal layer process, the photoresist needs to be stripped by wet etching; in order to etch the photoresist by the etching liquid during wet etching, the photoresist under the metal layer is effectively stripped. At the same time, the protection structure of the present application is arranged outside the functional region, which does not increase the area of the semiconductor chip and prevents damage to the epitaxial layer.

[0028] The protective structure of the present application is electrically connected with the ground terminal of the semiconductor chip, especially connected with the back metal layer of the semiconductor chip, and can shield and release the electric charge generated by the external environment during the use of the semiconductor chip. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 A schematic diagram of forming the isolation region B of the embodiment one of the present application.

[0030] Figure 2 A schematic diagram of forming the gate G of the embodiment one of the present application.

[0031] Figure 3 A schematic diagram of forming the first opening V1 of the embodiment one of the present application.

[0032] Figure 4 A top view schematic diagram of forming the first metal layer of the protective structure of the embodiment one of the present application.

[0033] Figure 5 A sectional schematic diagram of forming the first metal layer of the protective structure of the embodiment one of the present application.

[0034] Figure 6 A schematic diagram of forming the third dielectric layer 53 of the embodiment one of the present application.

[0035] Figure 7 A sectional schematic diagram of forming the top metal layer containing the protective structure of the embodiment one of the present application.

[0036] Figure 8 A sectional schematic diagram of forming the fourth dielectric layer 54 of the embodiment one of the present application.

[0037] Figure 9 A top view schematic diagram of forming the fourth dielectric layer 54 of the embodiment one of the present application.

[0038] Figure 10 A sectional schematic diagram of Figure 9 in the direction of a-a'.

[0039] Figure 11 A top view schematic diagram of the semiconductor chip of the embodiment two of the present application.

[0040] Figure 12 A sectional schematic diagram of the semiconductor chip of the embodiment two of the present application.

[0041] Figure 13 A top view schematic diagram of the semiconductor chip of the embodiment three of the present application.

[0042] Figure 14 A sectional schematic diagram of Figure 13 at P.

[0043] Figure 15 Fig. 1 is a cross-sectional view of a semiconductor chip according to an embodiment of the present application. Figure 14 Fig. 2 is a cross-sectional view of a semiconductor chip according to an embodiment of the present application.

[0044] Figure 16 Fig. 3 is a cross-sectional view of a semiconductor chip according to an embodiment of the present application.

[0045] Figure 17 Fig. 4 is a cross-sectional view of a semiconductor chip according to an embodiment of the present application.

[0046] Figure 18 Fig. 5 is a cross-sectional view of a semiconductor chip according to an embodiment of the present application.

[0047] Figure 19 Fig. 6 is a cross-sectional view of a semiconductor chip according to an embodiment of the present application.

[0048] Figure 20 Fig. 7 is a cross-sectional view of a semiconductor chip according to an embodiment of the present application.

[0049] Figure 21 Fig. 8 is a cross-sectional view of a semiconductor chip according to an embodiment of the present application.

[0050] Figure 22 Fig. 9 is a cross-sectional view of a semiconductor chip according to an embodiment of the present application.

[0051] Figure 23 Fig. 10 is a cross-sectional view of a semiconductor chip according to an embodiment of the present application.

[0052] Figure 24 Fig. 11 is a plan view of a semiconductor chip according to an embodiment of the present application.

[0053] Figure 25 Fig. 12 is a plan view of a protective structure according to an embodiment of the present application (the specific structure of the device region A is not shown).

[0054] Figure 26 Fig. 13 is a cross-sectional view of a semiconductor chip according to an embodiment of the present application.

[0055] Figure 27 Fig. 14 is a plan view of a semiconductor chip according to an embodiment of the present application.

[0056] Figure 28 Fig. 15 is a cross-sectional view of a semiconductor chip according to an embodiment of the present application. Figure 27 Fig. 16 is a cross-sectional view of a semiconductor chip according to an embodiment of the present application.

[0057] Figure 29 Fig. 17 is a cross-sectional view of a semiconductor chip according to an embodiment of the present application. Figure 27 Fig. 18 is a cross-sectional view of a semiconductor chip according to an embodiment of the present application.

[0058] Figure 30 For Figure 27 A cross-sectional view in the direction of e-e'.

[0059] Figure 31 A top view schematic of forming the first ion implantation region FC in the non-functional region Q' in Embodiment Nine of the present application. Figure 1 .

[0060] Figure 32 A top view schematic of forming the first ion implantation region FC in the non-functional region Q' in Embodiment Nine of the present application. Figure 2 .

[0061] Figure 33 A top view schematic of forming the second isolation region B2 in the non-functional region Q' and the first isolation region Bl in the functional region in Embodiment Nine of the present application.

[0062] Figure 34 A cross-sectional view of forming the gate G in Embodiment Nine of the present application.

[0063] Figure 35 A cross-sectional view of forming the first layer metal segment group Cl and the first source metal layer Sl, the first drain metal layer Dl of the protection structure in Embodiment Nine of the present application.

[0064] Figure 36 A cross-sectional view of the semiconductor chip in Embodiment Eleven of the present application. DETAILED DESCRIPTION

[0065] So that those skilled in the art can further understand the present application, some embodiments of the present application are specifically exemplified below, and the configuration content and the desired effects to be achieved of the present application are explained in detail with reference to the accompanying drawings. It should be noted that the accompanying drawings are simplified schematic diagrams, and for the convenience of explanation, the components shown in each drawing of the present application can not be drawn in actual number, shape, size, etc. in proportion, and in fact, the size of some features can be intentionally enlarged or reduced for discussion. The detailed circumstances can be adjusted according to the design requirements.

[0066] Embodiment One

[0067] The embodiment provides a semiconductor chip, which comprises a substrate and a semiconductor stack arranged on the substrate, wherein the semiconductor stack is provided with a functional area, the area in which a semiconductor element is formed is the functional area, the functional area comprises a device region and a pad region arranged at the periphery of the device region; the periphery of the device region is an isolation region in a top view, and the pad region of the semiconductor chip is arranged on the isolation region; the semiconductor chip further comprises a protection structure arranged on the isolation region of the semiconductor stack, the protection structure is arranged in a non-functional area, the protection structure comprises at least two metal layers; each metal layer comprises at least one metal segment; the metal layer of an upper layer is partially arranged on the metal layer of a lower layer; the projection shape of the protection structure in the direction from the semiconductor stack to the substrate is a first closed figure, the projection shape of each metal layer in the direction from the semiconductor stack to the substrate is a non-closed figure; the projection shape of the functional area in the direction from the semiconductor stack to the substrate is a second figure, and the second figure is located in the first closed figure. For example, the number of metal layers of the protection structure is two, three or four. In an embodiment, the number of metal layers of the protection structure is two, which are a bottom metal layer and a top metal layer, the projection shape of the bottom metal layer in the direction from the semiconductor stack to the substrate is a non-closed figure, the projection shape of the top metal layer in the direction from the semiconductor stack to the substrate is a non-closed figure, and the protection structure formed by the bottom metal layer and the top metal layer together has a first closed figure in the direction from the semiconductor stack to the substrate.

[0068] The pad region comprises a plurality of pads, and the plurality of pads are used as input / output terminals of the semiconductor chip.

[0069] In the embodiment, each metal layer of the protection structure is composed of a plurality of metal segments surrounding the periphery of the device region in a top view, the circumference of the first metal layer is L M1 , the circumference of the projection figure of the protection structure in the direction from the semiconductor stack to the substrate is L, and preferably 1>L M1 / L≥0.5, that is, the first metal layer is a non-closed surrounding structure, the medium layer without the first metal layer in the protection structure arrangement area of the semiconductor stack is provided with photoresist, which is beneficial to improve the metal stripping effect of the non-retained area after metal deposition, and the position without the first metal layer in the protection structure arrangement area is more easily dissolved by the organic solvent to strip the lower metal. M1 When L

[0070] In one specific implementation, the width W1 of the first metal layer of the protection structure is 6-20 μm. To enhance the effectiveness of the structure, subsequent metal layers of the protection structure are partially stacked on the first metal layer. The width of the first metal layer needs to be greater than the minimum width of the subsequent metal layers. Typically, the minimum width of the top metal layer is set to approximately 3-4 μm. The width of the first metal layer is also related to the number of metal layers in the protection structure.

[0071] The thickness of the first metal layer of the protection structure is d1; the shortest distance between any two adjacent metal segments of the first metal layer is e1, e1≥10×d1. The first metal layer serves as the bottom layer of the protection structure, and the subsequent metal layers of the protection structure will be partially stacked on the first metal layer. Therefore, the distance between any two adjacent metal segments of the first metal layer is controlled to avoid the collapse of the yellow light process photoresist due to the distance between any two adjacent metal segments (or when the first metal layer is composed of one metal segment, the shortest distance between the head and the end of the metal segment of the first metal layer) being too close when the metal layers of other layers of the subsequent protection structure are stacked above the first metal layer.

[0072] From the top view, the perimeter of the projection of the protection structure from the semiconductor stack to the substrate is L; the perimeter of the projection of the i-th metal layer of the protection structure from the semiconductor stack to the substrate is L Mi , i is a natural number greater than or equal to 1; the perimeter of the i-th metal layer is set in the same way as the perimeter of the first metal layer, that is, 1>L Mi / L≥0.5. The i-th layer in the i-th layer is a first metal layer, ..., an i-th metal layer, arranged in a direction from the substrate to the semiconductor stack.

[0073] Furthermore, the semiconductor chip includes a back metal layer arranged on the back side of the substrate, and the protection structure is electrically connected to the back metal layer. During packaging and subsequent use, the semiconductor chip shields and releases external charges.

[0074] In one embodiment, the semiconductor stack below the protection structure is provided with a backhole via, and the back metal layer is connected to the protection structure via the backhole via. In another embodiment, the protection structure is connected to an electrode of a semiconductor chip, the semiconductor stack below the electrode of the semiconductor chip is provided with a backhole via, and the back metal layer is connected to the electrode of the semiconductor chip via the backhole via. In other embodiments, the protection structure is connected to a pad area, the semiconductor stack and the substrate of a pad below the pad area are provided with a backhole via, the back metal layer is disposed on the back side of the substrate and within the backhole, and the back metal layer is connected to a pad via the backhole.

[0075] Take the GaN-based HEMT semiconductor device as an example. Figures 1 to 10As shown, the functional region Q includes the device region A and the pad region H, the device region A has a plurality of electrodes, respectively, a source electrode S, a drain electrode D, and a gate electrode G disposed between the source electrode S and the drain electrode D, and the pad region H is provided with input and output terminals of the semiconductor chip.

[0076] The pad region H of the semiconductor chip is provided with a source pad S0, a drain pad D0, and a gate pad G0 connected with the source electrode S, the drain electrode D, and the gate electrode G of the device region A respectively. The source pad S0 is a first pad.

[0077] The semiconductor chip of the embodiment takes a GaN-based HEMT semiconductor device as an example. The specific manufacturing is as follows:

[0078] Step 1, providing a semiconductor epitaxial structure 100, which includes a semiconductor stack formed in sequence on a substrate 1, the semiconductor stack including a buffer layer 2, a channel layer 3, and a barrier layer 4, wherein the buffer layer is an AlN layer, the channel layer is a GaN layer, and the barrier layer is an AlGaN layer.

[0079] In other embodiments, the channel layer 3 and the barrier layer 4 are further provided with an insertion layer, which can be an AlN layer, and a cap layer can be further provided on the barrier layer 4, which can be a GaN layer.

[0080] Step 2, forming an isolation region B, forming the isolation region B around the device region A of the functional region by ion implantation, as shown in Figure 1 The specific implementation is as follows: using photoresist as a mask, using the steps of glue coating, exposure, and development to make the region needing isolation for ion implantation, and removing the photoresist to form the isolation region B, wherein the implanted ions are nitrogen ions or helium ions.

[0081] Step 3, depositing a first dielectric layer 51, forming a gate opening GV in the first dielectric layer 51 of the gate region of the device region A of the functional region, and forming the gate electrode G through a photoetching and metal deposition process, as shown in Figure 2 .

[0082] Step 4, depositing a second dielectric layer 52, using photoresist as a mask, using the steps of glue coating, exposure, and development to form a first opening V1 (located in the non-functional region Q') in the first dielectric layer 51 and the second dielectric layer 52 of the isolation region B to expose the surface of the semiconductor stack; forming a first source opening VS1 and a first drain opening VD1 in the second dielectric layer 52 of the device region A; from a top view, the projection shape of the first opening V1 on the isolation region B from the semiconductor stack to the substrate direction is a non-closed structure, as shown in Figure 3 , wherein Figure 3 The first source opening VS1 and the first drain opening VD1 are not shown in .

[0083] Step 5, by a photolithography process, depositing a first metal layer M1, and removing photoresist, at the first opening V1, forming several metal segments, respectively first to fourth segments M11~M14 of the first layer metal segment group, constituting the first layer metal segment group C1, forming the first metal layer containing the protection structure; at the first source electrode opening VS1, forming the first source electrode metal layer S1; at the first drain electrode opening VD1, forming the first drain electrode metal layer D1, as shown in Figure 4 、 5 The shortest distance between the first segment M11 of the first layer metal segment group and the second segment M12 of the first layer metal segment group is d11, the shortest distance between the second segment M12 of the first layer metal segment group and the third segment M13 of the first layer metal segment group is d12, the shortest distance between the third segment M13 of the first layer metal segment group and the fourth segment M14 of the first layer metal segment group is d13, and the shortest distance between the first segment M11 of the first layer metal segment group and the fourth segment M14 of the first layer metal segment group is d14. It should be noted that the values of d11, d12, d13 and d14 can be the same or different, and preferably they are greater than 2 μm. The first segment M11 of the first layer metal segment group comprises three segments connected in sequence, and the length of each segment is L11, L12 and L13, respectively. The third segment M13 of the first layer metal segment group comprises three segments connected in sequence, and the length of each segment is L31, L32 and L33, respectively. The circumference of the first layer metal segment group C1 is L M1 L M1 =L1+L2+L3+L4; L1=L11+L12+L13; L3=L31+L32+L33. The second dielectric layer 52 at the position V adjacent to the first opening V1 (the position where the first metal layer is not provided in the protection structure arrangement area) is provided with photoresist, and organic solvents are more likely to enter this position to dissolve the photoresist and strip the metal.

[0084] Figure 4 The length of the first layer metal segment group C1 is shown by the dashed line, wherein the length of the first segment M11 of the first layer metal segment group is L1, the length of the second segment M12 of the first layer metal segment group is L2, the length of the third segment M13 of the first layer metal segment group is L3, and the length of the fourth segment M14 of the first layer metal segment group is L4.

[0085] The perimeter of the first metal layer of the protection structure is L1+L2+L3+L4; the width of the first metal layer of the protection structure is W1, the width of the first opening V1 is W1', W1'≤W1, the value range of W1 is 6-20 μm, and the width of the top metal layer of the protection structure is 1-4 μm. The first metal layer needs to be stacked with other layers of metal layers subsequently, preferably, the width of the upper metal layer is smaller than the width of the lower metal layer, and the width of the subsequently stacked metal layer needs to be smaller than the width of the first layer, so the width of the first metal layer needs to be greater than the minimum width of the subsequently stacked metal layer.

[0086] As preferred, the value range of W1-W1' is 0.5-2 μm, and the cross-sectional view of the first metal layer is T-shaped: W1' is the size of the first opening V1 of the first / second dielectric layer 51 / 52, and W1 is the width of the first metal layer. As preferred, the width of the first metal layer needs to cover the first opening V1 of the first / second dielectric layer 51 / 52, otherwise, the dielectric layer opening will expose the epitaxial layer, which will be damaged in the subsequent process of the chip, such as wet cleaning corrosion, high-temperature process, etc., thereby affecting the reliability of the chip.

[0087] Step 6, depositing a third dielectric layer 53, as shown in Figure 6 . Using photoresist as a mask, adopting the steps of glue coating, exposure and development, the third dielectric layer 53 at the isolation area B forms a second opening V2 to expose part of the upper surface of the first metal layer, and form a second source opening VS2 and a second drain opening VD2 in the functional area. From the top view, the second opening V2 of the isolation area is a non-closed pattern.

[0088] Step 7, depositing a second metal layer M2 by a photolithography process, and removing the photoresist, as shown in Figure 7 . At the second opening V2, a plurality of metal segments are formed, which are the first and second segments M21, M22 of the second metal segment group C2, respectively, to form the top metal layer of the protection structure; at the second source opening VS2, a second source metal layer S2 is formed, and at the second drain opening VD2, a second drain metal layer D2 is formed, the second source metal layer S2 is stacked on the first source metal layer S1 to form the source S of the semiconductor device; the second drain metal layer D2 is stacked on the first drain metal layer D1 to form the drain D of the semiconductor device; at least one pad (not shown) is formed on the third dielectric layer 53 of the pad area H in the functional area, and the pad area H forms at least one source pad, at least one gate pad and at least one drain pad, respectively; further, the source pad S0, the drain pad D0 and the gate pad G0 are connected with the source S, the drain D and the gate G, respectively.

[0089] Step 8, depositing a fourth dielectric layer 54, as shown in Figure 8 , 9 .

[0090] Figure 9 The four source pads S0, one drain pad D0 and one gate pad G0 are respectively connected to the source S, the drain D and the gate G of the semiconductor chip. In order to more clearly show the schematic, the first to fourth dielectric layers are omitted. Among them, Figure 10 Figure 9 The cross-sectional view of a-a' is shown. The shortest distance between the first segment M11 of the first layer metal segment group of the first layer metal of the protection structure and the second segment M12 of the first layer metal segment group is d11. Among them, d11>2μm.

[0091] Step 9: By coating the photoresist, exposing and developing, the fourth dielectric layer 54 is etched in the opening area, and the photoresist is removed, exposing part of the pad area of the semiconductor chip to expose the input / output terminals of the semiconductor chip.

[0092] In this embodiment, the first layer metal layer is composed of ohmic metal material, that is, the contact between the first layer metal layer and the semiconductor stack is ohmic contact.

[0093] Embodiment two

[0094] This embodiment provides a semiconductor chip, which is similar to embodiment one, except that an extension Y1 extending towards the inside is further provided and connected to the top layer metal layer (i.e. the second layer metal segment group C2) of the protection structure. The extension Y1 is formed in the same layer as the top layer metal layer of the protection structure, and the extension Y1 is connected to the source pad S0 of the pad area H. As shown in the accompanying Figure 11 As shown, the extension Y1 has an inside. Specifically, the semiconductor chip includes four extensions Y1 and four source pads S0, and the four extensions Y1 are respectively connected to the four source pads S0. The source pad S0 is at the same potential as the ground potential of the semiconductor chip, and the extension Y1 is used to conductively connect the first pad to the protection structure.

[0095] Further, this embodiment provides a schematic diagram of a semiconductor chip as shown in the accompanying Figure 12 As shown, the source S of the device area A corresponds to the semiconductor stack and the substrate, and a back hole 61 is provided at the semiconductor stack and the substrate. The back surface of the substrate of the semiconductor chip is provided with a back surface metal layer 6, and the back surface metal layer 6 is connected to the source S of the device. The extension Y1 connected to the top layer metal layer of the protection structure is electrically connected to the back surface metal layer 6 through the back hole 61. The protection structure is interconnected with the source through the interconnection metal line, which is equivalent to grounding the protection structure. In this way, the signal interference outside the semiconductor chip can be shielded, and the electric charge accumulated during the subsequent manufacturing process of the semiconductor chip can be grounded through the protection structure, reducing the damage of internal electric charge accumulation to the device structure of the semiconductor chip.

[0096] Embodiment three ​

[0097] The embodiment provides a semiconductor chip, which is similar to the embodiment two, and different from the embodiment two in that Figure 13 The protection structure further comprises a connecting metal segment, the extension Y1 is not directly connected with the source pad S0, but the extension Y1 electrically connects the source pad S0 with the protection structure through the first connecting metal segment C1'.

[0098] Figure 14 The protection structure further comprises a connecting metal segment, the extension Y1 is not directly connected with the source pad S0, but the extension Y1 electrically connects the source pad S0 with the protection structure through the first connecting metal segment C1'. Figure 13 The protection structure further comprises a connecting metal segment, the extension Y1 is not directly connected with the source pad S0, but the extension Y1 electrically connects the source pad S0 with the protection structure through the first connecting metal segment C1'. Figure 15 The protection structure further comprises a connecting metal segment, the extension Y1 is not directly connected with the source pad S0, but the extension Y1 electrically connects the source pad S0 with the protection structure through the first connecting metal segment C1'. Figure 14 The protection structure further comprises a connecting metal segment, the extension Y1 is not directly connected with the source pad S0, but the extension Y1 electrically connects the source pad S0 with the protection structure through the first connecting metal segment C1'. The protection structure further comprises a connecting metal segment, the extension Y1 is not directly connected with the source pad S0, but the extension Y1 electrically connects the source pad S0 with the protection structure through the first connecting metal segment C1'.

[0099] The extension Y1 of the top metal layer is not directly connected with the source pad S0 of the pad area, but is electrically connected through the first connecting metal segment C1'; wherein the shortest distance between the extension Y1 and the source pad S0 is f1, and f1 is 2-10 μm, f1 greater than 2 μm can avoid the extension Y1 being too close to the source pad S0, and ensure an effective distance, so as to improve the stripping effect of the subsequent metal stripping process; f1 greater than 10 μm will cause the device area to be obviously increased, and the chip cost to be increased. The protection structure further comprises a connecting metal segment, the extension Y1 is not directly connected with the source pad S0, but the extension Y1 electrically connects the source pad S0 with the protection structure through the first connecting metal segment C1'.

[0100] On the one hand, the protection structure is interconnected with the source S through the first connecting metal segment C1', which is equivalent to grounding the protection structure, so that the signal interference outside the semiconductor chip can be shielded, and in addition, the electric charge generated in the subsequent manufacturing process of the semiconductor chip can be accumulated and grounded through the protection structure, so that the damage of internal electric charge accumulation to the device structure of the semiconductor chip is reduced. On the other hand, the top metal layer of the protection structure is not directly connected with the source pad, and the top metal layer and the source pad and the active area form an approximately closed surrounding structure, which is beneficial to improve the stripping effect of the subsequent metal stripping process: non-approximate closure, and the organic solvent can enter the non-approximate closure area to improve the stripping effect. The source-drain spacing (the distance between the source and the drain) of the device area of the semiconductor is usually less than 5-8 um; the thickness of the top metal layer is greater than 2 μm, and is usually set to be 3-4 μm, if the top metal layer is directly connected with the source pad, the risk of the metal not being stripped clean is directly increased; in addition, the interconnection of the first connecting metal segment C1' and the source S increases the flexibility of the wiring, and when the top metal layer of the protection structure and the source pad are in poor contact, there is no other metal layer directly interconnected with the pad, so that the low-impedance grounding of the source pad is ensured. The protection structure further comprises a connecting metal segment, the extension Y1 is not directly connected with the source pad S0, but the extension Y1 electrically connects the source pad S0 with the protection structure through the first connecting metal segment C1'.

[0101] The manufacturing method of the semiconductor chip comprises the following steps: The manufacturing method of the semiconductor chip comprises the following steps:

[0102] Steps 1-3 are the same as those in the first embodiment, and will not be described again.

[0103] Step 4, depositing the second dielectric layer 52, using photoresist as mask, adopting the steps of coating, exposing and developing, forming the first opening V1 and the first connecting metal segment opening V1' in the second dielectric layer 52 of the isolation region B; forming the first source electrode opening VS1 and the first drain electrode opening VD1 in the second dielectric layer 52 of the device region A; from the top view, the projection shape of the first opening V1 on the isolation region B from the semiconductor stack to the substrate direction is a non-closed structure, as shown in Figure 16 Figure 16 The first source electrode opening VS1 and the first drain electrode opening VD1 are not shown in the middle, and the second dielectric layer 52 is not shown for a clearer display.

[0104] Step 5, depositing the first metal layer M1 and removing the photoresist, forming a plurality of metal segments at the first opening V1, which are the first to fourth segments M11-M14 of the first layer metal segment group, constituting the first layer metal segment group C1 containing structure, which is the first layer metal layer of the protection structure, forming the first connecting metal segment C1' at the first connecting metal segment opening V1', wherein the number of the first connecting metal segment C1' is 4, as shown in Figure 17 Preferably, the first connecting metal segment C1' is not connected with the first layer metal layer of the protection structure.

[0105] Step 6, depositing the third dielectric layer 53, using photoresist as mask, adopting the steps of coating, exposing and developing, forming the second opening V2 in the third dielectric layer 53 of the isolation region B to expose part of the upper surface of the first layer metal layer, forming the third opening V3 and the fourth opening V4 in the third dielectric layer 53 of the isolation region B to expose two parts of the upper surface of the first connecting metal segment C1', forming the second source electrode opening VS2 and the second drain electrode opening VD2 in the functional region; from the top view, the second opening V2 of the isolation region is a non-closed pattern.

[0106] ​Step 7, by a photolithography process, depositing a second metal layer M2, and removing the photoresist, at the second opening V2, forming a plurality of metal segments, forming a second layer metal segment group C2 of the protection structure, including a first and a second segment M21, M22 of the second layer metal segment group, i.e. forming a top metal layer of the protection structure; meanwhile, also forming an extension Y1, the third opening V3 is located below the extension Y1, the extension Y1 is connected with the first connecting metal segment C1’ through the second metal layer M2 deposited in the third opening V3, at the second source opening VS2, forming a second source metal layer S2, at the second drain opening VD2, forming a second drain metal layer D2, the second source metal layer S2 is stacked on the first source metal layer S1, constituting a source S of the semiconductor device; the second drain metal layer D2 is stacked on the first drain metal layer D1, constituting a drain D of the semiconductor device; at the pad area H of the functional area, at least one pad (not shown) is formed at a plurality of pad openings, the pad area H at the third dielectric layer 53 forms at least one source pad S0, at least one gate pad G0 and at least one drain pad D0 respectively; further, the source pad S0, the drain pad D0 and the gate pad G0 are connected with the source S, the drain D and the gate G respectively. The fourth opening V4 is located below the source pad S0, the source pad S0 is connected with the first connecting metal segment C1’ through the second metal layer M2 deposited in the fourth opening V4, to realize the electrical connection of the source pad S0 with the second layer metal segment group C2 of the protection structure through the first connecting metal segment C1’ and the extension Y1. The shortest distance between the extension Y1 and the source pad S0 is f1, preferably, 10 μm ≥ f1 ≥ 2 μm. On the one hand, it avoids the extension Y1 being too close to the source pad S0, ensuring an effective distance, so as to improve the stripping effect of the subsequent metal stripping process. If f1 is set too large, it will result in a significant increase in the device area and the chip cost.

[0107] Embodiment Four

[0108] The embodiment provides a semiconductor chip, which comprises a semiconductor stack, Figure 18 As shown, it is similar to the embodiments one to three, the difference is that the source and / or the drain of the device area A is respectively provided with a source ion implantation area FS and / or a drain ion implantation area FD, further reducing the contact resistance between the source and the drain of the semiconductor chip and the semiconductor stack. The ions implanted in the source ion implantation area FS and the drain ion implantation area FD include at least one selected from silicon Si ions and germanium Ge ions. The same parts of the embodiment and other embodiments are not described here.

[0109] Embodiment Five

[0110] The embodiment provides a semiconductor chip, which comprises a semiconductor stack, Figure 19As shown, the semiconductor chip comprises a substrate and a semiconductor stack, the semiconductor stack is provided with a functional region Q, the region where the semiconductor element is formed is the functional region, the functional region comprises a device region A and a pad region H arranged at the periphery of the device region A; as viewed from the top, the periphery of the device region A is an isolation region B, and the periphery of the isolation region B is a protection structure region; the pad region H of the semiconductor chip is arranged on the isolation region B; further comprising a protection structure arranged in the protection structure region of the semiconductor stack, the protection structure is arranged in a non-functional region Q', the protection structure comprises at least two metal layers; each layer of the metal layer comprises at least one metal segment; the upper layer of the metal layer is partially arranged on the lower layer of the metal layer; the projection shape of the protection structure in the direction from the semiconductor stack to the substrate is a first closed figure, the projection shape of each layer of the metal layer in the direction from the semiconductor stack to the substrate is a non-closed figure; the projection shape of the functional region in the direction from the semiconductor stack to the substrate is a second figure, and the second figure is located in the first closed figure. For example, the number of metal layers of the protection structure is two, three or four, etc. Different from the foregoing embodiments, in embodiments one to four, the protection structure is located above the isolation region B, while in the present embodiment, the protection structure is located in the protection structure region at the periphery of the isolation region, as shown in the accompanying drawings Figure 19 As shown, the source S and / or the drain D of the device region A is respectively provided with a source ion implantation region FS and a drain ion implantation region FD below, and the ions implanted in the ion implantation region include at least one selected from silicon Si ions and germanium Ge ions. The present embodiment is similar to embodiment four, and the difference lies in that the protection structure of embodiment four is arranged on the isolation region B, while the protection structure of the present embodiment is not arranged on the isolation region B, that is, the protection structure is arranged on the semiconductor stack which is not subjected to isolation treatment, and the same as embodiment four, which will not be repeated here.

[0111] Embodiment six

[0112] The present embodiment provides a semiconductor chip, which is similar to embodiment five, and the difference lies in that Figure 20 As shown, no ion implantation region is arranged below the source and / or the drain of the device region A. The same as embodiment five, which will not be repeated here.

[0113] Embodiment seven

[0114] The present embodiment provides a semiconductor chip, which is similar to embodiment five, and the difference lies in that a first ion implantation region FC is arranged below the protection structure, as shown in the accompanying drawings Figure 21 The first ion implantation region FC is formed by a synchronous ion implantation process with the source ion implantation region FS and / or the drain ion implantation region FD, and the ions implanted in the ion implantation region include at least one selected from silicon Si ions and germanium Ge ions. The same as embodiment five, which will not be repeated here.

[0115] The first ion implantation region FC is arranged under the protection structure, so as to reduce the contact resistance between the first metal layer of the protection structure and the semiconductor, and eliminate the accumulated electric charges in the semiconductor stack during the process. It should be noted that the ion implantation region can also be arranged under the source S and the drain D of the device of the semiconductor chip.

[0116] Embodiment eight

[0117] The embodiment provides a semiconductor chip, which is similar to the embodiment seven, and the difference is that, as shown in the figure, Figure 22 The protection structure further comprises an isolation region.

[0118] Embodiment nine

[0119] The embodiment provides a semiconductor chip, which is different from the first to ninth embodiments, and the difference is that, the protection structure comprises three metal layers, as shown in the figure, Figure 23 The semiconductor chip comprises a substrate and a semiconductor stack, and the semiconductor stack is provided with a functional region Q and a non-functional region Q'. The region in which the semiconductor element is formed is the functional region, and the functional region comprises a device region A and a pad region H arranged at the periphery of the device region A. As viewed from the top, the periphery of the device region A is an isolation region, and the pad region of the semiconductor chip is arranged on the isolation region. The semiconductor chip further comprises a protection structure arranged on the non-functional region Q' of the semiconductor stack, and the protection structure comprises three metal layers, i.e., a first metal layer, a middle metal layer and a top metal layer.

[0120] The projection shapes of the first metal layer, the middle metal layer and the top metal layer in the direction from the semiconductor stack to the substrate are all non-closed figures, and the projection shape of the protection structure in the direction from the semiconductor stack to the substrate is a first closed figure, Figure 24 、 25 The protection structure comprises a first metal segment group C1, a second metal segment group C2 and a third metal segment group C3. The first metal segment group C1 is configured to form the first metal layer of the protection structure on the semiconductor stack, as shown in the figure, Figure 24 The first metal layer is composed of the first metal segment group C1, and the first to fourth segments M11-M14 of the first metal segment group are included, so as to form the first metal layer of the protection structure. The middle metal layer is composed of the second metal segment group C2, and the top metal layer is composed of the third metal segment group C3.

[0121] The material of the first metal layer is different from that of the first to eighth embodiments, and the metal material of the first metal layer in the embodiment is a Schottky metal. The embodiment of the present application can solve the electric charge accumulation process during the process of manufacturing the gate of the semiconductor chip, and further improve the excellent product yield ratio of the semiconductor chip.

[0122] The semiconductor chip of the embodiment takes a GaN-based HEMT semiconductor device as an example, as shown in FIG. 1. The specific fabrication is as follows: Figures 23~25

[0123] Step 1, providing a semiconductor epitaxial structure 100, which includes a buffer layer 2, a channel layer 3, and a barrier layer 4 formed in sequence on a substrate 1, wherein the buffer layer is an AlN layer, the channel layer is a GaN layer, and the barrier layer is an AlGaN layer.

[0124] In other embodiments, the channel layer 3 and the barrier layer 4 are further provided with an interposed layer, which is an AlN layer, and a cap layer is further provided on the barrier layer 4, which is a GaN layer.

[0125] Step 2, forming an isolation region B, which is formed around the device region A of the functional region by ion implantation, and the specific implementation is as follows: using photoresist as a mask, ion implantation is performed in the required isolation region by using the steps of glue coating, exposure, and development, and the photoresist is removed to form the isolation region, wherein the implanted ions are nitrogen ions or helium ions.

[0126] Step 3, depositing a first dielectric layer 51, forming a gate opening in the gate region of the device region of the functional region, forming a first opening V1 at the non-functional region Q', and forming the first layer metal layer of the gate G and the protection structure by photoetching and depositing the first metal layer M1. From the top view, the projection shape of the first opening V1 at the non-functional region Q' from the semiconductor stack to the substrate direction is a non-closed structure. The material of the metal deposition in this step is a Schottky metal material. The first metal layer M1 is made of a multi-layer metal stack, such as a Ni / Au stack, a Ti / Pt / Au stack, a Pt / Ni / Au stack, etc.

[0127] The first layer metal layer is composed of a first layer metal segment group C1, including the first to fourth segments M11, M12, M13, and M14 of the first layer metal segment group, and the projection shape from the semiconductor stack to the substrate direction is a non-closed loop pattern, as shown in FIG. 2. Figure 24 .

[0128] Step 4, depositing a second dielectric layer 52, using photoresist as a mask, and using the steps of glue coating, exposure, and development to form a second opening V2 at the second dielectric layer 52 at the non-functional region Q'; forming a first source opening VS1 and a first drain opening VD1 at the second dielectric layer 52 at the device region A; from the top view, the projection shape of the second opening V2 on the non-functional region Q' from the semiconductor stack to the substrate direction is a non-closed structure.

[0129] ​Step 5, depositing a second metal layer M2 and removing the photoresist, forming a plurality of metal segments at the second opening V2 to form a second layer metal segment group C2, including the first to third segments M21-M23 of the second layer metal segment group, i.e. forming an intermediate metal layer including the protection structure; forming a first source metal layer S1 at the first source opening VS1; forming a first drain metal layer D1 at the first drain opening VD1; the second metal layer M2 can be selected as a Ti / Pt / Au stack.

[0130] Step 6, depositing a third dielectric layer 53. Using the photoresist as a mask, using the steps of coating, exposing and developing, the third dielectric layer 53 at the non-functional area Q' forms a third opening V3 to expose part of the upper surface of the second layer metal segment group C2, forming a second source opening VS2, a second drain opening VD2 and a gate opening VG in the device area A of the functional area; from the top view, the third opening V3 at the non-functional area Q' is a non-closed pattern.

[0131] Step 7, depositing a third metal layer M3 by a photolithography process and removing the photoresist, forming a plurality of metal segments at the third opening V3 to form a third layer metal segment group C3, including the first to second metal segments M31, M32 of the third layer metal segment group, i.e. forming a top metal layer of the protection structure; forming a second source metal layer S2 at the second source opening VS2 and a second drain metal layer D2 at the second drain opening VD2, the second source metal layer S2 is stacked on the first source metal layer S1 to form a source S of the semiconductor device; the second drain metal layer D2 is stacked on the first drain metal layer D1 to form a drain D of the semiconductor device; at least one pad (not shown) is formed on the third dielectric layer 53 of the pad area H of the functional area, and the pad area H forms at least one source pad, at least one gate pad and at least one drain pad; further, the source pad, the drain pad and the gate pad are connected to the source S, the drain D and the gate G respectively. The third metal layer M3 can be selected as a Ti / Pt / Au stack.

[0132] Step 8, depositing a fourth dielectric layer 54.

[0133] Step 9, using the photoresist as a mask, using the steps of coating, exposing and developing, the fourth dielectric layer 54 is etched to form an opening, and the photoresist is removed to expose part of the pad area of the semiconductor chip to expose the input / output terminals of the semiconductor chip.

[0134] The protection structure is located in the non-functional area Q', and in the embodiment of the present application, the semiconductor stack contacted by the protection structure is a non-isolation area. It should be noted that the semiconductor stack contacted by the protection structure can also be provided on the isolation area, or can be an ion implantation area.

[0135] It should be noted that the second metal layer M2 and the third metal layer M3 may also be Ti / Al / Ti, Ti / Al / Au stacked layers, etc.

[0136] Example 10

[0137] This embodiment provides a semiconductor chip. This embodiment differs from the first to eighth embodiments in that the protective structure of this embodiment includes three metal layers. This embodiment differs from the ninth embodiment in that, whereas the first metal layer in the ninth embodiment is made of a Schottky metal material, this embodiment uses an ohmic metal material. The ohmic metal material can be a Ti / Al / Ti, Ti / Al / Au, or Ti / Pt / Au metal stack.

[0138] As attached Figures 26~30 As shown, a semiconductor chip includes a substrate and a semiconductor stack, the semiconductor stack is provided with a functional area Q and a non-functional area Q', the area where the semiconductor elements are formed is the functional area, the functional area includes a device area A and a pad area H arranged outside the device area; from a top view, a first isolation area B1 is provided outside the device area A, and the pad area H of the semiconductor chip is arranged on the first isolation area B1; it also includes a protection structure arranged on the non-functional area Q' of the semiconductor stack, the protection structure includes three metal layers, namely a first metal layer, an intermediate metal layer and a top metal layer.

[0139] Figure 26 Schematic cross-sectional view of a semiconductor chip according to the tenth embodiment of the present invention. Figure 27 FIG. 1 is a schematic top view of a semiconductor chip according to a tenth embodiment of the present invention. Figure 28 for Figure 27 The distance between the fourth segment M24 of the second metal segment group and the first segment M21 of the second metal segment group is d24, and preferably, d24 is greater than 2 μm.

[0140] Figure 30 for Figure 27 Schematic diagram of the cross section along the e-e' direction.

[0141] Furthermore, from a top view, the protection structure is disposed on the semiconductor stack between the first isolation region B1 and the second isolation region B2.

[0142] Furthermore, the semiconductor stack below the protection structure is further provided with a first ion implantation region FC, wherein the implanted ions include at least one selected from silicon Si ions and germanium Ge ions. From a top view, the projection of the first ion implantation region FC below the protection structure in the direction from the semiconductor stack to the substrate may be a closed figure. Figure 32 , can also be a non-closed graph, see Figure 31 .

[0143] Further, the semiconductor stack at the periphery of the protection structure is also provided with a second isolation region B2 from the top view. Different from the embodiments one to eight, the intermediate metal layer is included.

[0144] The first metal layer, the intermediate metal layer and the top metal layer are all non-closed figures in the projection from the semiconductor stack to the substrate; the protection structure is a first closed figure in the projection from the semiconductor stack to the substrate, and the protection structure includes the first metal layer composed of the first metal segment group C1, the intermediate metal layer composed of the second metal segment group C2, and the top metal layer composed of the third metal segment group C3. The first metal segment group C1 includes the first and second segments M11-M12 of the first metal segment group, and forms the first metal layer of the protection structure. The second metal segment group C2 includes the first to fourth segments M21-M24 of the second metal segment group, and forms the intermediate metal layer of the protection structure. The third metal segment group C3 includes the first and second segments M31-M32 of the third metal segment group, and forms the top metal layer of the protection structure. The first to third metal segment groups C1-C3 are all non-closed figures in the projection from the semiconductor stack to the substrate.

[0145] The semiconductor chip of the embodiment takes a GaN-based HEMT semiconductor device as an example. The semiconductor chip includes a source S, a drain D, a gate G, a field plate electrode FP, and four source pads S0, one gate pad G0, and one drain pad D0. The source S includes a first source metal layer S1 and a second source metal layer S2, the drain D includes a first drain metal layer D1 and a second drain metal layer D2, and the protection structure includes the first to third metal segment groups C1-C3. The first metal segment group C1 of the protection structure is arranged in the same layer as the first source metal layer S1 and the first drain metal layer D1; the second metal segment group C2 of the protection structure is arranged in the same layer as the field plate electrode FP; and the third metal segment group C3 of the protection structure is arranged in the same layer as the second source metal layer S2 and the second drain metal layer D2.

[0146] Further, the semiconductor chip of the embodiment takes a GaN-based HEMT semiconductor device as an example. The semiconductor chip includes a source S, a drain D, a gate G, a field plate electrode FP, and four source pads S0, one gate pad G0, and one drain pad D0. The source S includes a first source metal layer S1 and a second source metal layer S2, the drain D includes a first drain metal layer D1 and a second drain metal layer D2, and the protection structure includes the first to third metal segment groups C1-C3. The first metal segment group C1 of the protection structure is arranged in the same layer as the first source metal layer S1 and the first drain metal layer D1; the second metal segment group C2 of the protection structure is arranged in the same layer as the field plate electrode FP; and the third metal segment group C3 of the protection structure is arranged in the same layer as the second source metal layer S2 and the second drain metal layer D2. Figure 29 Further, the semiconductor chip of the embodiment takes a GaN-based HEMT semiconductor device as an example. The semiconductor chip includes a source S, a drain D, a gate G, a field plate electrode FP, and four source pads S0, one gate pad G0, and one drain pad D0. The source S includes a first source metal layer S1 and a second source metal layer S2, the drain D includes a first drain metal layer D1 and a second drain metal layer D2, and the protection structure includes the first to third metal segment groups C1-C3. The first metal segment group C1 of the protection structure is arranged in the same layer as the first source metal layer S1 and the first drain metal layer D1; the second metal segment group C2 of the protection structure is arranged in the same layer as the field plate electrode FP; and the third metal segment group C3 of the protection structure is arranged in the same layer as the second source metal layer S2 and the second drain metal layer D2. Figure 27A schematic cross-sectional view taken along the d-d' direction. The top metal layer extension Y1 is not directly connected to the source pad S0 in the pad region, but is instead electrically connected via a second connecting metal segment C2'. The minimum distance between the extension Y1 and the source pad S0 is f1, preferably 10μm ≥ f1 ≥ 2μm. This prevents the extension Y1 from being too close to the source pad S0, ensuring an effective distance to enhance the subsequent metal lift-off process. An f1 greater than 10μm results in a significant increase in device area and chip cost.

[0147] The specific production is as follows:

[0148] Step 1: Provide a semiconductor epitaxial structure 100, which includes a buffer layer 2, a channel layer 3, and a barrier layer 4 sequentially formed on a substrate 1, wherein the buffer layer is an AlN layer, the channel layer is a GaN layer, and the barrier layer is an AlGaN layer.

[0149] In other embodiments, the channel layer 3 and the barrier layer 4 are further provided with an insertion layer, which is an AlN layer. A cap layer is further provided on the barrier layer 4, which is a GaN layer.

[0150] Step 2, such as Figure 31 As shown, ion implantation is performed in the non-functional region Q' and the device region A to form a first ion implantation region FC in the non-functional region Q'. Source ion implantation regions and / or drain ion implantation regions (not shown) are formed in the semiconductor stack at the source region and / or drain region of the device region A. The ions implanted in the ion implantation regions include at least one selected from silicon (Si) ions and germanium (Ge) ions. The projection of the first ion implantation region FC from the semiconductor stack toward the substrate is a non-closed shape. In other embodiments, a closed shape may also be formed, as shown in 32.

[0151] Step 3: Form the first isolation region B1 and the second isolation region B2 by ion implantation in the periphery of the device region A of the functional region. The specific implementation method is as follows: use photoresist as a mask, adopt the steps of coating, exposing and developing to make the isolation region for ion implantation, remove the photoresist to form the first isolation region B1 and the second isolation region B2, wherein the implanted ions are nitrogen ions or helium ions, such as Figure 33 shown.

[0152] Step 4: deposit a first dielectric layer 51, and form a gate opening in the gate region of the device region A in the functional area, and form a gate G through photolithography and metal deposition processes. Figure 34 As shown,

[0153] In step 5, a second dielectric layer 52 is deposited. Using a photoresist as a mask, a first opening V1 is formed in the second dielectric layer 52 in the non-functional area Q' by applying a resist, exposing, and developing step. A first source opening VS1 and a first drain opening VD1 are formed in the second dielectric layer 52 in the device area A. From a top view, the projection shape of the first opening V1 from the semiconductor stack to the substrate is a non-enclosed structure.

[0154] Step 6, such as Figure 35 As shown, a first metal layer M1 is deposited by a photolithography process, and several metal segments are formed at the first opening V1, namely the first segment M11 of the first metal segment group and the second segment M12 of the first metal segment group, forming the first metal segment group C1, forming the first metal layer including the protection structure; a first source metal layer S1 is formed at the first source opening VS1; and a first drain metal layer D1 is formed at the first drain opening VD1. Figure 30 As shown, the shortest distance between the first segment M11 of the first-layer metal segment group and the second segment M12 of the first-layer metal segment group is d12, which is greater than 2 μm.

[0155] Step 7: Deposit a third dielectric layer 53. A second opening V2 is formed in the third dielectric layer 53 in the non-functional region Q' to expose a portion of the upper surface of the first metal layer. A second source opening VS2 and a second drain opening VD2 are formed in the device region A. From a top view, the second opening is an open pattern.

[0156] In step 8, a second metal layer M2 is deposited through a photolithography process. Several metal segments are formed at the second opening V2 in the non-functional area Q', namely the first to fourth segments M21 to M24 of the second layer metal segment group, constituting the second layer metal segment group C2. A second connecting metal segment C2' is formed at the second connecting metal segment setting location, and a field plate electrode FP is formed at the field plate structure setting location.

[0157] In step 9, a fourth dielectric layer 54 is deposited to form a second source opening VS2, a second drain opening VD2, a third opening V3, a plurality of fourth openings V4, and a plurality of fifth openings V5, respectively exposing portions of the first source metal layer S1, the second drain metal layer D1, the second metal segment group C2, one end of the second connecting metal segment C2', and the other end of the second connecting metal segment C2'.

[0158] Step 10, by a photolithography process, a third metal layer M3 is deposited at the third opening V3 to form a plurality of metal segments, forming a third layer metal segment group C3, including the first to second segments M31~M32 of the third layer metal segment group, i.e. forming a top metal layer of the protection structure; meanwhile, an extension Y1 towards the inner side is also formed, the fourth opening V4 is located below the extension Y1, the extension Y1 is connected with the second connection metal segment C2’ through the third metal layer M3 deposited in the fourth opening V4, at the second source opening VS2, a second source metal layer S2 is formed, at the second drain opening VD2, a second drain metal layer D2 is formed, the second source metal layer S2 is stacked on the first source metal layer S1 to form a source S of the semiconductor device; the second drain metal layer D2 is stacked on the first drain metal layer D1 to form a drain D of the semiconductor device; at least one pad (not shown) is formed at the pad area of the functional area at a plurality of pad openings, the pad area H at the fourth dielectric layer 54 forms at least one source pad, at least one gate pad and at least one drain pad; further, the source pad S0, the drain pad D0 and the gate pad G0 are connected with the source S, the drain D and the gate G respectively. The fifth opening V5 is located below the source pad S0, the source pad S0 is connected with the second connection metal segment C2’ through the third metal layer deposited in the fifth opening V5. The shortest distance between the extension Y1 and the source pad S0 is f1, preferably, f1≥2μm.

[0159] Step 11, a fifth dielectric layer 55 is deposited.

[0160] Step 12, by a photoresist coating, exposure and development steps, the fifth dielectric layer 55 is lithographically opened at the opening area, the fifth dielectric layer 55 is etched, and the photoresist is removed to expose part of the pad area of the semiconductor chip to expose the input / output terminals of the semiconductor chip.

[0161] It also includes forming a back hole 61 and depositing a back metal layer 6 on the back surface of the substrate of the semiconductor chip.

[0162] Example eleven

[0163] Different from example ten, the first ion implantation area FC is provided with a groove, and the first metal layer is arranged on the groove of the first ion implantation area FC. The source ion implantation area FS and / or the drain ion implantation area FD are provided with a groove, as shown in Figure 36 .

[0164] Correspondingly, the present application provides an electronic device comprising the semiconductor chip in the above examples. In particular, the electronic device is applied in the field of radio frequency, such as a communication device, which comprises a receiving and / or transmitting module, the receiving module comprises a radio frequency amplifier or the transmitting module comprises a radio frequency amplifier. The radio frequency amplifier comprises the semiconductor chip of the present application.

[0165] For example, the electronic device includes a radio frequency amplifier including the embodiment of the application.

[0166] It should be noted that the semiconductor chip is provided with a back metal layer, the back metal layer is electrically connected with the source of the device area, and the back hole can be arranged in the device area or the pad area.

[0167] The above embodiments are only used to further illustrate the application, but the application is not limited to the embodiments. It should be noted that in the embodiments of the application, the number of metal layers listed in the protection structure is two or three, but is not limited thereto, and four or more layers can be provided according to the actual design requirements of the semiconductor chip. The functional area of the semiconductor chip listed in the embodiments of the application includes GaN HEMT devices, and can also include other devices such as pHEMT GaAs. Any simple modification, equivalent change and modification made according to the technical essence of the application to the above embodiments all fall within the protection scope of the technical scheme of the application.

Claims

1. A semiconductor chip, comprising a substrate and a semiconductor stack stacked on the substrate, the semiconductor stack being provided with a functional region, the functional region being formed with a semiconductor element, characterized in that: a protection structure is provided on the semiconductor stack, the protection structure being arranged in a non-functional region outside the functional region in a top view; the functional region comprises a device region and a pad region arranged outside the device region, the pad region being provided with at least one pad, and the device region being provided with at least one electrode; the protection structure comprises at least two metal layers, each metal layer comprising at least one metal segment, and the metal segments of the upper metal layer being partially stacked on the lower metal layer; and a projection of the protection structure on a direction from the semiconductor stack to the substrate is a first closed figure, and a projection of each metal layer on the direction from the semiconductor stack to the substrate is a non-closed figure. 2.The semiconductor chip of claim 1, characterized in that: the protection structure comprises a top metal layer, and the top metal layer is not connected with the pad in a top view. 3.The semiconductor chip of claim 1, characterized in that: further comprising a connecting metal segment, the protection structure comprises a top metal layer, and the pad region comprises at least a first pad, the connecting metal segment being used to electrically connect the first pad and the protection structure. 4.The semiconductor chip of claim 3, characterized in that: a dielectric layer is provided on the connecting metal segment. 5.The semiconductor chip of claim 4, characterized in that: the top metal layer has an extension towards an inner side, one end of the connecting metal segment is connected with the extension, and the other end of the connecting metal segment is connected with the first pad. 6.The semiconductor chip of claim 5, characterized in that: the dielectric layer provided on the connecting metal segment is provided with a first via hole and a second via hole, one end of the connecting metal segment is electrically connected with the top metal layer of the protection structure through the first via hole, and the other end of the connecting metal segment is electrically connected with the first pad through the second via hole. 7.The semiconductor chip of claim 1, characterized in that: the semiconductor stack further comprises a first ion implantation region, the protection structure comprises a first metal layer, and the first metal layer is stacked on the first ion implantation region. 8.The semiconductor chip of claim 7, characterized in that: the first ion implantation region is provided with a groove, and the first metal layer is arranged on the groove of the first ion implantation region. 9.The semiconductor chip of claim 1, characterized in that: in a top view, a projection of the electrode of the functional region and the pad of the pad region on a direction from the semiconductor stack to the substrate is a second figure, and the second figure is located in the first closed figure. 10.The semiconductor chip of claim 1, characterized in that: the semiconductor stack is further provided with an isolation region, the protection structure comprises a first metal layer, and the first metal layer is arranged on the isolation region. 11.The semiconductor chip of claim 1, characterized in that: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The semiconductor chip further comprises a back metal layer disposed on the back of the substrate; and the protection structure is electrically connected to the back metal layer.

12. The semiconductor chip of claim 1, wherein: The semiconductor stack further comprises a first isolation region and a second isolation region; and the pad region is disposed in the first isolation region as viewed from a top view; and the second isolation region is located at a periphery of the protection structure.

13. The semiconductor chip of claim 1, wherein: A perimeter of a projection of the protection structure from the semiconductor stack to the substrate is L; a perimeter of a projection of the i-th metal layer of the protection structure from the semiconductor stack to the substrate is L Mi , i is a natural number greater than or equal to 1; 1 > L Mi / L ≥ 0.

5.

14. The semiconductor chip of claim 1, wherein: When the first metal layer is composed of at least two metal segments, a shortest distance between any two adjacent metal segments is greater than or equal to 2 µm; When the first metal layer is composed of one metal segment, a shortest distance between a first end and a last end of the metal segment of the first metal layer is greater than or equal to 2 µm.

15. The semiconductor chip of claim 14, wherein: A thickness of the first metal layer is d1; and a shortest distance between any two adjacent metal segments of the first metal layer or a shortest distance between the first end and the last end of the metal segment of the first metal layer is e1, e1 ≥ 10 × d1.

16. The semiconductor chip of claim 1, wherein: The device region of the semiconductor chip comprises a HEMT device; the semiconductor chip comprises a back metal layer disposed on the back of the substrate; and the protection structure is electrically connected to the back metal layer; The protection structure comprises a first metal layer and a top metal layer; The HEMT device comprises a source, a drain, and a gate; the source comprises a source contact layer and a source metal layer disposed on the source contact layer; and the drain comprises a drain contact layer and a drain metal layer disposed on the drain contact layer; The first metal layer, the source contact layer, and the drain metal layer are disposed in the same layer; The top metal layer, the source metal layer, and the drain metal layer are disposed in the same layer.

17. The semiconductor chip of claim 16, wherein: The HEMT device further comprises a field plate electrode; the protection structure further comprises an intermediate metal layer; and the intermediate metal layer is disposed between the first metal layer and the top metal layer; The intermediate metal layer is disposed in the same layer as the field plate electrode.

18. A method for manufacturing a semiconductor chip, comprising: forming a semiconductor stack on a substrate; and dividing the semiconductor stack into a functional region; the functional region comprises a device region and a pad region outside the device region; forming a protection structure on the semiconductor stack outside the functional region by synchronizing a plurality of metal deposition processes for forming at least one electrode and at least one pad in the functional region; the protection structure comprises at least two metal layers; each metal layer comprises at least one metal segment; and a part of an upper metal layer is disposed on a lower metal layer; a projection of the protection structure from the semiconductor stack to the substrate is a first closed figure; and a projection of each metal layer from the semiconductor stack to the substrate is a non-closed figure; as viewed from a top view, a projection of the electrode of the functional region and a pad of the pad region from the semiconductor stack to the substrate is a second figure; and the second figure is located in the first closed figure.

19. An electronic device, comprising: A semiconductor chip comprising any one of claims 1 to 17.

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