Semiconductor device and method for manufacturing semiconductor device

Abstract

The purpose of the present invention is to provide a technique capable of stabilizing withstand voltage characteristics and switching characteristics. The semiconductor device includes a semiconductor substrate, a first electrode, and a second electrode. The semiconductor substrate includes a drift layer, a semiconductor layer, a first buffer layer, and a second buffer layer. When the maximum value of the oxygen concentration of the semiconductor substrate calculated using the conversion coefficient of the old ASTM is defined as max [Oi] and the impurity concentration of the first conductivity type of the drift layer is defined as Crift, max [Oi] = 9.40 * 1016 * ln (Crift)-2.27 * 1018 is satisfied.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] A structure has been proposed in which a distribution layer having the maximum impurity concentration is provided near the center of the drift layer of a power diode or near the collector of an IGBT (Insulated Gate Bipolar Transistor) (for example, Patent Document 1). According to this structure, even if the specific resistance of the semiconductor wafer, that is, the concentration of the drift layer, varies, it is possible to control the breakdown voltage, which is a basic performance of the semiconductor device, and the electric field strength on the back side (cathode or collector) during the turn-off operation. As a result, carriers can be retained on the back side, and the oscillation phenomenon during the turn-off operation can be suppressed. Therefore, the controllability during the dynamic operation can be improved. Prior Art Documents Patent Documents

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2014-99643 Summary of the Invention Technical Problem to be Solved by the Invention

[0004] In the manufacturing process, heat treatment in an oxygen-containing atmosphere or heat treatment after forming a thermal oxide film causes oxygen to diffuse into the semiconductor wafer, so that a distribution in which the oxygen concentration decreases in the depth direction of the semiconductor wafer is formed. On the other hand, a donor layer caused by hydrogen such as protons provided in Patent Document 1 and the like is easily affected by oxygen in the semiconductor wafer.

[0005] Therefore, due to the distribution in which the oxygen concentration decreases in the depth direction, the impurity distribution of the donor layer changes unstably in the depth direction, or the impurity concentration of the donor layer increases due to the thermal donorization phenomenon caused by oxygen. As a result, there is a problem that the donor layer cannot be formed as designed, and the breakdown voltage characteristics and switching characteristics become unstable.

[0006] Therefore, the present disclosure has been made in view of the above problems, and an object thereof is to provide a technique capable of stabilizing the breakdown voltage characteristics and switching characteristics. Technical Means for Solving the Technical Problem

[0007] The semiconductor device according to the present disclosure includes: a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; and a first electrode and a second electrode respectively provided on the first main surface and the second main surface. The semiconductor substrate includes: a drift layer of a first conductivity type provided between the first main surface and the second main surface; a semiconductor layer connected to the second electrode and including at least one of a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type; a first buffer layer of a first conductivity type provided between the semiconductor layer and the drift layer; and a second buffer layer of a first conductivity type provided between the first buffer layer and the drift layer, the impurity concentration of the first conductivity type being smaller than that of the first buffer layer and larger than that of the drift layer. When the maximum value of the oxygen concentration of the semiconductor substrate calculated using the conversion coefficient of the old ASTM is set as maximum[O i , and the impurity concentration of the first conductivity type of the drift layer is set as C drift , it satisfies maximum[O i = 9.40×10 16 ×ln(C drift ) - 2.27×10 18 . Advantages of the Invention

[0008] According to the present disclosure, when the maximum value of the oxygen concentration of the semiconductor substrate calculated using the conversion coefficient of the old ASTM is set as maximum[O i , and the impurity concentration of the first conductivity type of the drift layer is set as C drift , it satisfies maximum[O i = 9.40×10 16 ×ln(C drift ) - 2.27×10 18 . According to this structure, the breakdown voltage characteristics and the switching characteristics can be stabilized. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a top view showing the structure of the semiconductor device according to Embodiment 1. Figure 2 is a cross-sectional view showing the structures of the IGBT and the diode according to Embodiment 1. Figure 3 is a graph showing the relationship between the oxygen concentration [O i of the semiconductor substrate and the impurity concentration C - of the n drift -type drift layer. Figure 4It shows the Figure 2 measurement result of the impurity distribution in B-B' in Figure 5 It shows the static breakdown voltage (BV ces ) of an IGBT with an n-type second buffer layer having the distribution (new structure 1) related to Embodiment 1 and the relationship between the oxygen concentration ([O i ) in the MCZ wafer. Figure 6 It shows the relationship between the time-zero dielectric breakdown characteristics of the gate oxide film and the oxygen concentration ([O i ) in the MCZ wafer. Figure 7 It shows the output characteristics of the IGBT. Figure 8 It shows the graph of the operating temperature dependence of the on-state voltage (V CE (sat)) of the IGBT. Figure 9 It shows the graph of the operating temperature dependence of the breakdown voltage (BV CES ) of the IGBT. Figure 10 It shows the relationship between the maximum cut-off energy (E SC ) in the short-circuit state of the IGBT and the on-state voltage (V CE (sat)). Figure 11 It shows the trade-off characteristics between the switching loss (E REC ) of the diode and the on-state voltage (V F ). Figure 12 It shows the relationship between the maximum cut-off power density during diode turn-off and the maximum switching speed (dj / dt) during turn-off. Figure 13 It shows the Figure 2 measurement result of the impurity distribution in B-B' in Figure 14 It shows the device characteristics of the diode (b). Figure 15 It shows the relationship between the performance of the diode and the maximum peak C2 in the n-type second buffer layer. Figure 16 It shows the relationship between the performance of the diode and C2 / C1. Figure 17 It shows the Figure 2Graph showing the measurement results of the impurity distribution in B-B' Figure 18 is a graph showing the relationship between the maximum turn-off energy (E SC ) and the supply voltage (V cc ) in the short-circuit state of the IGBT. Figure 19 is a graph showing the simulation results of the internal state of the IGBT device. Figure 20 is a graph showing the relationship between the maximum turn-off energy (E SC ) and the depth X2 of the peak of the n-type impurity concentration in the n-type second buffer layer. Figure 21 (a) to (f) are cross-sectional views showing the manufacturing process steps related to Embodiment 4. Figure 22 (g) to (j) are cross-sectional views showing the manufacturing process steps related to Embodiment 4. Figure 23 (k) to (m) are cross-sectional views showing the manufacturing process steps related to Embodiment 4. Figure 24 is a flowchart showing a part of the manufacturing process related to Embodiment 4. Figure 25 (a) to (c) are cross-sectional views showing the manufacturing process steps related to Embodiment 5. Figure 26 (d) to (f) are cross-sectional views showing the manufacturing process steps related to Embodiment 5. Figure 27 (g) to (i) are cross-sectional views showing the manufacturing process steps related to Embodiment 5. Figure 28 is a flowchart showing a part of the manufacturing process related to Embodiment 5. Figure 29 is a flowchart showing a part of the manufacturing process related to Embodiment 5. Figure 30 is a cross-sectional view showing the structure of the semiconductor device related to Embodiment 6. Figure 31 is a cross-sectional view showing the structure of the semiconductor device related to Embodiment 6. Figure 32 is a cross-sectional view showing the structure of the semiconductor device related to Embodiment 6. Figure 33 is a cross-sectional view showing the structure of the semiconductor device related to Embodiment 6. Figure 34It is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 6. Figure 35 It is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 6. Figure 36 It is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 6. Figure 37 It is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 6. Detailed Embodiments

[0010] Hereinafter, the embodiments will be described with reference to the drawings. The features described in the following embodiments are exemplary, and not all features are essential. In addition, in the descriptions shown above, the same or similar reference numerals are assigned to the same structural elements in multiple embodiments, and mainly different structural elements are described. In addition, in the descriptions recorded below, specific positions and directions such as "upper", "lower", "left", "right", "front surface" or "back surface" do not necessarily coincide with the positions and directions in actual implementation. Also, for example, a certain part having a higher concentration than other parts may mean that the average concentration of a certain part is higher than the average concentration of other parts. Conversely, a certain part having a lower concentration than other parts may mean that the average concentration of a certain part is lower than the average concentration of other parts. In addition, hereinafter, the first conductivity type is assumed to be n-type and the second conductivity type is assumed to be p-type for description, but the first conductivity type may also be p-type and the second conductivity type may also be n-type.

[0011] <Embodiment 1> Figure 1 It is a top view showing the structure of a power semiconductor chip as an example of the semiconductor device according to this Embodiment 1. Figure 1 The semiconductor device defines an active region 1, an interface region 2, and a terminal region 3.

[0012] The active region 1 is a region that guarantees the basic performance of the semiconductor device, and an IGBT as the first semiconductor device or a diode as the second semiconductor device is provided as a semiconductor element. The interface region 2 is a region between the active region 1 and the terminal region 3, and is a region that supports the breakdown withstand voltage during the dynamic operation of the semiconductor device or supports the original performance of the semiconductor element provided in the active region 1. The terminal region 3 is a region that guarantees the voltage holding and the stability and reliability of the voltage withstand characteristics in the static state, suppresses the insufficient breakdown withstand voltage during the dynamic operation, or supports the basic performance of the semiconductor device.

[0013] In addition, Figure 1In [the figure], a case where the active region 1 is provided with an IGBT is shown, and the surface gate wiring portion 4 and the gate pad portion 38 are provided in the active region 1. In the case where a diode is provided in the active region 1, the surface gate wiring portion 4 and the gate pad portion 38 may not be provided in the active region 1.

[0014] Figure 2 It is a cross-sectional view showing the structures of the IGBT and the diode according to Embodiment 1. Figure 2 In [the figure], one type of IGBT and two types of diodes (diode (a) and diode (b)) are illustrated. The diode as the second semiconductor device may be a p-i-n structure diode, that is, diode (a), or a diode having an RFC (Relaxed Field of Cathode) structure, that is, diode (b). In addition, the name of the diode as the second semiconductor device may be a power diode or an FWD (Freewheeling diode).

[0015] First, the structural elements common to the two types of diodes among the structural elements of one type of IGBT will be mainly described. The IGBT includes a semiconductor substrate 51, a first electrode 5, and a second electrode 21.

[0016] The semiconductor substrate 51 has a front surface 51a as a first main surface and a back surface 51b as a second main surface opposite to the first main surface. The first electrode 5 is provided on the front surface 51a and includes, for example, aluminum wiring. The second electrode 21 is provided on the back surface 51b and includes, for example, a metal film. In addition, the final device thickness (t device ) corresponding to the thickness of the semiconductor substrate 51 is, for example, 40 to 700 μm.

[0017] The semiconductor substrate 51 according to Embodiment 1 is a silicon (Si) semiconductor wafer (hereinafter also referred to as an "MCZ wafer") manufactured by the MCZ (Magnetic field applied Czochralski) method. Oxygen and carbon introduced as impurities during the manufacture of the MCZ wafer are present at the interstitial positions and substitutional positions in the Si single crystal lattice, respectively. Therefore, in the following description, the first letters of interstitial and substitutional are added, and the oxygen concentration and nitrogen concentration of the semiconductor substrate 51 are denoted as [O i and [C s , respectively. Generally, the [O i of the MCZ wafer is two to three digits higher than that of the FZ (Floating Zone) wafer, but the [C i of the MCZ wafer and the FZ wafer are equal. s ​

[0018] The semiconductor substrate 51 includes an n-type drift layer as a drift layer of the first conductivity type, an n-type first buffer layer as a first buffer layer of the first conductivity type, an n-type second buffer layer as a second buffer layer of the first conductivity type, and a semiconductor layer described later. In addition, in this specification, the impurity concentration refers to the concentration of an element different from Si, and the element is appropriately described. Further, in the first embodiment, the element forming the diffusion layer is a dopant. - The n-type drift layer 15 corresponds to a portion of the MCZ wafer of the semiconductor substrate 51 that is substantially free of newly implanted impurities (ions, dopants).

[0019] n - The n-type impurity of the n-type drift layer 15 is, for example, phosphorus (P) or antimony (Sb). - The impurity concentration C of the n-type drift layer 15 - is, for example, 1.0×10 drift to 5.0×10 12 atoms / cm 14 . 3

[0020] In addition, when manufacturing a large-diameter semiconductor wafer, due to the segregation phenomenon of dopants in the Si single crystal ingot, the deviation of the impurity concentration in the crystal axis direction of the Si single crystal ingot (i.e., the impurity concentration C of the n-type drift layer 15) becomes large. However, the evaporation rate of antimony (1.3×10 - cm / sec) is approximately three orders of magnitude larger than the evaporation rate of phosphorus (1.6×10 drift cm / sec). Therefore, if antimony is used as the n-type impurity of the semiconductor wafer and a Si single crystal is fabricated by utilizing its characteristic evaporation control technology, the deviation of the impurity concentration C in the crystal axis direction of the Si single crystal ingot can be suppressed. -1 cm / sec) is approximately three orders of magnitude larger than the evaporation rate of phosphorus (1.6×10 -4 cm / sec). Therefore, if antimony is used as the n-type impurity of the semiconductor wafer and a Si single crystal is fabricated by utilizing its characteristic evaporation control technology, the deviation of the impurity concentration C in the crystal axis direction of the Si single crystal ingot can be suppressed. drift

[0021] n - The n-type drift layer 15 is provided between the front surface 51a and the back surface 51b, and extends, for example, from the main junction 12 on the front surface 51a side to the junction 22 on the back surface 51b side. When the voltage of the semiconductor element is held, a reverse bias is applied to the main junction 12. When a reverse bias is applied to the main junction 12, the depletion layer extends from the main junction 12 to the back surface 51b, and the electric field strength at the main junction 12 becomes the maximum. The junction 22 is a portion that contacts the depletion layer extending from the main junction 12 to the back surface 51b when the voltage is held, and is the second highest portion in terms of electric field strength after the main junction when the voltage is held.

[0022] ​​The semiconductor layer is connected to the second electrode 21 and includes at least one of a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. In addition, in this specification, for example, at least any one of A, B, C, ……, and Z means any one of all combinations obtained by extracting one or more types from the group of A, B, C, ……, and Z.

[0023] The above semiconductor layer of the IGBT includes a second semiconductor layer of a second conductivity type, that is, a p-type collector layer 18. In the p-type collector layer 18, the p-type impurity is, for example, boron (B), and the peak value of the impurity concentration is, for example, 1.0×10 16 ~1.0×10 20 atoms / cm 3 , and the depth from the back surface 51b is, for example, 0.3 to 0.8 μm.

[0024] The above semiconductor layer of the diode (a) includes a first semiconductor layer of a first conductivity type, that is, an n + -type cathode layer 19. In the n + -type cathode layer 19, the n-type impurity is, for example, arsenic (As) or phosphorus (P), and the peak value of the impurity concentration is, for example, 1.0×10 17 ~1.0×10 20 atoms / cm 3 , and the depth from the back surface 51b is, for example, 0.3 to 0.5 μm.

[0025] The above semiconductor layer of the diode (b) includes a first semiconductor layer of a first conductivity type, that is, an n + -type cathode layer 19 and a second semiconductor layer of a second conductivity type, that is, a p-type cathode layer 20. The n + -type cathode layer 19 of the diode (b) is the same as the n + -type cathode layer 19 of the diode (a). In the p-type cathode layer 20, the p-type impurity is, for example, boron (B), and the peak value of the impurity concentration is, for example, 1.0×10 16 ~1.0×10 18 atoms / cm 3 , and the depth from the back surface 51b is, for example, 0.3 to 0.5 μm.

[0026] Two buffer layers (an n-type first buffer layer 16 and an n-type second buffer layer 17) are provided to stabilize the voltage holding ability in the off state, reduce the power consumption during turn-off, improve the controllability during dynamic operation, and increase the breakdown voltage withstand. For example, the n-type first buffer layer 16 is provided to stabilize the voltage holding ability in the off state.

[0027] The n-type first buffer layer 16 is provided between the semiconductor layer connected to the second electrode 21 and the n -between the p-type drift layers 15. For example, the n-type first buffer layer 16 of the IGBT is disposed between the p-type collector layer 18 and the n - type drift layer 15. The n-type first buffer layer 16 of the diode (a) is disposed between the n + type cathode layer 19 and the n - type drift layer 15. The n-type first buffer layer 16 of the diode (b) is disposed between the n + type cathode layer 19 and each of the p-type cathode layers 20 and the n - type drift layer 15.

[0028] In the n-type first buffer layer 16, the n-type impurity is, for example, arsenic (As) or phosphorus (P), and the maximum peak value (C1) of the impurity concentration is, for example, 1.0×10 15 ~1.0×10 16 atoms / cm 3 , and the depth (X1) from the back surface 51b is, for example, 1.0 to 30 μm.

[0029] The n-type second buffer layer 17 is disposed between the n-type first buffer layer 16 and the n - type drift layer 15. The n-type impurity concentration of the n-type second buffer layer 17 is smaller than that of the n-type first buffer layer 16 and larger than that of the n - type drift layer 15.

[0030] In the n-type second buffer layer 17, the n-type impurity is, for example, a proton (H + ), the maximum peak value (C2) of the impurity concentration is, for example, less than the above C1, preferably 0.01×C1 or less, and the depth (X2) from the back surface 51b is, for example, 20 to 30 μm deeper than the depth (X1).

[0031] As will be described later, for the n - type drift layer 15, the n-type first buffer layer 16, and the n-type second buffer layer 17, the relationship of τ2<τ1≤τ t can be satisfied. Here, τ2 is the carrier lifetime of the n-type second buffer layer 17, and τ1 is the carrier lifetime of the n-type first buffer layer 16. τ2 is the n - type carrier lifetime of the drift layer 15, which has no influence on the conduction voltage of the IGBT (i.e., the conduction voltage of the gate electrode).

[0032] Next, other structural elements of the IGBT will be described. The semiconductor substrate 51 further includes an n + type emitter layer 7 as an emitter layer of the first conductivity type, a P + type layer 8, a p-type base layer 9 as a base layer of the second conductivity type, and an n-type layer 11.

[0033] The p-type base layer 9 is provided on the side closer to the front surface 51a of the n- - -type drift layer 15. In the p-type base layer 9, the p-type impurity is, for example, boron (B), and the peak value of the impurity concentration is, for example, 1.0×10 16 ~1.0×10 18 atoms / cm 3 , and the depth from the front surface 51a is deeper than that of the n- + -type emitter layer 7 and shallower than that of the n-type layer 11.

[0034] The n-type layer 11 is provided between the p-type base layer 9 and the n- - -type drift layer 15. In the n-type layer 11, the n-type impurity is, for example, arsenic (As) or phosphorus (P), and the peak value of the impurity concentration is, for example, 1.0×10 15 ~1.0×10 17 atoms / cm 3 , and the depth from the front surface 51a is, for example, 0.5 to 1.0 μm deeper than that of the p-type base layer 9.

[0035] The n- + -type emitter layer 7 is provided on the side closer to the front surface 51a of the p-type base layer 9. In the n- + -type emitter layer 7, the n-type impurity is, for example, arsenic (As) or phosphorus (P), and the peak value of the impurity concentration is, for example, 1.0×10 18 ~1.0×10 21 atoms / cm 3 , and the depth from the front surface 51a is, for example, 0.2 to 1.0 μm.

[0036] The p- + -type layer 8 is provided on the side closer to the front surface 51a of the p-type base layer 9. In the p- + -type layer 8, the p-type impurity is, for example, boron (B), and the surface impurity concentration is, for example, 1.0×10 18 ~1.0×10 21 atoms / cm 3 , and the depth from the front surface 51a is the same as that of the n- + -type emitter layer 7 or deeper than that of the n- + -type emitter layer 7.

[0037] The semiconductor substrate 51 of the IGBT is provided with a trench 24 that penetrates through the p-type base layer 9, the n- + -type emitter layer 7, and the n-type layer 11. The depth D of the trench 24 from the front surface 51a trench is, for example, 2.0 μm or more and deeper than that of the n-type layer 11.

[0038] On the inner wall of the trench 24, a gate electrode 14 as a trench electrode is provided via a gate oxide film 13. The gate electrode 14 is electrically connected to the surface gate wiring portion 4 of Figure 1 Figure 1 and is insulated from the first electrode 5 at the emitter potential by an interlayer film 6 including an oxide film and the like. In addition, as will be described later, in addition to the gate electrode 14, the trench electrodes provided in the trench 24 may include dummy electrodes connected to the first electrode 5 at the emitter potential. When the trench electrodes include dummy electrodes, suppression of the oscillation in the no-load short-circuit state and improvement of the short-circuit withstand capacity can be expected by suppressing the saturation current density of the IGBT and controlling the capacitance characteristics. In addition, a decrease in the conduction voltage can be expected by increasing the carrier concentration on the emitter side.

[0039] Next, other structural elements of the diode (a) and the diode (b) will be described. As described above, the difference between the diode (a) and the diode (b) lies in the presence or absence of the p-type cathode layer 20.

[0040] The semiconductor substrate 51 further includes a p-type cathode layer 10 as an anode layer of the second conductivity type. The p-type anode layer 10 is provided closer to the front surface 51a side of the n - -type drift layer 15. In the p-type anode layer 10, the p-type impurity is, for example, boron (B), and the surface impurity concentration is, for example, 1.0×10 16 atoms / cm 3 or more, and the peak of the impurity concentration is, for example, 2.0×10 16 to 1.0×10 18 atoms / cm 3 . The depth of the p-type anode layer 10 from the front surface 51a is, for example, 2.0 to 10.0 μm.

[0041] In addition, as will be described later, similar to the p + -type layer 8 of the IGBT, a p + -type layer 8 can be provided. The p + -type layer 8 is provided closer to the front surface 51a side of the p-type anode layer 10 and is a second-conductivity-type impurity diffusion layer having a higher p-type impurity concentration than the p-type anode layer 10.

[0042] In addition to the n - -type drift layer 15, the n-type first buffer layer 16, and the n-type second buffer layer 17, the p-type collector layer 18, n +The p-type cathode layer 19 and the p-type cathode layer 20 form a vertical structure. The vertical structure is a region that ensures the stability and reliability of the total loss (loss obtained by adding the loss of the on-state voltage, the loss in the on-state, and the loss in the off-state) performance, the withstand voltage retention and withstand voltage characteristics in the static state, and the leakage characteristics (off-loss) during voltage retention at high temperature. In addition, the vertical structure is a region that ensures the controllability and breakdown tolerance during dynamic operation and supports the basic performance of the semiconductor device.

[0043] In the manufacturing process of Si semiconductor wafers constituting the above IGBT and diode, if oxygen is introduced into the semiconductor wafer, the oxygen becomes a donor through the thermal donor phenomenon at a specific annealing temperature, n - The n-type impurity concentration C of the drift layer 15 drift In particular, the increase in MCZ wafers is more significant than that in FZ method semiconductor wafers.

[0044] In order to solve the problem caused by this, the first embodiment is configured to set the maximum value of the oxygen concentration of the semiconductor substrate 51 to maximum [O i ], the following formula (1) is satisfied:

[0045] maximum[O i ]=9.40×10 16 ×ln(C drift )-2.2 7×10 18 ···(1)

[0046] In addition, [O i ] is calculated using the detection value obtained by detecting oxygen in Si by FTIR (Fourier Transform Infrared Spectroscopy) and the conversion factor adopted in F121-79 (old ASTM) of ASTM (American Society for Testing and Materials). Impurity concentration C drift For example, n － A representative value (eg, average value, median value, etc.) of the n-type impurity concentration in the n-type drift layer 15. i ] and the impurity concentration C drift The units are the same (e.g. [cm －3 ]), ln is the natural logarithm.

[0047] Figure 3 is the oxygen concentration [O] of the semiconductor substrate 51 as the MCZ wafer in equation (1). i ] and n- The impurity concentration C of the type drift layer 15 drift The graph of the relationship

[0048] According to the structure related to the first embodiment that satisfies this relationship, even if the n - The impurity concentration C of the type drift layer 15 drift Changes due to the thermal donor phenomenon, and it is possible to suppress the adverse effects on the basic performance of the semiconductor device, that is, the voltage (static breakdown voltage) holding ability in the off state. In addition, it is possible to suppress adverse effects such as instability and changes in the impurity distribution of the n-type second buffer layer 17 caused by oxygen. In particular, when the semiconductor substrate 51 is an MCZ wafer having a uniform oxygen concentration distribution, the suppression of this adverse effect is effective. In addition, maximum[O i can be called the limit value of [O i , when n － The impurity concentration C of the type drift layer 15 drift Changes due to thermal donor formation caused by oxygen in the MCZ wafer, the voltage holding ability for maintaining the off state

[0049] The [O i in formula (1) is calculated using the conversion factor of the old ASTM as described above. When [O i is calculated using the conversion factor of ASTM F121-83 (new ASTM), the following formula (2) is satisfied. When [O i is calculated using the conversion factor of International Oxygen Coefficient (International Oxygen Coefficient) 1988 (IOC 88), the following formula (3) is satisfied.

[0050] maximum[O i = 4.78×10 16 ×ln(C drift ) - 1.1 6×10 18 ···(2)

[0051] maximum[O i = 6.13×10 16 ×ln(C drift ) - 1.4 8×10 18 ···(3)

[0052] Figure 4 Is a graph showing the measurement results of the impurity distribution related to the first embodiment along the depth direction of B-B' of Figure 2 In addition, Figure 4The result is obtained by the SRA (Spreading Resistance Analysis) method, and the impurity concentration of the p-type collector layer 18 is not detected under the measurement accuracy of SRA.

[0053] Figure 4 In [O i , the impurity distributions of the new structure 1, the new structure 2, the new structure with height [O

[0054] , and the existing structure are shown.

[0055] In the new structure 1, the n-type second buffer layer 17 includes a second-1 buffer layer to a second-n buffer layer. The second-1 buffer layer to the second-n buffer layer are sequentially provided from the n-type first buffer layer 16 toward the n － -type buffer layer 15, and respectively have C 2,1 ~C 2,n as the peaks of the n-type impurity concentration. When the maximum peak of the n-type impurity concentration in the n-type second buffer layer 17 in the new structure 1 is set as C2, C2 corresponds to C 2,1 . In addition, the new structure 1 is described in Embodiments 1 and 2.

[0056] In the new structure 2, the n-type second buffer layer 17 is a single layer having C 2，0 as the peak of the n-type impurity concentration. When the maximum peak of the n-type impurity concentration in the n-type second buffer layer 17 in the new structure 2 is set as C2, C2 corresponds to C 2,0 . In addition, the new structure 2 is described in Embodiment 3.

[0057] Except for not satisfying the formula (1), the new structure with height [O i has the impurity distribution of the same semiconductor device as the new structure 1. Generally, even for an MCZ wafer with an impurity distribution of [O i that is substantially constant in the depth direction of the horizontal axis of Figure 4 , the thermal donor phenomenon caused by oxygen in the semiconductor wafer will occur. However, if [O i is higher than the maximum [O i , compared with the case where it is below the maximum [O i , the impurity distribution of the n-type second buffer layer 17 becomes wider in the depth direction, and the impurity concentration of the n-type second buffer layer 17 becomes higher.

[0058] As a result, in the n-type second buffer layer 17, it is assumed that the impurity distribution of the new structure 1 in Figure 4 cannot be stably achieved. Therefore, even for [Oi an MCZ wafer in which the impurity distribution is substantially constant in the junction depth direction. From the viewpoint of stabilizing the impurity distribution of the n-type second buffer layer 17, [O i needs to be controlled below the maximum [O i .

[0059] In contrast, in the present Embodiment 1, the n-type buffer layer includes an n-type first buffer layer 16 and an n-type second buffer layer 17, and the semiconductor substrate 51 includes the n-type second buffer layer 17, etc. [O i is an MCZ wafer controlled below the maximum [O i . Therefore, the impurity distribution of the n-type second buffer layer 17 can be stabilized.

[0060] Further, the n-type second buffer layer 17 is a hydrogen-induced donors layer, and its existence is due to a donor-type composite defect formed by a point defect reaction of hydrogen and an interstitial Si pair (I + ) generated when a proton (H si ) is introduced into Si. Point defects include, for example, G center (I Si3 cluster, 1.019 eV (*), E V + 0.1 eV), X center (I Si4 cluster, 1.040 eV (*), E V + 0.32 eV). The energy value with an attached (*) is the photon energy calculated from the PL spectrum when analyzed by the Photoluminescence (PL) method. The PL method is an analysis method in which light is irradiated onto a semiconductor, and the light emitted when electron-hole pairs recombine via defect energy levels is observed.

[0061] In the existing structure, which is the impurity distribution of an existing semiconductor device, near the junction (X j，n1 ) of the n-type first buffer layer 16 and the n-type second buffer layer 17, there is a crystal defect layer 23 having a concentration lower than the impurity concentration C － of the n drift -type drift layer 15.

[0062] As defects of the crystal defect layer 23, similar to the HDs layer of the n-type second buffer layer 17, there are point defects (G center and X center) originating from interstitial Si pairs. However, in the existing structure without supplementing protons (H + ), there is a shortage of hydrogen. Therefore, the point defects do not react with hydrogen and do not form an HDs layer. In addition, [O i is higher, then H +The more the composite defects caused by oxygen trapped in Si (e.g., VO (Vacancy-Oxygen pair), CiOi (interstitial Carbon-interstitial Oxygen pair), V2 (di-Vacancy)) turn into VOH, C i O i H n 、V2H2, H + Diffusion in the direction of the back surface 51b is blocked by oxygen.

[0063] Therefore, Figure 4 in the existing structure of, since [O i in the MCZ wafer blocks the diffusion of hydrogen in the direction of the back surface 51b, therefore, a crystal defect layer 23 with an impurity concentration lower than that of the n － -type drift layer 15 is formed. On the other hand, in the new structure 1 of Embodiments 1 to 2, protons (H drift ) are introduced into the n-type second buffer layer 17, so that the crystal defect layer 23 is not formed. In addition, in the new structure 2 of Embodiment 3, protons (H + ) are introduced near the junction (X j，n1 ) of the n-type first buffer layer 16, so that the crystal defect layer 23 is not formed. +

[0064] Figure 5 is an IGBT (3.3 kV class, C drift : 2.0×10 13 cm -3 ) having the impurity distribution of the new structure 1 with respect to the n-type second buffer layer 17, showing a graph of the relationship between the static breakdown voltage (BV ces ) and the oxygen concentration ([O i ) in the MCZ wafer. As can be seen from Figure 5 , if [O i is higher than 6.0×10 17 cm -3 , the static breakdown voltage (BV ces ) decreases. The [O 17 higher than 6.0×10 -3 is higher than the i maximum [O Figure 3 . From this, it can be seen that since the n-type second buffer layer 17 has the impurity distribution of the new structure 1, the maximum [O i is lower than 6.0×10 i cm 17 -3The IGBT has sufficient off-state voltage (static withstand voltage) retention ability even at a low temperature of 218K.

[0065] Figure 6 It is an IGBT (3.3 kV class, C drift : 2.0×10 13 cm -3 , temperature 298K) with a new structure 1 impurity distribution for the n-type second buffer layer 17, showing a graph of the relationship between the time-zero dielectric breakdown characteristics of the gate oxide film 13 and the oxygen concentration ([O i ) in the MCZ wafer. Figure 6 The lower [O i in corresponds to Figure 3 's maximum [O i , Figure 6 The higher [O i in is higher than Figure 3 's maximum [O i . At lower [Oi], even at a higher voltage, the probability of dielectric breakdown (the probability corresponding to cumulative frequency) is lower.

[0066] Figure 7 It is an IGBT (6.5 kV class, C drift : 5.0×10 12 cm -3 ) with a new structure 1 or existing structure impurity distribution for the n-type second buffer layer 17, showing a graph of the output characteristics of the IGBT. In the impurity distribution of the existing structure, there is a crystal defect layer 23, and at the initial stage of IGBT conduction, the hole injection efficiency from the back surface 51b is reduced. Therefore, as Figure 7 shows, a snap-back characteristic occurs where J C does not increase monotonically with respect to V CE . Therefore, the normal conduction operation of the IGBT cannot be achieved. On the other hand, in the impurity distribution of the new structure 1, there is no crystal defect layer 23 that hinders hole injection from the back surface 51b of the IGBT, and as Figure 7 shows, J C increases monotonically with respect to V CE , so the normal conduction operation of the IGBT can be achieved.

[0067] Figure 8 It is an IGBT (6.5 kV class, C drift : 5.0×1012 cm -3 ) showing the operating temperature dependence of the on-voltage (V CE (sat)) of the IGBT. In the impurity distribution of the existing structure, there is a crystal defect layer 23, and Figure 7 such a springback characteristic is generated. Therefore, as Figure 8 such, it shows that V CE (sat) decreases to a specific temperature and increases from the specific temperature. On the other hand, in the impurity distribution of the new structure 1, as Figure 8 shown, the dependence of V CE (sat) on temperature (i.e., the rate of change) remains positive. Therefore, it is effective at the operating level of a power module in which multiple semiconductor devices are assembled in parallel.

[0068] Figure 9 is an IGBT (6.5 kV class, C drift : 5.0×10 12 cm -3 ) having the impurity distribution of the new structure 1 or the existing structure for the n-type second buffer layer 17, showing the operating temperature dependence of the breakdown voltage (BV CES ). As Figure 9 shown, the breakdown voltage holding ability in the off state of the impurity distribution of the new structure 1 is higher than that of the impurity distribution of the existing structure. The reason can be considered that in the impurity distribution of the existing structure, the part of the depletion layer extending from the main junction 12 on the front surface 51a side to the crystal defect layer 23 during voltage holding of the semiconductor device becomes the leakage power generation source during voltage holding, resulting in a decrease in the voltage holding ability.

[0069] Figure 10 is an IGBT (6.5 kV class, C drift : 5.0×10 12 cm -3 ) having the impurity distribution of the new structure 1 or the existing structure for the n-type second buffer layer 17, showing the relationship between the maximum turn-off energy (E SC ) and the on-voltage (V CE (sat)) in the short-circuit state. As Figure 10 shown, the maximum turn-off energy (E SC ) in the short-circuit state of the impurity distribution of the new structure 1 is higher than the maximum turn-off energy (E SC) is higher. In the impurity distribution of the existing structure, there is a crystalline defect layer 23. Therefore, carriers on the back side 51b of the IGBT in the short-circuit state disappear. Due to this behavior, the carrier concentration on the back side 51b of the IGBT in the short-circuit state decreases, resulting in an increase in the electric field strength and an imbalance in the internal state of the device. Therefore, it can be considered that the cut-off ability in the short-circuit state of the IGBT with the impurity distribution of the existing structure decreases. On the other hand, it can be considered that there is no crystalline defect layer 23 in the IGBT with the impurity distribution of the new structure 1. Therefore, the breakdown withstand voltage during dynamic operation is improved.

[0070] Figure 11 is a diode (b) (6.5 kV class, C with a new structure 1 or an existing structure impurity distribution for the n-type second buffer layer 17 drift : 5.0×10 12 cm -3 ), showing a graph of the trade-off characteristics of the switching loss (E REC ) and the on-state voltage (V F ). Compared with the diode with the impurity distribution of the existing structure, the waveform during recovery in the turn-off operation of the diode with the impurity distribution of the new structure 1 is improved. As a result, as Figure 11 shown, compared with the diode with the impurity distribution of the existing structure, the diode with the impurity distribution of the new structure 1 can reduce the switching loss (E REC ) at the same on-state voltage. Therefore, in the diode with the impurity distribution of the new structure 1, the trade-off characteristics between E REC and V F are improved.

[0071] Figure 12 is a diode (b) (6.5 kV class, C with a new structure 1 or an existing structure impurity distribution for the n-type second buffer layer 17 drift : 5.0×10 12 cm -3 ), showing a graph of the relationship between the maximum cut-off power density during turn-off and the maximum switching speed (dj / dt) during turn-off. As Figure 12 shown, compared with the diode with the impurity distribution of the existing structure, the diode with the impurity distribution of the new structure 1 can cut off a higher power density at the same switching speed (dj / dt).

[0072] <Summary of Embodiment 1> According to the semiconductor device (IGBT, diode (a) or diode (b)) according to the above Embodiment 1, when the maximum value of the oxygen concentration of the semiconductor substrate 51 calculated using the conversion coefficient of the old ASTM is set to maximum[O i , and n －The impurity concentration of the type drift layer is set to C drift In the case of, satisfying maximum[O i = 9.40×10 16 ×ln(C drift ) - 2.27×10 18 . According to this structure, for example, while having sufficient breakdown voltage holding ability in the off state, normal conduction operation and an increase in breakdown voltage withstand during dynamic operation can be achieved. That is, the breakdown voltage characteristics and switching characteristics can be stabilized.

[0073] <Embodiment 2> The cross-sectional structure of the semiconductor device according to this Embodiment 2 is the same as the cross-sectional structure of the semiconductor device according to Embodiment 1 ( Figure 2 the cross-sectional structure). Figure 13 is a diagram showing the measurement result of the impurity distribution in the depth direction along Figure 2 B-B' of this Embodiment 2.

[0074] In the semiconductor device according to this Embodiment 2, maximum[O i satisfies Equation (1), and the n-type second buffer layer 17 has Figure 4 the impurity distribution of the new structure 1. Therefore, the n-type second buffer layer 17 includes a second-1 buffer layer to a second-n buffer layer (where n≥2). The second-1 buffer layer to the second-n buffer layer are sequentially provided from the n-type first buffer layer 16 toward the n － type buffer layer 15, and respectively have C 2,1 ~C 2,n as the peak values of the n-type impurity concentration.

[0075] That is, in the direction from the junction (X j，n1 ) of the n-type first buffer layer 16 and the n-type second buffer layer 17 toward the junction (X － ) of the n-type second buffer layer 17 and the n j，n2n type buffer layer 15, the second-1 buffer layer to the second-n buffer layer are sequentially provided. In this Embodiment 2, C 2，n <……<C 2，2 <C 2，1 is satisfied.

[0076] Figure 13 In, not only the new structure 1, but also the impurity distributions of the new structure 1-(a) and the new structure 1-(b) compared with the new structure 1 are shown. In the impurity distribution of the new structure 1-(a), the relationship of the above-mentioned peak values is opposite to that of the impurity distribution of the new structure 1, and C 2，1 <C 2，2 <……<C 2，n。In the impurity distribution of the new structure 1-(b), the above-mentioned peak is substantially the same as the impurity distribution of the new structure 1, satisfying C 2，n ≈……≈C 2，2 ≈C 2，1 。In addition, in any of the three impurity distributions (new structure 1, new structure 1-(a), new structure 1-(b)), the total dose, i.e., the total amount of the dose during ion implantation for forming the second-1 buffer layer to the second-n buffer layer, is set to be the same.

[0077] Figure 14 is a diagram showing the device characteristics of the diode (b) (1200V class) having any of the three impurity distributions with Figure 13 . Compared with the diodes having the impurity distributions of the new structure 1-(a) or the new structure 1-(b), the on-voltage (V F ) of the diode having the impurity distribution of the new structure 1 is lower, the leakage current (J R ) during 1200V holding is lower, and the Safe Operating Area (SOA) in the dynamic state is wider.

[0078] In the diode having the impurity distribution of the new structure 1, during dynamic operation, the extension of the depletion layer reaching the n-type second buffer layer 17 from the main junction 12 becomes slow. Therefore, the carrier plasma layer tends to remain in the back surface 51b region. The carrier plasma layer is a layer formed by conductivity modulation in the n － -type drift layer 15 where electrons and holes are injected during conduction of the semiconductor device, and is a neutral layer with an equal level of electron concentration and hole concentration. The behavior of the remaining carrier plasma layer can be defined as the action of controlling the interaction between the carrier plasma layer and the electric field strength during the dynamic operation of the semiconductor device (IGBT, diode (a), diode (b)).

[0079] Through the above behavior, in the diode having the impurity distribution of the new structure 1, the maximum voltage (V AK ) in the V snap-off waveform during the recovery operation of the SOA representing the snappy mode can be made lower than the rated voltage (1200V). Therefore, it is possible to achieve breakdown suppression and improved controllability during dynamic operation.

[0080] In addition, through the above behavior, in the diode having the impurity distribution of the new structure 1, the maximum cut-off current density (J CC ) during the recovery operation of the SOA representing the high power supply voltage (V A ) and high current mode increases. Therefore, the SOA in the dynamic state can be expanded.

[0081] Figure 15 Diode (b) (1200V class) with impurity distribution of new structure 1 for n-type second buffer layer 17, a graph showing the relationship between the performance of the diode and the maximum peak C2 in the n-type second buffer layer 17 of the diode. Figure 15 In, the performance of the diode includes breakdown voltage (BV RRM ), and dynamic SOA, and the maximum peak C2 corresponds to C of the second-first buffer layer 2，1 . Figure 15 The Safe Operating Temperature on the vertical axis of [] is the lowest operating temperature that can be cut off under the snappy recovery of the diode.

[0082] Figure 15 The range of the physical quantity on the horizontal axis of [] (i.e., the range of the maximum peak C2 of the n-type second buffer layer 17) is preferably such that the physical quantity on the vertical axis does not depend on the range of the physical quantity on the horizontal axis ( Figure 15 in, 1.0×10 15 cm -3 or less range). Therefore, in the second embodiment, it is configured to satisfy the following formula (4), so that the breakdown voltage holding ability in the fully off state of the diode can be maintained while ensuring the dynamic SOA.

[0083] C drift <C2≦1. 0×10 15 cm －3 · · · (4)

[0084] Figure 16 Diode (b) (6.5kV class) with impurity distribution of new structure 1 for n-type second buffer layer 17, a graph showing the relationship between the performance of the diode (breakdown voltage (BV RRm ) and the safe operating temperature in the fast recovery mode) and C2 / C1. In addition, C2 / C1 is the ratio of the maximum peak C2 of the n-type impurity concentration in the n-type second buffer layer 17 to the maximum peak C1 of the n-type impurity concentration in the n-type first buffer layer 16.

[0085] Figure 16 The range of the physical quantity on the horizontal axis of [] (i.e., the range of C2 / C1) is preferably such that the physical quantity on the vertical axis does not depend on the range of the physical quantity on the horizontal axis ( Figure 16 in, 1.0×10 -4 ~1.0×10 -1 cm -3 range). Therefore, in the second embodiment, it is configured to satisfy the following formula (5), so that the breakdown voltage holding ability in the fully off state of the diode can be maintained while ensuring the dynamic SOA.

[0086] 1.0×10－4 ≦ C2 / C1 ≦ 1.0×10 －1 ···(5)

[0087] <Embodiment 3> The cross-sectional structure of the semiconductor device according to Embodiment 3 is the same as that of the semiconductor device according to Embodiment 1 ( Figure 2 ). Figure 17 It is a diagram showing the measurement results of the impurity distribution according to Embodiment 3 in the depth direction along Figure 2 B - B'.

[0088] In the semiconductor device according to Embodiment 3, maximum[O i satisfies Equation (1), and the n-type second buffer layer 17 has Figure 4 the impurity distribution of the new structure 2. Therefore, the n-type second buffer layer 17 is a single layer with a single peak.

[0089] Figure 17 In , not only for the new structure 1 and the new structure 2, but also for the new structure 2-(a) and the new structure 2-(b) compared with the new structure 2, the impurity distributions are illustrated. X1 is the depth of the peak of the n-type impurity concentration in the n-type first buffer layer 16 starting from the back surface 51b, and X2 is the depth of the peak of the n-type impurity concentration in the n-type second buffer layer 17 starting from the back surface 51b. In the impurity distribution of the new structure 2-(a), the depth X2 of the peak of the n-type second buffer layer 17 is deeper than that of the impurity distribution of the new structure 2. In the impurity distribution of the new structure 2-(b), the depth X2 of the peak of the n-type second buffer layer 17 is deeper than that of the impurity distribution of the new structure 2-(a).

[0090] Figure 18 It is a diagram showing the relationship between the maximum cut-off energy (E Figure 17 ) and the power supply voltage (V SC ) in the short-circuit state for an IGBT (6.5 kV class) having any one of the four impurity distributions with CC . Figure 19 It is a diagram showing the simulation results of the internal state (carrier concentration and electric field strength) of the device in the short-circuit state (V CC = 2000 V, 298 K). Additionally, Figure 19 the position at the left end of the horizontal axis of corresponds to the position of the front surface 51a, and the position at the right end of the horizontal axis corresponds to the position of the back surface 51b.

[0091] As Figure 18 shown, in the impurity distributions of the new structure 2-(a) and the new structure 2-(b), in the region where V CC is 1500 - 3500 V, E SC decreases and the SOA of the short-circuit mode narrows. AsFigure 19 As shown by the thin dotted line, in the impurity distributions of the new structures 2-(a) and 2-(b), the electric field strength in the n-buffer layer on the back surface 51b of the IGBT rises to the same level as the electric field strength of the main junction 12 on the front surface 51a. As a result, in the impurity distributions of the new structures 2-(a) and 2-(b), there is an imbalance inside the device in the short-circuit state, so it can be considered that the SOA in the short-circuit mode becomes narrower. Here, the imbalance inside the device in the short-circuit state means a state where the electric field strength of the main junction 12 on the front surface 51a described later is higher than the electric field strength in the n-buffer layer on the back surface 51b.

[0092] On the other hand, as Figure 18 shown, in the impurity distributions of the new structures 1 and 2, as the power supply voltage (V CC ) rises, the maximum cut-off energy (E SC ) in the short-circuit state rises linearly. In addition, as Figure 19 shown, in the impurity distributions of the new structures 1 and 2, even in the short-circuit state, the electric field strength of the main junction 12 on the front surface 51a is higher than the electric field strength in the n-buffer layer on the back surface 51b, and the state of the electric field strength distribution inside the device in the short-circuit state does not become imbalanced. Therefore, the SOA in the short-circuit mode does not become narrower.

[0093] Figure 20 is a graph showing the relationship between the maximum cut-off energy (E Figure 17 ) in the short-circuit state and the depth X2 before the peak of the n-type impurity concentration in the n-type second buffer layer 17 for an IGBT (6.5 kV class) having any one of the SC four impurity distributions. Figure 20 The depth X2 of the peak in the impurity distribution of the new structure 1 is close to the depth of the peak (C － ) of the second-n buffer layer of the n-type drift layer 15. In the semiconductor device according to the third embodiment (semiconductor device having the new structure 2), considering the 2，n relationship, it is configured to satisfy the following formula (6). According to this structure, the dynamic SOA of the IGBT can be ensured. Figure 20 relationship, it is configured to satisfy the following formula (6). According to this structure, the dynamic SOA of the IGBT can be ensured.

[0094] X1 < X2 ≤ 4.0 μm ··· (6)

[0095] In addition, assuming that the maximum peak C2 is a single peak (C 2，0 ) in the impurity distribution of the new structure 2, the relationship of the formula described in the second embodiment can also be satisfied within the range where matching is achieved in the third embodiment.

[0096] <Embodiment 4> In the present Embodiment 4, a method for manufacturing an IGBT according to Embodiments 1 to 3 will be described. Figures 21 to 23 FIG. is a cross-sectional view showing the steps of the manufacturing method of the present Embodiment 4. In the manufacturing method according to the present Embodiment 4, an n-type first buffer layer 16 and an n-type second buffer layer 17 are formed as diffusion layers on a semiconductor substrate 51 including an MCZ wafer, and one or more different acceleration energies and doses are used in the formation of the n-type second buffer layer 17.

[0097] First, as Figure 21 (a) shows, on the front surface 51a side of an n-type drift layer 15 which is a part of the semiconductor substrate 51, a p-type base layer 9 and an n-type layer 11 are formed using ion implantation and annealing. Next, as － (b) shows, on the front surface 51a side of the p-type base layer 9, an n-type emitter layer 7 is formed using ion implantation and annealing. Figure 21 (b) shows, on the front surface 51a side of the p-type base layer 9, an n-type emitter layer 7 is formed using ion implantation and annealing. + type emitter layer 7.

[0098] After that, as Figure 21 (c) shows, a trench 24 penetrating the n-type emitter layer 7 is formed by etching, and the inner wall of the trench 24 is cleaned, smoothed, and chamfered by etching and oxidation. Next, as + (d) shows, a gate oxide film 13 is formed on the inner wall of the trench 24, and a polysilicon film 14a doped with an n-type element (such as arsenic or phosphorus) having a concentration of 1×10 Figure 21 atoms / cm 19 or more is formed on the gate oxide film 13. In addition, 3 above is formed. In addition, Figure 21 (d), a gate oxide film 13 and a polysilicon film 14a are also formed on the back surface 51b side of the semiconductor substrate 51.

[0099] As will be described later, in the step of Figure 21 (e) to Figure 22 (g), in the step of Figure 22 (h), an adsorption layer composed of a polysilicon film 27, a high-concentration n-type layer 28 on the back surface 51b side, and a high crystal defect density layer 29 is formed. The adsorption layer restores the carrier lifetime of the n-type drift layer 15 so that the n-type drift layer 15 has a value above the carrier lifetime calculated by the following formula (7). + type layer 28, and a high crystal defect density layer 29 is formed. The adsorption layer restores the carrier lifetime of the n-type drift layer 15 so that the n-type drift layer 15 has a value above the carrier lifetime calculated by the following formula (7). － type drift layer 15 has a value above the carrier lifetime calculated by the following formula (7). － type drift layer 15 has a value above the carrier lifetime calculated by the following formula (7).

[0100] τ t ≧1.5×10 －5 exp(5.4×10 3 ×t n－ )···(7)

[0101] In addition, t n- [m] is the thickness of the n － -type drift layer 15, which is equivalent to t Figure 2 in device of the device parameters. τ t [sec] is the carrier lifetime in the n － -type drift layer 15 that has no effect on the on-state voltage of the IGBT.

[0102] The on-state voltages of the semiconductor devices (IGBT, diode (a), diode (b)) depend on the carrier lifetime of the n － -type drift layer 15, and Equation (7) represents an index of the carrier lifetime required to minimize this dependence. When τ t satisfies Equation (7), the influence of the carrier lifetime on the switching loss and the loss caused by turn-off can be suppressed. Therefore, a reduction in the loss caused by turn-off and suppression of thermal runaway can be expected.

[0103] Hereinafter, the process will be described in detail starting from Figure 21 (e). First, as shown in Figure 21 (e), the upper part of the polysilicon film 14a on the front surface 51a side is removed to form the gate electrode 14, and the P + -type layer 8 and the interlayer film 6 are formed. Next, as shown in Figure 21 (f), in order to expose the back surface 51b of the semiconductor substrate 51, the gate oxide film 13 and the polysilicon film 14a on the back surface 51b side are removed by wet etching with hydrofluoric acid or a mixed acid (for example, a mixture of hydrofluoric acid / nitric acid / acetic acid).

[0104] After that, as shown in Figure 22 (g), a polysilicon film 27 doped with an n-type element is formed on the front surface 51a and the back surface 51b of the semiconductor substrate 51 by the LPCVD (low-pressure CVD) method. This polysilicon film 27 is used as a source, and this source is used to form Figure 22 the high-concentration n + -type 28 and the high crystal defect density layer 29 shown in + (h). Among the n-type elements (atoms), an element (atom) that can diffuse into Si and form an n 19 -type layer, such as phosphorus, arsenic, or antimony, etc., is used, and this element (atom) is doped into the polysilicon film 27 at a concentration of, for example, 1 × 10 3 atoms / cm

[0105] Next, in a state where the back surface 51b of the semiconductor substrate 51 is directly in contact with the polysilicon film 27 doped with high-concentration impurities of an n-type element, annealing is performed at 900 to 1000 °C in a nitrogen atmosphere. After that, the temperature is decreased to 500 to 700 °C at an arbitrary cooling rate, and annealing at a temperature lower than the previous annealing temperature is performed in a nitrogen atmosphere.

[0106] As Figure 22 (h) shows, through this annealing, the high-concentration impurities in the polysilicon film 27 diffuse into the back surface 51b of the semiconductor substrate 51 directly in contact with the polysilicon film 27, forming a high-concentration n + -type layer 28. In the high-concentration n + -type layer 28, the surface impurity concentration is, for example, 1.0×10 20 ~1.0×10 22 atoms / cm 3 , and the depth from the back surface 51b is, for example, 1.0 to 10 μm.

[0107] While forming the high-concentration n + -type layer 28, a high crystal defect density layer 29 introducing a high density of dislocations and lattice defects is secondarily formed below the n - -type drift layer 15. In addition, in a state where the polysilicon film 27 and the back surface 51b of the semiconductor substrate 51 with different coefficients of thermal expansion are directly in contact, the above annealing is performed, so that strain is generated in the surface layer portion of the polysilicon film 27 and the high-concentration n + -type layer 28 as the Si junction. As a result, the high-concentration n + -type layer 28 including the Si junction, the high crystal defect density layer 29, and the polysilicon film 27 become adsorption sites. As a result, during the above annealing, heavy metals and contaminant atoms absorbed by the semiconductor substrate 51 diffuse into the lattice and are trapped at the adsorption sites.

[0108] By trapping heavy metals and contaminant atoms at the adsorption sites, the carrier lifetime of the n - -type drift layer 15 that decreased in the previous wafer process can be restored as shown in Equation (7). That is, the carrier lifetime of the n - -type drift layer 15 can be made long enough so that the carrier lifetime of the n - -type drift layer 15 does not affect the electrical characteristics and even the carrier lifetime of IGBTs with various breakdown voltage ratings.

[0109] In addition, since the front surface 51a of the semiconductor substrate 51 is not directly in contact with the polysilicon film 27 through the interlayer film 6, an adsorption layer including the polysilicon film 27, the high-concentration n + -type layer 28, and the high crystal defect density layer 29 is not formed on the front surface 51a side of the semiconductor substrate 51.

[0110] Instead of using the polysilicon film 27 to form the high crystal defect density layer 29, a laser with a wavelength of 500 to 1000 nm can be used, and a laser annealing capable of rapid heating / rapid cooling and local annealing is used to form the high crystal defect density layer 29 on the semiconductor substrate 51. The power density of the laser annealing is, for example, 4 J / cm 2 or more. After the laser annealing, the same annealing as described above is performed. That is, annealing is performed at 900 to 1000 °C and in a nitrogen atmosphere, and then the temperature is set to 500 to 700 °C at an arbitrary cooling rate, and annealing at a temperature lower than the previous annealing temperature is performed in a nitrogen atmosphere. In this case, heavy metals and contaminant atoms absorbed by the semiconductor substrate 51 diffuse into the lattice and are trapped by the adsorption layer. As a result, the carrier lifetime of the n - -type drift layer 15 can be restored.

[0111] As described above, the adsorption layer including the polysilicon film 27, the high-concentration n + -type layer 28, and the high crystal defect density layer 29 is removed before the process of forming the n-type first buffer layer 16, the n-type second buffer layer 17, and the p-type collector layer 18 Figure 23 (m). Figure 23 (l).

[0112] As Figure 22 (i) shows, the polysilicon film 27 on the front side 51a of the semiconductor substrate 51 is removed by etching. Next, as Figure 22 (j) shows, the interlayer film 6 is patterned. Figure 22 In (j), a part of the gate electrode 14 is exposed from the interlayer film 6, but all the gate electrodes 14 can also be covered by the interlayer film 6.

[0113] As Figure 23 (k) shows, a silicide layer 30a, a barrier metal layer 30b, and a first electrode 5 are sequentially formed on the front side 51a of the semiconductor substrate 51 and on the interlayer film 6. In addition, the gate electrode 14 exposed from the interlayer film 6 and connected to the first electrode 5 becomes a dummy electrode 41. That is, Figure 23 in the example of (k), the trench electrode provided in the trench 24 includes the gate electrode 14 and the dummy electrode 41. By the process up to Figure 23 (k), an n-type semiconductor substrate 51 is formed, which has a front side 51a provided with the first electrode 5 and a back side 51b opposite to the front side 51a.

[0114] As Figure 23 (l) shows, after forming the protective film 31 on the first electrode 5, the polysilicon film 27, the high-concentration n + -type layer 28, and the high crystal defect density layer 29 are removed by polishing and wet etching. For example, Figure 2 the device thickness (tdevice ) is set to 40 to 700 μm. In addition, after the process of Figure 23 (l), the carrier lifetime of the n - -type drift layer 15 also satisfies Equation (7).

[0115] As Figure 23 (m) shows, an n-type first buffer layer 16, an n-type second buffer layer 17, and a p-type collector layer 18 are formed on the back surface 51b, and the protective film 31 is removed. Thus, a vertical structure is formed on the back surface 51b side. On the front surface 51a where no vertical structure is formed, there already exists a trench structure of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) included in the IGBT, and there already exist a first electrode 5 and an interlayer film 6, etc. Therefore, when forming the n-type first buffer layer 16, the n-type second buffer layer 17, and the p-type collector layer 18 that constitute the vertical structure, it is important to keep the temperature of the first electrode 5 on the front surface 51a lower than the melting point of the metal of the first electrode 5 (for example, the melting point of aluminum is 660 °C). To achieve this, laser annealing can be performed using a laser having a temperature gradient in the depth direction of the semiconductor substrate 51 and a wavelength at which heat is not easily transferred to the front surface 51a, or annealing in a diffusion furnace at a low temperature below the metal melting point can be used.

[0116] Hereinafter, a method for manufacturing the IGBT described in Embodiments 1 and 2 by performing the process of Figure 23 (l) and then Figure 23 (m) will be mainly described. In the IGBTs described in Embodiments 1 and 2, the n-type second buffer layer 17 is sequentially provided from the n-type first buffer layer 16 toward the n - -type drift layer 15 and includes a second-1 buffer layer to a second-n buffer layer having C 2,1 ~C 2,n as the peak of the n-type impurity concentration.

[0117] In such a method for manufacturing an IGBT, it is important to control point defects and composite defects in the second-1 buffer layer to the second-n buffer layer, and to form the second-1 buffer layer without disturbing the n-type first buffer layer 16 and the second-1 buffer layer. To achieve this, as described below, the formation order of the n-type first buffer layer 16 and the n-type second buffer layer 17, and the setting of the peak position of the acceleration energy during ion implantation of the second-1 buffer layer to the second-n buffer layer become important.

[0118] Figure 24 shows the process of forming the structure on the back surface 51b side in the manufacturing method according to the present Embodiment 4, that is, Figure 23 (l) andFigure 23 (m) Process flow chart. First, in step S1, as Figure 23 (l), a protective film 31 is formed on the first electrode 5. Through the polishing in step S2 and the etching in step S3, the polysilicon film 27, the high-concentration n + -type layer 28 and the high-crystal-defect-density layer 29 are removed, and Figure 2 the device thickness (t device ) is set to, for example, 40 to 700 μm.

[0119] In step S4, the first ion implantation is performed on the side closer to the back surface 51b of the n - -type drift layer 15. In step S5, through the first annealing of the first ions, an n-type first buffer layer 16 is formed as Figure 23 (m). The first ions include, for example, arsenic or phosphorus.

[0120] In step S6, the second ions are implanted between the n-type first buffer layer 16 and the n - -type drift layer. The second ions include protons (H + ). In addition, the implantation of protons can use a cyclotron instead of a general ion implantation.

[0121] In this step S6, protons (second ions) are introduced between the n-type first buffer layer 16 and the n - -type drift layer with more than one different acceleration energy and dose. For example, protons (second ions) are implanted in the order from high to low acceleration energy, so that the dose of the protons implanted with the first acceleration energy is lower than the dose of the protons implanted with the second acceleration energy lower than the first acceleration energy. Thus, the protons are implanted in the order from the protons of the second-n buffer layer on the n - -type drift layer 15 side to the protons of the second-1 buffer layer on the n-type first buffer layer 16 side, and the dose of the protons increases. As a result, when annealing the protons (second ions), an n-type second buffer layer 17 including the second-1 buffer layer to the second-n buffer layer can be formed.

[0122] In addition, the peak of the second-1 buffer layer in contact with the n-type first buffer layer 16 is set to be on the side of the junction (X j,n1 ) of the n-type first buffer layer 16 and the second-1 buffer layer and closer to the junction (X - ) of the n j,n2n -type drift layer 15 and the second-n buffer layer. Thus, the interference between the n-type first buffer layer 16 and the second-1 buffer layer is suppressed, and the second-1 buffer layer can be formed with high precision. In addition, in the case of manufacturing the IGBT according to Embodiment 3, it is only necessary to introduce protons (second ions) with one different acceleration energy and dose.

[0123] Thus, if annealing of protons (the second ions) is performed after step S6, an n-type second buffer layer 17 can be formed. However, it is assumed that the first annealing in step S5 for forming the n-type first buffer layer 16 and the second annealing in step S10 for forming a p-type collector layer 18 described later are at a higher temperature than the third annealing temperature for activating the n-type second buffer layer 17. Therefore, if annealing at a temperature higher than the third annealing temperature is performed after the third annealing, it will have an adverse effect on the impurity distribution of the HDs layer and the types of point defects and composite defects in the n-type second buffer layer 17 introduced for forming the n-type second buffer layer 17. As a result, it will have an adverse effect on the carriers (electrons or holes) in the on state of the device.

[0124] Therefore, in the fourth embodiment, the third annealing (step S12) for forming the n-type second buffer layer 17 is performed after the first annealing (step S5) for forming the n-type first buffer layer 16 and the second annealing (step S10) for forming the p-type collector layer 18.

[0125] If protons (the second ions) are introduced in step S6 and the third annealing is performed in step S12, the HDs layer is formed as in the following steps A1 to A4. First, in step A1, holes (v) and lattice Si pairs (I Si ) are generated by introducing protons into Si. In step A2, the lattice Si pairs aggregate at room temperature to generate W centers (I Si3 clusters) as point defects. In step A3, through the third annealing, the lattice Si pairs aggregate again to generate X centers (I Si4 clusters) as point defects. In step A4, the hydrogen introduced by the protons reacts with the W centers (I Si3 clusters) and the X centers (I Si4 clusters) to produce donor-type composite defects, thereby forming the HDs layer.

[0126] When the HDs layer is formed on the semiconductor substrate 51 using an MCZ wafer, the thermal donorization phenomenon caused by oxygen in Si is applied to form the final n-type second buffer layer 17. When an FZ wafer is used for the semiconductor substrate 51, the HDs layer directly becomes the n-type second buffer layer 17. As a result, an n layer doped with an impurity concentration higher than that of the n - type drift layer 15 serves as the n-type second buffer layer 17 and contributes to the operation of the device. In the fourth embodiment, an MCZ wafer is used, so the composite defects formed in the n-type second buffer layer 17 are utilized to improve the device performance.

[0127] In addition, among the composite defects formed in the n-type second buffer layer 17, there are also defects that become lifetime killers that reduce the carrier lifetime. Therefore, in the fourth embodiment, as Figure 24As shown, after the formation of the n-type first buffer layer 16 (step S5), the second ion implantation (step S6) and the third annealing (step S12) of the n-type second buffer layer 17 are performed. According to such a manufacturing method, the composite defects in the n-type second buffer layer 17 can be controlled. Therefore, the defects that become lifetime killers can be eliminated, and the distribution of the n-type second buffer layer 17 can be stabilized.

[0128] In step S7, photolithography is performed, and the photoresist patterned on the back surface 51b is used as a mask to form. In step S8, the third ion implantation is performed on the back surface 51b side of the n-type first buffer layer 16 exposed from the mask. The third ion contains boron, for example. The photoresist is removed in step S9. In addition, when it is not necessary to locally form the p-type collector layer 18, the processes of steps S7 and S9 can be deleted. In step S10, a semiconductor layer including the p-type collector layer 18 is formed by performing the second annealing of boron (the third ion). In the second annealing, for example, the same annealing as the first annealing process is performed. In step S11, the protective film 31 on the first electrode 5 is removed.

[0129] In step S12, the n-type second buffer layer 17 is formed by performing the third annealing of protons (the second ion). As the third annealing for donorizing the n-type second buffer layer 17, annealing is performed on protons (the second ion) for a time of 90 minutes or more at a temperature of 375 °C or higher and 425 °C or lower. In the third annealing, an annealing different from the first annealing process is performed.

[0130] In step S13, photoetching is performed on the back surface 51b of the semiconductor substrate 51. In step S14, a metal film serving as the second electrode 21 is formed on the back surface 51b of the semiconductor substrate 51 by sputtering. The metal film is, for example, an AlSi film with a Si addition amount of 1 to 3%. In step S15, the second electrode 21 is formed by performing the fourth annealing for forming an alloy layer or a silicide layer between the back surface 51b of the semiconductor substrate 51 and the metal film. The temperature of the fourth annealing is, for example, a temperature lower than the third annealing, for example, less than 375 °C.

[0131] As described above, the IGBTs according to Embodiments 1 to 3 are completed. In addition, when the maximum value of the oxygen concentration of the semiconductor substrate 51 is set to maximum[O i , the formula (1) is satisfied. In addition, regarding the carrier lifetime, between the n - -type drift layer 15, the n-type first buffer layer 16, and the n-type second buffer layer 17, the following formula (8) is satisfied.

[0132] τ2 < τ1 ≦ τ t ··· (8)

[0133] In addition, τ2 is the carrier lifetime of the n-type second buffer layer 17, and τ1 is the carrier lifetime of the n-type first buffer layer 16. τ2 is the carrier lifetime of the n- － type drift layer 15, which has no effect on the conduction voltage of the IGBT (i.e., the conduction voltage of the gate electrode).

[0134] According to the manufacturing method of the semiconductor device according to the fourth embodiment as described above, the IGBTs according to the first to third embodiments can be formed. In addition, in the fourth embodiment, an n-type second buffer layer 17 can be formed, which is composed of an MCZ wafer made of Si with a relatively high oxygen concentration, contains an HDs layer through the third annealing of protons (second ions), and undergoes a heat donor phenomenon to obtain it. In addition, in the fourth embodiment, the formation order of the n-type first buffer layer 16 and the n-type second buffer layer 17, and the setting of the peak position of the acceleration energy during ion implantation of the second-1 buffer layer to the second-n buffer layer are optimized. Therefore, point defects and composite defects in the second-1 buffer layer to the second-n buffer layer can be controlled, and interference between the n-type first buffer layer 16 and the second-1 buffer layer can be suppressed.

[0135] <Embodiment 5> In the fifth embodiment, the manufacturing methods of the diodes (a) and (b) according to the first to third embodiments will be described. Figures 25 to 27 FIG. is a cross-sectional view showing the steps of the manufacturing method of the fifth embodiment, specifically, a cross-sectional view showing the steps of the manufacturing method of the diode (b). In the fifth embodiment, similar to the fourth embodiment, an n-type first buffer layer 16 and an n-type second buffer layer 17 are also formed on a semiconductor substrate 51 including an MCZ wafer. In the formation of the n-type second buffer layer 17, one or more different acceleration energies and doses are used.

[0136] First, as Figure 25 (a) shows, photolithography and photoresist removal are performed on the front surface 51a of the semiconductor substrate 51 to form a patterned oxide film 33. After that, a thin oxide film 34 is formed by re-oxidation, and ion implantation, photolithography, photoresist removal, and annealing are used to form a p-type layer 32 on the front surface 51a side of the n- - type drift layer 15 in the terminal region 3. Then, as Figure 25 (b) shows, ion implantation, photolithography, photoresist removal, and annealing are used to form a p-type anode layer 10 on the front surface 51a side of the n- - type drift layer 15 in the active region 1. After that, as Figure 25 (c) shows, a part of the oxide film 33 in the terminal region 3 is removed, and ion implantation, photolithography, photoresist removal, and annealing are used to form an n- +Type layer 35. After that, after forming an interlayer film 6 such as an oxide film on the front surface 51a, a polysilicon film 27 described in Embodiment 4 is formed on the front surface 51a side and the back surface 51b side.

[0137] Next, annealing is performed at 900 to 1000 °C in a nitrogen atmosphere. After that, the temperature is set to 500 to 700 °C at an arbitrary cooling rate, and annealing at a temperature lower than the previous annealing temperature is performed in a nitrogen atmosphere. Thus, as Figure 26 (d) shows, an adsorption layer is formed on the back surface 51b side, which includes a high-concentration n + -type layer 28 containing Si junctions, a high crystal defect density layer 29, and a polysilicon film 27. As a result, similar to the n - -type drift layer 15 related to Embodiment 4, the n - -type drift layer 15 related to this Embodiment 5 also recovers the carrier lifetime and satisfies Equation (7).

[0138] Then, as Figure 26 (e) shows, the polysilicon film 27 on the front surface 51a side is removed by etching. Next, as Figure 26 (f) shows, the interlayer film 6 and the like are patterned, and the first electrode 5 is formed on the exposed p-type anode layer 10, p-type layer 32, and n + -type layer 35, and on the interlayer film 6. In addition, similar to Figure 23 (k), an adsorption layer 30a and a barrier metal layer 30b can be provided.

[0139] Next, as Figure 27 (g) shows, a passivation film 36 is formed on the first electrode 5. Then, as Figure 27 (h) shows, after forming a protective film 31 on the first electrode 5, the polysilicon film 27, the high-concentration n + -type layer 28, and the high crystal defect density layer 29 are removed by polishing and wet etching. Then, as Figure 27 (i) shows, an n-type first buffer layer 16, an n-type second buffer layer 17, an n + -type cathode layer 19, and a p-type cathode layer 20 are formed on the back surface 51b, and the protective film 31 is removed.

[0140] Figure 28 is a flowchart showing the steps of forming the structure on the back surface 51b side in the manufacturing method related to this Embodiment 5 of the diode (b), that is, Figure 27 (h) and Figure 27 (i). Figure 28 The steps of Figure 24 are the same as the steps after adding step S21 to the steps of

[0141] In step S21 between step S6 and step S7, a third ion containing, for example, boron is implanted on the back surface 51b side of the n-type first buffer layer 16. In step S8a after step S7, a third ion containing, for example, arsenic or phosphorus is implanted on the back surface 51b side of the n-type first buffer layer 16 exposed from the mask. In addition, the third ions in step 8a and the third ions in step S21 form a semiconductor layer connected to the second electrode 21, but the conductivity type of the third ions in step 8a is different from that of the third ions in step S21. After step S9, in step S10a, by performing a second annealing of the third ions, a semiconductor layer including an n + -type cathode layer 19 and a p-type cathode layer 20 is formed.

[0142] Figure 29 FIG. is a flowchart showing a process of forming a structure on the back surface 51b side in the manufacturing method according to Embodiment 5 of the diode (a). Figure 29 The process of Figure 28 is the same as the process after deleting step S21 and changing step S10a to step S10b for + . If the second annealing of the third ions is performed in step S10b, a semiconductor layer including an n + -type cathode layer 19 but not including the p-type cathode layer 20 is formed. In addition, when it is not necessary to locally form the n

[0143] -type cathode layer 19, the processes of step S7 and step S9 can be deleted.

[0144] <Embodiment 6> In the semiconductor devices according to Embodiments 1 to 3, an IGBT or a diode is provided in the active region 1 of the semiconductor substrate 51, but both an IGBT and a diode can be provided in the active region 1 of the same semiconductor substrate 51.

[0145] Figures 30 to 37This is a cross-sectional view showing the configuration of the semiconductor device according to Embodiment 6 of the present invention. The semiconductor device according to Embodiment 6 is an RC-IGBT (Reverse Conducting-IGBT), which includes an IGBT and a diode provided on the same semiconductor substrate 51 and has a trench gate structure. The semiconductor substrate 51 of the RC-IGBT defines an IGBT region 52a that functions as an IGBT and a diode region 52b that functions as a diode.

[0146] In the IGBT region 52a, the same structure as the IGBTs according to Embodiments 1 to 3 including an n-type first buffer layer 16, an n-type second buffer layer 17, and a p-type collector layer 18 is provided. In the diode region 52b, similar to the diode (a) or diode (b) according to Embodiments 1 to 3, both an n-type first buffer layer 16 and an n-type second buffer layer 17, an + n-type cathode layer 19 and a p-type cathode layer 20, or an + n-type cathode layer 19 are provided.

[0147] Figure 30 In the diode region 52b of, the same structure as the diode (a) according to Embodiments 1 to 3 is provided, which includes an + n-type cathode layer 19 and does not include a p-type cathode layer 20. In addition, a p-type layer 8 having a higher p-type impurity concentration than the p-type anode layer 10 is provided between the first electrode 5 and the p-type anode layer 10. + The structure of is the same as the structure obtained by deleting the p-type layer 8 from the structure of, and the p-type anode layer 10 is in contact with the first electrode 5. According to the

[0148] Figure 31 structure, compared with the Figure 30 structure, the hole injection efficiency starting from the p-type anode layer 10 in the on-state of the diode can be reduced. + The structure of is the same as the structure obtained by deleting the p-type layer 8 from the structure of, and the p-type anode layer 10 is in contact with the first electrode 5. According to Figure 31 the structure, compared with the Figure 30 structure, the hole injection efficiency starting from the p-type anode layer 10 in the on-state of the diode can be reduced.

[0149] Figure 32 In the diode region 52b of, the same structure as the diode (b) according to Embodiments 1 to 3 is provided, which includes both an + n-type cathode layer 19 and a p-type cathode layer 20. In addition, a p-type layer 8 having a higher p-type impurity concentration than the p-type anode layer 10 is provided between the first electrode 5 and the p-type anode layer 10. + The structure of is the same as the structure obtained by deleting the p-type layer 8 from the structure of, and the p-type anode layer 10 is in contact with the first electrode 5. According to

[0150] Figure 33 the structure, compared with the Figure 32 structure, the hole injection efficiency starting from the p-type anode layer 10 in the on-state of the diode can be reduced. + the structure, compared with theFigure 33 The structure, compared with Figure 32 the structure, can reduce the hole injection efficiency from the p-type anode layer 10 in the on-state of the diode. In addition, according to Figure 32 and Figure 33 the structure, through the p-type cathode layer 20, compared with Figure 30 and Figure 31 the structure, can reduce the electron injection efficiency from the back surface 51b in the on-state of the diode.

[0151] Compared with Figure 30 the RC-IGBT, Figures 31 to 33 the RC-IGBT can suppress the hole injection efficiency from the p-type base layer or the electron injection efficiency from the back surface 51b in the on-state of the diode. Therefore, it is possible to suppress the high-speed part of the curve representing the trade-off characteristics between the turn-off loss (E REC ) and the on-state voltage (V F ) of the diode gate region 52b (the part with low E REC and high V F ) from depending on the carrier lifetime control of charged particles such as electron beams. In particular, by performing carrier lifetime control based on charged particles, the adverse effects of impurities such as oxygen and carbon in the MCZ wafer on the diode performance become significant. Therefore, in the case where the semiconductor substrate 51 is an MCZ wafer, the structure of REC and F that can suppress the performance of the high-speed part of the curve representing the trade-off characteristics between E Figures 31 to 33 from depending on the carrier lifetime control is effective.

[0152] Figures 34 to 37 In the structure of Figures 30 to 33 the structure, the trench electrode in a part of the trench 24 is electrically connected to the first electrode 5, thereby becoming a virtual electrode 41 having the same emitter potential as the first electrode 5. According to this structure, by suppressing the saturation current density of the IGBT region 52a and controlling the capacitance characteristics, it is possible to suppress the oscillation in the no-load short-circuit state, and thus, it is possible to achieve an improvement in short-circuit withstand capacity and a decrease in the on-state voltage based on an increase in the carrier concentration on the emitter side.

[0153] According to the sixth embodiment as described above, it includes the IGBTs according to Embodiments 1 to 3 and the diode (a) or diode (b) according to Embodiments 1 to 3. According to this structure, for example, similar to Embodiment 1 and the like, for example, in the RC-IGBT, while having sufficient withstand voltage holding ability in the off-state, it is possible to achieve normal on-operation and an improvement in the breakdown withstand capacity during dynamic operation.

[0154] <Variation> In the above description, the semiconductor substrate 51 is made of silicon, but it is not limited thereto. For example, the semiconductor substrate 51 may be made of a wide-bandgap semiconductor such as silicon carbide (SiC). When the semiconductor substrate 51 is made of a wide-bandgap semiconductor, stable operation at high temperatures and high voltages, as well as high-speed switching speed, can be achieved. In addition, a MOSFET may be provided instead of the IGBT, and the diode may also be an SBD (Schottky Barrier Diode) or a PND (PN junction diode).

[0155] In addition, the respective embodiments and respective modification examples can be freely combined, and the respective embodiments and respective modification examples can be appropriately deformed and omitted.

[0156] Hereinafter, the respective aspects of the present disclosure will be summarized and described as appended notes.

[0157] (Appended Note 1) A semiconductor device, comprising: A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; and A first electrode and a second electrode respectively provided on the first main surface and the second main surface, The semiconductor substrate includes: A drift layer of a first conductivity type provided between the first main surface and the second main surface; A semiconductor layer connected to the second electrode and including at least one of a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type; A first buffer layer of a first conductivity type provided between the semiconductor layer and the drift layer; and A second buffer layer of a first conductivity type provided between the first buffer layer and the drift layer, the impurity concentration of the first conductivity type being smaller than that of the first buffer layer and larger than that of the drift layer, When the maximum value of the oxygen concentration of the semiconductor substrate calculated using the conversion coefficient of the old ASTM is set as maximum[O i , and the impurity concentration of the first conductivity type of the drift layer is set as C drift , the following is satisfied maximum[O i = 9.40×10 16 ×ln(C drift ) - 2.2 7×10 18 .

[0158] (Supplementary Note 2) The semiconductor device as described in Supplementary Note 1, the second buffer layer includes a second - 1 buffer layer to a second - n buffer layer, which are sequentially arranged from the first buffer layer toward the drift layer and have C 2,1 to C 2,n as the peak of the impurity concentration of the first conductivity type, and satisfy C 2，n <···<C 2，2 <C 2，1 .

[0159] (Supplementary Note 3) The semiconductor device as described in Supplementary Note 1 or 2, when the maximum peak of the impurity concentration of the first conductivity type of the second buffer layer is set to C2, it satisfies C drift <C2≦1.0×10 15 cm －3 .

[0160] (Supplementary Note 4) The semiconductor device as described in any one of Supplementary Notes 1 to 3, when the maximum peak of the impurity concentration of the first conductivity type of the first buffer layer is set to C1 and the maximum peak of the impurity concentration of the first conductivity type of the second buffer layer is set to C2, it satisfies 1.0×10 －4 ≦C2 / C1≦1.0×10 －1 .

[0161] (Supplementary Note 5) The semiconductor device as described in Supplementary Note 1, the second buffer layer is a single layer, when the depth of the peak of the impurity concentration of the first conductivity type of the first buffer layer from the second main surface is set to X1 and the depth of the peak of the impurity concentration of the first conductivity type of the second buffer layer from the second main surface is set to X2, it satisfies X1<X2≦4.0μm.

[0162] (Supplementary Note 6) The semiconductor device as described in any one of Supplementary Notes 1 to 5, the maximum peak of the impurity concentration of the first conductivity type of the second buffer layer is less than the maximum peak of the impurity concentration of the first conductivity type of the first buffer layer.

[0163] (Supplementary Note 7) The semiconductor device as described in any one of Supplementary Notes 1 to 6, the impurity of the first conductivity type in the drift layer contains antimony.

[0164] (Supplementary Note 8) The semiconductor device as described in any one of Supplementary Notes 1 to 7, The semiconductor substrate further includes: a base layer of a second conductivity type disposed closer to the first main surface side than the drift layer; and an emitter layer of a first conductivity type disposed closer to the first main surface side than the base layer, a trench electrode including a gate electrode is disposed in a trench penetrating the base layer and the emitter layer, the semiconductor layer includes the second semiconductor layer connected to the second electrode.

[0165] (Supplementary Note 9) The semiconductor device according to Supplementary Note 1, setting the carrier lifetime of the drift layer that has no effect on the conduction voltage as τ t , setting the carrier lifetime of the first buffer layer as τ1, and setting the carrier lifetime of the second buffer layer as τ2. In this case, the following is satisfied τ2 < τ1 ≤ τ t .

[0166] (Supplementary Note 10) The semiconductor device according to any one of Supplementary Notes 1 to 6, the semiconductor substrate further includes an anode layer of a second conductivity type, and the anode layer of the second conductivity type is disposed closer to the first main surface side than the drift layer, the semiconductor layer includes the first semiconductor layer connected to the second electrode.

[0167] (Supplementary Note 11) The semiconductor device according to any one of Supplementary Notes 1 to 6, the semiconductor substrate further includes an anode layer of a second conductivity type, and the anode layer of the second conductivity type is disposed closer to the first main surface side than the drift layer, the semiconductor layer includes the first semiconductor layer and the second semiconductor layer connected to the second electrode.

[0168] (Supplementary Note 12) A semiconductor device includes: a first semiconductor device, which is the semiconductor device described in Supplementary Note 8; and a second semiconductor device, which is disposed on the semiconductor substrate provided with the first semiconductor device and is the semiconductor device described in Supplementary Note 10.

[0169] (Supplementary Note 13) A semiconductor device includes: a first semiconductor device, which is the semiconductor device described in Supplementary Note 8; and a second semiconductor device, which is disposed on the semiconductor substrate provided with the first semiconductor device and is the semiconductor device described in Supplementary Note 11.

[0170] (Supplementary Note 14) The semiconductor device as described in Supplementary Note 12 or 13, The semiconductor substrate of the second semiconductor device further includes an impurity diffusion layer of a second conductivity type, which is disposed between the first electrode and the anode layer, and the impurity concentration of the second conductivity type is higher than that of the anode layer.

[0171] (Supplementary Note 15) The semiconductor device as described in any one of Supplementary Notes 12 to 14, The anode layer is in contact with the first electrode.

[0172] (Supplementary Note 16) The semiconductor device as described in any one of Supplementary Notes 12 to 15, The trench electrode further includes a virtual electrode, which is electrically connected to the first electrode.

[0173] (Supplementary Note 17) The semiconductor device as described in any one of Supplementary Notes 1 to 16, The impurity of the first conductivity type in the first buffer layer contains arsenic or phosphorus, The impurity of the first conductivity type in the second buffer layer contains protons.

[0174] (Supplementary Note 18) A method for manufacturing a semiconductor device, including: A step of preparing a semiconductor substrate of a first conductivity type having a first main surface provided with a first electrode and a second main surface opposite to the first main surface; A step of forming a first buffer layer of a first conductivity type by implanting a first ion on a side closer to the second main surface than a drift layer which is a part of the semiconductor substrate and annealing the first ion; A step of implanting a second ion between the first buffer layer and the drift layer; A step of implanting a third ion on the second main surface side of the first buffer layer; A step of forming a semiconductor layer including at least one of a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type by annealing the third ion; A step of forming a second buffer layer of a first conductivity type having an impurity concentration of the first conductivity type smaller than that of the first buffer layer and larger than that of the drift layer by annealing the second ion; and A step of forming a second electrode on the second main surface, When the maximum value of the oxygen concentration of the semiconductor substrate calculated using the conversion coefficient of the old ASTM is set as maximum[O i , and the impurity concentration of the first conductivity type of the drift layer is set as C drift , it satisfies maximum[O i = 9.40×10 16 ×ln(C drift ) - 2.27×10 18 。

[0175] (Note 19) The manufacturing method of the semiconductor device as described in Note 18, The semiconductor layer includes the first semiconductor layer.

[0176] (Note 20) The manufacturing method of the semiconductor device as described in Note 18, The semiconductor layer includes the second semiconductor layer.

[0177] (Note 21) The manufacturing method of the semiconductor device as described in Note 18, The semiconductor layer includes the first semiconductor layer and the second semiconductor layer.

[0178] (Note 22) The manufacturing method of the semiconductor device as described in any one of Notes 18 to 21, The second ions are implanted in the order of decreasing acceleration energy, The dose of the second ions implanted with the first acceleration energy is lower than the dose of the second ions implanted with a second acceleration energy lower than the first acceleration energy.

[0179] (Note 23) The manufacturing method of the semiconductor device as described in any one of Notes 18 to 22, The first ions include arsenic or phosphorus, The second ions include protons.

[0180] (Note 24) The manufacturing method of the semiconductor device as described in any one of Notes 18 to 23, The second ions are annealed for 90 minutes or more at a temperature of 375 °C or higher and 425 °C or lower.

[0181] (Note 25) The manufacturing method of the semiconductor device as described in any one of Notes 18 to 24, The semiconductor substrate includes a semiconductor wafer made by the MCZ method.

[0182] (Note 26) The manufacturing method of the semiconductor device as described in any one of Notes 18 to 25, The semiconductor substrate includes antimony as an impurity of the first conductivity type. Reference numeral description

[0183] 5 The first electrode 7n + -type emitter layer 8p + type layer 9 p-type base layer 10 p-type anode layer 14 gate electrode 15n - type drift layer 16n-type first buffer layer 17n-type second buffer layer 18p-type collector layer 19n + type cathode layer 20 p-type cathode layer 24 trench 21 second electrode 41 dummy electrode 51 semiconductor substrate 51a front side 51b back side.

Claims

1. A semiconductor device, characterized in that, Comprising: A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; And A first electrode and a second electrode, the first electrode and the second electrode being disposed on the first main surface and the second main surface respectively, The semiconductor substrate includes: A drift layer of a first conductivity type, the drift layer of the first conductivity type being disposed between the first main surface and the second main surface; A semiconductor layer connected to the second electrode and including at least one of a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type; A first buffer layer of a first conductivity type, the first buffer layer of the first conductivity type being disposed between the semiconductor layer and the drift layer; and A second buffer layer of a first conductivity type, the second buffer layer of the first conductivity type being disposed between the first buffer layer and the drift layer, the impurity concentration of the first conductivity type being smaller than that of the first buffer layer and larger than that of the drift layer, When the maximum value of the oxygen concentration of the semiconductor substrate calculated using the conversion coefficient of the old ASTM is set to maximum[O i , and the impurity concentration of the first conductivity type of the drift layer is set to C drift , the following is satisfied maximum[O i = 9.40×10 16 ×ln(C drift ) - 2.2 7×10 18 。 2. The semiconductor device according to claim 1, wherein The second buffer layer includes a second-1 buffer layer to a second-n buffer layer, which are sequentially arranged from the first buffer layer toward the drift layer and have C 2,1 ~C 2,n as the peak value of the impurity concentration of the first conductivity type and satisfy C 2，n < ··· < C 2，2 < C 2，1 。 3. The semiconductor device according to claim 1 or 2, wherein When the maximum peak value of the impurity concentration of the first conductivity type of the second buffer layer is set as C2, it satisfies C drift <C2 ≤ 1.0 × 10 15 cm －3 。 4. The semiconductor device according to any one of claims 1 to 3, wherein When the maximum peak value of the impurity concentration of the first conductivity type of the first buffer layer is set as C1 and the maximum peak value of the impurity concentration of the first conductivity type of the second buffer layer is set as C2, it satisfies 1.0×10 －4 ≦ C2 / C1 ≦ 1.0×10 －1 。 5. The semiconductor device according to claim 1, wherein The second buffer layer is a single layer, When the depth of the peak value of the impurity concentration of the first conductivity type of the first buffer layer from the second main surface is set as X1 and the depth of the peak value of the impurity concentration of the first conductivity type of the second buffer layer from the second main surface is set as X2, it satisfies X1 < X2 ≦ 4.0 μm.

6. The semiconductor device according to any one of claims 1 to 5, wherein The maximum peak value of the impurity concentration of the first conductivity type of the second buffer layer is less than the maximum peak value of the impurity concentration of the first conductivity type of the first buffer layer.

7. The semiconductor device according to any one of claims 1 to 6, wherein The impurity of the first conductivity type of the drift layer contains antimony.

8. The semiconductor device according to any one of claims 1 to 7, wherein The semiconductor substrate further includes: A base layer of a second conductivity type disposed closer to the first main surface side than the drift layer; and An emitter layer of a first conductivity type disposed closer to the first main surface side than the base layer, A trench electrode including a gate electrode is disposed in a trench penetrating the base layer and the emitter layer, The semiconductor layer includes the second semiconductor layer connected to the second electrode.

9. The semiconductor device according to claim 1, wherein Let the carrier lifetime of the drift layer that has no effect on the turn-on voltage be τ t , let the carrier lifetime of the first buffer layer be τ1, and let the carrier lifetime of the second buffer layer be τ2. In this case, it satisfies τ2 < τ1 ≤ τ t .

10. The semiconductor device according to any one of claims 1 to 6, wherein The semiconductor substrate further includes an anode layer of a second conductivity type, and the anode layer of the second conductivity type is disposed closer to the first main surface side than the drift layer. The semiconductor layer includes the first semiconductor layer connected to the second electrode.

11. The semiconductor device according to any one of claims 1 to 6, wherein The semiconductor substrate further includes an anode layer of a second conductivity type, and the anode layer of the second conductivity type is disposed closer to the first main surface side than the drift layer. The semiconductor layer includes the first semiconductor layer and the second semiconductor layer connected to the second electrode.

12. A semiconductor device, characterized in that, Comprising: A first semiconductor device, which is the semiconductor device described in claim 8; And A second semiconductor device, which is disposed on the semiconductor substrate provided with the first semiconductor device and is the semiconductor device described in claim 10.

13. A semiconductor device, characterized in that, Comprising: A first semiconductor device, which is the semiconductor device described in claim 8; And A second semiconductor device, which is disposed on the semiconductor substrate provided with the first semiconductor device and is the semiconductor device described in claim 11.

14. The semiconductor device according to claim 12 or 13, wherein The semiconductor substrate of the second semiconductor device further includes a second-conductivity-type impurity diffusion layer, which is disposed between the first electrode and the anode layer, and the impurity concentration of the second conductivity type is higher than that of the anode layer.

15. The semiconductor device according to any one of claims 12 to 14, wherein The anode layer is in contact with the first electrode.

16. The semiconductor device according to any one of claims 12 to 15, wherein The trench electrode further includes a virtual electrode, which is electrically connected to the first electrode.

17. The semiconductor device according to any one of claims 1 to 16, wherein The impurity of the first conductivity type in the first buffer layer includes arsenic or phosphorus, The impurity of the first conductivity type in the second buffer layer includes protons.

18. A method of manufacturing a semiconductor device, characterized in that, Comprising: A step of preparing a first-conductivity-type semiconductor substrate having a first main surface provided with a first electrode and a second main surface opposite to the first main surface; A step of forming a first buffer layer of a first conductivity type by implanting a first ion into a side closer to the second main surface than the drift layer, which is a part of the semiconductor substrate, and annealing the first ion; A step of implanting a second ion between the first buffer layer and the drift layer; A step of implanting a third ion into the second main surface side of the first buffer layer; A step of forming a semiconductor layer including at least one of a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type by annealing the third ion; A step of forming a second buffer layer of a first conductivity type having an impurity concentration of the first conductivity type smaller than that of the first buffer layer and larger than that of the drift layer by annealing the second ion; And A step of forming a second electrode on the second main surface, When the maximum value of the oxygen concentration of the semiconductor substrate calculated using the conversion coefficient of the old ASTM is set to maximum[O i , and the impurity concentration of the first conductivity type of the drift layer is set to C drift , the following is satisfied maximum[O i = 9.40×10 16 ×ln(C drift ) - 2.2 7×10 18 。 19. The manufacturing method of the semiconductor device according to claim 18, wherein: the semiconductor layer includes the first semiconductor layer.

20. The manufacturing method of the semiconductor device according to claim 18, wherein: the semiconductor layer includes the second semiconductor layer.

21. The manufacturing method of the semiconductor device according to claim 18, wherein: the semiconductor layer includes the first semiconductor layer and the second semiconductor layer.

22. The manufacturing method of the semiconductor device according to any one of claims 18 to 21, wherein: the second ions are implanted in the order of decreasing acceleration energy, and the dose of the second ions implanted with the first acceleration energy is lower than the dose of the second ions implanted with a second acceleration energy lower than the first acceleration energy.

23. The manufacturing method of the semiconductor device according to any one of claims 18 to 22, wherein: the first ions include arsenic or phosphorus, and the second ions include protons.

24. The manufacturing method of the semiconductor device according to any one of claims 18 to 23, wherein: the second ions are annealed at a temperature of 375 °C or higher and 425 °C or lower for 90 minutes or longer.

25. The manufacturing method of the semiconductor device according to any one of claims 18 to 24, wherein: the semiconductor substrate includes a semiconductor wafer made by the MCZ method.

26. The manufacturing method of the semiconductor device according to any one of claims 18 to 25, wherein: the semiconductor substrate includes antimony as an impurity of the first conductivity type.

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