Integrated circuit device including gate line

Abstract

An integrated circuit device includes: a fin-type active region extending in a first horizontal direction on a substrate; a gate line extending in a second horizontal direction crossing the first horizontal direction on the fin-type active region; a source / drain region disposed on the fin-type active region; a gate dielectric layer disposed on the gate line; a source / drain contact disposed on the source / drain region; a via contact portion integrally connected with the source / drain contact portion and protruding in a vertical direction; a gate contact plug integrally connected with the gate line and protruding in a vertical direction; a first wiring layer electrically connected to the via contact and the gate contact plug; and a via rail connected to the first wiring layer and extending in the first horizontal direction at a vertical level lower than a vertical level of the first wiring layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0011184, filed with the Korean Intellectual Property Office on January 24, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present inventive concept relates to an integrated circuit device, and more particularly, to an integrated circuit device including gate lines. Background art

[0004] Due to the development of electronic technology, the size reduction of integrated circuit devices has been rapidly advancing. Accordingly, the line width and pitch of gate lines included in integrated circuit devices, as well as contact structures connected to the gate lines, have become increasingly fine. Accordingly, an integrated circuit device capable of improving electrical characteristics and reliability is currently being developed. Summary of the invention

[0005] According to an embodiment of the present inventive concept, an integrated circuit device includes: a fin-type active region extending in a first horizontal direction on a substrate; gate lines extending in a second horizontal direction crossing the first horizontal direction on the fin-type active region and the substrate; source / drain regions disposed on the fin-type active region; a gate dielectric layer disposed on lower surfaces and sidewalls of the gate lines; source / drain contact portions disposed on the source / drain regions to contact the source / drain regions; via contact portions integrally connected to the source / drain contact portions and protruding in a vertical direction; gate contact plugs integrally connected to the gate lines and protruding in a vertical direction; a first wiring layer electrically connected to the via contact portions and the gate contact plugs and extending in the first horizontal direction; and via rails connected to the first wiring layer and extending in the first horizontal direction at a vertical level lower than a vertical level of the first wiring layer.

[0006] According to an embodiment of the present inventive concept, an integrated circuit device includes: a fin-type active region extending in a first horizontal direction on a substrate; gate lines extending in a second horizontal direction crossing the first horizontal direction on the fin-type active region and the substrate; source / drain regions disposed on the fin-type active region; a gate dielectric layer disposed on lower surfaces and sidewalls of the gate lines; source / drain contact portions disposed on the source / drain regions to contact the source / drain regions; via contact portions integrally connected to the source / drain contact portions and configured to protrude in a vertical direction; gate contact plugs integrally connected to the gate lines and protruding in a vertical direction; a first wiring layer electrically connected to the via contact portions and the gate contact plugs and extending in the first horizontal direction; and via rails extending in the first horizontal direction and contacting the first wiring layer, wherein the via rails contact sidewalls of the via contact portions.

[0007] According to an embodiment of the inventive concept, an integrated circuit device includes: a fin-type active region extending in a first horizontal direction on a substrate; a gate line extending in a second horizontal direction crossing the first horizontal direction on the fin-type active region and the substrate; source / drain regions disposed on the fin-type active region; a gate dielectric layer disposed on a lower surface and sidewalls of the gate line; source / drain contacts disposed on the source / drain regions to contact the source / drain regions; via contacts integrally connected to the source / drain contacts and protruding in a vertical direction; gate contact plugs integrally connected to the gate line and protruding in the vertical direction; a first wiring layer electrically connected to the via contacts and the gate contact plugs and extending in the first horizontal direction; via contact extension portions disposed between the first wiring layer and the via contacts; gate contact plug extension portions disposed between the first wiring layer and the gate contact plugs; a first spacer configured to conformally cover an upper surface of the gate line, an upper surface of the source / drain contacts, sidewalls of the gate contact plugs, and sidewalls of the via contacts; a second spacer configured to cover the first spacer and including a material having an etching selectivity different from that of the first spacer; and via rails extending in the first horizontal direction and contacting the first wiring layer, wherein the via rails contact sidewalls of the via contacts and sidewalls of the via contact extension portions. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects of the inventive concept will become more apparent by describing embodiments of the inventive concept in detail with reference to the accompanying drawings, in which:

[0009] Figure 1 is a plan layout view of an integrated circuit device according to an embodiment of the inventive concept;

[0010] Figure 2A is a cross-sectional view taken along line X1-X1' in Figure 1 ;

[0011] Figure 2B is a cross-sectional view taken along line X2-X2' in Figure 1 ;

[0012] Figure 2C is a cross-sectional view taken along line Y1-Y1' in Figure 1 ;

[0013] Figure 2D is a cross-sectional view taken along line Y2-Y2' in Figure 1 ; and

[0014] Figures 3A to 9D is a cross-sectional view for describing a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept, wherein: Figure 3A, Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A are cross-sectional views of portions corresponding to the cross-sectional view taken along line X1-X1' in Figure 1 ; Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B and Figure 9B are cross-sectional views of portions corresponding to the cross-sectional view taken along line X2-X2' in Figure 1 ; Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C and Figure 9C are cross-sectional views of portions corresponding to the cross-sectional view taken along line Y1-Y1' in Figure 1 ; and Figure 3D , Figure 4D , Figure 5D , Figure 6D , Figure 7D , Figure 8D and Figure 9D are cross-sectional views of portions corresponding to the cross-sectional view taken along line Y2-Y2' in Figure 1 . DETAILED DESCRIPTION

[0015] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals are used for like components, and their repeated description is omitted.

[0016] Figure 1 is a plan layout view of an integrated circuit device 100 according to an embodiment.

[0017] Figure 2A is a cross-sectional view taken along line X1-X1' in Figure 1 .

[0018] Figure 2B is a cross-sectional view taken along line X2-X2' in Figure 1 .

[0019] Figure 2C is a cross-sectional view taken along line Y1-Y1' in Figure 1 .

[0020] Figure 2D is a cross-sectional view taken along line Y2-Y2' in Figure 1The cross-sectional view taken along line Y2-Y2' in

[0021] Reference Figure 1 and Figures 2A to 2D describes an integrated circuit device 100 including a field effect transistor TR having an active region including a nanowire or having a nanosheet shape, and a gate-all-around structure including a gate surrounding the active region. However, the integrated circuit device 100 according to the inventive concept is not limited thereto, and may also include a transistor having a fin field effect transistor (FINFET) structure.

[0022] Reference Figure 1 、 Figures 2A to 2D , the integrated circuit device 100 may include a plurality of fin active regions F1 and a plurality of nanosheet stacks NSS. The plurality of fin active regions F1 protrude from a substrate 102 and extend in a first horizontal direction (X direction). The plurality of nanosheet stacks NSS are disposed on the fin upper surface FT of the fin active regions F1 at positions spaced apart from the plurality of fin active regions F1 in a vertical direction (Z direction). The term "nanosheet" used in the inventive concept may refer to a conductive structure having a cross-section substantially perpendicular to the current flow direction. The nanosheet should be understood to include nanowires.

[0023] The substrate 102 may include trenches T1 defining the plurality of fin active regions F1, and the trenches T1 may be filled with a device isolation layer 112. The substrate 102 may include a semiconductor such as Si and Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, InGaAs, and InP. The terms SiGe, SiC, GaAs, InAs, InGaAs, and InP used in the inventive concept may refer to materials including the elements contained in each term, but may not refer to chemical formulas representing stoichiometric relationships. The substrate 102 may include a conductive region, for example, a well doped with impurities or a structure doped with impurities. For example, the device isolation layer 112 may include an oxide layer, a nitride layer, or a combination thereof.

[0024] A plurality of gate lines 160 may be respectively disposed on the plurality of fin active regions F1. Each of the plurality of gate lines 160 may extend in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction).

[0025] A plurality of nanosheet stacks NSS can be disposed on the fin upper surface FT of each of the plurality of fin active regions F1 in a region where the plurality of fin active regions F1 and the plurality of gate lines 160 cross each other. The plurality of nanosheet stacks NSS can include at least one nanosheet. Each of the plurality of nanosheet stacks NSS can include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 that overlap each other in the vertical direction (Z direction) on the fin active region F1. The vertical distances (Z-direction distances) of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 from the fin upper surface FT of the fin active region F1 can be different from each other. Each of the plurality of gate lines 160 can surround the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS and overlapping each other in the vertical direction (Z direction).

[0026] In Figure 1 it is shown that the planar shape of the nanosheet stack NSS has a substantially rectangular shape, but the inventive concept is not limited thereto. The nanosheet stack NSS can have various planar shapes according to the planar shape of each of the fin active region F1 and each of the plurality of gate lines 160. In the present embodiment, the intersection between the plurality of nanosheet stacks NSS and the plurality of gate lines 160 can be disposed on one fin active region F1, and a configuration is shown in which the plurality of nanosheet stacks NSS are arranged in a line in the first horizontal direction (X direction) on one fin active region F1. However, the number of nanosheet stacks NSS and gate lines 160 disposed on one fin active region F1 can be not particularly limited. In an embodiment of the inventive concept, it is shown that each of the plurality of nanosheet stacks NSS includes three nanosheets, but the inventive concept is not limited thereto. For example, the nanosheet stack NSS can include at least one nanosheet, and the number of nanosheets constituting the nanosheet stack NSS is not particularly limited.

[0027] Each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS can have a channel region. In an embodiment of the inventive concept, each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS can include a Si layer, a SiGe layer, or a combination thereof.

[0028] In an embodiment of the inventive concept, each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have a thickness in the range of about 4 nm to about 6 nm, but the inventive concept is not limited thereto. In this case, the thickness of each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may be a dimension in the vertical direction (Z direction). In an embodiment of the inventive concept, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have substantially the same thickness as each other in the vertical direction (Z direction). In an embodiment of the inventive concept, at least some of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have different thicknesses from each other in the vertical direction (Z direction).

[0029] The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in one nanosheet stack NSS may have the same size or similar sizes in the first horizontal direction (X direction). In an embodiment of the inventive concept, at least some of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in one nanosheet stack NSS may have different sizes from each other in the first horizontal direction (X direction).

[0030] Each of the plurality of gate lines 160 may include a main gate portion 160M and a plurality of sub - gate portions 160S. The main gate portion 160M may cover the upper surface of the nanosheet stack NSS and extend in the second horizontal direction (Y direction). The plurality of sub - gate portions 160S may be integrally connected to the main gate portion 160M, and each of the plurality of sub - gate portions 160S may be disposed between each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 and between the first nanosheet N1 and the fin - type active region F1. In the vertical direction (Z direction), the thickness of each of the plurality of sub - gate portions 160S may be less than the thickness of the main gate portion 160M.

[0031] A plurality of grooves RC may be formed on the fin - type active region F1. The vertical level of the lowermost surface of each of the plurality of grooves RC may be lower than the vertical level of the fin upper surface FT. The term "vertical level" used in the inventive concept may be a distance from the main surface 102M of the substrate 102 in the vertical direction (Z direction).

[0032] Multiple source / drain regions 130 may be respectively disposed in multiple grooves RC. Each of the multiple source / drain regions 130 may be disposed at a position adjacent to at least one of the multiple gate lines 160. Each of the multiple source / drain regions 130 may have a surface facing the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the adjacent nanosheet stack NSS. Each of the multiple source / drain regions 130 may have a surface in contact with the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the adjacent nanosheet stack NSS.

[0033] Each of the multiple gate lines 160 may include, for example, a metal, a metal nitride, a metal carbide, or a combination thereof. For example, the metal may include Mo, Ru, Cu, or W. The metal nitride may include, for example, TiN, TaN, TiAlN, or a combination thereof. The metal carbide may include, for example, TiAlC. However, the material constituting the multiple gate lines 160 is not limited to the above examples.

[0034] The gate dielectric layer 152 may be disposed between the nanosheet stack NSS and the gate line 160. In an embodiment of the inventive concept, the gate dielectric layer 152 may have a stacked structure of an interfacial dielectric layer and a high-k layer. The interfacial dielectric layer may include a low-dielectric material layer having a dielectric constant of about 9 or less, such as a silicon oxide layer, a silicon oxynitride layer, or a combination thereof. In an embodiment of the inventive concept, the interfacial dielectric layer may be omitted. The high-k layer may include a material having a dielectric constant greater than that of the silicon oxide layer. For example, the high-k layer may have a dielectric constant of about 10 to about 25. The high-k layer may include, for example, hafnium oxide, but the inventive concept is not limited thereto.

[0035] The multiple fin active regions F1 on the substrate 102 and the multiple insulating spacers 118 on the nanosheet stack NSS may extend in a second horizontal direction (Y direction). Two sidewalls of the gate line 160 may be covered with a pair of insulating spacers 118. The insulating spacers 118 may cover two sidewalls of the main gate portion 160M on the upper surface of the multiple nanosheet stacks NSS. The insulating spacers 118 may be spaced apart from the gate line 160, and the gate dielectric layer 152 is between the insulating spacers 118 and the gate line 160. The insulating spacers 118 may include, for example, silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. The terms SiCN, SiBN, SiON, SiOCN, SiBCN, and SiOC used in the inventive concept may refer to materials including the elements contained in each term, but may not refer to chemical formulas representing stoichiometric relationships.

[0036] A pair of insulating spacers 118 covering two sidewalls of the gate line 160 may extend in a second horizontal direction (Y direction). The gate line 160 may cover the fin-type active region F1 and the nanosheet stack NSS and extend in the second horizontal direction (Y direction). The gate dielectric layer 152 may contact the surface of the fin-type active region F1 and the surface of each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS, and may contact the lower surface and the two sidewalls of the gate line 160. The gate dielectric layer 152 may extend in the second horizontal direction (Y direction).

[0037] Two sidewalls of each of the plurality of sub-gate portions 160S may be spaced apart from the source / drain regions 130, with the gate dielectric layer 152 and the insulating spacers 118 therebetween. The gate dielectric layer 152 may be disposed between the sub-gate portions 160S included in the gate line 160 and each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3, and between the sub-gate portions 160S included in the gate line 160 and the source / drain regions 130.

[0038] The plurality of nanosheet stacks NSS may be disposed on the fin upper surfaces FT of each of the plurality of fin-type active regions F1 in a region where the plurality of fin-type active regions F1 and the plurality of gate lines 160 cross each other, and may be disposed on the fin upper surfaces FT of the fin-type active regions F1 at positions where the plurality of nanosheet stacks NSS are spaced apart from the fin-type active regions F1. A plurality of field effect transistors TR may be formed on the substrate 102 in a region where the plurality of fin-type active regions F1 and the plurality of gate lines 160 cross each other.

[0039] A plurality of gate contact plugs CB may be disposed on the plurality of gate lines 160. The gate contact plugs CB may have a structure integrally connected to the gate line 160. The gate contact plugs CB may be integrally formed with the main gate portion 160M and may protrude from the upper surface of the main gate portion 160M in a vertical direction (Z direction). Accordingly, the gate contact plugs CB and the main gate portion 160M may have a single structure without an interface therebetween. In this case, sidewall portions of the gate contact plugs CB connected to the main gate portion 160M may have a circular shape.

[0040] In embodiments of the inventive concept, the plurality of gate lines 160 and the plurality of gate contact plugs CB may include the same material. For example, each of the plurality of gate lines 160 and the plurality of gate contact plugs CB may include a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may include, for example, Mo, Ru, Cu, or W. The metal nitride may include, for example, TiN, TaN, TiAlN, or a combination thereof. The metal carbide may include, for example, TiAlC. However, the material constituting the plurality of gate lines 160 is not limited to the above examples.

[0041] The gate contact plug extension CBE may be disposed on the gate contact plug CB. The gate contact plug extension CBE may electrically connect the gate contact plug CB to the upper wiring layer M1. In this case, the gate contact plug extension CBE may include the same material as the source / drain contact CA and the via contact VA to be described below. However, the inventive concept is not limited thereto, and the gate contact plug extension CBE may include a material different from the materials of the source / drain contact CA and the via contact VA. For example, the gate contact plug extension CBE may include the same material as the gate line 160 and the gate contact plug CB.

[0042] The metal silicide layer 172 may be formed on the upper surface of each of the plurality of source / drain regions 130. For example, the metal silicide layer 172 may include a metal including Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the metal silicide layer 172 may include titanium silicide, but the inventive concept is not limited thereto.

[0043] The insulating liner 142 and the inter-gate insulating layer 144 may be sequentially disposed on the plurality of source / drain regions 130 and the plurality of metal silicide layers 172. The insulating liner 142 and the inter-gate insulating layer 144 may constitute an insulating structure. The insulating spacer 118 and the plurality of source / drain regions 130 may be covered with the insulating liner 142. In embodiments of the inventive concept, the insulating liner 142 may include silicon nitride (SiN), SiCN, SiBN, SiON, SiOCN, SiBCN, or a combination thereof, but the inventive concept is not limited thereto. The inter-gate insulating layer 144 may include a silicon oxide layer, but the inventive concept is not limited thereto. In embodiments of the inventive concept, the insulating liner 142 may be omitted. When the insulating liner 142 is omitted, the inter-gate insulating layer 144 may be in contact with the plurality of source / drain regions 130.

[0044] Multiple source / drain contact portions CA may be respectively disposed on multiple source / drain regions 130. Each of the multiple source / drain contact portions CA may penetrate an insulating structure including an inter-gate insulating layer 144 and an insulating liner 142 in a vertical direction (Z direction), and may be in contact with a metal silicide layer 172. Each of the multiple source / drain contact portions CA may be configured to be electrically connected to the source / drain region 130 via the metal silicide layer 172. The multiple source / drain contact portions CA may be spaced apart from a main gate portion 160M in a first horizontal direction (X direction), and insulating spacers 118 may be between the multiple source / drain contact portions CA and the main gate portion 160M.

[0045] Multiple via contact portions VA may be respectively disposed on the multiple source / drain contact portions CA. The multiple via contact portions VA may have a structure in which the multiple via contact portions VA are integrally connected to the multiple source / drain contact portions CA respectively. The source / drain contact portions CA and the via contact portions VA integrally connected to each other respectively may constitute a source / drain contact structure. The source / drain contact structure may include a conduction blocking layer 174 and a contact plug 176. The conduction blocking layer 174 may cover a lower surface and two sidewalls in a first horizontal direction (X direction) of the contact plug 176. The conduction blocking layer 174 and the contact plug 176 may respectively include a lower portion constituting the source / drain contact portion CA and an upper portion constituting the via contact portion VA. A lower portion and an upper portion of each of the conduction blocking layer 174 and the contact plug 176 may be an integrally connected structure. The conduction blocking layer 174 may be disposed between the metal silicide layer 172 and the contact plug 176. For example, the conduction blocking layer 174 may include a surface in contact with the metal silicide layer 172 and a surface in contact with the contact plug 176. In an embodiment of the inventive concept, the conduction blocking layer 174 may also be omitted.

[0046] The via contact portion VA may have a structure in which the via contact portion VA is integrally connected to the source / drain contact portion CA. The via contact portion VA may be integrally formed with the source / drain contact portion CA and may protrude from an upper surface of the source / drain contact portion CA in a vertical direction (Z direction). Accordingly, the via contact portion VA and the source / drain contact portion CA may be a single structure without an interface therebetween. In this case, a sidewall portion of the via contact portion VA connected to the source / drain contact portion CA may have a circular shape.

[0047] The multiple source / drain contact portions CA and the multiple via contact portions VA may include the same material as each other. For example, the conductive barrier layer 174 formed on the multiple source / drain contact portions CA and the multiple via contact portions VA may include a metal or a metal nitride. For example, the conductive barrier layer 174 may include Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but is not limited thereto. The contact plugs 176 constituting the multiple source / drain contact portions CA and the multiple via contact portions VA may include the following metals: molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), and combinations thereof.

[0048] The via contact extension portion VAE may be disposed on the via contact portion VA. The via contact extension portion VAE may electrically connect the via contact portion VA to the upper wiring layer M1. In this case, the via contact extension portion VAE may include the same material as the source / drain contact portion CA and the via contact portion VA. However, the inventive concept is not limited thereto, and the via contact extension portion VAE may include a material different from the materials of the source / drain contact portion CA and the via contact portion VA.

[0049] The upper surfaces of the multiple via contact portions VA and the upper surfaces of the multiple gate contact plugs CB may be at substantially the same vertical level with respect to each other. In addition, the upper surfaces of the gate contact plug extension portion CBE and the via contact extension portion VAE may be at substantially the same vertical level with respect to each other. In this case, the thicknesses of the gate contact plug extension portion CBE and the via contact extension portion VAE in the vertical direction (Z direction) may be about 5 nm.

[0050] The first spacer 154 may conformally cover the gate line 160, the source / drain contact portion CA, the gate contact plug CB, the via contact portion VA, the gate contact plug extension portion CBE, and the via contact extension portion VAE. For example, the first spacer 154 may cover the upper surface of the gate line 160 where the gate contact plug CB is not disposed, and the upper surface of the source / drain contact portion CA where the via contact portion VA is not disposed. In addition, the first spacer 154 may cover the sidewalls of each of the gate contact plug CB, the via contact portion VA, the gate contact plug extension portion CBE, and the via contact extension portion VAE.

[0051] The second spacer 156 may be disposed on the first spacer 154. In this case, the upper surfaces of the first spacer 154, the second spacer 156, the gate contact plug extension CBE, and the via contact extension VAE may be substantially coplanar with each other. In an embodiment of the inventive concept, the second spacer 156 may include a material having an etch selectivity different from that of the first spacer 154. For example, the first spacer 154 may include a SiOC material, and the second spacer 156 may include silicon nitride.

[0052] The via rail VAR may extend in a first horizontal direction (X direction). For example, the via rail VAR may extend longitudinally in the first horizontal direction (X direction). The via rail VAR may be disposed to contact the via contact portion VA and the via contact extension VAE. One of the sidewalls of the via rail VAR in a second horizontal direction (Y direction) may contact the sidewall of the via contact portion VA. In addition, the via rail VAR and the via contact extension VAE may be disposed to partially overlap each other in the second horizontal direction (Y direction). In this case, the sidewall of the via rail VAR in the second horizontal direction (Y direction) may have a circular shape. In addition, the sidewall of the via contact portion VA in the second horizontal direction (Y direction) may have a circular shape. In this case, the via rail VAR may include the same material as the source / drain contact portion CA and the via contact portion VA. However, the inventive concept is not limited thereto, and the via contact extension VAE may include a material different from the materials of the source / drain contact portion CA and the via contact portion VA. In an embodiment of the inventive concept, the lower surface of the via rail may be circular.

[0053] The integrated circuit device 100 according to the inventive concept may include a gate contact plug CB integrally formed with the gate line 160 and a via contact portion VA integrally formed with the source / drain contact portion CA to improve the integration degree of the integrated circuit device 100. By integrally forming the gate contact plug CB connected to the upper wiring layer M1 with the gate line 160 and integrally forming the via contact portion VA connected to the upper wiring layer M1 with the source / drain contact portion CA, misalignment and poor connection (e.g., short circuit) between wirings can be prevented, and the electrical performance of the integrated circuit device 100 can be improved.

[0054] In addition, the integrated circuit device 100 according to the inventive concept may include a first spacer 154 and a second spacer 156 having different etching selectivities from each other. Accordingly, the via rail VAR may be arranged to contact the via contact portion VA and the via contact extension portion VAE. In this case, since the via rail VAR includes the same material as the via contact portion VA, an interface may not be formed between the via rail VAR and the via contact portion VA. Since a separate barrier metal layer is not formed between the via rail VAR and the via contact portion VA, the resistance of the via rail VAR and the via contact portion VA may be reduced, thereby improving the electrical characteristics of the integrated circuit device 100.

[0055] The upper surfaces of each of the first spacer 154, the second spacer 156, the gate contact plug extension portion CBE, and the via contact extension portion VAE may be covered by an etch stop layer 185 and an interlayer insulating layer 187. The etch stop layer 185 may include silicon carbide (SiC), SiN, SiCN, SiOC, AlN, AlON, AlO, AlOC, or a combination thereof. The interlayer insulating layer 187 may include an oxide layer, a nitride layer, an ultra-low-k (ULK) layer having an ultra-low dielectric constant k of about 2.2 to about 2.4, or a combination thereof. For example, the interlayer insulating layer 187 may include a tetraethyl orthosilicate (TEOS) layer, a high-density plasma (HDP) layer, a borophosphosilicate glass (BPSG) layer, a flowable chemical vapor deposition (FCVD) oxide layer, a SiON layer, a SiOC layer, a SiCOH layer, or a combination thereof, but the inventive concept is not limited thereto.

[0056] A plurality of upper wiring layers M1 penetrating the etch stop layer 185 and the interlayer insulating layer 187 may be disposed on the substrate 102. The plurality of upper wiring layers M1 may extend longitudinally in a first horizontal direction (X direction). In this case, the vertical level of the plurality of upper wiring layers M1 may be higher than the vertical levels of the via contact extension portion VAE and the gate contact plug extension portion CBE. The plurality of upper wiring layers M1 may include an upper wiring layer M1 connected to the via contact portion VA and an upper wiring layer M1 connected to the gate contact plug CB. The upper wiring layer M1 may be connected to the via contact extension portion VAE and the gate contact plug extension portion CBE. The plurality of upper wiring layers M1 may include, for example, Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, a combination thereof, or an alloy thereof, but the inventive concept is not limited thereto.

[0057] A power wiring layer MPW penetrating the etch stop layer 185 and the interlayer insulating layer 187 may be arranged on the substrate 102. The power wiring layer MPW may extend longitudinally along the first horizontal direction (X direction). In this case, the vertical level of the power wiring layer MPW may be higher than the vertical level of the via contact extension portion VAE and the via track VAR. The upper surface of the power wiring layer MPW is substantially coplanar with the upper portion of the interlayer insulating layer 187 and the upper surface of the upper wiring layer M1. The power wiring layer MPW may be connected to the via contact portion VA and the via track VAR. The power wiring layer MPW may be simultaneously connected to the via contact portion VA and the via track VAR. The power wiring layer MPW may be simultaneously connected to the via contact extension portion VAE and the via track VAR. The width of the power wiring layer MPW in the second horizontal direction (Y direction) may be substantially equal to the sum of the widths of the via contact portion VA and the via track VAR in the second horizontal direction (Y direction). However, the inventive concept is not limited thereto. For example, the width of the power wiring layer MPW in the second horizontal direction (Y direction) may be greater than or less than the sum of the widths of the via contact VA and the via rail VAR in the second horizontal direction (Y direction). The power wiring layer MPW may include, for example, Mo, Cu, W, Co, Ru, Mn, Ti, Ta, Al, a combination thereof, or an alloy thereof, but the inventive concept is not limited thereto.

[0058] Figures 3A to 9D is a cross-sectional view for describing a method of manufacturing an integrated circuit device according to an embodiment of the inventive concept. Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A According to the process sequence and along Figure 1 A cross-sectional view of a portion corresponding to the cross-sectional view taken along line X1 - X1 ′ in FIG. Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B and Figure 9B According to the process sequence and along Figure 1 A cross-sectional view of a portion corresponding to the cross-sectional view taken along line X2-X2' in FIG. Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C and Figure 9C According to the process sequence and along Figure 1 A cross-sectional view of a portion corresponding to the cross-sectional view taken along line Y1 - Y1 ′ in FIG. Figure 3D , Figure 4D , Figure 5D ,Figure 6D , Figure 7D , Figure 8D and Figure 9D are cross-sectional views corresponding to portions corresponding to the cross-sectional view taken along line Y2 - Y2’ in Figure 1 .

[0059] Referring to Figures 3A to 3D , a plurality of nanosheet stacks NSS and a plurality of source / drain regions 130 can be formed on a substrate 102 having a plurality of fin-type active regions F1. In addition, a plurality of gate lines 160 and a plurality of source / drain contact portions CA can be formed on the substrate 102.

[0060] By alternately stacking a plurality of sacrificial semiconductor layers and a plurality of nanosheet semiconductor layers on the substrate 102 one by one, and etching a plurality of sacrificial semiconductor layers, a plurality of nanosheet semiconductor layers, and a part of the substrate 102, a plurality of fin-type active regions F1 protruding from the substrate 102 can be formed. In this case, the plurality of sacrificial semiconductor layers and the plurality of nanosheet semiconductor layers can include semiconductor materials having different etching selectivities from each other. For example, the plurality of nanosheet semiconductor layers can include Si layers, and the plurality of sacrificial semiconductor layers can include SiGe layers. A device isolation layer 112 covering the sidewalls of each of the plurality of fin-type active regions F1 can be formed on the substrate 102.

[0061] Subsequently, a plurality of insulating spacers 118 can be formed, and the plurality of insulating spacers 118 cover the sidewalls of each of the plurality of dummy gate structures and the plurality of dummy gate structures located on the stacked structure of the plurality of sacrificial semiconductor layers and the plurality of nanosheet semiconductor layers. By using the plurality of dummy gate structures and the plurality of insulating spacers 118 as an etching mask to etch a part of each of the plurality of sacrificial semiconductor layers and the plurality of nanosheet semiconductor layers and a part of the fin-type active region F1, the plurality of nanosheet semiconductor layers can be divided into a plurality of nanosheet stacks NSS, and a plurality of grooves RC can be formed on the fin-type active region F1. Each of the plurality of nanosheet stacks NSS can include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3. To form the plurality of grooves RC, the etching process can be performed by using, for example, a dry etching process, a wet etching process, or a combination thereof.

[0062] Subsequently, a plurality of source / drain regions 130 respectively filling the plurality of grooves RC can be formed. To form the plurality of source / drain regions 130, semiconductor materials can be epitaxially grown from the surface of the lower surface of the fin-type active region F1 where the plurality of grooves RC are formed, and the sidewalls of each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS. An insulating liner 142 covering the plurality of source / drain regions 130 can be formed on the plurality of source / drain regions 130, and an inter-gate insulating layer 144 can be formed on the insulating liner 142.

[0063] Subsequently, the dummy gate structure can be removed to provide a gate space, and a plurality of nanosheet stacks NSS can be exposed through the gate space. Subsequently, through the gate space, a plurality of sacrificial semiconductor layers remaining on the fin active region F1 are removed, and the gate space can extend to the space between each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 and the space between the first nanosheet N1 and the fin upper surface FT. In an embodiment of the inventive concept, in order to selectively remove the plurality of sacrificial semiconductor layers, the difference in etching selectivity between the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 and the plurality of sacrificial semiconductor layers can be utilized. A liquid or gaseous etchant can be used to selectively remove the plurality of sacrificial semiconductor layers. For example, in order to selectively remove the plurality of sacrificial semiconductor layers, an etchant based on CH3COOH can be used, such as an etchant solution containing a mixture of CH3COOH, HNO3, and HF, and an etchant solution containing a mixture of CH3COOH, H2O2, and HF, but the inventive concept is not limited thereto.

[0064] Subsequently, a gate dielectric layer 152 can be formed to cover the exposed surfaces of each of the first nanosheet N1, the second nanosheet N2, the third nanosheet N3, and the fin active region F1. The atomic layer deposition (ALD) process can be used to form the gate dielectric layer 152. A gate line 160 can be formed on the gate dielectric layer 152.

[0065] Subsequently, a plurality of source / drain contact holes can be formed, and the plurality of source / drain contact holes penetrate an insulating structure including an insulating liner 142 and an inter-gate insulating layer 144 and expose the source / drain regions 130. In addition, a portion of the source / drain region 130 can be removed by using an anisotropic etching process through each of the plurality of source / drain contact holes, and a metal silicide layer 172 can be formed on the source / drain region 130 exposed at the bottom side of each of the plurality of source / drain contact holes. Subsequently, a plurality of source / drain contact portions CA extending in the second horizontal direction (Y direction) can be formed by disposing a conduction barrier layer 174 and a contact plug 176 in each of the plurality of source / drain contact holes.

[0066] Reference Figures 4A to 4D, a first insulating layer 151 and a second insulating layer 153 may be sequentially formed on the substrate 102. The first insulating layer 151 and the second insulating layer 153 may be formed to cover the gate line 160 and the source / drain contact portion CA. For example, the first insulating layer 151 may include silicon nitride, and the second insulating layer 153 may include a carbon-based material, such as a spin-on hard mask (SOH), but the inventive concept is not limited thereto. Subsequently, a plurality of pillars 155 penetrating the first insulating layer 151 and the second insulating layer 153 may be formed. The plurality of pillars 155 may be disposed on the plurality of gate lines 160 and the plurality of source / drain contact portions CA. The plurality of pillars 155 may be arranged to be spaced apart from each other at a certain interval in the first horizontal direction (X direction) and / or the second horizontal direction (Y direction). In this case, the pillar 155 may include silicon oxide.

[0067] Reference Figures 5A to 5D , a first groove R1 and a second groove R2 may be formed by removing a part of the pillar 155, the first insulating layer 151, and the second insulating layer 153. The first groove R1 may be formed by removing a part of the upper end of the gate line 160. In addition, an upper portion of the inter-gate insulating layer 144, the insulating liner 142, and the insulating spacer 118 may be removed. A part of the upper end of the gate line 160 may be removed to form a gate contact plug CB protruding from the upper surface of the gate line 160 in the vertical direction (Z direction). The gate contact plug CB may be integrally formed with the gate line 160.

[0068] The second groove R2 may be formed by removing a part of the upper end of the source / drain contact portion CA. A part of the upper end of the source / drain contact portion CA may be removed to form a via contact portion VA protruding from the upper surface of the source / drain contact portion CA in the vertical direction (Z direction). The via contact portion VA may be integrally formed with the source / drain contact portion CA.

[0069] In this case, the upper surfaces of the gate contact plug CB and the via contact portion VA may be formed to be substantially coplanar with each other. For example, the heights of the gate contact plug CB and the via contact portion VA in the vertical direction (Z direction) may be within about 15 nm.

[0070] Reference Figures 6A to 6D, the first spacer 154 and the second spacer 156 may be sequentially formed on the substrate 102. The first spacer 154 may be formed to cover the gate line 160 and the source / drain contact CA. In addition, the first spacer 154 may be formed to cover the sidewalls of the gate contact plug CB and the via contact VA. In addition, the first spacer 154 may be formed to cover the upper surface and the sidewalls of the pillar 155. The first spacer 154 may conformally cover the gate line 160, the source / drain contact CA, the gate contact plug CB, the via contact VA, and the pillar 155. In this case, the first spacer 154 may have a thickness of about 10 nm. The second spacer 156 may be formed on the first spacer 154. The second spacer 156 may conformally cover the first spacer 154. In this case, the thickness of the second spacer 156 may be about 20 nm. The second spacer 156 may include a material having an etch selectivity different from that of the first spacer 154. In an embodiment of the inventive concept, the first spacer 154 may include a SiOC material, and the second spacer 156 may include silicon nitride.

[0071] Reference Figures 7A to 7D , a portion of the first spacer 154, a portion of the second spacer 156, and a portion of the pillar 155 may be removed by using a chemical mechanical polishing (CMP) process. In this case, the upper surfaces of the first spacer 154, the second spacer 156, and the pillar 155 may be formed into a coplanar flat surface by using a planarization process, and the height of the pillar 155 in the vertical direction (Z direction) may be about 10 nm.

[0072] Subsequently, reference Figure 7D , a via rail notch OP1 may be formed by removing a portion of the first spacer 154 and a portion of the second spacer 156. The via rail notch OP1 may extend longitudinally in the first horizontal direction (X direction). For example, a portion of the first spacer 154 extending along the sidewall of the pillar 155 and the sidewall of the source / drain contact CA may be removed. In this case, the via rail notch OP1 may expose the sidewall of the via contact VA and the sidewall of the pillar 155. In addition, the via rail notch OP1 may expose the remaining portion of the first spacer 154. Since the etch selectivities of the first spacer 154 and the second spacer 156 are different during the formation of the via rail notch OP1, the second spacer 156 may be removed, and a portion of the first spacer 154 may be retained and exposed.

[0073] Reference Figures 8A to 8D , a plurality of pillars 155 may be removed to form a plurality of openings OP2. The plurality of pillars 155 may be removed by using a cleaning process. By removing the plurality of pillars 155, the upper surface of the gate contact plug CB and the upper surface of the via contact VA may be exposed.

[0074] Reference Figures 9A to 9D , a conductive layer that forms the filled via track notch OP1 and the plurality of openings OP2 can be formed. The conductive layer can fill the via track notch OP1 and the plurality of openings OP2, and can cover the upper surfaces of the first spacer 154 and the second spacer 156. The conductive layer can include the same material as the source / drain contact portion CA. For example, the conductive layer can include the following metals: molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), or a combination thereof. In this case, the conductive layer can grow upward from the lower portions of the via track notch OP1 and the plurality of openings OP2.

[0075] Subsequently, by applying a planarization process to remove a portion of the first spacer 154, a portion of the second spacer 156, and a portion of the conductive layer, a via track VAR, a via contact extension VAE, and a gate contact plug extension CBE can be formed.

[0076] The via track VAR can be formed in the via track notch OP1. The via track VAR can be arranged to contact the via contact portion VA and the via contact extension VAE. One of the sidewalls of the via track VAR in the second horizontal direction (Y direction) can contact the sidewall of the via contact portion VA. In addition, the via track VAR and the via contact extension VAE can be arranged to partially overlap each other in the second horizontal direction (Y direction).

[0077] In addition, the via contact extension VAE and the gate contact plug extension CBE can be formed in the plurality of openings OP2. In this case, the via track VAR, the via contact extension VAE, and the gate contact plug extension CBE can include the same material. For example, the via track VAR and the via contact extension VAE can be integrally formed with each other. Since the via track VAR includes the same material as the via contact portion VA, an interface may not be formed between the via track VAR and the via contact portion VA. Since no separate barrier metal layer is formed between the via track VAR and the via contact portion VA, the resistance between the via track VAR and the via contact portion VA can be reduced, thereby improving the electrical characteristics of the integrated circuit device 100.

[0078] The upper surfaces of each of the first spacer 154, the second spacer 156, the via track VAR, the via contact extension VAE, and the gate contact plug extension CBE can be substantially coplanar. In this case, the thicknesses of the gate contact plug extension CBE and the via contact extension VAE in the vertical direction (Z direction) can be about 5 nm.

[0079] Subsequently, as Figures 2A to 2DAs shown, an etch stop layer 185 and an interlayer insulating layer 187 that cover the upper surfaces of the first spacer 154, the second spacer 156, the via rail VAR, the via contact extension VAE, and the gate contact plug extension CBE can be formed, and the integrated circuit device 100 can be manufactured by forming an upper wiring layer M1 and a power wiring layer MPW such that they penetrate both the etch stop layer 185 and the interlayer insulating layer 187.

[0080] Although the inventive concept has been described with reference to embodiments of the inventive concept, those of ordinary skill in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the inventive concept.

Claims

1. An integrated circuit device, comprising: A fin-type active region extending in a first horizontal direction on a substrate; A gate line extending in a second horizontal direction crossing the first horizontal direction on the fin-type active region and the substrate; A source / drain region disposed on the fin-type active region; A gate dielectric layer disposed on a lower surface and sidewalls of the gate line; A source / drain contact portion disposed on the source / drain region to contact the source / drain region; A via contact portion integrally connected to the source / drain contact portion and protruding in a vertical direction; A gate contact plug integrally connected to the gate line and protruding in the vertical direction; A first wiring layer electrically connected to the via contact portion and the gate contact plug and extending in the first horizontal direction; And A via rail connected to the first wiring layer and extending in the first horizontal direction at a vertical level lower than a vertical level of the first wiring layer.

2. The integrated circuit device according to claim 1, wherein, The via rail contacts a sidewall of the via contact portion.

3. The integrated circuit device according to claim 1, further comprising: A via contact extension portion disposed between the first wiring layer and the via contact portion; And A gate contact plug extension portion disposed between the first wiring layer and the gate contact plug.

4. The integrated circuit device according to claim 3, wherein, The via rail, the via contact extension portion, and the gate contact plug extension portion include the same material as the source / drain contact portion.

5. The integrated circuit device according to claim 3, wherein, Upper surfaces of the via rail, the via contact extension portion, and the gate contact plug extension portion are coplanar.

6. The integrated circuit device according to claim 3, wherein, The via rail overlaps the via contact extension portion in the second horizontal direction.

7. The integrated circuit device according to claim 3, wherein, The via rail and the via contact extension portion are integrally formed.

8. The integrated circuit device according to claim 3, wherein, The via contact extension portion and the gate contact plug extension portion have a thickness of about 5 nm or less in the vertical direction.

9. The integrated circuit device according to claim 1, further comprising: A first spacer configured to conformally cover an upper surface of the gate line, an upper surface of the source / drain contact portion, sidewalls of the gate contact plug, and sidewalls of the via contact portion; And A second spacer configured to cover the first spacer.

10. The integrated circuit device according to claim 9, wherein, The first spacer and the second spacer include materials having different etching selectivities.

11. The integrated circuit device according to claim 1, further comprising: A second wiring layer simultaneously connected to the via rail and the via contact portion.

12. An integrated circuit device, comprising: A fin-type active region extending in a first horizontal direction on a substrate; A gate line extending in a second horizontal direction crossing the first horizontal direction on the fin-type active region and the substrate; A source / drain region disposed on the fin-type active region; A gate dielectric layer disposed on a lower surface and sidewalls of the gate line; A source / drain contact portion disposed on the source / drain region to contact the source / drain region; A via contact portion integrally connected to the source / drain contact portion and configured to protrude in a vertical direction; A gate contact plug integrally connected to the gate line and protruding in the vertical direction; A first wiring layer, electrically connected to the via contact portion and the gate contact plug, and extending in the first horizontal direction; and A via rail, extending in the first horizontal direction and in contact with the first wiring layer, wherein the via rail is in contact with a sidewall of the via contact portion.

13. The integrated circuit device according to claim 12, further comprising: A via contact extension portion, disposed between the first wiring layer and the via contact portion; and A gate contact plug extension portion, disposed between the first wiring layer and the gate contact plug.

14. The integrated circuit device according to claim 13, wherein, Each of the via rail, the via contact extension portion, and the gate contact plug extension portion includes the same material as the source / drain contact portion.

15. The integrated circuit device according to claim 13, wherein, The via rail overlaps the via contact extension portion in the second horizontal direction.

16. The integrated circuit device according to claim 12, wherein The via contact portion is disposed below the via contact extension portion and the first wiring layer, and A lower surface of the via rail is circular.

17. The integrated circuit device according to claim 12, further comprising: A second wiring layer, simultaneously connected to the via rail and the via contact portion.

18. An integrated circuit device, comprising: A fin-shaped active region, extending in a first horizontal direction on a substrate; A gate line, extending in a second horizontal direction intersecting the first horizontal direction on the fin-shaped active region and the substrate; Source / drain regions, disposed on the fin-shaped active region; A gate dielectric layer, disposed on a lower surface and sidewalls of the gate line; Source / drain contact portions, disposed on the source / drain regions to contact the source / drain regions; Via contact portions, integrally connected to the source / drain contact portions and protruding in a vertical direction; Gate contact plugs, integrally connected to the gate lines and protruding in the vertical direction; A first wiring layer, electrically connected to the via contact portions and the gate contact plugs, and extending in the first horizontal direction; Via contact extension portions, disposed between the first wiring layer and the via contact portions; Gate contact plug extension portions, disposed between the first wiring layer and the gate contact plugs; A first spacer, configured to conformally cover an upper surface of the gate line, an upper surface of the source / drain contact portions, sidewalls of the gate contact plugs, and sidewalls of the via contact portions; A second spacer, configured to cover the first spacer and including a material having an etching selectivity different from that of the first spacer; and Via rails, extending in the first horizontal direction and in contact with the first wiring layer, wherein the via rails are in contact with sidewalls of the via contact portions and sidewalls of the via contact extension portions.

19. The integrated circuit device according to claim 18, wherein, Each of the via rails, the via contact extension portions, and the gate contact plug extension portions includes the same material as the source / drain contact portions.

20. The integrated circuit device according to claim 18, wherein, The via rails and the via contact extension portions are integrally formed.

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