Display device

Abstract

The invention relates to a display device. The display device includes: a first conductive layer including a first initialization voltage line extending in a first direction; a first semiconductor layer; a second conductive layer including a first gate electrode; a third conductive layer including a first connection electrode electrically connecting the first semiconductor layer to the first initialization voltage line, and a first data connection line extending in the first direction; and a fourth conductive layer including a driving voltage line extending in a second direction crossing the first direction, and a second data connection line. The driving voltage line has a hole defined therein. The hole overlaps the first connection electrode. The driving voltage line includes a shielding portion overlapping the first data connection line.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2024 - 0011239, filed with the Korean Intellectual Property Office (KIPO) on January 24, 2024, and Korean Patent Application No. 10 - 2024 - 0077166, filed with the KIPO on June 13, 2024. The disclosures of these two Korean patent applications are incorporated herein by reference in their entirety. Technical field

[0003] One or more embodiments relate to a display device. Background art

[0004] In recent years, display devices have become increasingly thin and light, and the range of use of display devices has diversified. A display device may include a plurality of pixels. Each of the plurality of pixels may include a light - emitting diode and a pixel circuit for controlling the brightness of the light - emitting diode. The pixel circuit may include transistors and capacitors, which are connected to wirings such as data lines, gate signal lines, voltage lines, etc.

[0005] As display devices are used more widely and the number of functions that can be connected to or linked to display devices has increased, various types of display devices have been developed. Summary of the invention

[0006] However, in a display device according to the prior art, the coupling between a data connection line for transmitting a data signal to a data line and a pixel electrode of a light - emitting diode may cause spots in an image displayed by the display device due to a brightness difference between pixels of the display device.

[0007] One or more embodiments include a display device that displays a high - quality image by reducing the coupling between a data connection line and a pixel electrode. However, this purpose is merely illustrative, and the scope of the embodiments of the present disclosure is not limited thereto.

[0008] Additional aspects will be set forth in part in the following description, and in part will be obvious from the description, or may be learned by practice of the presented embodiments of the present disclosure.

[0009] According to an embodiment, a display device includes a first conductive layer, a first semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on a substrate. The first conductive layer includes a first initialization voltage line extending in a first direction. The first semiconductor layer is disposed on the first conductive layer. The second conductive layer is disposed on the first semiconductor layer. The second conductive layer includes a first gate electrode. The third conductive layer is disposed on the second conductive layer. The third conductive layer includes a first connection electrode electrically connecting the first semiconductor layer and the first initialization voltage line to each other and a first data connection line extending in the first direction. The fourth conductive layer is disposed on the third conductive layer. The fourth conductive layer includes a driving voltage line extending in a second direction intersecting the first direction and a second data connection line. The driving voltage line has a hole defined therein. The hole overlaps with the first connection electrode. The driving voltage line includes a shielding portion overlapping with the first data connection line.

[0010] In an embodiment, the first initialization voltage line may include a first portion and a second portion protruding from the first portion in the second direction, the first semiconductor layer may include a first portion extending in the first direction and a second portion protruding from the first portion of the first semiconductor layer in the second direction, and the first connection electrode may electrically connect the second portion of the first initialization voltage line and the second portion of the first semiconductor layer to each other.

[0011] In an embodiment, the first portion of the first initialization voltage line may overlap with the first portion of the first semiconductor layer.

[0012] In an embodiment, the fourth conductive layer may further include a second connection electrode overlapping with the hole, and the first connection electrode may be disposed between the second connection electrode and the first data connection line in a plan view.

[0013] In an embodiment, the display device may further include a fifth conductive layer disposed on the fourth conductive layer and including a pixel electrode, and the pixel electrode may be electrically connected to the second connection electrode.

[0014] In an embodiment, the pixel electrode may overlap with the first data connection line, and the shielding portion may be disposed between the pixel electrode and the first data connection line.

[0015] In an embodiment, the third conductive layer may further include a second initialization voltage line extending in the first direction, and the first connection electrode may be disposed between the first data connection line and the second initialization voltage line in a plan view.

[0016] In an embodiment, the fourth conductive layer may further include a data line extending in the second direction, and the first data connection line may be electrically connected to the data line and the second data connection line.

[0017] In an embodiment, the substrate may include a display area and a peripheral area outside the display area, and a first data connection line may be electrically connected to a data line in the display area.

[0018] In an embodiment, the display device may further include a second semiconductor layer disposed between the substrate and the first conductive layer, the first semiconductor layer may include an oxide-based semiconductor material, and the second semiconductor layer may include a silicon-based semiconductor material.

[0019] According to an embodiment of the present disclosure, a display device includes: a plurality of pixels; a first data connection line extending in a first direction; a second data connection line extending in a second direction intersecting the first direction; and a driving voltage line extending in the second direction. The driving voltage line has a hole defined therein. The driving voltage line further has a shielding portion that overlaps with the first data connection line. Each of the plurality of pixels may include: a light-emitting diode including a pixel electrode, a counter electrode, and an intermediate layer between the pixel electrode and the counter electrode; a first transistor including a first semiconductor layer and a first gate electrode on the first semiconductor layer; a second transistor electrically connected between the data line and the first transistor; a third transistor electrically connected between a first initialization voltage line and the first gate electrode; a fourth transistor electrically connected between the driving voltage line and the first transistor; a fifth transistor electrically connected to the first transistor and the light-emitting diode; and a first connection electrode electrically connecting the first initialization voltage line and the third transistor to each other and overlapping with the hole.

[0020] In an embodiment, each of the plurality of pixels may further include a second connection electrode electrically connected between the pixel electrode and the fifth transistor; and the second connection electrode may overlap with the hole.

[0021] In an embodiment, the first connection electrode may be disposed between the second connection electrode and the first data connection line in a plan view.

[0022] In an embodiment, the pixel electrode may overlap with the first data connection line, and the shielding portion may be disposed between the pixel electrode and the first data connection line.

[0023] In an embodiment, the light-emitting diode may emit green light.

[0024] In an embodiment, the first data connection line may be disposed in the same layer as the first connection electrode.

[0025] In an embodiment, each of the plurality of pixels may further include a sixth transistor electrically connected between a second initialization voltage line and the light-emitting diode.

[0026] In an embodiment, the second initialization voltage line may extend in a first direction, and the first connection electrode may be disposed between the second initialization voltage line and the first data connection line in a plan view.

[0027] In an embodiment, the first data connection line may be electrically connected to a data line and a second data connection line.

[0028] In an embodiment, the display device may further include a conductive bias voltage line extending in the first direction, and each of the plurality of pixels may further include a seventh transistor electrically connected between the conductive bias voltage line and the first transistor.

[0029] Other aspects, features, and advantages in addition to the above description will be apparent from the details of the drawings, the claims claimed, and the details of the embodiments of the present disclosure. Description of the Drawings

[0030] From the following description in conjunction with the drawings, the above and other aspects, features, and advantages of some non-limiting embodiments of the present disclosure will become more apparent, in the drawings:

[0031] Figure 1 is a plan view schematically showing a part of a display device according to an embodiment of the present disclosure;

[0032] Figure 2 is a plan view schematically showing a part of a display device according to an embodiment of the present disclosure;

[0033] Figure 3A and Figure 3B are respectively plan views schematically showing a part of the Figure 2 display device shown according to an embodiment of the present disclosure;

[0034] Figure 4A and Figure 4B are respectively plan views schematically showing a part of the Figure 2 display device shown according to an embodiment of the present disclosure;

[0035] Figure 5 is an equivalent circuit diagram of a pixel of a display device according to an embodiment of the present disclosure;

[0036] Figure 6 is a layout diagram schematically showing a part of a display device according to an embodiment of the present disclosure;

[0037] Figures 7 to 13 is a layout diagram schematically showing a part of the Figure 6 display device shown according to each layer according to an embodiment of the present disclosure;

[0038] Figure 14 is an enlarged plan view schematically showing part II of the display device according to an embodiment of the present disclosure; and Figure 6 is a cross-sectional view schematically showing a part of the display device according to an embodiment of the present disclosure.

[0039] Figure 15 is an enlarged plan view schematically showing a part of the display device according to an embodiment of the present disclosure; and Figure 14 is a cross-sectional view schematically showing a part of the display device according to an embodiment of the present disclosure. Detailed Embodiments

[0040] Now, non-limiting embodiments will be described in detail, examples of which are shown in the accompanying drawings, where the same reference numerals always denote the same elements. In this regard, the embodiments of the present disclosure may have different forms and should not be construed as limited to the descriptions set forth herein. Therefore, the embodiments are described below only by referring to the accompanying drawings to explain aspects of the present specification. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items. Throughout the present disclosure, the expression "at least one of a, b, and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0041] Since various modifications and various embodiments are possible, non-limiting embodiments are shown in the accompanying drawings and are described in detail in the detailed embodiments section. Referring to the embodiments described in detail below in conjunction with the accompanying drawings, the effects and features of the present disclosure and the methods for achieving them will be apparent. However, the present disclosure is not limited to the embodiments described herein but can be implemented in various forms.

[0042] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings, and the same or corresponding components are denoted by the same reference numerals, and redundant explanations will be omitted.

[0043] In this specification, terms such as first and second are used for the purpose of distinguishing one element from other elements and are not used in a limiting sense.

[0044] In this specification, unless the context is clearly different, singular expressions include plural expressions.

[0045] In this specification, terms such as including or having mean that there are the described features or elements in the specification and do not exclude the possibility of adding one or more other features or elements.

[0046] In this specification, when a part such as a layer, a region, an element, etc. is on another part, this means not only when the part is directly on the other part, but also when other elements are interposed between the part and the other part. When a part such as a layer, a region, an element, etc. is directly on another part, no element may be interposed between the part and the other part.

[0047] In this specification, when layers, regions, components, etc. are connected to each other, the layers, regions, and components are directly connected to each other, and / or the layers, regions, and components may be indirectly connected to each other and other layers, other regions, and other components are interposed between the layers, regions, and components. For example, when layers, regions, components, etc. are electrically connected to each other in this specification, the layers, regions, components, etc. are directly electrically connected to each other, and / or the layers, regions, components, etc. are indirectly electrically connected to each other and other layers, other regions, and other components are interposed between the layers, regions, and components.

[0048] In this specification, the x-axis direction, the y-axis direction, and the z-axis direction are not limited to the three axes on the Cartesian coordinate system, and may be interpreted in a broad sense including them. For example, the x-axis direction, the y-axis direction, and the z-axis direction may be perpendicular to each other, but may represent different directions that are not orthogonal to each other.

[0049] When referred to as a "plan view" herein, this means when viewing the target part from above (e.g., when viewing from a direction perpendicular to the upper surface of the substrate), and when referred to as a "cross-sectional view", this means when viewing the cross-section of the target part vertically cut from the side.

[0050] In this specification, the first component "overlapping" the second component means that the first component is disposed above or below the second component, and at least a part of the first component overlaps the second component in a plan view.

[0051] In this specification, in cases where some embodiments can be implemented in this specification, a specific process sequence may be performed in a different order from the described order. For example, two consecutively described processes may be performed substantially simultaneously, or in an order opposite to the order to be described.

[0052] In the drawings, for ease of explanation, the dimensions of elements may be exaggerated or reduced. For example, since the dimensions and thicknesses of each component shown in the drawings may be arbitrarily indicated for ease of illustration, the present disclosure is not necessarily limited to the illustration.

[0053] Figure 1 is a plan view schematically showing a part of a display device according to an embodiment.

[0054] Reference Figure 1, the display device 1 may include a display area DA in which an image is displayed, and a peripheral area PA at the periphery of the display area DA (e.g., at its periphery in a plan view). The display device 1 may provide a specific image by using light emitted from a plurality of pixels arranged in the display area DA. In an embodiment, as Figure 1 shown, the display area DA may have a rectangular shape in a plan view. However, embodiments of the present disclosure are not necessarily limited thereto, and the display area DA may have various shapes such as other polygonal shapes, circular shapes, elliptical shapes, or amorphous shapes (e.g., having such a shape in a plan view).

[0055] The peripheral area PA may be an area at the periphery of the display area DA and may be a non-display area in which a plurality of pixels are not arranged. In an embodiment, the display area DA may be completely surrounded by the peripheral area PA (e.g., completely surrounded by the peripheral area PA in the x-axis direction and the y-axis direction). Various wirings, circuits, and pads attached to a printed circuit board or a driver integrated circuit (IC) chip for transmitting electrical signals to be applied to the display area DA may be located in the peripheral area PA.

[0056] The display device according to an embodiment of the present disclosure may be a device for displaying at least one moving image and / or still image, and may be used for display screens of various products such as portable electronic devices (e.g., mobile phones, smartphones, tablet personal computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile personal computers (UMPCs)), televisions, laptop computers, monitors, billboards, Internet of Things (IoT) devices, etc. However, embodiments of the present disclosure are not necessarily limited thereto. In addition, the display device 1 according to an embodiment may be used for wearable devices such as smart watches, watch phones, glasses-type displays, or head-mounted displays (HMDs). In addition, the display device 1 according to an embodiment may be used as an instrument panel of a vehicle, a central information display (CID) provided on a central dashboard or instrument panel of a vehicle, an in-vehicle mirror display for replacing a side mirror of a vehicle, and a display provided on a rear surface of a front seat. In addition, the display device 1 may be a flexible device, a rollable device, a foldable device, or a stretchable device.

[0057] Figure 2 is a plan view schematically showing a part of a display device according to an embodiment.

[0058] Referring to Figure 2 , the display device may include a display panel 10 and a printed circuit board 30. The display panel 10 may include a substrate 100. Various components of the display panel 10 may be provided on the substrate 100.

[0059] In an embodiment, the substrate 100 may include glass, metal, or a polymer resin. Figure 2 It is shown that the display panel 10 is not bent and is in a flat state. However, in an embodiment, a part of the display panel 10 may be bent, and thus, the display panel 10 may be disposed on the rear surface of the substrate 100. When the display panel 10 is bent, the substrate 100 may have flexible or bendable characteristics.

[0060] In an embodiment, the substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. In an embodiment, various modifications are possible, such as the substrate 100 may have a multilayer structure including two layers containing a polymer resin and a barrier layer therebetween, where the barrier layer includes an inorganic material (e.g., silicon nitride, silicon oxide, or silicon oxynitride, etc.).

[0061] A plurality of pixels P may be disposed in the display area DA. Each of the plurality of pixels P may be a sub-pixel and may include a display element such as an organic light-emitting diode OLED (see Figure 5 ). In an embodiment, for example, each pixel P may emit red, green, blue, or white light. However, the embodiments of the present disclosure are not necessarily limited thereto.

[0062] The pixel P may be electrically connected to an external circuit disposed in the peripheral area PA. In an embodiment, the first scan driving circuit 11, the second scan driving circuit 12, the emission control driving circuit 13, the terminal 14, the first power supply wiring 15, the second power supply wiring 16, and the data driving circuit 20 may be arranged in the peripheral area PA.

[0063] Each of the first scan driving circuit 11 and the second scan driving circuit 12 may provide a scan signal to the pixel P through a gate signal line GL. The second scan driving circuit 12 may be arranged parallel to the first scan driving circuit 11 (e.g., parallel to it in the y-axis direction), and the display area DA is therebetween (e.g., the display area DA is therebetween in the x-axis direction). A part of the pixels P disposed in the display area DA may be electrically connected to the first scan driving circuit 11, and another part thereof may be connected to the second scan driving circuit 12. In some embodiments, the second scan driving circuit 12 may be omitted, and all the pixels P disposed in the display area DA may be electrically connected to the first scan driving circuit 11.

[0064] In an embodiment, the emission control driving circuit 13 may be arranged at the first scan driving circuit 11 and may provide an emission control signal to the pixel P through an emission control line EL.Figure 2 It is shown that the emission control driving circuit 13 is provided only on one side of the display area DA (for example, the left side in the x-axis direction). However, in some embodiments, the emission control driving circuit 13 may be provided on both sides of the display area DA similar to the first scan driving circuit 11 and the second scan driving circuit 12.

[0065] The terminal 14 may be provided in the second peripheral area PA2 of the substrate 100. In an embodiment, the terminal 14 may not be covered by an insulating layer and may be exposed, and may be electrically connected to the printed circuit board 30. The terminal 34 of the printed circuit board 30 may be electrically connected to the terminal 14 of the display panel 10.

[0066] In an embodiment, the printed circuit board 30 may transmit signals or power of the controller to the display panel 10. The control signals generated in the controller may be transmitted to each of the driving circuits 11, 12, 13, and 20 through the printed circuit board 30. In addition, the controller may transmit a driving voltage (see Figure 5 ELVDD) to the first power supply wiring 15, and may supply a common voltage (see Figure 5 ELVSS) to the second power supply wiring 16. The driving voltage ELVDD may be transmitted to each pixel P through the driving voltage line PL connected to the first power supply wiring 15, and the common voltage ELVSS may be transmitted to the opposite electrode of the pixel P connected to the second power supply wiring 16. The first power supply wiring 15 may have such a shape that it extends from the lower side of the second peripheral area PA2 in one direction (for example, the y-axis direction), and extends in another direction (for example, the x-axis direction) at a portion of the peripheral area PA adjacent to the lower side of the display area DA. The second power supply wiring 16 may be in an annular shape with an open side, and may partially surround the display area DA.

[0067] The controller may generate a data signal (see Figure 5 Dm), and the generated data signal Dm may be transmitted to the input line IL through the data driving circuit 20, and may be transmitted to the pixel P through the data line DL connected to the input line IL. Figure 2 It is shown that the data driving circuit 20 is mounted in the second peripheral area PA2 of the substrate 100. However, the embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment, the data driving circuit 20 may be mounted on the printed circuit board 30.

[0068] In this specification, "line" may mean "wiring". This also applies to the following embodiments and their modifications.

[0069] Figure 3A and Figure 3B respectively schematically show Figure 2A plan view of a part of the display device shown. Figure 3A is Figure 2 a schematic enlarged view of region I of.

[0070] A plurality of pixels (see Figure 2 P) can be arranged in the display area DA. Data signals (see Figure 5 Dm) for controlling the brightness of each pixel P can be applied to the pixels P arranged in the display area DA.

[0071] Refer to Figure 3A and Figure 3B , data lines DL1 to DL6 can be arranged in the display area DA. The data lines DL1 to DL6 are spaced apart from each other in a first direction (e.g., the x-axis direction) and extend in a second direction (e.g., the y-axis direction) crossing the first direction (e.g., the x-axis direction) and are substantially parallel to each other. In some embodiments, the data lines DL1 to DL6 can have a shape extending from the peripheral area PA into the interior of the display area DA as Figure 3A shown. In an embodiment, in addition to the data lines DL1 to DL6, various wirings such as power lines and gate signal lines can also be located inside and outside the display area DA.

[0072] In an embodiment, the peripheral area PA can include a first peripheral area PA1 and a second peripheral area PA2. The first input lines IL1 to the sixth input lines IL6 can be arranged in the second peripheral area PA2. The first input lines IL1 to the sixth input lines IL6 can be connected to a data driving circuit (see Figure 2 20), and can receive data signals Dm. In an embodiment, the first data lines DL1 to the sixth data lines DL6 can be electrically connected to the first input lines IL1 to the sixth input lines IL6 and can transmit the data signals Dm to the pixels in the display area DA.

[0073] For ease of explanation, Figure 3A and Figure 3B show six input lines and six data lines. However, the embodiments of the present disclosure are not necessarily limited thereto, and in some embodiments, the number of input lines and data lines can be greater than six.

[0074] The first input lines IL1 to the sixth input lines IL6 can be sequentially arranged in a direction (e.g., the +x-axis direction) from the edge of the second peripheral area PA2 (e.g., the edge adjacent to the first peripheral area PA1) toward the center of the second peripheral area PA2.

[0075] In an embodiment, the odd-numbered first input line IL1, third input line IL3, and fifth input line IL5 may be electrically connected to the first data line DL1, third data line DL3, and fifth data line DL5 that are arranged adjacent to each other. As Figure 3A and Figure 3B shown, in an embodiment, the first input line IL1, third input line IL3, and fifth input line IL5 may be electrically connected to the first data line DL1, third data line DL3, and fifth data line DL5 through first contact holes CNT1, respectively. Figure 3A and Figure 3B show that the first contact holes CNT1 are located in the peripheral area PA. However, the embodiments of the present disclosure are not necessarily limited thereto. For example, in some embodiments, the first contact holes CNT1 may also be provided in the display area DA.

[0076] In an embodiment, the first data line DL1, third data line DL3, and fifth data line DL5 may receive data signals Dm from the first input line IL1, third input line IL3, and fifth input line IL5. In an embodiment, the first data line DL1, third data line DL3, and fifth data line DL5 may be arranged in a layer different from the first input line IL1, third input line IL3, and fifth input line IL5. In this embodiment, at least one insulating layer may be provided between the first data line DL1, third data line DL3, and fifth data line DL5 and the first input line IL1, third input line IL3, and fifth input line IL5. However, the embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment, the first data line DL1, third data line DL3, and fifth data line DL5 may be arranged in the same layer as the first input line IL1, third input line IL3, and fifth input line IL5. Each of the first input line IL1, third input line IL3, and fifth input line IL5 may also be integrally formed with a corresponding one of the first data line DL1, third data line DL3, and fifth data line DL5.

[0077] In an embodiment, as Figure 3A shown, the even-numbered second input line IL2, fourth input line IL4, and sixth input line IL6 may be electrically connected to the adjacent second data line DL2, fourth data line DL4, and sixth data line DL6 through the first data transmission line DTL1, second data transmission line DTL2, and third data transmission line DTL3. The second data line DL2, fourth data line DL4, and sixth data line DL6 may receive data signals Dm from the second input line IL2, fourth input line IL4, and sixth input line IL6 through the first data transmission line DTL1, second data transmission line DTL2, and third data transmission line DTL3.

[0078] In an embodiment, the first data transmission line DTL1, the second data transmission line DTL2, and the third data transmission line DTL3 may be arranged to span a part of the display area DA, such as arranged to pass through the display area DA. The second input line IL2 may be electrically connected to the second data line DL2 through the first data transmission line DTL1, the fourth input line IL4 may be electrically connected to the fourth data line DL4 through the second data transmission line DTL2, and the sixth input line IL6 may be electrically connected to the sixth data line DL6 through the third data transmission line DTL3.

[0079] In an embodiment, one end of each of the first data transmission line DTL1, the second data transmission line DTL2, and the third data transmission line DTL3 may be electrically connected to the second input line IL2, the fourth input line IL4, and the sixth input line IL6 through the second contact hole CNT2, and the other end of each of the first data transmission line DTL1, the second data transmission line DTL2, and the third data transmission line DTL3 may be electrically connected to the second data line DL2, the fourth data line DL4, and the sixth data line DL6 through the third contact hole CNT3. Figure 3A and Figure 3B It is shown that the second contact hole CNT2 is provided in the peripheral area PA. However, the embodiments of the present disclosure are not necessarily limited thereto. For example, the second contact hole CNT2 may also be provided in the display area DA. The third contact hole CNT3 may also be provided in the display area DA.

[0080] However, the embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment, the first data transmission line DTL1, the second data transmission line DTL2, and the third data transmission line DTL3 may be arranged in the same layer as the second input line IL2, the fourth input line IL4, and the sixth input line IL6. Each of the first data transmission line DTL1, the second data transmission line DTL2, and the third data transmission line DTL3 may be integrally formed with a corresponding one of the second input line IL2, the fourth input line IL4, and the sixth input line IL6.

[0081] With this structure, the second input line IL2 may be configured to transmit the data signal Dm to the second data line DL2, the fourth input line IL4 may be configured to transmit the data signal Dm to the fourth data line DL4, and the sixth input line IL6 may be configured to transmit the data signal Dm to the sixth data line DL6.

[0082] Figure 3B Is shown in detail Figure 3A the configuration of the first data transmission line DTL1, the second data transmission line DTL2, and the third data transmission line DTL3.

[0083] As referenced Figure 3AAs described, the second input line IL2, the fourth input line IL4, and the sixth input line IL6 can be electrically connected to the second data line DL2, the fourth data line DL4, and the sixth data line DL6 through the first data transmission line DTL1, the second data transmission line DTL2, and the third data transmission line DTL3. In this embodiment, the first data transmission line DTL1 can include a first vertical connection line DV1 and a first horizontal connection line DH1. Similarly, the second data transmission line DTL2 can include a second vertical connection line DV2 and a second horizontal connection line DH2. The third data transmission line DTL3 can include a third vertical connection line DV3 and a third horizontal connection line DH3.

[0084] The first vertical connection line DV1, the second vertical connection line DV2, and the third vertical connection line DV3 can be arranged to be substantially parallel to the first data line DL1 to the sixth data line DL6. In an embodiment, the first horizontal connection line DH1, the second horizontal connection line DH2, and the third horizontal connection line DH3 can extend in a first direction (e.g., the x-axis direction) that intersects a second direction (e.g., the y-axis direction), wherein the first data line DL1 to the sixth data line DL6 extend in the second direction (e.g., the y-axis direction).

[0085] In an embodiment, each of the second input line IL2, the fourth input line IL4, and the sixth input line IL6 can be electrically connected to the first vertical connection line DV1, the second vertical connection line DV2, and the third vertical connection line DV3 through the second contact hole CNT2, respectively. In an embodiment, each of the first horizontal connection line DH1, the second horizontal connection line DH2, and the third horizontal connection line DH3 can be electrically connected to the first vertical connection line DV1, the second vertical connection line DV2, and the third vertical connection line DV3 through a first connection contact hole DH-CNT1 located at one end of each of the first horizontal connection line DH1, the second horizontal connection line DH2, and the third horizontal connection line DH3, respectively. Each of the first horizontal connection line DH1, the second horizontal connection line DH2, and the third horizontal connection line DH3 can be electrically connected to the second data line DL2, the fourth data line DL4, and the sixth data line DL6 through a second connection contact hole DH-CNT2 located at the other end of each of the first horizontal connection line DH1, the second horizontal connection line DH2, and the third horizontal connection line DH3, respectively. The second connection contact hole DH-CNT2 can be Figure 3A the third contact hole CNT3.

[0086] In an embodiment, the first additional vertical connection line DV1', the second additional vertical connection line DV2', and the third additional vertical connection line DV3' may be arranged to be substantially parallel to the second data line DL2, the fourth data line DL4, and the sixth data line DL6 (e.g., substantially parallel to the second data line DL2, the fourth data line DL4, and the sixth data line DL6 in the y-axis direction). The first additional vertical connection line DV1', the second additional vertical connection line DV2', and the third additional vertical connection line DV3' may be configured to reduce the structural differences between the pixels through which the first vertical connection line DV1, the second vertical connection line DV2, and the third vertical connection line DV3 pass and the pixels through which the first vertical connection line DV1, the second vertical connection line DV2, and the third vertical connection line DV3 do not pass. Accordingly, a display device capable of displaying a high-quality image by reducing the luminance deviation between pixels can be achieved.

[0087] In an embodiment, the first data line DL1 to the sixth data line DL6, the first vertical connection line DV1 to the third vertical connection line DV3, and the first additional vertical connection line DV1' to the third additional vertical connection line DV3' may be located in the same layer. The first horizontal connection line DH1 to the third horizontal connection line DH3 may be located in a layer different from the first data line DL1 to the sixth data line DL6. In some embodiments, specific components located in the same layer may mean that these components are simultaneously formed of the same material by the same mask process. In this embodiment, these components include materials having the same layer structure and the same characteristics and the like.

[0088] When viewed in a direction perpendicular to the substrate 100 (e.g., the z-axis direction), the first horizontal connection line DH1 may cross the first data line DL1, the second horizontal connection line DH2 may cross the first data line DL1 to the third data line DL3, and the third horizontal connection line DH3 may cross the first data line DL1 to the fifth data line DL5. Accordingly, in order to prevent the first horizontal connection line DH1 to the third horizontal connection line DH3 from contacting the intersecting data lines, as described above, the first horizontal connection line DH1, the second horizontal connection line DH2, and the third horizontal connection line DH3 may be located below the first data line DL1 to the sixth data line DL6.

[0089] As Figure 3B shown, the display device according to an embodiment may further include dummy wirings.

[0090] For example, the display device may include a first auxiliary horizontal connection line ADH1 that is spaced apart from the first horizontal connection line DH1 (e.g., spaced apart therefrom in the x-axis direction), is electrically insulated from the first horizontal connection line DH1 and the second data line DL2, and has the same extension axis as the extension axis of the first horizontal connection line DH1. For example, in an embodiment, the display device may include a first auxiliary horizontal connection line ADH1 located on one side of the first horizontal connection line DH1 (e.g., one side in the -x-axis direction), and a first auxiliary horizontal connection line ADH1 located on the other side of the first horizontal connection line DH1 (e.g., the other side in the +x-axis direction). Similarly, the display device may include a second auxiliary horizontal connection line ADH2 located on one side of the second horizontal connection line DH2 (e.g., one side in the -x-axis direction) and a second auxiliary horizontal connection line ADH2 located on the other side of the second horizontal connection line DH2 (e.g., the other side in the +x-axis direction), a third auxiliary horizontal connection line ADH3 located on one side of the third horizontal connection line DH3 (e.g., one side in the -x-axis direction), and a third auxiliary horizontal connection line ADH3 located on the other side of the third horizontal connection line DH3 (e.g., the other side in the +x-axis direction).

[0091] Accordingly, the structural difference between the pixels through which the first horizontal connection line DH1 to the third horizontal connection line DH3 pass and the pixels through which the first horizontal connection line DH1 to the third horizontal connection line DH3 do not pass can be reduced. As a result, a display device capable of displaying a high-quality image by reducing the brightness difference that appears in the pixels when the same electrical signal is applied to the pixels can be achieved. In an embodiment, the first auxiliary horizontal connection line ADH1 to the third auxiliary horizontal connection line ADH3 and the first horizontal connection line DH1 to the third horizontal connection line DH3 may be provided in the same layer.

[0092] Similarly, the display device according to an embodiment may include a first auxiliary vertical connection line ADV1 that is spaced apart from the first vertical connection line DV1 (e.g., spaced apart therefrom in the y-axis direction), is electrically insulated from the first vertical connection line DV1 and the first horizontal connection line DH1, has the same extension axis as the extension axis of the first vertical connection line DV1, and is located on one side of the first vertical connection line DV1 (e.g., one side in the +y-axis direction). Similarly, the display device may include a second auxiliary vertical connection line ADV2 located on one side of the second vertical connection line DV2 (e.g., one side in the +y-axis direction), and a third auxiliary vertical connection line ADV3 located on one side of the third vertical connection line DV3 (e.g., one side in the +y-axis direction). The first auxiliary vertical connection line ADV1 to the third auxiliary vertical connection line ADV3 and the first vertical connection line DV1 to the third vertical connection line DV3 may be provided in the same layer.

[0093] To this end, the first auxiliary vertical connection line ADV1, the second auxiliary vertical connection line ADV2, and the third auxiliary vertical connection line ADV3 can reduce the structural difference between the pixels through which the first vertical connection line DV1 to the third vertical connection line DV3 pass and the pixels through which the first vertical connection line DV1 to the third vertical connection line DV3 do not pass. Accordingly, a display device can be realized in which the luminance deviation between pixels can be reduced, and thus a high-quality image can be displayed.

[0094] In an embodiment, the first additional vertical connection lines DV1' to DV3', the first auxiliary horizontal connection lines ADH1 to ADH3, and the first auxiliary vertical connection lines ADV1 to ADV3 can be configured to transmit a constant voltage (e.g., a common voltage ELVSS). The first additional vertical connection lines DV1' to DV3', the first auxiliary horizontal connection lines ADH1 to ADH3, and the first auxiliary vertical connection lines ADV1 to ADV3 can be electrically connected to each other and can form a constant voltage mesh structure.

[0095] Figure 4A and Figure 4B are respectively schematic plan views showing Figure 2 a part of the display device shown.

[0096] Figure 4A Similar to Figure 3A , however, the difference is that each of the first data transmission line DTL1, the second data transmission line DTL2, and the third data transmission line DTL3 is connected to the second data line DL2, the fourth data line DL4, and the sixth data line DL6 in the first peripheral region PA1.

[0097] Referring to Figure 4A , the first input line IL1 to the sixth input line IL6 can be sequentially arranged in a direction (e.g., the +x-axis direction) from the edge of the second peripheral region PA2 (the edge adjacent to the first peripheral region PA1) toward the center of the second peripheral region PA2.

[0098] In an embodiment, the odd-numbered first input line IL1, third input line IL3, and fifth input line IL5 can be electrically connected to the first data line DL1, third data line DL3, and fifth data line DL5 arranged adjacent to each other. In an embodiment, each of the first input line IL1, third input line IL3, and fifth input line IL5 can be electrically connected to the first data line DL1, third data line DL3, and fifth data line DL5 through the first contact hole CNT1, respectively.

[0099] In an embodiment, the even-numbered second input lines IL2, fourth input lines IL4, and sixth input lines IL6 may be electrically connected to adjacent second data lines DL2, fourth data lines DL4, and sixth data lines DL6 through a first data transmission line DTL1, a second data transmission line DTL2, and a third data transmission line DTL3. One end of each of the first data transmission line DTL1, the second data transmission line DTL2, and the third data transmission line DTL3 may be electrically connected to the second input line IL2, the fourth input line IL4, and the sixth input line IL6 through a second contact hole CNT2, and the other end of each of the first data transmission line DTL1, the second data transmission line DTL2, and the third data transmission line DTL3 may be electrically connected to the second data line DL2, the fourth data line DL4, and the sixth data line DL6 in a first peripheral region PA1.

[0100] Figure 4B is shown in detail Figure 4A the configurations of the first data transmission line DTL1, the second data transmission line DTL2, and the third data transmission line DTL3.

[0101] As described in Figure 4A In an embodiment, the second input lines IL2, fourth input lines IL4, and sixth input lines IL6 may be electrically connected to the second data lines DL2, fourth data lines DL4, and sixth data lines DL6 through a first data transmission line DTL1, a second data transmission line DTL2, and a third data transmission line DTL3. In this embodiment, the first data transmission line DTL1 may include a first vertical connection line DV1, a first horizontal connection line DH1, and a first additional vertical connection line DV1'. Similarly, the second data transmission line DTL2 may include a second vertical connection line DV2, a second horizontal connection line DH2, and a second additional vertical connection line DV2'. The third data transmission line DTL3 may include a third vertical connection line DV3, a third horizontal connection line DH3, and a third additional vertical connection line DV3'.

[0102] In an embodiment, the first vertical connection lines DV1 to DV3 and the first additional vertical connection lines DV1' to DV3' may extend in a second direction (e.g., the y-axis direction) and may be arranged substantially parallel to the first data lines DL1 to DL6. The first horizontal connection lines DH1 to DH3 may extend in a first direction (e.g., the x-axis direction).

[0103] In an embodiment, each of the second input line IL2, the fourth input line IL4, and the sixth input line IL6 may be electrically connected to the first vertical connection line DV1, the second vertical connection line DV2, and the third vertical connection line DV3 through the second contact hole CNT2, respectively. Each of the first horizontal connection line DH1, the second horizontal connection line DH2, and the third horizontal connection line DH3 may be electrically connected to the first vertical connection line DV1, the second vertical connection line DV2, and the third vertical connection line DV3 through the first connection contact hole DH-CNT1 located at one end of each of the first horizontal connection line DH1, the second horizontal connection line DH2, and the third horizontal connection line DH3, respectively. Each of the first horizontal connection line DH1, the second horizontal connection line DH2, and the third horizontal connection line DH3 may be electrically connected to the first additional vertical connection line DV1', the second additional vertical connection line DV2', and the third additional vertical connection line DV3' through the second connection contact hole DH-CNT2 located at the other end of each of the first horizontal connection line DH1, the second horizontal connection line DH2, and the third horizontal connection line DH3, respectively. Each of the first additional vertical connection line DV1', the second additional vertical connection line DV2', and the third additional vertical connection line DV3' may be integrally formed with a corresponding one of the second data line DL2, the fourth data line DL4, and the sixth data line DL6.

[0104] In an embodiment, the first data line DL1 to the sixth data line DL6, the first vertical connection line DV1 to the third vertical connection line DV3, and the first additional vertical connection line DV1' to the third additional vertical connection line DV3' may be located in the same layer. The first horizontal connection line DH1 to the third horizontal connection line DH3 may be located in a layer different from that of the first data line DL1 to the sixth data line DL6.

[0105] In an embodiment, the display device may include a first auxiliary horizontal connection line ADH1 that is spaced apart from the first horizontal connection line DH1 (e.g., spaced apart therefrom in the x-axis direction), electrically insulated from the first horizontal connection line DH1 and the second data line DL2, and has the same extension axis as the extension axis of the first horizontal connection line DH1. The display device may include a first auxiliary horizontal connection line ADH1 located on one side of the first horizontal connection line DH1 (e.g., one side in the -x axis direction), and a first auxiliary horizontal connection line ADH1 located on the other side of the first horizontal connection line DH1 (e.g., the other side in the +x axis direction). Similarly, the display device may include a second auxiliary horizontal connection line ADH2 located on one side of the second horizontal connection line DH2 (e.g., one side in the -x axis direction) and a second auxiliary horizontal connection line ADH2 located on the other side of the second horizontal connection line DH2 (e.g., the other side in the +x axis direction), a third auxiliary horizontal connection line ADH3 located on one side of the third horizontal connection line DH3 (e.g., one side in the -x axis direction) and a third auxiliary horizontal connection line ADH3 located on the other side of the third horizontal connection line DH3 (e.g., the other side in the +x axis direction). The first auxiliary horizontal connection line ADH1 to the third auxiliary horizontal connection line ADH3 and the first horizontal connection line DH1 to the third horizontal connection line DH3 may be provided in the same layer.

[0106] Similarly, the display device according to an embodiment of the present disclosure may include a first auxiliary additional vertical connection line ADV1' that is spaced apart from the first additional vertical connection line DV1' (e.g., spaced apart therefrom in the y-axis direction), electrically insulated from the first additional vertical connection line DV1' and the first horizontal connection line DH1, has the same extension axis as the extension axis of the first additional vertical connection line DV1', and is located on one side of the first additional vertical connection line DV1' (e.g., one side in the +y axis direction). Similarly, the display device may include a second auxiliary additional vertical connection line ADV2' located on one side of the second additional vertical connection line DV2' (e.g., one side in the +y axis direction), and a third auxiliary additional vertical connection line ADV3' located on one side of the third additional vertical connection line DV3' (e.g., one side in the +y axis direction). The first auxiliary additional vertical connection line ADV1' to the third auxiliary additional vertical connection line ADV3', and the first additional vertical connection line DV1' to the third additional vertical connection line DV3' may be provided in the same layer.

[0107] In addition, the display device may include a first auxiliary vertical connection line ADV1, which is spaced apart from the first vertical connection line DV1 (e.g., spaced apart therefrom in the y-axis direction), electrically insulated from the first vertical connection line DV1 and the first horizontal connection line DH1, has the same extension axis as the extension axis of the first vertical connection line DV1, and is located on one side of the first vertical connection line DV1 (e.g., on one side in the +y-axis direction). Similarly, the display device may include a second auxiliary vertical connection line ADV2 located on one side of the second vertical connection line DV2 (e.g., on one side in the +y-axis direction), and a third auxiliary vertical connection line ADV3 located on one side of the third vertical connection line DV3 (e.g., on one side in the +y-axis direction). The first auxiliary vertical connection line ADV1 to the third auxiliary vertical connection line ADV3 and the first vertical connection line DV1 to the third vertical connection line DV3 may be provided in the same layer.

[0108] In an embodiment, the first auxiliary additional vertical connection lines ADV1' to the third auxiliary additional vertical connection lines ADV3', the first auxiliary horizontal connection lines ADH1 to the third auxiliary horizontal connection lines ADH3, and the first auxiliary vertical connection lines ADV1 to the third auxiliary vertical connection lines ADV3 may be configured to transmit a constant voltage (e.g., a common voltage ELVSS). In an embodiment, the first auxiliary additional vertical connection lines ADV1' to the third auxiliary additional vertical connection lines ADV3', the first auxiliary horizontal connection lines ADH1 to the third auxiliary horizontal connection lines ADH3, and the first auxiliary vertical connection lines ADV1 to the third auxiliary vertical connection lines ADV3 may be electrically connected to each other and may form a constant voltage mesh structure.

[0109] Figure 5 is an equivalent circuit diagram of a pixel of a display device according to an embodiment.

[0110] Reference Figure 5 , a pixel P may include an organic light-emitting diode OLED and a pixel circuit PC electrically connected to the organic light-emitting diode OLED. In an embodiment, the pixel circuit PC may include a first transistor T1 to an eighth transistor T8 and a storage capacitor Cst. The first transistor T1 may be a driving transistor that outputs a driving current Id corresponding to a data signal Dm, and the second transistor T2 to the eighth transistor T8 may be switching transistors for transmitting signals.

[0111] The first terminal (e.g., the first electrode) of each of the first transistor T1 to the eighth transistor T8 may be a source or a drain, and its second terminal (e.g., the second electrode) may be a terminal different from the first terminal. For example, in an embodiment where the first terminal is a drain, the second terminal may be a source.

[0112] The node connected to (e.g., electrically connected to) the gate of the first transistor T1 can be defined as the first node N1, the node connected to (e.g., electrically connected to) the first terminal S of the first transistor T1 can be defined as the second node N2, and the node connected to (e.g., electrically connected to) the second terminal D of the first transistor T1 can be defined as the third node N3.

[0113] In an embodiment, the pixel circuit PC of each pixel P can be connected to (e.g., electrically connected to) a first gate signal line GWL for transmitting a first gate signal GW, a second gate signal line GIL for transmitting a second gate signal GI, a third gate signal line GCL for transmitting a third gate signal GC, a fourth gate signal line GBL for transmitting a fourth gate signal GB, an emission control signal line EML for transmitting an emission control signal EM, a data line DL for transmitting a data signal Dm, a driving voltage line PL for transmitting a driving voltage ELVDD, a first initialization voltage line VL1 for transmitting a first initialization voltage VINT, a second initialization voltage line VL2 for transmitting a second initialization voltage VAINT, and a conduction bias voltage line VL3 for transmitting a conduction bias voltage VOBS.

[0114] In an embodiment, the first transistor T1 can include a gate (e.g., gate electrode) connected to (e.g., electrically connected to) the first node N1, a first terminal S connected to (e.g., electrically connected to) the second node N2, and a second terminal D connected to (e.g., electrically connected to) the third node N3. The first terminal S of the first transistor T1 can be connected to (e.g., electrically connected to) the driving voltage line PL via a fifth transistor T5, and the second terminal D of the first transistor T1 can be connected to (e.g., electrically connected to) the pixel electrode (e.g., anode) of the organic light emitting diode OLED via a sixth transistor T6. The first transistor T1 can control the amount of the driving current Id flowing through the pixel electrode of the organic light emitting diode OLED by receiving the data signal Dm according to the switching operation of the second transistor T2.

[0115] The second transistor T2 can be connected between the data line DL and the first transistor T1. In an embodiment, the second transistor T2 can include a gate connected to (e.g., electrically connected to) the first gate signal line GWL, a first terminal connected to (e.g., electrically connected to) the data line DL, and a second terminal connected to (e.g., electrically connected to) the second node N2. The second transistor T2 can be turned on by the first gate signal GW transmitted to the first gate signal line GWL, can be configured to electrically connect the data line DL to the second node N2, and can transmit the data signal Dm from the data line DL to the second node N2.

[0116] The third transistor T3 may be connected between the gate of the first transistor T1 and the second terminal D of the first transistor T1. In an embodiment, the third transistor T3 may include a gate connected to (e.g., electrically connected to) a third gate signal line GCL, a first terminal connected to (e.g., electrically connected to) the first node N1, and a second terminal connected to (e.g., electrically connected to) the third node N3. The third transistor T3 may be turned on by a third gate signal GC transmitted to the third gate signal line GCL, thereby connecting the first node N1 and the third node N3 diodically to each other.

[0117] The fourth transistor T4 may be connected between the first initialization voltage line VL1 and the gate of the first transistor T1. In an embodiment, the fourth transistor T4 may include a gate connected to (e.g., electrically connected to) a second gate signal line GIL, a first terminal connected to (e.g., electrically connected to) the first node N1, and a second terminal connected to (e.g., electrically connected to) the first initialization voltage line VL1. The fourth transistor T4 may be turned on by a second gate signal GI transmitted to the second gate signal line GIL and may transmit a first initialization voltage VINT from the first initialization voltage line VL1 to the first node N1.

[0118] The fifth transistor T5 may be connected between the drive voltage line PL and the first transistor T1. In an embodiment, the fifth transistor T5 may include a gate connected to (e.g., electrically connected to) an emission control signal line EML, a first terminal connected to (e.g., electrically connected to) the drive voltage line PL, and a second terminal connected to (e.g., electrically connected to) the second node N2.

[0119] The sixth transistor T6 may be connected between the first transistor T1 and the organic light-emitting diode OLED. In an embodiment, the sixth transistor T6 may include a gate connected to (e.g., electrically connected to) an emission control signal line EML, a first terminal connected to (e.g., electrically connected to) the third node N3, and a second terminal connected to (e.g., electrically connected to) the pixel electrode of the organic light-emitting diode OLED. In an embodiment, the fifth transistor T5 and the sixth transistor T6 may be turned on simultaneously by an emission control signal EM transmitted to the emission control signal line EML, such that a drive current Id may flow through the pixel electrode of the organic light-emitting diode OLED.

[0120] The seventh transistor T7 may be connected between the second initialization voltage line VL2 and the organic light-emitting diode OLED. In an embodiment, the seventh transistor T7 may include a gate connected to (e.g., electrically connected to) the fourth gate signal line GBL, a first terminal connected to (e.g., electrically connected to) the second initialization voltage line VL2, and a second terminal connected to (e.g., electrically connected to) the pixel electrode of the organic light-emitting diode OLED. In an embodiment, the seventh transistor T7 may be turned on by the fourth gate signal GB transmitted to the fourth gate signal line GBL, and may transmit the second initialization voltage VAINT from the second initialization voltage line VL2 to the pixel electrode of the organic light-emitting diode OLED.

[0121] The eighth transistor T8 may be connected between the conduction bias voltage line VL3 and the first transistor T1. In an embodiment, the eighth transistor T8 may include a gate connected to (e.g., electrically connected to) the fourth gate signal line GBL, a first terminal connected to (e.g., electrically connected to) the second node N2, and a second terminal connected to (e.g., electrically connected to) the conduction bias voltage line VL3. In an embodiment, the eighth transistor T8 may be turned on by the fourth gate signal GB transmitted to the fourth gate signal line GBL, and may transmit the conduction bias voltage VOBS from the conduction bias voltage line VL3 to the second node N2.

[0122] In an embodiment, the display device may support variable refresh rate (VRR). The refresh rate is the frequency at which the data signal Dm is substantially written to the first transistor T1 of the pixel P, and may represent the screen scanning rate, the screen refresh rate, and the number of image frames played within one second. One frame may include an address scanning period and a self-scanning period according to the refresh rate. In an embodiment of driving the display device at a low refresh rate, the conduction bias voltage VOBS may be applied to the second node N2 during the self-scanning period, thereby preventing the first transistor T1 from deteriorating.

[0123] The storage capacitor Cst may be connected between the driving voltage line PL and the gate of the first transistor T1. In an embodiment, the first capacitor electrode CE1 of the storage capacitor Cst may be connected to (e.g., electrically connected to) the first node N1, and the second capacitor electrode CE2 may be connected to (e.g., electrically connected to) the driving voltage line PL. The storage capacitor Cst may store the threshold voltage of the first transistor T1 and the voltage corresponding to the data signal Dm.

[0124] An organic light-emitting diode (OLED) may include a pixel electrode (e.g., an anode), a counter electrode facing the pixel electrode (e.g., a cathode), and an intermediate layer between the pixel electrode and the counter electrode. In an embodiment, the counter electrode may receive a common voltage ELVSS and may be a common electrode shared by a plurality of pixels P. However, embodiments of the present disclosure are not necessarily limited thereto.

[0125] Some of the first transistor T1 to the eighth transistor T8 may be P-channel transistors, while the other part may be N-channel transistors. In an embodiment, the first transistor T1, the second transistor T2, and the fifth transistor T5 to the eighth transistor T8 may be P-channel transistors, and the third transistor T3 and the fourth transistor T4 may be N-channel transistors. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in some embodiments, all of the first transistor T1 to the eighth transistor T8 may be N-channel transistors, or they may all be P-channel transistors.

[0126] In an embodiment, some of the transistors included in the pixel circuit PC may be oxide thin-film transistors, and the other transistors may be silicon thin-film transistors. The oxide thin-film transistor may be a low-temperature polycrystalline oxide (LTPO) thin-film transistor, in which the active pattern (e.g., the semiconductor layer) includes an oxide. The silicon thin-film transistor may be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, in which the active pattern (e.g., the semiconductor layer) includes amorphous silicon and polycrystalline silicon, etc.

[0127] Figure 5 It is shown that the pixel circuit PC includes the first transistor T1 to the eighth transistor T8 and the storage capacitor Cst. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in some embodiments, some of the transistors and capacitors may be omitted, or additional transistors and capacitors may be added.

[0128] Figure 6 is a layout diagram schematically showing a part of a display device according to an embodiment, and Figures 7 to 13 are respectively schematically showing according to each layer Figure 6 the layout diagram of a part of the display device shown.

[0129] Referring to Figure 6 , the display area (see Figure 1 DA) may include where pixel circuits are arranged (see Figure 5Multiple pixel regions PCA and PCB of a PC). In two first pixel regions PCA and a second pixel region PCB adjacent to each other along a first direction (e.g., the x-axis direction), pixel circuits PC linearly symmetric with respect to a virtual straight line VSL extending in a second direction (e.g., the y-axis direction) can be provided. Unless otherwise specified, components of the pixel circuit PC arranged in the first pixel region PCA can be linearly symmetric with components of the pixel circuit PC arranged in the second pixel region PCB. For ease of description, reference numerals are assigned only to one of the symmetric components. Hereinafter, this will be described in conjunction with Figures 6 to 13 together.

[0130] The first conductive layer 1100 can be arranged on a substrate (see Figure 2 100). In an embodiment, the first conductive layer 1100 can include a conductive material containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and can have a multi-layer or single-layer structure including the materials described above.

[0131] Reference Figure 7 , the first conductive layer 1100 can include a first conductive pattern 1110. The first conductive pattern 1110 can include a first connection portion longitudinally extending in a first direction (e.g., the x-axis direction), a second connection portion longitudinally extending in a second direction (e.g., the y-axis direction), and a body portion. The body portion of the first conductive pattern 1110 can overlap with the channel region A1 of the first transistor T1 (e.g., overlap with it in the z-axis direction), so that the first transistor T1 can be prevented from being deteriorated by external light or the like.

[0132] For ease of description, Figure 8 a first semiconductor layer 1200 and a second conductive layer 1300 overlapping each other (e.g., overlapping each other in the z-axis direction) are shown. Reference Figure 8 , the first semiconductor layer 1200 can be arranged on the first conductive layer 1100, and the second conductive layer 1300 can be arranged on the first semiconductor layer 1200. In an embodiment, at least one insulating layer can be respectively arranged between the first conductive layer 1100 and the first semiconductor layer 1200 and between the first semiconductor layer 1200 and the second conductive layer 1300 (e.g., arranged between them in the z-axis direction).

[0133] In an embodiment, the first semiconductor layer 1200 can include a silicon-based semiconductor material, such as amorphous silicon or polycrystalline silicon. The second conductive layer 1300 can include a conductive material containing Mo, Al, Cu, Ti, etc., and can have a multi-layer or single-layer structure including the materials described above. However, the embodiments of the present disclosure are not necessarily limited thereto.

[0134] In an embodiment, the first semiconductor layer 1200 may include a first semiconductor pattern 1201 and a second semiconductor pattern 1202 that are linearly symmetric with respect to a virtual straight line VSL. Each of the first semiconductor pattern 1201 and the second semiconductor pattern 1202 may include a channel region A1 of the first transistor T1, a channel region A2 of the second transistor T2, a channel region A5 of the fifth transistor T5, a channel region A6 of the sixth transistor T6, a channel region A7 of the seventh transistor T7, and a channel region A8 of the eighth transistor T8. Source regions and drain regions may be disposed on both sides of each of the channel regions A1, A2, A5, A6, A7, and A8.

[0135] In an embodiment, the second conductive layer 1300 may include a second conductive pattern 1310, a third conductive pattern 1320, a fourth conductive pattern 1330, a first gate signal line GWL, a second gate signal line GIL, and a fourth gate signal line GBL. In an embodiment, the second conductive pattern 1310, the third conductive pattern 1320, and the fourth conductive pattern 1330 may have an island configuration. Each of the first gate signal line GWL, the second gate signal line GIL, and the fourth gate signal line GBL may extend longitudinally substantially in a first direction (e.g., the x-axis direction). The first gate signal line GWL may be configured to transmit a first gate signal (see Figure 5 GW) to pixel circuits arranged in the same pixel row, the second gate signal line GIL may be configured to transmit a second gate signal (see Figure 5 GI) to pixel circuits arranged in the same pixel row, and the fourth gate signal line GBL may be configured to transmit a fourth gate signal (see Figure 5 GB) to pixel circuits arranged in the same pixel row.

[0136] In an embodiment, the channel region A1 of the first transistor T1 may overlap with the second conductive pattern 1310 (e.g., overlap therewith in the z-axis direction), and may have a curved shape. The second conductive pattern 1310 may be a gate electrode G1 of the first transistor T1. A source region S1 and a drain region D1 may be disposed on both sides of the channel region A1 of the first transistor T1.

[0137] The channel region A2 of the second transistor T2 may overlap with the first gate signal line GWL (e.g., overlap therewith in the z-axis direction). A portion of the first gate signal line GWL that overlaps with the channel region A2 of the second transistor T2 may be a gate electrode G2 of the second transistor T2. A source region S2 and a drain region D2 may be disposed on both sides of the channel region A2 of the second transistor T2. The drain region D2 of the second transistor T2 may be connected to the source region S1 of the first transistor T1.

[0138] The channel region A5 of the fifth transistor T5 may overlap with the third conductive pattern 1320 (e.g., overlap therewith in the z-axis direction). The third conductive pattern 1320 may be the gate electrode G5 of the fifth transistor T5. The source region S5 and the drain region D5 may be disposed on both sides of the channel region A5 of the fifth transistor T5. The drain region D5 of the fifth transistor T5 may be connected to the source region S1 of the first transistor T1.

[0139] The channel region A6 of the sixth transistor T6 may overlap with the fourth conductive pattern 1330 (e.g., overlap therewith in the z-axis direction). The fourth conductive pattern 1330 may be the gate electrode G6 of the sixth transistor T6. The source region S6 and the drain region D6 may be disposed on both sides of the channel region A6 of the sixth transistor T6. The source region S6 of the sixth transistor T6 may be connected to the drain region D1 of the first transistor T1.

[0140] The channel region A7 of the seventh transistor T7 may overlap with the fourth gate signal line GBL (e.g., overlap therewith in the z-axis direction). The portion of the fourth gate signal line GBL that overlaps with the channel region A7 of the seventh transistor T7 (e.g., overlaps therewith in the z-axis direction) may be the gate electrode G7 of the seventh transistor T7. The source region S7 and the drain region D7 may be disposed on both sides of the channel region A7 of the seventh transistor T7. The drain region D7 of the seventh transistor T7 may be connected to the drain region D6 of the sixth transistor T6.

[0141] The channel region A8 of the eighth transistor T8 may overlap with the fourth gate signal line GBL (e.g., overlap therewith in the z-axis direction). The portion of the fourth gate signal line GBL that overlaps with the channel region A8 of the eighth transistor T8 (e.g., overlaps therewith in the z-axis direction) may be the gate electrode G8 of the eighth transistor T8. The source region S8 and the drain region D8 may be disposed on both sides of the channel region A8 of the eighth transistor T8. The drain region D8 of the eighth transistor T8 may be connected to the source region S1 of the first transistor T1.

[0142] Reference Figure 9 ,The third conductive layer 1400 may be disposed on the second conductive layer 1300. At least one insulating layer may be disposed between the second conductive layer 1300 and the third conductive layer 1400 (e.g., disposed therebetween in the z-axis direction). In an embodiment, the third conductive layer 1400 may include a conductive material including Mo, Al, Cu, Ti, etc., and may have a multi-layer or single-layer structure including the above-described materials. In an embodiment, the third conductive layer 1400 may include a fifth conductive pattern 1410, a sixth conductive pattern 1420, and a first initialization voltage line VL1.

[0143] In an embodiment, the fifth conductive pattern 1410 may include a connection portion and a body portion that extend longitudinally in a first direction (e.g., the x-axis direction). In an embodiment, the body portion of the fifth conductive pattern 1410 may overlap the second conductive pattern 1310 (e.g., overlap therewith in the z-axis direction), and may form a storage capacitor (see Figure 5 for Cst). For example, the second conductive pattern 1310 may be a first capacitor electrode of the storage capacitor Cst (see Figure 5 for CE1), and the fifth conductive pattern 1410 may be a second capacitor electrode of the storage capacitor Cst (see Figure 5 for CE2). The fifth conductive pattern 1410 may include a first hole 1410h that exposes a part of the second conductive pattern 1310.

[0144] In an embodiment, the sixth conductive pattern 1420 may be arranged in an island pattern. The sixth conductive pattern 1420 may overlap the channel region A3 of a third transistor T3 to be described later (e.g., overlap therewith in the z-axis direction).

[0145] In an embodiment, the first initialization voltage line VL1 may include a first portion VL1a that extends longitudinally substantially in the first direction (e.g., the x-axis direction), and a second portion VL1b that protrudes from the first portion VL1a in a second direction (e.g., the y-axis direction). In an embodiment, the second portion VL1b of the first initialization voltage line VL1 may not be linearly symmetric, but may be arranged only in the first pixel region PCA. The first initialization voltage line VL1 may be configured to transmit a first initialization voltage (see Figure 5 for VINT) to pixel circuits arranged in the same pixel row.

[0146] For ease of description, Figure 10 a second semiconductor layer 1500 and a fourth conductive layer 1600 that overlap each other (e.g., overlap each other in the z-axis direction) are shown. Referring to Figure 10 , the second semiconductor layer 1500 may be disposed on the third conductive layer 1400, and the fourth conductive layer 1600 may be disposed on the second semiconductor layer 1500. At least one insulating layer may be respectively disposed between the third conductive layer 1400 and the second semiconductor layer 1500 and between the second semiconductor layer 1500 and the fourth conductive layer 1600 (e.g., disposed therebetween in the z-axis direction).

[0147] In an embodiment, the second semiconductor layer 1500 may include an oxide-based semiconductor material, for example, an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cerium (Ce), and zinc (Zn). In an embodiment, the second semiconductor layer 1500 may be In-Ga-Zn-O (IGZO) or In-Sn-Ga-Zn-O (ITGZO).

[0148] The fourth conductive layer 1600 may include a conductive material including Mo, Al, Cu, Ti, etc., and may have a multi-layer or single-layer structure including the materials described above.

[0149] The second semiconductor layer 1500 may include a third semiconductor pattern 1501. In an embodiment, the third semiconductor pattern 1501 may include a first portion 1501a longitudinally extending in a first direction (e.g., the x-axis direction), a second portion 1501b protruding from the first portion 1501a in a second direction (e.g., the y-axis direction), and a third portion 1501c protruding from the first portion 1501a in the second direction (e.g., the y-axis direction). In an embodiment, the second portion 1501b of the second semiconductor layer 1500 may be linearly symmetric with respect to a virtual straight line VSL. In contrast, the third portion 1501c of the third semiconductor pattern 1501 may not be linearly symmetric, but may be disposed only in the second pixel region PCB.

[0150] In an embodiment, the second portion 1501b of the third semiconductor pattern 1501 may include a channel region A3 of the third transistor T3 and a channel region A4 of the fourth transistor T4. In an embodiment, the third semiconductor pattern 1501 may be integrally provided, and source regions and drain regions may be disposed on both sides of each of the channel regions A3 and A4.

[0151] In an embodiment, the fourth conductive layer 1600 may include a seventh conductive pattern 1610, an eighth conductive pattern 1620, a third gate signal line GCL, an emission control signal line EML, and a conduction bias voltage line VL3. Each of the third gate signal line GCL, the emission control signal line EML, and the conduction bias voltage line VL3 may extend longitudinally substantially in the first direction (e.g., the x-axis direction). The third gate signal line GCL may be configured to transmit a third gate signal (see Figure 5 GC) to pixels provided in the same pixel row, and the emission control signal line EML may be configured to transmit an emission control signal (see Figure 5to the pixel circuits disposed in the same pixel row. The turn-on bias voltage line VL3 can be configured to transmit a turn-on bias voltage (see Figure 5 VOBS) to the pixel circuits disposed in the same pixel row.

[0152] The channel region A3 of the third transistor T3 can overlap with the third gate signal line GCL (e.g., overlap therewith in the z-axis direction). The portion of the third gate signal line GCL that overlaps with the channel region A3 of the third transistor T3 (e.g., overlaps therewith in the z-axis direction) can be the upper gate electrode G3 of the third transistor T3. The third gate signal line GCL can be connected to the sixth conductive pattern 1420 of the third conductive layer 1400 through a contact hole CT4. The sixth conductive pattern 1420 can receive a third gate signal GC from the third gate signal line GCL to the lower gate electrode of the third transistor T3. The source region S3 and the drain region D3 can be disposed on both sides of the channel region A3 of the third transistor T3.

[0153] The channel region A4 of the fourth transistor T4 can overlap with the seventh conductive pattern 1610 (e.g., overlap therewith in the z-axis direction). The seventh conductive pattern 1610 can be electrically connected to the second gate signal line GIL of the second conductive layer 1300 through a contact hole CT3. The seventh conductive pattern 1610 can receive a second gate signal GI from the second gate signal line GIL to the upper gate electrode G4 of the fourth transistor T4. The portion of the second gate signal line GIL that overlaps with the channel region A4 of the fourth transistor T4 (e.g., overlap therewith in the z-axis direction) can be the lower gate electrode of the fourth transistor T4. The source region S4 and the drain region D4 can be disposed on both sides of the channel region A4 of the fourth transistor T4. The drain region D4 of the fourth transistor T4 can be connected to the source region S3 of the third transistor T3.

[0154] In an embodiment, the emission control signal line EML can be electrically connected to the third conductive pattern 1320 of the second conductive layer 1300 through a contact hole CT1, and can be electrically connected to the fourth conductive pattern 1330 of the second conductive layer 1300 through a contact hole CT2. The third conductive pattern 1320 can be the gate electrode G5 of the fifth transistor T5, and can receive an emission control signal EM from the emission control signal line EML. The fourth conductive pattern 1330 can be the gate electrode G6 of the sixth transistor T6, and can receive an emission control signal EM from the emission control signal line EML.

[0155] Reference Figure 11 and Figure 12, the fifth conductive layer 1700 may be disposed on the fourth conductive layer 1600, and the sixth conductive layer 1800 may be disposed on the fifth conductive layer 1700. At least one insulating layer may be respectively disposed between the fourth conductive layer 1600 and the fifth conductive layer 1700 and between the fifth conductive layer 1700 and the sixth conductive layer 1800 (e.g., disposed between them in the z-axis direction).

[0156] In an embodiment, each of the fifth conductive layer 1700 and the sixth conductive layer 1800 may include a conductive material containing Mo, Al, Cu, Ti, etc., and may have a multi-layer or single-layer structure including the above-described materials. In an embodiment, each of the fifth conductive layer 1700 and the sixth conductive layer 1800 may have a multi-layer structure of Ti / Al / Ti.

[0157] In an embodiment, the fifth conductive layer 1700 may include a ninth conductive pattern 1710, a tenth conductive pattern 1720, an eleventh conductive pattern 1730, a twelfth conductive pattern 1740, a thirteenth conductive pattern 1750, a fourteenth conductive pattern 1760, a fifteenth conductive pattern 1770, a horizontal data connection line BRLh, and a second initialization voltage line VL2. In an embodiment, the sixth conductive layer 1800 may include a 16-1 conductive pattern 1810a, a 16-2 conductive pattern 1810b, a data line DL, a driving voltage line PL, and a vertical data connection line BRLv.

[0158] In an embodiment, the ninth conductive pattern 1710 may be electrically connected to the source region S3 of the third transistor T3 and the drain region D4 of the fourth transistor T4 through a contact hole CT14, and may be electrically connected to the second conductive pattern 1310 through a contact hole CT15. The source region S3 of the third transistor T3, the drain region D4 of the fourth transistor T4, the gate electrode G1 of the first transistor T1, and the first capacitor electrode of the storage capacitor (see Figure 5 Cst) (see Figure 5 CE1) may be electrically connected through the ninth conductive pattern 1710.

[0159] In an embodiment, the tenth conductive pattern 1720 may be electrically connected to the source region S2 of the second transistor T2 through a contact hole CT13, and may be electrically connected to the data line DL of the sixth conductive layer 1800 through a contact hole CT12. The data line DL may extend longitudinally in a second direction (e.g., the y-axis direction), and may be configured to transmit data signals corresponding to pixel circuits arranged in the same pixel row (see Figure 5In an embodiment, the data line DL may overlap with the channel region A5 of the fifth transistor T5 (e.g., overlap therewith in the z-axis direction). The source region S2 of the second transistor T2 may receive the data signal Dm from the data line DL through the tenth conductive pattern 1720.

[0160] The eleventh conductive pattern 1730 may be electrically connected to the drain region D3 of the third transistor T3 through the contact hole CT16, and may be electrically connected to the drain region D1 of the first transistor T1 and the source region S6 of the sixth transistor T6 through the contact hole CT17. The drain region D3 of the third transistor T3, the drain region D1 of the first transistor T1, and the source region S6 of the sixth transistor T6 may be electrically connected to each other through the eleventh conductive pattern 1730.

[0161] The twelfth conductive pattern 1740 may include a connection portion and a main body portion. The connection portion of the twelfth conductive pattern 1740 may extend in the first direction (e.g., the x-axis direction), and may connect the main body portion located in the first pixel region PCA and the main body portion located in the second pixel region PCB to each other. The twelfth conductive pattern 1740 may be electrically connected to the fifth conductive pattern 1410 of the third conductive layer 1400 through the contact hole CT6, may be electrically connected to the source region S5 of the fifth transistor T5 through the contact hole CT7, and may be electrically connected to the driving voltage line PL of the sixth conductive layer 1800 through the contact hole CT18. The source region S5 of the fifth transistor T5 and the second capacitor electrode of the storage capacitor (see Figure 5 CE2 of Figure 5 Cst) may receive the driving voltage (see Figure 5 ELVDD) from the driving voltage line PL through the twelfth conductive pattern 1740.

[0162] The thirteenth conductive pattern 1750 may be electrically connected to the drain region D6 of the sixth transistor T6 and the drain region D7 of the seventh transistor T7 through the contact hole CT20, and may be electrically connected to the 16-1 conductive pattern 1810a or the 16-2 conductive pattern 1810b of the sixth conductive layer 1800 through the contact hole CT19. Each of the 16-1 conductive pattern 1810a and the 16-2 conductive pattern 1810b may be electrically connected to an organic light emitting diode (see Figure 5 OLED) to be described later through the contact hole CT21a or CT21b. In an embodiment, the drain region D6 of the sixth transistor T6, the drain region D7 of the seventh transistor T7, and the organic light emitting diode OLED may be electrically connected to each other through the thirteenth conductive pattern 1750 and the 16-1 conductive pattern 1810a or the thirteenth conductive pattern 1750 and the 16-2 conductive pattern 1810b.

[0163] In an embodiment, the fourteenth conductive pattern 1760 may be electrically connected to the source region S4 of the fourth transistor T4 through the contact hole CT5 and may be electrically connected to the first initialization voltage line VL1 through the contact hole CT11. For example, the fourteenth conductive pattern 1760 may electrically connect the third part 1501c of the third semiconductor pattern 1501 to the second part VL1b of the first initialization voltage line VL1. The source region S4 of the fourth transistor T4 may receive the first initialization voltage from the first initialization voltage line VL1 through the fourteenth conductive pattern 1760 (see Figure 5 VINT in ). The fourteenth conductive pattern 1760 may be referred to as a connection electrode or a first connection electrode.

[0164] The fifteenth conductive pattern 1770 may be electrically connected to the conduction bias voltage line VL3 through the contact hole CT9 and may be electrically connected to the source region S8 of the eighth transistor T8 through the contact hole CT8. The source region S8 of the eighth transistor T8 may receive the conduction bias voltage from the conduction bias voltage line VL3 through the fifteenth conductive pattern 1770 (see Figure 5 VOBS in ).

[0165] The horizontal data connection line BRLh may extend longitudinally in a first direction (e.g., the x-axis direction). The vertical data connection line BRLv may extend in a second direction (e.g., the y-axis direction) that intersects the first direction (e.g., the x-axis direction). Figure 6 , Figure 11 and Figure 12 The horizontal data connection line BRLh and the vertical data connection line BRLv shown in are electrically separated from each other by at least one insulating layer. However, in some partial regions, the horizontal data connection line BRLh and the vertical data connection line BRLv corresponding to the horizontal data connection line BRLh may be electrically connected to each other through contact holes. Similarly, in some pixel regions, the horizontal data connection line BRLh and the data line DL may be electrically connected to each other through contact holes. The horizontal data connection line BRLh may be referred to as a first data connection line. The vertical data connection line BRLv may be referred to as a second data connection line.

[0166] The horizontal data connection line BRLh and the vertical data connection line BRLv may be configurations corresponding to the data transmission lines described with reference to Figure 3A and Figure 4A For example, in an embodiment, the horizontal data connection line BRLh may be electrically connected to the data line DL and the vertical data connection line BRLv and may transmit data signals (see Figure 5Dm). As described above, in some pixel regions where no horizontal data connection line BRLh and vertical data connection line BRLv are arranged, dummy wirings (e.g., additional connection lines, auxiliary connection lines, etc.) having the same shape as each of the horizontal data connection line BRLh and vertical data connection line BRLv can be provided therein.

[0167] The second initialization voltage line VL2 can extend longitudinally in a first direction (e.g., the x-axis direction) and can be electrically connected to pixel circuits arranged in the same pixel row. The second initialization voltage line VL2 can be electrically connected to the source region S7 of the seventh transistor T7 through a contact hole CT10. The source region S7 of the seventh transistor T7 can receive a second initialization voltage from the second initialization voltage line VL2 (see Figure 5 VAINT).

[0168] The driving voltage line PL can extend longitudinally in a second direction (e.g., the y-axis direction) and can overlap with the first pixel region PCA and the second pixel region PCB. The driving voltage line PL can have a second hole PLh defined therein and overlapping with the fourteenth conductive pattern 1760, and can include a shielding portion SHL. The 16-1 conductive pattern 1810a and the 16-2 conductive pattern 1810b can be arranged to overlap with the second hole PLh of the driving voltage line PL (e.g., overlap therewith in the z-axis direction). The shielding portion SHL of the driving voltage line PL can overlap with the horizontal data connection line BRLh, the third transistor T3, and the fourth transistor T4, and can reduce the electrical effect between the components below the second pixel electrode 1902 to be described later and the shielding portion SHL.

[0169] In an embodiment, the horizontal data connection line BRLh, the fourteenth conductive pattern 1760, and the second initialization voltage line VL2 can be arranged in the same layer. The fourteenth conductive pattern 1760 can be arranged between the horizontal data connection line BRLh and the second initialization voltage line VL2 (e.g., arranged between them in the y-axis direction). Since the fourteenth conductive pattern 1760 is arranged to deviate from the first part VL1a of the first initialization voltage line VL1 in the second direction (e.g., the y-axis direction), the horizontal data connection line BRLh can not bypass the fourteenth conductive pattern 1760 and can extend to overlap with the shielding portion SHL of the driving voltage line PL (e.g., overlap therewith in the z-axis direction).

[0170] The seventh conductive layer 1900 can be arranged on the sixth conductive layer 1800. At least one insulating layer can be arranged between the sixth conductive layer 1800 and the seventh conductive layer 1900 (e.g., arranged between them in the z-axis direction). Figure 13It is an arrangement diagram for describing the arrangement of pixel electrodes 1901, 1902, and 1903. The pixel electrodes 1901, 1902, and 1903 can be repeatedly arranged in a first direction (e.g., the x-axis direction) and a second direction (e.g., the y-axis direction) according to a specific pattern.

[0171] In an embodiment, the pixel electrodes 1901, 1902, and 1903 can be arranged in a checkerboard (or diamond) arrangement. For example, in an embodiment, a first emission region EA1 defined in the first pixel electrode 1901 can emit red light, a second emission region EA2 defined in the second pixel electrode 1902 can emit green light, and a third emission region EA3 defined in the third pixel electrode 1903 can emit blue light. The second pixel electrode 1902 can be disposed at each of the rectangular vertices centered on the first pixel electrode 1901 or the third pixel electrode 1903.

[0172] Each of the first pixel electrode 1901 and the third pixel electrode 1903 can be electrically connected to the 16-2 conductive pattern 1810b through a contact hole CT21b, and the second pixel electrode 1902 can be connected to the 16-1 conductive pattern 1810a through a contact hole CT21a. The second pixel electrode 1902 can be arranged to overlap with a shielding portion SHL of the driving voltage line PL (e.g., overlap therewith in the z-axis direction).

[0173] In an embodiment, the first pixel electrode 1901 and the third pixel electrode 1903 can have a substantially chamfered rectangular shape. The second pixel electrode 1902 can have an inclined octagonal shape. However, the embodiments of the present disclosure are not necessarily limited thereto. The pixel electrodes 1901, 1902, and 1903 can be arranged in various forms such as a stripe arrangement, a mosaic arrangement, etc., and each of the pixel electrodes 1901, 1902, and 1903 can have various shapes such as other polygonal shapes, circular, and elliptical.

[0174] Figure 14 is a schematic enlarged plan view of part II of the Figure 6 display device shown, and Figure 15 is a schematic cross-sectional view of a part of the Figure 14 display device shown. Figure 15 is a cross-sectional view taken along the Figure 14 line III-III' in

[0175] Refer to Figure 14 and Figure 15, the first insulating layer 101 may be disposed on the substrate 100 (e.g., directly disposed on the substrate 100 in the z-axis direction), and the second insulating layer 103 may be disposed on the first insulating layer 101 (e.g., directly disposed on the first insulating layer 101 in the z-axis direction). The first conductive layer (see Figure 7 's 1100) may be disposed between the substrate 100 and the first insulating layer 101, and the first semiconductor layer (see Figure 8 's 1200) may be disposed between the first insulating layer 101 and the second insulating layer 103 (e.g., disposed therebetween in the z-axis direction).

[0176] The second conductive layer (see Figure 8 's 1300) may be disposed on the second insulating layer 103, and the second conductive layer 1300 may include a second gate signal line GIL longitudinally extending in a first direction (e.g., the x-axis direction).

[0177] The third insulating layer 105 may be disposed on the second conductive layer 1300, and the third conductive layer (see Figure 9 's 1400) may be disposed on the third insulating layer 105. The third conductive layer 1400 may include a first initialization voltage line VL1 longitudinally extending in a first direction (e.g., the x-axis direction). The first initialization voltage line VL1 may include a first portion VL1a longitudinally extending in a first direction (e.g., the x-axis direction), and a second portion VL1b protruding from the first portion VL1a in a second direction (e.g., the y-axis direction).

[0178] The fourth insulating layer 106 may be disposed on the third conductive layer 1400, and the second semiconductor layer (see Figure 10 's 1500) may be disposed on the fourth insulating layer 106. The second semiconductor layer 1500 may include a third semiconductor pattern 1501, and the third semiconductor pattern 1501 may include a first portion 1501a longitudinally extending in a first direction (e.g., the x-axis direction), a second portion 1501b protruding from the first portion 1501a in a second direction (e.g., the y-axis direction), and a third portion 1501c protruding from the first portion 1501a in a second direction (e.g., the y-axis direction). The second portion 1501b of the third semiconductor pattern 1501 may include a channel region A4 of the fourth transistor T4.

[0179] As Figure 14As shown, the second semiconductor layer 1500 may protrude from a first portion VL1a of the first initialization voltage line VL1 such that the first portion VL1a of the first initialization voltage line VL1 may overlap with a first portion 1501a of the third semiconductor pattern 1501 (e.g., overlap therewith in the z-axis direction), and a second portion VL1b of the first initialization voltage line VL1 may not overlap with the first portion 1501a of the third semiconductor pattern 1501 (e.g., not overlap therewith in the z-axis direction).

[0180] The fifth insulating layer 107 may be disposed on the second semiconductor layer 1500, and a fourth conductive layer (see Figure 10 1600) may be disposed on the fifth insulating layer 107. In an embodiment, in a plan view, the fifth insulating layer 107 may have a shape corresponding to the shape of the fourth conductive layer 1600.

[0181] The fourth conductive layer 1600 may include a seventh conductive pattern 1610. The seventh conductive pattern 1610 may be electrically connected to a second gate signal line GIL of the second conductive layer 1300 through a contact hole CT3 passing through the third insulating layer 105, the fourth insulating layer 106, and the fifth insulating layer 107. The seventh conductive pattern 1610 may receive a second gate signal GI from the second gate signal line GIL to an upper gate electrode G4 of the fourth transistor T4. In an embodiment, a portion of the second gate signal line GIL overlapping with a channel region A4 of the fourth transistor T4 may be a lower gate electrode of the fourth transistor T4.

[0182] The sixth insulating layer 108 may be disposed on the fourth conductive layer 1600, and a fifth conductive layer (see Figure 11 1700) may be disposed on the sixth insulating layer 108. The fifth conductive layer 1700 may include a fourteenth conductive pattern 1760 and a horizontal data connection line BRLh.

[0183] The fourteenth conductive pattern 1760 may be a connection electrode that electrically connects the first initialization voltage line VL1 of the third conductive layer 1400 and the third semiconductor pattern 1501 of the second semiconductor layer 1500 to each other. For example, the fourteenth conductive pattern 1760 may be configured to electrically connect a second portion VL1b of the first initialization voltage line VL1 and a third portion 1501c of the third semiconductor pattern 1501 to each other.

[0184] The horizontal data connection line BRLh may be configured corresponding to the horizontal connection line described with reference to Figure 3B and Figure 4B The horizontal data connection line BRLh may be electrically connected to a data line (see Figure 12 DL) and a vertical data connection line (see Figure 12of BRLv). The horizontal data connection line BRLh may extend in a first direction (e.g., the x-axis direction).

[0185] In an embodiment, each of the first insulating layer 101 to the sixth insulating layer 108 may be a single-layer or multi-layer structure including an inorganic material such as silicon oxide, silicon nitride, silicon oxynitride, etc.

[0186] The seventh insulating layer 109 may be disposed on the fifth conductive layer 1700, and the sixth conductive layer (see Figure 12 1800) may be disposed on the seventh insulating layer 109. In an embodiment, the sixth conductive layer 1800 may include the 16-1 conductive pattern 1810a and the driving voltage line PL.

[0187] The driving voltage line PL may define a second hole PLh overlapping with the fourteenth conductive pattern 1760 (e.g., overlapping therewith in the z-axis direction), and may include a shielding portion SHL overlapping with the horizontal data connection line BRLh (e.g., overlapping therewith in the z-axis direction). The shielding portion SHL of the driving voltage line PL may be disposed between the horizontal data connection line BRLh and the second pixel electrode 1902, and may reduce the parasitic capacitance between the horizontal data connection line BRLh and the second pixel electrode 1902.

[0188] The 16-1 conductive pattern 1810a may be a connection electrode electrically connected to the second pixel electrode 1902 (see Figure 13 1900) of the seventh conductive layer through a contact hole CT21a passing through the seventh insulating layer 109. For example, the 16-1 conductive pattern 1810a may be referred to as a second connection electrode. The 16-1 conductive pattern 1810a may overlap with the second hole PLh of the driving voltage line PL (e.g., overlapping therewith in the z-axis direction).

[0189] The fourteenth conductive pattern 1760 may deviate from a first portion VL1a of the first initialization voltage line VL1 and a first portion 1501a of the third semiconductor pattern 1501 in a second direction (e.g., the y-axis direction), and may be disposed substantially between the 16-1 conductive pattern 1810a and the horizontal data connection line BRLh in the second direction (e.g., the y-axis direction). Therefore, the horizontal data connection line BRLh may be sufficiently spaced apart from the 16-1 conductive pattern 1810a in the second direction (e.g., the y-axis direction), and may reduce the parasitic capacitance between the horizontal data connection line BRLh and the 16-1 conductive pattern 1810a.

[0190] The eighth insulating layer 111 may be disposed on the sixth conductive layer 1800, and the organic light-emitting diode OLED may be disposed on the eighth insulating layer 111. Each of the seventh insulating layer 109 and the eighth insulating layer 111 may be a single-layer or multi-layer structure including an inorganic material and / or an organic material. In an embodiment, the inorganic material may include silicon oxide, silicon nitride, or silicon oxynitride, and the organic material may include an acrylic-based resin, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO).

[0191] In an embodiment, Figure 15 The illustrated organic light-emitting diode OLED may be an organic light-emitting diode OLED that emits green light. However, embodiments of the present disclosure are not necessarily limited thereto. The organic light-emitting diode OLED may include a second pixel electrode 1902, a counter electrode 230 facing the second pixel electrode 1902, and an intermediate layer 220 between the second pixel electrode 1902 and the counter electrode 230.

[0192] The second pixel electrode 1902 may be a (semi)transparent electrode or a reflective electrode. In an embodiment, the second pixel electrode 1902 may include a reflective layer and a transparent or semi-transparent electrode layer formed on the reflective layer, and the reflective layer includes Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof. In an embodiment, the transparent or semi-transparent electrode layer may include at least one material selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In an embodiment, the second pixel electrode 1902 may include ITO / Ag / ITO.

[0193] The second pixel electrode 1902 may be arranged to overlap with a shielding portion SHL of the driving voltage line PL (e.g., overlap therewith in the z-axis direction). The second pixel electrode 1902 may overlap with the horizontal data connection line BRLh, and the shielding portion SHL of the driving voltage line PL may be disposed between the horizontal data connection line BRLh and the second pixel electrode 1902 (e.g., disposed therebetween in the z-axis direction). Similarly, the second pixel electrode 1902 may overlap with the third transistor (see Figure 10 T3) and the fourth transistor T4, and the shielding portion SHL of the driving voltage line PL may be disposed between the third transistor T3, the fourth transistor T4, and the second pixel electrode 1902 (e.g., disposed therebetween in the z-axis direction).

[0194] In an embodiment, a pixel defining layer PDL may be disposed on the eighth insulating layer 111 to cover the edge of the second pixel electrode 1902. The pixel defining layer PDL may include an opening for exposing a part of the second pixel electrode 1902. The emission area EA of the organic light emitting diode OLED may be defined by the opening of the pixel defining layer PDL.

[0195] The pixel defining layer PDL may increase the distance between the edge of the second pixel electrode 1902 and the counter electrode 230, thereby preventing the occurrence of an arc or the like at the edge of the second pixel electrode 1902. In an embodiment, the pixel defining layer PDL may include one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic-based resin, BCB, and phenol-based resin. In an embodiment, the pixel defining layer PDL may include a light blocking material and may be colored black. The light blocking material may include carbon black, carbon nanotubes, a resin or paste including a black dye, metal particles such as Ni, Al, Mo, and their alloys, metal oxide particles (e.g., chromium oxide), or metal nitride particles (e.g., chromium nitride).

[0196] The intermediate layer 220 may be disposed on the second pixel electrode 1902. The intermediate layer 220 may include a light emitting layer 222. The light emitting layer 222 may include a polymer or a low molecular weight organic material that emits light of a specific color. In an embodiment, in addition to various organic materials, the light emitting layer 222 may further include a compound containing a metal (such as an organometallic compound), an inorganic material (such as a quantum dot), and the like. In an embodiment, the light emitting layer 222 may be patterned to correspond to the exposed portion of the second pixel electrode 1902.

[0197] The first functional layer 221 may be disposed between the light emitting layer 222 and the second pixel electrode 1902, and the second functional layer 223 may be disposed between the light emitting layer 222 and the counter electrode 230. The first functional layer 221 may be a hole transport layer (HTL). Optionally, the first functional layer 221 may include a hole injection layer (HIL) and a hole transport layer. The second functional layer 223 may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer 221 and the second functional layer 223 may be integrally formed to correspond to a plurality of organic light emitting diodes OLED. However, the embodiments of the present disclosure are not necessarily limited thereto. For example, in some embodiments, the first functional layer 221 or the second functional layer 223 may be omitted.

[0198] The counter electrode 230 may be disposed on the light-emitting layer 222. In an embodiment, the counter electrode 230 may include lithium (Li), Ag, Mg, Al, Al-Li, calcium (Ca), Mg-In, Mg-Ag, ytterbium (Yb), Ag-Yb, ITO, IZO, or any combination thereof. The counter electrode 230 may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. In an embodiment, the counter electrode 230 may be integrally formed to correspond to a plurality of organic light-emitting diodes OLEDs.

[0199] In a comparative example, when the fourteenth conductive pattern is set to overlap with the first portion of the first initialization voltage line (e.g., overlap therewith in the z-axis direction), the horizontal data connection line may be set adjacent to the 16-1 conductive pattern to bypass the fourteenth conductive pattern. In this case, the horizontal data connection line deviates from the shielding portion of the driving voltage line, and a parasitic capacitance may be formed with the overlapping pixel electrode and the 16-1 conductive pattern. Therefore, due to the coupling between the horizontal data connection line and the pixel electrode, the brightness of some pixels may increase or decrease, resulting in blotches in the image displayed by the display device.

[0200] On the other hand, in an embodiment of the present disclosure, the shielding portion SHL of the driving voltage line PL is disposed between the horizontal data connection line BRLh and the second pixel electrode 1902 (e.g., disposed therebetween in the z-axis direction), and since the horizontal data connection line BRLh and the 16-1 conductive pattern 1810a are sufficiently spaced apart from each other in the second direction (e.g., the y-axis direction), a display device capable of displaying a high-quality image by reducing the brightness deviation between pixels can be achieved.

[0201] According to the embodiment of the present disclosure as described above, a display device can be achieved that can display a high-quality image by reducing the parasitic capacitance between the data connection line and the pixel electrode. Of course, the scope of the embodiments of the present disclosure is not limited by these effects.

[0202] It should be understood that the embodiments of the present disclosure described herein should be considered only for descriptive purposes and not for the purpose of limitation. The description of the features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments of the present disclosure have been described with reference to the drawings, those of ordinary skill in the art will understand that various changes in form and detail can be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A display device, comprising: A first conductive layer disposed on a substrate, the first conductive layer including a first initialization voltage line extending in a first direction; A first semiconductor layer disposed on the first conductive layer; A second conductive layer disposed on the first semiconductor layer, the second conductive layer including a first gate electrode; A third conductive layer disposed on the second conductive layer, the third conductive layer including a first connection electrode that electrically connects the first semiconductor layer and the first initialization voltage line to each other and a first data connection line extending in the first direction; And A fourth conductive layer disposed on the third conductive layer, the fourth conductive layer including a drive voltage line extending in a second direction intersecting the first direction and a second data connection line, Wherein the drive voltage line has a hole defined therein, the hole overlapping the first connection electrode, and the drive voltage line includes a shielding portion overlapping the first data connection line.

2. The display device according to claim 1, wherein: The first initialization voltage line includes a first portion and a second portion protruding from the first portion in the second direction; The first semiconductor layer includes a first portion extending in the first direction and a second portion protruding from the first portion of the first semiconductor layer in the second direction; And The first connection electrode electrically connects the second portion of the first initialization voltage line and the second portion of the first semiconductor layer to each other.

3. The display device according to claim 2, wherein The first portion of the first initialization voltage line overlaps the first portion of the first semiconductor layer.

4. The display device according to claim 1, wherein, The fourth conductive layer further includes a second connection electrode overlapping the hole, and the first connection electrode is disposed between the second connection electrode and the first data connection line in a plan view.

5. The display device according to claim 4 further includes a fifth conductive layer disposed on the fourth conductive layer, and the fifth conductive layer includes pixel electrodes, wherein, The pixel electrode is electrically connected to the second connection electrode.

6. The display device according to claim 5, wherein: The pixel electrode overlaps the first data connection line; and The shielding portion is disposed between the pixel electrode and the first data connection line.

7. The display device according to claim 1, wherein: The third conductive layer further includes a second initialization voltage line extending in the first direction; and The first connection electrode is disposed between the first data connection line and the second initialization voltage line in a plan view.

8. The display device according to claim 1, wherein: The fourth conductive layer further includes a data line extending in the second direction; and The first data connection line is electrically connected to the data line and the second data connection line.

9. The display device according to claim 8, wherein: The substrate includes a display area and a peripheral area outside the display area; and The first data connection line is electrically connected to the data line in the display area.

10. The display device according to claim 1 further includes a second semiconductor layer disposed between the substrate and the first conductive layer, wherein, The first semiconductor layer includes an oxide-based semiconductor material, and the second semiconductor layer includes a silicon-based semiconductor material.

11. A display device, comprising: A plurality of pixels; A first data connection line extending in a first direction; A second data connection line extending in a second direction intersecting the first direction; and A driving voltage line extending in the second direction, the driving voltage line having a hole defined therein and a shielding portion overlapping the first data connection line, wherein each of the plurality of pixels includes: A light-emitting diode including a pixel electrode, a counter electrode, and an intermediate layer between the pixel electrode and the counter electrode; A first transistor including a first semiconductor layer and a first gate electrode on the first semiconductor layer; A second transistor electrically connected between a data line and the first transistor; A third transistor electrically connected between a first initialization voltage line and the first gate electrode; A fourth transistor electrically connected between the driving voltage line and the first transistor; A fifth transistor electrically connected to the first transistor and the light-emitting diode; and A first connection electrode electrically connecting the first initialization voltage line and the third transistor to each other, the first connection electrode overlapping the hole.

12. The display device according to claim 11, wherein: Each of the plurality of pixels further includes a second connection electrode electrically connected between the pixel electrode and the fifth transistor; and The second connection electrode overlaps the hole.

13. The display device according to claim 12, wherein, The first connection electrode is disposed between the second connection electrode and the first data connection line in a plan view.

14. The display device according to claim 11, wherein: The pixel electrode overlaps the first data connection line; and The shielding portion is disposed between the pixel electrode and the first data connection line.

15. The display device according to claim 14, wherein, The light-emitting diode emits green light.

16. The display device according to claim 11, wherein, The first data connection line is disposed in the same layer as the first connection electrode.

17. The display device according to claim 11, wherein, Each of the plurality of pixels further includes a sixth transistor electrically connected between a second initialization voltage line and the light-emitting diode.

18. The display device according to claim 17, wherein: The second initialization voltage line extends in the first direction; and The first connection electrode is disposed between the second initialization voltage line and the first data connection line in a plan view.

19. The display device according to claim 11, wherein, The first data connection line is electrically connected to the data line and the second data connection line.

20. The display device according to claim 11 further includes a conduction bias voltage line extending in the first direction, wherein, Each of the plurality of pixels further includes a seventh transistor electrically connected between a conduction bias voltage line and the first transistor.

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