Magnetic field sensor with bias resistor

Abstract

The present disclosure generally relates to a magnetic field sensor with a bias resistor in an integrated circuit (IC). In an example, an IC includes a magnetic field sensor (102) and a resistor (104). The magnetic field sensor (102) includes a first doped well (202-1) and a second doped well (202-2). The first doped well (202-1) and the second doped well (202-2) are in a semiconductor substrate (302). A first spacing (282) is between the first doped well (202-1) and the second doped well (202-2). The resistor (104) includes a third doped well (204-1) in the semiconductor substrate (302). A second spacing (284) is between the first doped well (202-1) and the third doped well (204-1). The second interval (284) is equal to the first interval (282).

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 624,105, filed on Jan. 23, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to a semiconductor, and more particularly to a magnetic field sensor having a bias resistor. Background Art

[0004] Various types of sensors have been developed to detect the presence of a magnetic field. A Hall sensor is a type of sensor that can be used to detect the presence of a magnetic field and measure the magnitude of the magnetic field. The output voltage of a Hall sensor can be proportional to the magnetic field strength passing through the Hall sensor. Hall sensors can be used for proximity sensing, positioning, speed detection, and current sensing applications. Summary of the Invention

[0005] The Summary of the Invention is provided to introduce a brief selection of the disclosed concepts in a simplified form, which will be further described in the Detailed Description below, which includes the provided drawings. The various disclosed devices and methods can be advantageously applied in the context of an integrated circuit (IC) that includes a magnetic field sensor (e.g., a Hall sensor) having a bias resistor. Some of the examples described herein can be applied in such ICs and in the manufacture of such ICs. While such examples may be expected to particularly achieve improved drift compensation for Hall sensors, no particular result is required unless explicitly recited in the specific claims.

[0006] Examples described herein are ICs. The IC includes a magnetic field sensor and a resistor. The magnetic field sensor includes a first doped well and a second doped well. The first doped well and the second doped well are in a semiconductor substrate. A first spacing is between the first doped well and the second doped well. The resistor includes a third doped well in the semiconductor substrate. A second spacing is between the first doped well and the third doped well. The second spacing is equal to the first spacing.

[0007] Another example described herein is an IC. The IC includes a sensor unit on a semiconductor substrate. The sensor unit includes a magnetic field sensor and a resistor. The magnetic field sensor includes a sensor doped well in the semiconductor substrate. The resistor includes a resistor doped well in the semiconductor substrate.

[0008] Another example described herein is a method of manufacturing an IC. A first doped well, a second doped well, and a third doped well are formed in a semiconductor substrate. A first spacer is between the first doped well and the second doped well. A second spacer is between the first doped well and the third doped well. The second spacer is equal to the first spacer. The first doped well and the second doped well are electrically connected in a magnetic field sensor in the IC. The third doped well is electrically connected in a resistor in the IC.

[0009] The foregoing summary quite broadly outlines various features of the examples of the present disclosure so that the following detailed description may be better understood. Additional features and advantages of such examples will be described hereinafter. The described examples may readily be used as a basis for modifying or designing other examples within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] To understand the manner in which the above-recited features can be obtained, a detailed description is provided below with reference to the accompanying drawings.

[0011] Figure 1 is an integrated circuit including a Hall sensor and a bias resistor according to some examples.

[0012] Figure 2 is a layout diagram of a sensor unit including a Hall sensor and a bias resistor according to some examples.

[0013] Figure 3A and 3B are cross-sectional views of the sensor unit of Figure 2 according to some examples, respectively.

[0014] Figure 4 is a flowchart of a method for manufacturing an integrated circuit according to some examples.

[0015] The drawings and the accompanying detailed description are provided to understand the features of the various examples and do not limit the scope of the appended claims. The examples illustrated in the drawings and described in the accompanying detailed description may readily be used as a basis for modifying or designing other examples within the scope of the appended claims. Wherever possible, the same reference numerals are used to refer to the same elements common in the drawings. The drawings are drawn to clearly illustrate the relevant elements or features and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0016] The following describes various features with reference to the accompanying drawings. The illustrated examples may not have all aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and may be practiced in any other example, even if not so stated or explicitly described. Additionally, the methods described herein may be described with a particular order of operations, but other methods according to other examples may be implemented with various other orders of more or fewer operations (e.g., including different serial or parallel executions of various operations).

[0017] The present disclosure relates to an integrated circuit (IC) including a magnetic field sensor (e.g., a Hall sensor) and a bias resistor. In some examples, the IC includes a sensor unit on a semiconductor substrate. The sensor unit includes a magnetic field sensor and a resistor. The magnetic field sensor includes one or more sensor doped wells in the semiconductor substrate, and the resistor includes one or more dummy / resistor doped wells in the semiconductor substrate. In some examples, the dummy / resistor doped wells may be electrically connected to act as a bias resistor in the IC. Various examples may achieve improved drift compensation of the magnetic field sensor and reduced area consumption on the semiconductor die of the IC. Other benefits or advantages may be achieved by various examples.

[0018] The examples described herein implement a Hall sensor as an example magnetic field sensor. The Hall sensors in these examples include sensor doped wells in a semiconductor substrate, where the sensor doped wells are electrically connected (e.g., via metal contacts, metal vias, and metal lines) to detect a magnetic field through the Hall effect. The examples illustrated in the drawings show vertical or in-plane Hall sensors. Additionally, the examples illustrated in the drawings show unidirectional vertical or in-plane Hall sensors. Other examples may implement horizontal or out-of-plane Hall sensors and / or multi-directional Hall sensors (e.g., two vertical or in-plane directions or other directions). Additionally, the Hall sensors depicted in the drawings include four sensor doped wells (e.g., in a quadrilateral shape). In other examples, the Hall sensor may include any number of sensor doped wells (e.g., one, two, four, eight, etc.). Other magnetic field sensors may also be implemented in the IC.

[0019] Figure 1 is an IC 100 including a Hall sensor 102 and a bias resistor 104 according to some examples. The IC 100 is on a single die or chip. The components of the IC 100 may be fabricated on and / or in a semiconductor substrate. The IC 100 is an example IC in which a sensor unit including sensor doped wells of the Hall sensor 102 and dummy / resistor doped wells for forming the bias resistor 104 may be implemented. In other examples, other ICs including such a sensor unit may be implemented.

[0020] IC 100 includes a first operational amplifier (op amp) 106, a first transistor 108, a second transistor 110, a third transistor 112, and a first resistor 114. In the illustrated example, the first transistor 108 and the second transistor 110 are respective p-type transistors, such as p-type field effect transistors (pFETs) (e.g., p-type metal oxide semiconductor (pMOS) FETs). In the illustrated example, the third transistor 112 is an n-type transistor, such as an n-type field effect transistor (nFET) (e.g., n-type metal oxide semiconductor (nMOS) FET).

[0021] The first transistor 108 and the second transistor 110 are electrically connected in a current mirror configuration. The respective source nodes of the first transistor 108 and the second transistor 110 are electrically connected to a positive power supply node (VDD), and the respective gate nodes of the first transistor 108 and the second transistor 110 are electrically connected together, electrically connected to the drain node of the first transistor 108, and electrically connected to the drain node of the third transistor 112. The gate node of the third transistor 112 is electrically connected to the output node of the first op amp 106. A back gate voltage node (VBG) is electrically connected to the positive input node of the first op amp 106. The source node of the third transistor 112 is electrically connected to the negative input node of the first op amp 106. The negative input node of the first op amp 106 and the source node of the third transistor 112 are further electrically connected to a first node of a bias resistor 104. The second node (opposite the first node) of the bias resistor 104 is a negative power supply node (VSS) or is electrically connected to the negative power supply node (VSS). As illustrated, the bias resistor 104 includes a plurality of resistors connected in parallel between the first node and the second node. The resistors may be formed in respective doped wells in a semiconductor substrate, as detailed subsequently. In other examples, the bias resistor 104 may be a single resistor between the first node and the second node, or may include a plurality of resistors connected in any network connection of series and / or parallel configurations. The drain node of the second transistor 110 is electrically connected to a first terminal of the first resistor 114, and the second terminal of the first resistor 114 is a negative power supply node (VSS) or is electrically connected to the negative power supply node (VSS).

[0022] IC 100 further includes a second op amp 120, a fourth transistor 122, a fifth transistor 124, a second resistor 126, and a third op amp 128. In the illustrated example, the fourth transistor 122 is a p-type transistor, such as a pFET (e.g., pMOS FET). In the illustrated example, the fifth transistor 124 is an n-type transistor, such as an nFET (e.g., nMOS FET).

[0023] The source node of the fourth transistor 122 is electrically connected to the positive power supply node (VDD), and the drain node of the fourth transistor 122 is electrically connected to the first node (T1) of the Hall sensor 102. The third node (T3) of the Hall sensor 102 is electrically connected to the drain node of the fifth transistor 124. The source node of the fifth transistor 124 is electrically connected to the negative input node of the second op amp 120. The negative input node of the second op amp 120 and the source node of the fifth transistor 124 are further electrically connected to the first terminal of the second resistor 126. The second terminal of the second resistor 126 is the negative power supply node (VSS) or is electrically connected to the negative power supply node (VSS). The positive input node of the second op amp 120 is electrically connected to the drain node of the second transistor 110 and the first terminal of the first resistor 114.

[0024] The Hall sensor 102 includes resistors electrically connected together in a Wheatstone bridge configuration, the Wheatstone bridge configuration having a pair of differential nodes (T2, T4) between which a sensor voltage (V SEN ) can be detected. Resistor 102-1 is electrically connected between the first node (T1) and the second node (T2); resistor 102-2 is electrically connected between the second node (T2) and the third node (T3); resistor 102-3 is electrically connected between the third node (T3) and the fourth node (T4); and resistor 102-4 is electrically connected between the fourth node (T4) and the first node (T1). The pair of differential nodes (T2, T4) is electrically connected to the pair of differential input nodes of the third op amp 128. The input nodes of the third op amp 128 are electrically connected to one-half of the analog positive power supply node (AVDD / 2). The output node of the third op amp 128 is electrically connected to the gate node of the fourth transistor 122. The third op amp 128 is configured to set the common-mode voltage at the pair of differential nodes (T2, T4) of the Hall sensor 102. The third op amp 128 senses the differential voltage between the pair of differential nodes (T2, T4) of the Hall sensor 102 and applies a voltage at the gate node of the fourth transistor 122 that will generate a current that is converted to AVDD / 2 by the resistors of the Hall sensor 102.

[0025] Figure 2 is a layout diagram of a sensor unit 200 including a Hall sensor and a bias resistor according to some examples. The layout is shown in the x-y plane. Figure 2 The layout of the sensor unit 200 shows cross-sections A-A and B-B. Cross-sections A-A, B-B are in the z-y plane. Figure 3A Illustrates cross-section A-A, and Figure 3B Illustrates cross-section B-B. Reference may be made to Figure 2 、 3ARefer to FIGS. 3A and 3B to understand the following description.

[0026] The sensor unit 200 includes sensor doped wells 202-1, 202-2, 202-3, 202-4 (collectively or individually referred to as sensor doped wells 202) and dummy or resistor (hereinafter referred to as, "dummy / resistor") doped wells 204-1, 204-2, 204-3, 204-4 (collectively or individually referred to as dummy / resistor doped wells 204). Four sensor doped wells 202 and four dummy / resistor doped wells 204 are illustrated. In other examples, other numbers of sensor doped wells and dummy / resistor doped wells may be implemented, such as one sensor doped well, two sensor doped wells, eight sensor doped wells, etc. and corresponding dummy / resistor doped wells. Cross-section A-A is through the sensor doped well 202-1. Although Figure 3A the sensor doped well 202-1 is illustrated, Figure 3A it may also represent any of the sensor doped wells 202. Similarly, cross-section B-B is through the dummy / resistor doped well 204-1. Although Figure 3B the dummy / resistor doped well 204-1 is illustrated, Figure 3B it may also represent any of the dummy / resistor doped wells 204.

[0027] A shallow isolation structure 212 (e.g., a shallow trench isolation (STI) structure) is located between the sensor doped wells 202 and the dummy / resistor doped wells 204 and laterally defines the sensor doped wells 202 and the dummy / resistor doped wells 204. A deep isolation structure 214 laterally surrounds or encloses the sensor doped wells 202, the dummy / resistor doped wells 204, and the shallow isolation structure 212.

[0028] The sensor doped wells 202 and the dummy / resistor doped wells 204 have respective longitudinal axes (axes along the major axis of the structure) that are parallel to each other (e.g., in the respective y-directions). The sensor doped wells 202-1, 202-4 are longitudinally aligned (e.g., in the y-direction), and the sensor doped wells 202-2, 202-3 are longitudinally aligned (e.g., in the y-direction). The dummy / resistor doped wells 204-1, 204-4 are longitudinally aligned (e.g., in the y-direction), and the dummy / resistor doped wells 204-2, 204-3 are longitudinally aligned (e.g., in the y-direction). The sensor doped wells 202-1, 202-2 are laterally located between the dummy / resistor doped wells 204-1, 204-2 (e.g., in the x-direction), such that the sensor doped wells 202-1, 202-2 are aligned with the midpoints of the respective longitudinal axes of the dummy / resistor doped wells 204-1, 204-2 (e.g., in the x-direction). The sensor doped wells 202-3, 202-4 are laterally located between the dummy / resistor doped wells 204-3, 204-4 (e.g., in the x-direction), such that the sensor doped wells 202-3, 202-4 are aligned with the midpoints of the respective longitudinal axes of the dummy / resistor doped wells 204-3, 204-4 (e.g., in the x-direction).

[0029] The respective spacing between the dummy / resistor doped wells 204 and the adjacent sensor doped wells 202 (or the dummy / resistor doped wells 204) can be equal to the spacing between the adjacent sensor doped wells 202 in the same direction. As illustrated, there is a spacing 282 between adjacent sensor doped wells 202 in the x-direction (e.g., sensor doped wells 202-1, 202-2 or sensor doped wells 202-3, 202-4). Each dummy / resistor doped well 204 has a spacing 284 from the adjacent sensor doped well 202 in the x-direction. More specifically, the respective spacing 284 is located between the dummy / resistor doped well 204-1 and the sensor doped well 202-1, between the dummy / resistor doped well 204-2 and the sensor doped well 202-2, between the dummy / resistor doped well 204-3 and the sensor doped well 202-3, and between the dummy / resistor doped well 204-4 and the sensor doped well 202-4. The spacings 282, 284 can be equal and are illustrated as equal. Similarly, in the y-direction, the respective spacing between adjacent sensor doped wells 202 (e.g., between sensor doped wells 202-1, 202-4) can be equal to and is illustrated as equal to the respective spacing between adjacent dummy / resistor doped wells 204 (e.g., between dummy / resistor doped wells 204-1, 204-4). In some instances, the spacing 284 between the dummy / resistor doped wells 204 and the adjacent sensor doped wells 202 is equal to or less than 10 μm, e.g., in the range of 4 μm to 10 μm.

[0030] Figure 3AAnd 3B illustrates a semiconductor substrate 302. The semiconductor substrate 302 can be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or other semiconductor substrates, and in some cases, can include one or more epitaxial layers epitaxially grown on a underlying substrate. In some instances, the semiconductor substrate 302 is or includes (e.g., singulated from a wafer) a bulk silicon substrate, which can further include one or more silicon epitaxial layers epitaxially grown on the bulk silicon substrate.

[0031] The shallow isolation structure 212 extends into the semiconductor substrate 302 and laterally defines the sensor doped well 202-1 and the dummy / resistor doped well 204-1. The shallow isolation structure 212 extends from the upper surface of the semiconductor substrate 302 into the semiconductor substrate 302 to a certain depth. The shallow isolation structure 212 can be or include silicon oxide or another dielectric material. In some instances, the shallow isolation structure 212 is a shallow trench isolation (STI), and in other instances, the shallow isolation structure 212 can be another isolation region, such as a field oxide (FOX) and / or local oxidation of silicon (LOCOS) structure.

[0032] The deep isolation structure 214 extends into the semiconductor substrate 302 and laterally surrounds or encloses the sensor doped well 202, the dummy / resistor doped well 204, and the shallow isolation structure 212 (as Figure 2 illustrated). The deep isolation structure 214 extends from the upper surface of the semiconductor substrate 302 into the semiconductor substrate 302 to a certain depth, which is greater than the depth to which the shallow isolation structure 212 extends into the semiconductor substrate 302. The deep isolation structure 214 can be or include silicon oxide, another dielectric material, a dielectric liner with a filling material (which can be or can not be a dielectric material), or another isolation structure. In some instances, the deep isolation structure 214 is a deep trench isolation (DTI) structure.

[0033] The doped buried layer 304 is in the semiconductor substrate 302, and the sensor doped well 202-1 and the dummy / resistor doped well 204-1 are above the doped buried layer 304. In Figure 3A , the doped buried layer 304 and the sensor doped well 202-1 are laterally located between portions of the shallow isolation structure 212. In Figure 3BIn [the figure], the doped buried layer 304 and the dummy / resistor doped well 204-1 are laterally located between portions of the shallow isolation structure 212. The doped buried layer 304, the sensor doped well 202, and the dummy / resistor doped well 204 may be doped with dopants of the same conduction type. In some examples, the doped buried layer 304, the sensor doped well 202, and the dummy / resistor doped well 204 are doped with n-type dopants. In such examples, the doped buried layer 304 may be an n-doped buried layer (NBL), and the sensor doped well 202 and the dummy / resistor doped well 204 may be n-doped wells (NWell). As used herein, a buried layer (BL) is a layer in a semiconductor substrate and having characteristics such as a conduction type or a dopant concentration, which is spaced apart from the top surface of the semiconductor substrate by a spacer layer or material having significantly different characteristics such as a different conduction type or a different dopant concentration. For example, the BL may be an n-doped diffusion layer spaced apart from the top surface of the substrate by an n-type or p-type in-situ doped epitaxial layer. In some examples, the doped buried layer 304 may be omitted. In some examples, another doped buried layer may be between the doped buried layer 304 and each sensor doped well 202 and between the doped buried layer 304 and each dummy / resistor doped well 204, and may be doped with a conduction type opposite to that of the doped buried layer 304, the sensor doped well 202, and the dummy / resistor doped well 204 (e.g., a p-type dopant).

[0034] Reference Figure 3A , the doped contact regions 312-1, 312-2, 312-3, 312-4, 312-5, 312-6 (collectively or individually referred to as the doped contact regions 312) are in the sensor doped well 202-1 in the semiconductor substrate 302. The doped contact regions 312 extend from the upper surface of the semiconductor substrate 302 into the semiconductor substrate 302 and into the sensor doped well 202-1 to a certain depth. In the illustrated example, the sensor doped well 202-1 includes six doped contact regions 312. In other examples, the sensor doped well 202 may include other numbers of doped contact regions 312. The doped contact regions 312 may be doped with dopants of the same conduction type as the sensor doped well 202-1 and the doped buried layer 304. For example, the doped contact regions 312, the sensor doped well 202-1, and the doped buried layer 304 may each be n-type doped. The doped contact regions 312 may be doped to a concentration greater than the dopant concentration of the sensor doped well 202-1, and the dopant concentration of the sensor doped well 202-1 may be less than the dopant concentration of the doped buried layer 304.

[0035] Reference Figure 3B, the doped contact regions 314-1, 314-2, 314-3, 314-4, 314-5, 314-6 (collectively or individually referred to as the doped contact region 314) are in the dummy / resistor doped well 204-1 in the semiconductor substrate 302. The doped contact regions 314 extend from the upper surface of the semiconductor substrate 302 into the semiconductor substrate 302 and into the dummy / resistor doped well 204-1 to a certain depth. In the illustrated example, the dummy / resistor doped well 204-1 includes six doped contact regions 314. In other examples, the dummy / resistor doped well 204 may include other numbers of doped contact regions 314. The doped contact regions 314 may be doped with dopants of the same conductivity type as the dummy / resistor doped well 204-1 and the doped buried layer 304. For example, the doped contact regions 314, the dummy / resistor doped well 204-1, and the doped buried layer 304 may each be n-type doped. The doped contact regions 314 may be doped to a concentration greater than the dopant concentration of the dummy / resistor doped well 204-1, and the dopant concentration of the dummy / resistor doped well 204-1 may be less than the dopant concentration of the doped buried layer 304.

[0036] In some examples, the n-type dopant concentration of each doped contact region 312, 314 may be in the range of 1×10 19 cm -3 to 1×10 21 cm -3 . In some examples, the n-type dopant concentration of each sensor doped well 202 and each dummy / resistor doped well 204 may be in the range of 1×10 16 cm -3 to 1×10 18 cm -3 . In some examples, the n-type dopant concentration of the doped buried layer 304 may be in the range of 1×10 18 cm -3 to 1×10 20 cm -3 . Other dopant concentrations may be implemented.

[0037] Referring to Figure 3A and 3B , the interconnect structure is on or above the semiconductor substrate 302. As illustrated, the interconnect structure includes a dielectric layer 324. The dielectric layer 324 may include a pre-metal dielectric (PMD) layer, one or more etch stop layers (ESL), etc. or a combination thereof. Each dielectric layer 324 may be or include silicon oxide, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), silicon nitride, silicon oxynitride, carbon oxynitride, carbon silicon oxide, etc.

[0038] In Figure 3AAmong them, metal contacts 222-11, 222-12, 222-13, 222-14, 222-15, 222-16 (collectively or individually referred to as metal contacts 222) pass through the dielectric layer 324 and contact the corresponding doped contact regions 312-1, 312-2, 312-3, 312-4, 312-5, 312-6. In Figure 3B Among them, metal contacts 224-11, 224-12, 224-13, 224-14, 224-15, 224-16 (collectively or individually referred to as metal contacts 224) pass through the dielectric layer 324 and contact the corresponding doped contact regions 314-1, 314-2, 314-3, 314-4, 314-5, 314-6. As Figure 2 As shown, each sensor doped well 202-m has metal contacts 222-m1, 222-m2, 222-m3, 222-m4, 222-m5, 222-m6 (with the corresponding doped contact region 312), and each dummy / resistor doped well 204-n has metal contacts 224-n1, 224-n2, 224-n3, 224-n4, 224-n5, 224-n6 (with the corresponding doped contact region 314). The metal contacts 222, 224 can include: (i) one or more barrier and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc. or a combination thereof) conformally disposed in the corresponding openings through the dielectric layer 324, and (ii) a fill metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc. or a combination thereof) on the one or more barrier and / or adhesion layers.

[0039] Although not shown, the interconnect structure can include additional dielectric layers above the dielectric layer 324, such as an intermetal dielectric (IMD) layer, ESL, etc. or a combination thereof. The additional dielectric layers can each be or include silicon oxide, BPSG, PSG, silicon nitride, silicon oxynitride, carbon oxynitride, carbon silicon oxide, etc. Additionally, metal lines and metal vias can be on and / or in the dielectric layer to interconnect various components. The metal vias and metal lines can include one or more barrier and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc. or a combination thereof), and a fill metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc. or a combination thereof) on the one or more barrier and / or adhesion layers.

[0040] As an example of forming electrical connections of Hall sensors in an interconnect structure, metal contacts 222-12, 222-23, 222-34, 222-45 can be electrically connected together as a first node (T1); metal contacts 222-22, 222-33, 222-44, 222-15 can be electrically connected together as a second node (T2); metal contacts 222-32, 222-43, 222-14, 222-25 can be electrically connected together as a third node (T3); and metal contacts 222-42, 222-13, 222-24, 222-35 can be electrically connected together as a fourth node (T4). The sensor doped well 202 forms a resistance 102-1 in the portion between the metal contacts 222 forming the first node (T1) and the metal contacts 222 forming the second node (T2). Figure 1 The sensor doped well 202 forms a resistance 102-2 in the portion between the metal contacts 222 forming the second node (T2) and the metal contacts 222 forming the third node (T3). Figure 1 The sensor doped well 202 forms a resistance 102-3 in the portion between the metal contacts 222 forming the third node (T3) and the metal contacts 222 forming the fourth node (T4). Figure 1 The sensor doped well 202 forms a resistance 102-4 in the portion between the metal contacts 222 forming the fourth node (T4) and the metal contacts 222 forming the first node (T1). Figure 1 Resistance 102-4.

[0041] Metal contacts 224 can be electrically connected together to form Figure 1 a bias resistor 104. The bias resistor 104 is formed by a resistance through the dummy / resistor doped well 204, and the dummy / resistor doped well is electrically connected to form the bias resistor 104. As an example, Figure 2The sensor unit 200 includes metal wires 242, 244, 252, and 254. The metal wire 242 (connected to a metal via (not shown)) is electrically connected to the metal contacts 224-12 and 224-43. The metal wire 244 (connected to a metal via (not shown)) is electrically connected to the metal contacts 224-14 and 224-45. Thus, the resistance of the dummy / resistor doped well 204-1 between the metal contacts 224-12 and 224-14 (illustrated by the resistor 234-1) and the resistance of the dummy / resistor doped well 204-4 between the metal contacts 224-43 and 224-45 (illustrated by the resistor 234-4) are electrically connected in parallel. The metal wire 252 (connected to a metal via (not shown)) is electrically connected to the metal contacts 224-22 and 224-33. The metal wire 254 (connected to a metal via (not shown)) is electrically connected to the metal contacts 224-24 and 224-35. Thus, the resistance of the dummy / resistor doped well 204-2 between the metal contacts 224-22 and 224-24 (illustrated by the resistor 234-2) and the resistance of the dummy / resistor doped well 204-3 between the metal contacts 224-33 and 224-35 (illustrated by the resistor 234-3) are electrically connected in parallel. Additionally, the metal wires 242 and 252 can be electrically connected together, for example, through other metal layers, and the metal wires 244 and 254 can be electrically connected together, such that the resistances (illustrated by the resistors 234-1, 234-2, 234-3, and 234-4) can be electrically connected in parallel.

[0042] In other examples, different metal contacts 224 can be electrically connected to form any resistance network of the dummy / resistor doped wells 204. In some examples, some of the dummy / resistor doped wells 204 are not electrically connected as part of the bias resistor 104 and can simply be used as dummy doped wells. In such examples where any of the dummy / resistor doped wells 204 are not electrically connected to another component (e.g., another dummy / resistor doped well 204) through an additional metal layer, the dummy / resistor doped well 204 can be electrically isolated from each other dummy / resistor doped well 204 and each sensor doped well 202.

[0043] Individual dummy / resistor doped wells 204 can have the same characteristics as individual sensor doped wells 202 within process variations. The dummy / resistor doped wells 204 can each have the same lateral width, lateral length, depth, and doping profile as the sensor doped wells 202. As Figure 2As described, the sensor doped wells 202 each have a transverse width 262, and the dummy / resistor doped wells 204 each have a transverse width 264. In the illustrated example, the transverse widths 262, 264 are equal. The sensor doped wells 202 each have a transverse length 272, and the dummy / resistor doped wells 204 each have a transverse length 274. In the illustrated example, the transverse lengths 272, 274 are equal. As Figure 3A and 3B described, the sensor doped wells 202 are each formed to a depth 342 in the semiconductor substrate 302 starting from the upper surface of the semiconductor substrate 302, and the dummy / resistor doped wells 204 are formed to a depth 344 in the semiconductor substrate 302 starting from the upper surface of the semiconductor substrate 302. In the illustrated example, the depths 342, 344 are equal. The sensor doped wells 202 and the dummy / resistor doped wells 204 can be doped using the same process and thus have the same dopant (and more generally, the same dopant type) and the same dopant concentration profile, which can be any combination of a uniform concentration and / or a graded concentration.

[0044] The presence of the dummy / resistor doped wells 204 can reduce the variability of the residual offset of the Hall sensor formed by the sensor doped wells 202. For example, in some instances, it has been found that the presence of the dummy / resistor doped wells 204 reduces the standard deviation of the residual offset by 20% relative to a Hall sensor having sensor doped wells without a neighboring dummy doped well.

[0045] Using the dummy / resistor doped well 204 within the sensor unit 200 as the bias resistor 104 in the IC 100 can provide drift compensation for the Hall sensor 102 formed using the sensor unit 200. By being in the same sensor unit 200, the dummy / resistor doped well 204 is extremely close to the sensor doped well 202 used to form the Hall sensor 102. In the case where the dummy / resistor doped well 204 forms the bias resistor 104, the dummy / resistor doped well 204 can provide compensation for process, voltage, and / or temperature (PVT) variations and strain variations. Strain can be caused by packaging, thermal expansion (e.g., different coefficients of thermal expansion (CTE) of different materials), humidity, etc. The dummy / resistor doped well 204 can provide such compensation because the dummy / resistor doped well 204 is formed by the same process as the sensor doped well 202, and the dummy / resistor doped well 204 may experience the same environmental and processing factors as the sensor doped well 202 due to being extremely close. The dummy / resistor doped well 204 and the sensor doped well 202 may also have matching piezoelectric coefficients. Additionally, the dummy / resistor doped well 204 can continue to reduce the standard deviation of the residual offset of the Hall sensor, even when implemented as a bias resistor. Additionally, implementing the bias resistor in the dummy / resistor doped well 204 can reduce the area consumed by the bias resistor on the die or chip.

[0046] Figure 4 is a flowchart of a method 400 for manufacturing an integrated circuit according to some examples. The integrated circuit includes a Hall sensor and a bias resistor as described above.

[0047] At block 402, a shallow isolation structure 212 is formed in the semiconductor substrate 302. At block 404, a deep isolation structure 214 is formed in the semiconductor substrate 302. At block 406, a sensor doped well 202 and a dummy / resistor doped well 204 are formed in the semiconductor substrate 302. Blocks 402 - 406 can be performed in various orders and using various techniques.

[0048] For example, the shallow isolation structure 212 can be formed in the semiconductor substrate 302 (e.g., a bulk semiconductor substrate) by etching a shallow trench and filling the shallow trench with a dielectric material or with a dielectric liner and another filling material above the dielectric liner. Then, the deep isolation structure 214 can be formed in the semiconductor substrate 302 by etching a deep trench and filling the deep trench with a dielectric material or with a dielectric liner and another filling material above the dielectric liner. Then, the sensor doped well 202 and the dummy / resistor doped well 204 can be formed by implanting dopants into the semiconductor substrate 302, where the shallow isolation structure 212 defines the lateral boundaries of the sensor doped well 202 and the dummy / resistor doped well 204.

[0049] As another example, semiconductor substrate 302 includes an epitaxial semiconductor layer over a support substrate. The epitaxial semiconductor layer can be doped in-situ with dopants during epitaxial growth, which forms the dopant profiles of sensor doping wells 202 and dummy / resistor doping wells 204. Then, shallow isolation structures 212 can be formed in semiconductor substrate 302 by etching shallow trenches and filling the shallow trenches with a dielectric material or with a dielectric liner and another fill material over the dielectric liner. The shallow isolation structures 212 define the lateral boundaries of sensor doping wells 202 and dummy / resistor doping wells 204. Then, deep isolation structures 214 can be formed in semiconductor substrate 302 by etching deep trenches and filling the deep trenches with a dielectric material or with a dielectric liner and another fill material over the dielectric liner.

[0050] At block 408, doped contact regions 312, 314 are formed in sensor doping wells 202 and dummy / resistor doping wells 204 in semiconductor substrate 302. The doped contact regions 312, 314 can be formed by implanting dopants. At block 410, a dielectric layer 324 is formed over semiconductor substrate 302. Any suitable deposition process can be used to form dielectric layer 324. At block 412, metal contacts 222, 224 are formed through dielectric layer 324 to the respective doped contact regions 312, 314. The metal contacts 222, 224 can be formed by forming openings through dielectric layer 324 to doped contact regions 312, 314 (e.g., by suitable lithography and etching processes) and depositing metal in the openings using a suitable deposition process. Excess metal can be removed by patterning the metal (e.g., by suitable lithography and etching processes) or by a planarization process (e.g., chemical mechanical polishing (CMP)). At block 414, a metal layer is formed to be electrically connected to metal contacts 222, 224, and to electrically connect sensor doping well 202 to form a Hall sensor and to electrically connect one or more dummy / resistor doping wells 204 to form a resistor, where the resistor is a bias resistor in an integrated circuit. The metal layer can be formed in the interconnect structure using suitable processes in back-end-of-line (BEOL) processing.

[0051] Although various examples have been described in detail, it should be understood that various changes, substitutions, and alterations can be made to them without departing from the scope defined by the appended claims.

Claims

1. An integrated circuit IC, comprising: A magnetic field sensor, comprising a first doped well and a second doped well, the first doped well and the second doped well being in a semiconductor substrate, a first spacing being between the first doped well and the second doped well; And A resistor, comprising a third doped well in the semiconductor substrate, a second spacing being between the first doped well and the third doped well, the second spacing being equal to the first spacing.

2. The IC according to claim 1, further comprising: A first isolation structure, in the semiconductor substrate and between the first doped well, the second doped well, and the third doped well; And A second isolation structure, in the semiconductor substrate and surrounding the first doped well, the second doped well, the third doped well, and the first isolation structure, the second isolation structure extending into the semiconductor substrate to a depth greater than the depth to which the first isolation structure extends.

3. The IC according to claim 1, wherein: The first doped well has a first lateral width and a first lateral length, and extends into the semiconductor substrate to a first depth; The third doped well has a second lateral width and a second lateral length, and extends into the semiconductor substrate to a second depth; The first lateral width is equal to the second lateral width; The first lateral length is equal to the second lateral length; and The first depth is equal to the second depth.

4. The IC according to claim 1, wherein: The first doped well has a first doping profile; The third doped well has a second doping profile; and The first doping profile is the same as the second doping profile.

5. The IC according to claim 1, wherein the first doped well, the second doped well, and the third doped well are longitudinally parallel to each other.

6. The IC according to claim 1, further comprising a fourth doped well in the semiconductor substrate, a third spacing being between the fourth doped well and the second doped well, the third spacing being equal to the first spacing.

7. The IC according to claim 6, wherein: The magnetic field sensor comprises a fifth doped well and a sixth doped well, the fifth doped well and the sixth doped well being in the semiconductor substrate; and The resistor comprises a seventh doped well in the semiconductor substrate; The first doped well, the second doped well, the third doped well, and the fourth doped well are longitudinally parallel to each other; The fifth doped well, the sixth doped well, and the seventh doped well are longitudinally parallel to each other; The first doped well and the fifth doped well are longitudinally aligned; The second doped well and the sixth doped well are longitudinally aligned; And The third doped well and the seventh doped well are longitudinally aligned.

8. The IC according to claim 1, wherein the resistor further comprises a fourth doped well in the semiconductor substrate, a third spacing being between the fourth doped well and the second doped well, the third spacing being equal to the first spacing.

9. The IC according to claim 8, wherein: The magnetic field sensor includes a fifth doped well and a sixth doped well, and the fifth doped well and the sixth doped well are in the semiconductor substrate; and The resistor includes a seventh doped well and an eighth doped well, and the seventh doped well and the eighth doped well are in the semiconductor substrate; The first doped well, the second doped well, the third doped well, and the fourth doped well are longitudinally parallel to each other; The fifth doped well, the sixth doped well, the seventh doped well, and the eighth doped well are longitudinally parallel to each other; The first doped well and the fifth doped well are longitudinally aligned; The second doped well and the sixth doped well are longitudinally aligned; The third doped well and the seventh doped well are longitudinally aligned; and The fourth doped well and the eighth doped well are longitudinally aligned.

10. An integrated circuit IC, comprising: A sensor unit on a semiconductor substrate, the sensor unit comprising: A magnetic field sensor including a first sensor doped well in the semiconductor substrate; and A resistor including a first resistor doped well in the semiconductor substrate.

11. The IC according to claim 10, wherein the first sensor doped well and the first resistor doped well have the same doping profile.

12. The IC according to claim 10, wherein: The first sensor doped well has a first transverse length and a first transverse width, and the first sensor doped well extends into the semiconductor substrate to a first depth; The first resistor doped well has a second transverse length and a second transverse width, and the first resistor doped well extends into the semiconductor substrate to a second depth; The first transverse length and the second transverse length are parallel and equal to each other; The first transverse width and the second transverse width are equal to each other; and The first depth and the second depth are equal to each other.

13. The IC according to claim 10, wherein the sensor unit includes a deep trench isolation along the periphery of the sensor unit.

14. The IC according to claim 10, wherein: The magnetic field sensor includes a second sensor doped well in the semiconductor substrate; The first sensor doped well, the second sensor doped well, and the first resistor doped well are longitudinally parallel to each other; and The spacing between the first sensor doped well and the second sensor doped well is equal to the spacing between the first sensor doped well and the first resistor doped well.

15. The IC according to claim 10, wherein the sensor unit includes a dummy doped well in the semiconductor substrate, and the dummy doped well is electrically isolated from the first sensor doped well and the first resistor doped well.

16. The IC according to claim 10, wherein: The magnetic field sensor includes a second sensor doped well in the semiconductor substrate; The resistor includes a second resistor doped well in the semiconductor substrate; The first sensor doped well, the second sensor doped well, the first resistor doped well, and the second resistor doped well are longitudinally parallel to each other; and The first sensor doped well and the second sensor doped well are laterally located between the first resistor doped well and the second resistor doped well.

17. The IC according to claim 10, wherein: The magnetic field sensor includes a second sensor doped well in the semiconductor substrate; The resistor includes a second resistor doped well in the semiconductor substrate; The first sensor doped well and the first resistor doped well are longitudinally parallel to each other; The second sensor doped well and the second resistor doped well are longitudinally parallel to each other; The first sensor doped well and the second sensor doped well are longitudinally aligned; And The first resistor doped well and the second resistor doped well are longitudinally aligned.

18. The IC according to claim 10, wherein: The magnetic field sensor includes a second sensor doped well, a third sensor doped well, and a fourth sensor doped well in the semiconductor substrate; The resistor includes a second resistor doped well in the semiconductor substrate; The first sensor doped well, the second sensor doped well, the third sensor doped well, the fourth sensor doped well, the first resistor doped well, and the second resistor doped well are longitudinally parallel to each other; The first sensor doped well and the third sensor doped well are longitudinally aligned; And The second sensor doped well and the fourth sensor doped well are longitudinally aligned.

19. A method of manufacturing an integrated circuit (IC), the method comprising: Forming a first doped well, a second doped well, and a third doped well in a semiconductor substrate, a first spacing between the first doped well and the second doped well, a second spacing between the first doped well and the third doped well, the second spacing being equal to the first spacing; Electrically connecting the first doped well and the second doped well in a magnetic field sensor in the IC; And Electrically connecting the third doped well in a resistor in the IC.

20. The method according to claim 19, wherein: The first doped well, the second doped well, and the third doped well each have the same lateral length; The first doped well, the second doped well, and the third doped well each have the same lateral width; The first doped well, the second doped well, and the third doped well each extend into the semiconductor substrate to the same depth; and The first doped well, the second doped well, and the third doped well each have the same doping profile.

Images