System and method for context-dependent multi-core interrupt facilitation

Abstract

A multi-core processor can include a plurality of cores including at least a first core and a second core, a shared peripheral including a plurality of interrupt register sets including at least a first interrupt register set dedicated to the first core and a second interrupt register set dedicated to the second core, and a plurality of communication bridges including at least a first bridge interfacing between the first core and the shared peripheral and at least a second bridge interfacing between the second core and the shared peripheral. The first core can be configured to program the first interrupt register set via the first bridge to configure the shared peripheral for access by the first core. The second core can be configured to program the second interrupt register set via the second bridge to configure the shared peripheral for access by the second core.

Description

Technical Field

[0001] This disclosure generally relates to circuitry for electronic devices, including but not limited to personal portable devices such as cordless phones and media players, and more specifically to systems and methods for context-dependent interrupt facilitation in multi-core processing devices. Background Technology

[0002] Many mobile devices (such as mobile phones) include one or more cameras for capturing images. To provide image stabilization and focus, the position of the camera in a plane substantially parallel to the image object and the position of the camera lens in a direction perpendicular to that plane can be controlled by multiple motors under the control of the camera controller. The control system can be implemented using an application processor of the mobile device, which is local to the camera and its various motors, via a communication interface (e.g., an internal integrated circuit or an I2C interface). For example, the application processor can communicate a data vector about the target position of the application processor to the camera controller, while the camera controller can communicate a vector about the actual position of the camera sensed by multiple magnetic sensors (e.g., Hall sensors) and / or other suitable sensors to the application processor.

[0003] As mobile devices become increasingly complex, so too does camera control on these devices. Consequently, camera controllers are increasingly being implemented using multi-core processors, which can include multiple processing cores and multiple peripheral blocks on a single integrated circuit. Within such multi-core processors, multiple processes may run on different cores, consuming data or context from the peripheral blocks, or running in different execution contexts provided by the peripheral blocks.

[0004] In embedded multicore systems, there may be static, serial, and / or joint ownership of processing and / or data from peripheral blocks, which can present numerous challenges. One challenge in embedded multicore systems is that accessing peripheral blocks not specified in the core domain risks core communication bus conflicts / overhead and / or communication bus stalls.

[0005] The second challenge is that while interrupt request lines may be mapped to different cores on a multi-core processor, each core may require a mechanism to individually enable / disable or clear / set interrupts based on channel readiness or associated error conditions. For example, in a specific use case, the first core might need a data-ready interrupt from a sensor channel to handle control math, while the second core might need a voltage-dependent interrupt to perform signal compensation associated with voltage levels. Each of the two cores may also need to access an interrupt register without conflicting with writes to the other core.

[0006] The third challenge may be context awareness. In addition to making the interrupt request register accessible to each core, the peripheral block must also be able to detect the context in which an interrupt is generated. Individual cores may need the ability to enable / disable interrupts based on the type of transport on a communication link (also known as an endpoint). Endpoint-based interrupts provide the execution context, and the core must be able to configure and schedule tasks associated with that endpoint. Summary of the Invention

[0007] Based on the teachings of this disclosure, some of the drawbacks and problems associated with existing methods of implementing multi-core systems can be reduced or eliminated.

[0008] According to embodiments of this disclosure, a multi-core processor may include: a plurality of cores, including at least a first core and a second core; a shared peripheral device including a plurality of interrupt register groups, the plurality of interrupt register groups including at least a first interrupt register group dedicated to the first core and a second interrupt register group dedicated to the second core; and a plurality of communication bridges, the plurality of communication bridges including at least a first bridge interface between the first core and the shared peripheral device and at least a second bridge interface between the second core and the shared peripheral device. The first core may be configured to program the first interrupt register group via the first bridge to configure the shared peripheral device for access by the first core. The second core may be configured to program the second interrupt register group via the second bridge to configure the shared peripheral device for access by the second core.

[0009] According to these and other embodiments of this disclosure, a method can be provided for a multi-core processor having: a plurality of cores, including at least a first core and a second core; a shared peripheral device including a plurality of interrupt register groups, the plurality of interrupt register groups including at least a first interrupt register group dedicated to the first core and a second interrupt register group dedicated to the second core; and a plurality of communication bridges, including at least a first bridge interface between the first core and the shared peripheral device and at least a second bridge interface between the second core and the shared peripheral device. The method may include configuring a first core to program the first interrupt register group via the first bridge to configure the shared peripheral device for access by the first core, and configuring a second core to program the second interrupt register group via the second bridge to configure the shared peripheral device for access by the second core.

[0010] The technical advantages of this disclosure will be apparent to those skilled in the art from the accompanying drawings, specification, and claims included herein. The objects and advantages of the embodiments will be realized and achieved, at least by means of the elements, features, and combinations particularly pointed out in the claims.

[0011] It should be understood that the foregoing general description and the following detailed description are illustrative and explanatory, and do not limit the claims set forth in this disclosure. Attached Figure Description

[0012] A more complete understanding of the examples, embodiments, and certain advantages thereof can be obtained by referring to the following description taken in conjunction with the accompanying drawings, wherein like reference numerals indicate like features, and wherein:

[0013] Figure 1 A block diagram of selected components of an example mobile device according to an embodiment of the present disclosure is shown;

[0014] Figure 2 A block diagram of selected components of an example multi-core processor according to an embodiment of the present disclosure is shown. This example multi-core processor can be used to implement a control subsystem for a camera controller; and

[0015] Figure 3A and Figure 3B (It may be collectively referred to herein as "Figure 3") shows a timing diagram of the time division of communication transmission according to an embodiment of the present disclosure. Detailed Implementation

[0016] Figure 1 A block diagram of selected components of an example mobile device 102 according to an embodiment of the present disclosure is shown. Figure 1 As shown, the mobile device 102 may include a housing 101, an application processor 103, a microphone 106, a radio transmitter / receiver 108, a speaker 110, and a camera module 109 including a camera 107 and a camera controller 112.

[0017] Housing 101 may include any suitable shell, cover, or other enclosure for housing various components of mobile device 102. Housing 101 may be made of plastic, metal, and / or any other suitable material. Furthermore, housing 101 may be adapted (e.g., in size and shape) to allow mobile device 102 to be easily carried by a user of mobile device 102. Therefore, mobile device 102 may include, but is not limited to, smartphones, tablet computing devices, handheld computing devices, personal digital assistants, laptops, video game controllers, or any other device that can be easily carried by a user of mobile device 102.

[0018] Application processor 103 may be housed within housing 101 and may include any system, device, or apparatus configured to interpret and / or execute program instructions and / or process data, and may include, but is not limited to, microprocessors, microcontrollers, digital signal processors (DSPs), application-specific integrated circuits (ASICs), or any other digital or analog circuit configured to interpret and / or execute program instructions and / or process data. In some embodiments, application processor 103 may interpret and / or execute program instructions and / or process data stored in memory (not explicitly shown) and / or other computer-readable media accessible to application processor 103.

[0019] Microphone 106 may be at least partially housed within housing 101, communicatively coupled to application processor 103, and may include any system, device, or apparatus configured to convert incident sound at microphone 106 into an electrical signal that can be processed by application processor 103, wherein such sound conversion is performed using a diaphragm or sheet with capacitance that varies based on acoustic vibrations received at the diaphragm or sheet. Microphone 106 may include an electrostatic microphone, a condenser microphone, an electret microphone, a microelectromechanical system (MEMS) microphone, or any other suitable condenser microphone.

[0020] The radio transmitter / receiver 108 may be housed within a housing 101, communicatively coupled to an application processor 103, and may include any system, device, or apparatus configured to generate and transmit radio frequency signals with the aid of an antenna, and to receive radio frequency signals and convert the information carried by these received signals into a form usable by the application processor 103. The radio transmitter / receiver 108 may be configured to transmit and / or receive various types of radio frequency signals, including but not limited to cellular communications (e.g., 2G, 3G, 4G, LTE, etc.), short-range wireless communications (e.g., BLUETOOTH), commercial radio signals, television signals, satellite radio signals (e.g., GPS), and wireless fidelity.

[0021] The loudspeaker 110 may be at least partially housed within or outside housing 101, communicatively coupled to application processor 103, and may include any system, device, or apparatus configured to generate sound in response to an electro-audio signal input. In some embodiments, the loudspeaker 110 may include a dynamic amplifier employing a lightweight diaphragm mechanically coupled to a rigid frame via a flexible suspension that constrains axial movement of the voice coil through a magnetic gap. When an electrical signal is applied to the voice coil, a current in the voice coil generates a magnetic field, making it a variable electromagnet. The magnetic systems of the voice coil and driver interact to generate mechanical forces that cause the voice coil (and thus the attached cone) to move back and forth, thereby reproducing sound under the control of an applied electrical signal from the amplifier.

[0022] Camera 107 may be at least partially housed within housing 101 (and partially outside housing 101 to allow light to enter the lens of camera 107), and may include any suitable system, device, or apparatus for recording images (motion or still) into one or more electrical signals, which may be processed by application processor 103. Figure 1 As shown, camera 107 may include multiple motors 114, sensors 116, and image capture components 118.

[0023] Image capture component 118 may include a set of components configured to capture images, including but not limited to one or more lenses and image sensors for sensing the intensity and wavelength of received light. Such image capture component 118 may be coupled to application processor 103, so that camera 107 may transmit captured images to application processor 103.

[0024] Motor 114 may be mechanically coupled to one or more image capture components 118, and each motor 114 may include any suitable system, device or apparatus configured to mechanically move one or more such image capture components 118 to the desired camera position based on a control signal received from camera controller 112 indicating the desired camera position.

[0025] Sensor 116 may be mechanically coupled to one or more of image capture components 118 and / or motors 114, and may be configured to sense the position associated with camera 107. For example, a first sensor 116 may sense a first position of camera 107 relative to a first linear direction (e.g., x-position), a second sensor 116 may sense a second position of camera 107 relative to a second linear direction perpendicular to the first linear direction (e.g., y-position), and a third sensor 116 may sense a third position of camera 107 (e.g., lens position) relative to a third linear direction perpendicular to the first and second linear directions (e.g., z-position).

[0026] Camera controller 112 may be housed within housing 101, communicatively coupled to camera 107 and application processor 103 (e.g., via an internal integrated circuit (I2C) interface), and may include any system, device, or apparatus configured to control motor 114 or other components of camera 107 to position components of camera 107 in a desired location. Camera controller 112 may also be configured to receive signals from sensor 116 regarding the actual position of camera 107 and / or the state of camera 107. Figure 1 As shown, the camera controller 112 may include a control subsystem 111 and a motor driver 113.

[0027] The control subsystem 111 may be integrated into the camera controller 112 and may include any system, device, or apparatus configured to interpret and / or execute program instructions and / or process data, and may include, but is not limited to, a microprocessor, microcontroller, digital signal processor (DSP), application-specific integrated circuit (ASIC), or any other digital or analog circuit configured to interpret or execute program commands and / or process data. In some embodiments, the control subsystem 111 may interpret and / or execute program instructions and / or process data stored in memory and / or other computer-readable media accessible to the control subsystem 110. Specifically, the control subsystem 111 may be configured to perform the functions of the camera controller 112, including but not limited to controlling the motor 114 and receiving and processing data from the sensor 116. In some embodiments, the control subsystem 111 may include a multi-core processor.

[0028] The motor driver 113 may include multiple circuits, each of which is configured to receive one or more control signals (including, but not limited to, signals indicating a desired target current for the motor 114) from the control subsystem 111 and drive a drive signal (e.g., a current-mode signal) to the corresponding motor 114 in accordance with the one or more control signals in order to control the operation of such corresponding motor 114.

[0029] Figure 2 A block diagram of selected components of an example multi-core processor 200 according to an embodiment of the present disclosure is shown. This example multi-core processor 200 can be used to implement a control subsystem 111 of a camera controller 112. Figure 2As shown, the multi-core processor 200 may include: multiple cores 202 including cores 202a and 202b, memory 204 (e.g., memory 204a and 204b), bus matrix 206, multiple bridges 208 including bridges 208a and 208b each dedicated to a corresponding core 202, shared peripherals 210, and multiple interrupt request lines 222 including interrupt request lines 222a and 222b each dedicated to a corresponding core 202. Although for clarity and illustration purposes, Figure 2 Only a single shared peripheral device 210 is depicted, but it is understood that the multi-core processor 200 may include multiple shared peripheral devices 210.

[0030] Each core 202 may include a separate processing unit that can read and execute program instructions, enabling the multi-core processor 200 to execute instructions simultaneously on multiple cores 202. This can improve the overall execution speed of instruction programs that support multithreading or other parallel computing technologies. In some embodiments, the core 202 may interpret and / or execute program instructions and / or process data stored in one or more memories 204 and / or another component of the multi-core processor 200.

[0031] Memory 204 may be communicatively coupled to core 202 via bus matrix 206 and may include any system, device, or apparatus (e.g., computer-readable medium) configured to retain program instructions and / or data for a period of time. Memory 204 may include any suitable selection and / or array of RAM, EEPROM, PCMCIA card, flash memory, magnetic storage, optical-magnetic storage, or volatile or non-volatile memory.

[0032] Bus matrix 206 may include any suitable communication bus for communicatively coupling core 202, memory 204, and bridge 208 to each other. In some embodiments, bus matrix 206 may include an Advanced High-Performance Bus (AHB) conforming to the Advanced Microcontroller Bus Architecture specification.

[0033] Bridge 208 may include a peripheral bus interface configured to communicatively couple shared peripheral device 210 to core 202 via bus matrix 206. Specifically, each bridge 208 may be dedicated to a specific core 202; for example, bridge 208a may be dedicated to bus communication between core 202a and shared peripheral device 210, and bridge 208b may be dedicated to bus communication between core 202b and shared peripheral device 210. Thus, by using bridge 208, core 202 can access features of shared peripheral device 210, such as the register interface of peripheral register 212 of shared peripheral device 21. In some embodiments, bridge 208 may include an Advanced Peripheral Bus (APB) conforming to the Advanced Microcontroller Bus Architecture specification.

[0034] The shared peripheral device 210 may include any auxiliary block of the multi-core processor 200, which can receive and send information from the core 202. For example, the shared peripheral device 210 may actually include an input / output interface of the multi-core processor 200 that can interface with components external to the multi-core processor 200 (e.g., motor 114, sensor 116, and / or application processor 103). Figure 2 As shown, the shared peripheral device 210 may include a peripheral register 212 and a peripheral interrupt interface 214.

[0035] Peripheral register 212 may include memory that is local to shared peripheral device 210 for storing any relevant data and / or metadata related to core 202 accessing shared peripheral device 21.

[0036] Peripheral interrupt interface 214 may include any suitable interface for configuring interrupt handling of interrupt requests from shared peripheral device 210 to core 202, and may include multiple interrupt register groups 216, including interrupt register groups 216a and 216b, each dedicated to a respective core 202. For its respective core 202, each interrupt register group 216 may include a static interrupt configuration 218 for enabling and disabling channel data-based interrupts and a statically configured but dynamically triggered interrupt configuration 220 for enabling and disabling endpoint-based interrupts. In other words, interrupt register group 216a may include a static interrupt configuration 218a for enabling and disabling channel data-based interrupts and a statically configured but dynamically triggered interrupt configuration 220a for enabling and disabling endpoint-based interrupts for core 202a, while interrupt register group 216b may include a static interrupt configuration 218b for enabling and disabling channel data-based interrupts and a statically configured but dynamically triggered interrupt configuration 220b for enabling or disabling endpoint-based interrupts for core 202b.

[0037] For example, each core 202 can individually enable channel data ready interrupts for available channels by programming the appropriate registers of the associated static interrupt configuration 218 for that core. The replication of the interrupt registers for each core 202 allows each core 202 to select which channels to interrupt.

[0038] As another example, each core 202 can individually enable endpoint-based interrupts by programming the appropriate registers of the associated interrupt configuration 220 for that core. The endpoint communication hardware can dynamically detect the endpoint (i.e., the transmission type) embedded in the communication packet and generate an interrupt request for each core 202 for which interrupts have been enabled.

[0039] In addition, such as Figure 2 As shown, based on the interrupt configuration settings, the shared interrupt interface 214 can map the dedicated interrupt request line 222 to each core 202.

[0040] Furthermore, based on interrupt configuration settings, the shared interrupt interface 214 can allow interrupts to be dynamically redistributed from one core 202 to a subset of one or more other cores 202 in order to effectively perform load balancing according to the configuration control mode.

[0041] therefore, Figure 2 The architecture of the multi-core processor 200 shown and described above can be provided for the following:

[0042] • A mapping of each of the multiple interrupt request lines 222, wherein each interrupt request line 222 is dedicated to a corresponding core 202;

[0043] • Multiple interrupt register groups 216 for accessing and configuring multiple cores 202, wherein each interrupt register group 216 is dedicated to a corresponding core 202;

[0044] The interrupt register group 216 may include static interrupt configuration 218 for enabling and disabling channel-based interrupts for its respective core 202;

[0045] Interrupt register group 216 may include statically configured but dynamically triggered interrupt configuration 220 for enabling and disabling endpoint-based interrupts for its respective core 202; and

[0046] • Multiple bridges 208, each bridge 208 being dedicated to a corresponding core 202.

[0047] Equipping each core with a dedicated bridge 208 can significantly minimize arbitration through the bus matrix 206, but may make the bus structure of the bus matrix 206 more complex and larger, which may negatively impact the overall maximum clock speed of the core 202. To reduce or eliminate these drawbacks caused by the core 202 simultaneously accessing the shared peripheral device 210, the multi-core processor 200 may include a software architecture configured to time-divide the core 202's access to the shared peripheral device. In this case, time-division may refer to dividing communication transmissions into non-overlapping time periods, such as time periods for time-critical transmissions and time periods for non-critical transmissions. As a specific example, a core 202a may be an application core managing peripheral interactions in time-critical segments, while an operating system core may manage peripheral interactions in non-critical time periods. Figure 3 illustrates a timing diagram according to an embodiment of the present disclosure for time-dividing communication transmissions from the core 202 to the shared peripheral device 210 between time-critical time periods 302 and non-time-critical time periods 304. Other time-sharing techniques may include managing access to the shared peripheral device 210 by core 202 within interrupts with different periodicity among cores 202. While such time-sharing techniques may not completely eliminate arbitration via bus matrix 206, they can significantly minimize arbitration.

[0048] Although the use of multi-core processors in the context of camera controllers has been considered above, it should be understood that the systems and methods described herein can be applied to any suitable application.

[0049] As used herein, when two or more elements are referred to as “coupled” to each other, the term indicates that the two or more elements are connected in electronic or mechanical communication (where applicable), whether indirectly or directly, with or without intermediate elements.

[0050] This disclosure includes all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that will be understood by those skilled in the art. Similarly, where appropriate, the appended claims include all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that will be understood by those skilled in the art. Furthermore, in the appended claims, references to means or systems or components of means or systems adapted to, arranged to, capable of, configured to, enabled to, operable to, or operable to perform a particular function include that means, system, or component, whether or not it or the particular function is activated, turned on, or unlocked, provided that the means, system, or component is so adapted, arranged, capable of, configured, enabled, operable, or operable. Therefore, modifications, additions, or omissions may be made to the systems, means, or methods described herein without departing from the scope of this disclosure. For example, components of systems and means may be integrated or separated. Furthermore, the operation of the systems and means disclosed herein may be performed by more, fewer, or other components, and the described methods may include more, fewer, or other steps. Furthermore, the steps may be performed in any suitable order. As used in this document, “each” means each member of a set or each member of a subset of a set.

[0051] Although exemplary embodiments are shown in the accompanying drawings and described below, the principles of this disclosure can be implemented using any number of techniques, whether currently known or not. This disclosure should not be limited in any way to the exemplary embodiments and techniques shown in the drawings and described above.

[0052] Unless otherwise specified, the items depicted in the accompanying drawings are not necessarily drawn to scale.

[0053] All examples and conditional language described herein are intended for educational purposes to aid the reader in understanding the concepts contributed by the inventors to the further development of the art, and are to be construed as not being limited to these specific examples and conditions. Although embodiments of the present disclosure have been described in detail, it should be understood that various changes, substitutions, and modifications may be made to the disclosure without departing from its spirit and scope.

[0054] While specific advantages have been listed above, various embodiments may include some, none, or all of the listed advantages. Furthermore, other technical advantages may become apparent to those skilled in the art after reading the foregoing figures and description.

[0055] In order to help the Patent Office and any reader of any patent published in this application interpret the appended claims, the applicants wish to note that they do not intend to invoke 35 U.S.SC §112(f) for any of the appended claims or claim elements unless the words “means for…” or “steps for…” are expressly used in a particular claim.

Claims

1. A multi-core processor, comprising: Multiple cores, including at least a primary core and a secondary core; The shared peripheral device includes multiple interrupt register groups, which include at least a first interrupt register group dedicated to the first core and a second interrupt register group dedicated to the second core; as well as Multiple communication bridges, including at least a first bridge that interfaces between the first core and the shared peripheral device, and at least a second bridge that interfaces between the second core and the shared peripheral device; in: The first core is configured to program the first interrupt register set via the first bridge to configure the shared peripheral device for access by the first core; and The second core is configured to program the second interrupt register group via the second bridge to configure the shared peripheral device for access by the second core.

2. The multi-core processor according to claim 1, wherein, The shared peripheral device is configured as follows: In response to the first core programming the first interrupt register group, the first interrupt request line is mapped to the first core; and In response to the second core programming the second interrupt register group, the second interrupt request line is mapped to the second core.

3. The multi-core processor according to claim 1, wherein: The first interrupt register group includes a first static interrupt configuration for the first core for dynamically enabling and disabling channel data-based interrupts; and The second interrupt register group includes a second static interrupt configuration for the second core for dynamically enabling and disabling channel data-based interrupts.

4. The multi-core processor according to claim 1, wherein: The first interrupt register set includes a first static interrupt configuration for enabling and disabling endpoint-based interrupts for the first core; and The second interrupt register group includes a second static interrupt configuration for the second core for enabling and disabling endpoint-based interrupts.

5. The multi-core processor according to claim 1 further includes a bus matrix, the bus matrix serving as an interface between the plurality of cores and the plurality of communication bridges.

6. The multi-core processor of claim 1 further includes a software architecture configured to time-divide accesses of the plurality of cores to the shared peripheral device.

7. The multi-core processor of claim 1 further includes a software architecture configured to time-divide access to the shared peripheral device by the plurality of cores between time-critical and non-time-critical time periods.

8. The multi-core processor according to claim 1, wherein, The multiple cores are configured to dynamically reallocate interrupts from one of the multiple cores to a subset of one or more other cores based on interrupt configuration settings and configuration control modes, in order to load balance the interrupts.

9. A method for a multi-core processor, the multi-core processor having: a plurality of cores, including at least a first core and a second core; a shared peripheral device including a plurality of interrupt register groups, the plurality of interrupt register groups including at least a first interrupt register group dedicated to the first core and a second interrupt register group dedicated to the second core; and a plurality of communication bridges, including at least a first bridge interfaced between the first core and the shared peripheral device and at least a second bridge interfaced between the second core and the shared peripheral device, the method comprising: Configure the first core to program the first interrupt register group via the first bridge to configure the shared peripheral device for access by the first core; and Configure the second core to program the second interrupt register group via the second bridge to configure the shared peripheral device for access by the second core.

10. The method of claim 9, further comprising: In response to the first core programming the first interrupt register group, the first interrupt request line is mapped to the first core through the shared peripheral device; as well as In response to the second core programming the second interrupt register group, the second interrupt request line is mapped to the second core via the shared peripheral device.

11. The method according to claim 9, wherein: The first interrupt register group includes a first static interrupt configuration for the first core for dynamically enabling and disabling channel data-based interrupts; and The second interrupt register group includes a second static interrupt configuration for the second core for dynamically enabling and disabling channel data-based interrupts.

12. The method according to claim 9, wherein: The first interrupt register set includes a first static interrupt configuration for enabling and disabling endpoint-based interrupts for the first core; and The second interrupt register group includes a second static interrupt configuration for the second core for enabling and disabling endpoint-based interrupts.

13. The method of claim 9 further includes interfacing a bus matrix between the plurality of cores and the plurality of communication bridges.

14. The method of claim 9 further includes using a software architecture to time-divide the access of the plurality of cores to the shared peripheral device.

15. The method of claim 9 further includes using software architecture to divide the access of the plurality of cores to the shared peripheral device into time periods between time-critical and non-time-critical time periods.

16. The method of claim 9 further includes, based on interrupt configuration settings and configuration control modes, dynamically reallocating the interrupts of one of the multiple cores to a subset of one or more other cores among the multiple cores, so as to perform interrupt load balancing.

Images