Event-driven tracking in static timing analysis of digital circuit designs

Abstract

A method includes: receiving a circuit design (100) including circuit stages; deriving an initial logical condition of a web in a fan-out cone (302) of the input port (110) based on the original event (141); for the original event, initializing a priority queue of a logic transition event; determining a trigger event from the priority queue, the trigger event having a timestamp equal to or earlier than all other events in the priority queue and representing a logical transition at an input pin of a current circuit stage; simulating an arc from the input pin of the current circuit stage to an input pin (131) of a fan-out circuit stage (130) to generate a propagation event (147); calculating a propagation event timestamp based on: the trigger event timestamp; and a delay of the arc; enabling the propagation event to be enqueued on the priority queue; and generating a static analysis report based on the propagation event timestamp.

Description

[0001] Inventors:

[0002] Jacob Philip Thomas, Paul Gross, Norbert Heindl, Clayton McDonald Technical Field

[0003] This disclosure relates to electronic design automation (EDA) systems. In particular, this disclosure relates to event-driven tracing in static timing analysis of digital circuit design. Background Art

[0004] Digital electronic circuits include multiple (e.g., tens of millions or hundreds of millions) of transistors arranged in logic gates and other circuit elements forming subcircuits, with one or more clock signals synchronizing their activities. Signals introduce timing delays (e.g., affected by factors such as switching parameters of individual transistors, parasitic capacitance, resistance, and inductance, crosstalk (coupling between nets or wires), and the speed of light) as they propagate through these subcircuits and along wires connecting transistors within a subcircuit and between different subcircuits, and different paths through the circuit may introduce different amounts of delay between an input port and an output port.

[0005] The design process of a digital electronic circuit includes timing analysis for detecting potential timing violations (or timing constraint violations) in the circuit design between the input and output interfaces of the circuit. These timing analyses may include identifying critical timing paths between the presentation of data at the input interface of the circuit and the appearance of a valid output at the output interface of the circuit, where these critical paths include the minimum delay path (setting the lower bound of the timing delay) and the maximum delay path (setting the upper bound of the timing delay). Subsequently, these critical paths may limit the digital circuit to operate correctly only within a certain clock frequency range. Summary of the Invention

[0006] Aspects of this disclosure relate to event-driven static timing analysis of digital circuit design. According to some aspects, event-driven static timing analysis automatically identifies critical timing paths between the input and output of a circuit. Some aspects further relate to event-driven or event-based static analysis to estimate power consumption along various paths through the circuit, e.g., identifying paths with the highest power consumption. Additional aspects relate to detecting glitch behavior (e.g., at the circuit level where a circuit design exhibits glitch behavior at its output).

[0007] According to one embodiment of the present disclosure, a method includes: receiving a digital circuit design including multiple circuit levels; deriving, by a processing device, initial logic conditions of a plurality of nets in a fan-out cone of an input port based on original events at the input port of the digital circuit design; initializing a priority queue of logic transition events prioritized by corresponding timestamps for the original events; determining a trigger event from the priority queue, wherein the trigger event has a trigger event timestamp equal to or earlier than the timestamps of all other logic transition events in the priority queue, and the trigger event represents a logic transition at an input pin of a current circuit level among the multiple circuit levels; simulating a first arc of the digital circuit design from the input pin of the current circuit level to an output pin of a fan-out circuit level of the digital circuit design connected to an output of the current circuit level to generate a propagation event representing a logic transition at the input pin of the fan-out circuit level; calculating a propagation event timestamp of the propagation event based on: the trigger event timestamp; and a delay associated with the first arc connecting the current circuit level to the fan-out circuit level; enqueuing, by the processing device, the propagation event onto the priority queue according to the propagation event timestamp; and generating a static analysis report of the digital circuit design based on the propagation event timestamp.

[0008] The method may further include: determining a second trigger event from the priority queue, the second trigger event having a second trigger event timestamp equal to or earlier than the timestamps of all other logic transition events in the priority queue, the second trigger event being associated with a second current circuit level among the multiple circuit levels; simulating a second arc of the digital circuit design from an input pin of the second current circuit level to an input pin of a second fan-out circuit level of the digital circuit design connected to an output of the second current circuit level to generate a second propagation event representing a logic transition at the input pin of the second fan-out circuit level; calculating a second propagation event timestamp of the second propagation event based on: the second trigger event timestamp; and a delay associated with the second arc connecting the second current circuit level to the second fan-out circuit level; and enqueuing the second propagation event onto the priority queue according to the second propagation event timestamp, wherein the first arc and the second arc are on different timing paths through the digital circuit design.

[0009] The method may further include: determining a second trigger event from the priority queue, the second trigger event having a second trigger event timestamp equal to or earlier than the timestamps of all other logic transition events in the priority queue, the second trigger event being associated with a second current circuit level among the multiple circuit levels; and preventing the second trigger event based on determining infeasible sensitization according to logic conditions of side inputs of the second current circuit level.

[0010] The method may further include: determining a second trigger event from the priority queue, the second trigger event having a second trigger event timestamp that is equal to or earlier than all other logical transition events in the priority queue, the second trigger event being associated with a second current circuit level among the plurality of circuit levels; simulating a second arc of the digital circuit design from an input pin of the second current circuit level to an input pin of a second fanout circuit level of the digital circuit design connected to an output of the second current circuit level to generate a second propagation event representing a logical transition at the input pin of the second fanout circuit level; determining that the second propagation event does not cause a change in the logical condition at the input pin of the second fanout circuit level; and canceling the second propagation event.

[0011] Simulating the first arc of the digital circuit design may include: searching for other events on one or more other input pins of the current circuit level in a multi-input switching window around the trigger event timestamp; and in response to detecting one or more other events, applying all events in the multi-input switching window when simulating the first arc.

[0012] The method may further include: identifying a second propagation event representing a logical transition different from the logical transition of the propagation event at the input pin of the fanout circuit level, the second propagation event having a second propagation event timestamp earlier than the propagation event timestamp; and detecting runt interference based on the following function: the difference between the propagation event timestamp and the second propagation event timestamp; and the inertial delay of the timing arc.

[0013] The method may further include: determining that the current circuit level associated with the trigger event is a volatile circuit level; and adding the trigger event to an overflow queue for processing after emptying the priority queue.

[0014] The method may further include: enqueuing one or more additional primitive events at the input port of the digital circuit design onto the priority queue, the one or more additional primitive events having timestamps later than the primitive event.

[0015] The method may further include: deriving additional initial logical conditions of a plurality of nets in one or more additional fanout cones of the one or more additional input ports according to the earliest primitive event of the one or more primitive events at each of the one or more additional input ports of the digital circuit design; and enqueuing the one or more primitive events at each of the one or more additional input ports onto the priority queue.

[0016] According to one embodiment of the present disclosure, a system includes: a memory that stores instructions; and a processor coupled to the memory and executing the instructions, the instructions when executed causing the processor to: receive a digital circuit design including a plurality of circuit levels among the plurality of circuit levels; derive initial logic conditions of a plurality of nets in a fan - out cone at an input port of the digital circuit design based on a primitive event at the input port; initialize a priority queue of logic transition events prioritized by corresponding timestamps for the primitive event; determine a trigger event from the priority queue, wherein the trigger event has a trigger event timestamp equal to or earlier than the trigger event timestamps of all other logic transition events in the priority queue, the trigger event representing a logic transition at an input pin of the current circuit level; the trigger event has the highest priority value among one or more priority values of one or more events in the priority queue, the one or more priority values being calculated based on the corresponding timestamps of the one or more events in the priority queue; simulate a first arc of the digital circuit design from the input pin of the current circuit level to an input pin of a fan - out circuit level connected to an output of the current circuit level to generate a propagation event representing a logic transition at the input pin of the fan - out circuit level; calculate a propagation event timestamp of the propagation event based on: the trigger event timestamp; and a delay associated with the first arc connecting the current circuit level to the fan - out circuit level; enqueue the propagation event to the priority queue according to the propagation event timestamp; and generate a static analysis report based on the propagation event timestamp, the static analysis report including critical timing paths of the digital circuit design including the current circuit level and the fan - out circuit level.

[0017] The memory may further store instructions, the instructions when executed causing the processor to: determine a second trigger event from the priority queue, the second trigger event having a second trigger event timestamp equal to or earlier than the second trigger event timestamps of all other logic transition events in the priority queue, the second trigger event being associated with a second current circuit level among the plurality of circuit levels; and prevent the second trigger event based on determining infeasible sensitization according to logic conditions of side inputs of the second current circuit level.

[0018] The memory may further store instructions that, when executed, cause the processor to: determine a second trigger event from the priority queue, the second trigger event having a second trigger event timestamp that is equal to or earlier than all other logical transition events in the priority queue, the second trigger event being associated with a second current circuit level among the plurality of circuit levels; simulate a second arc of the digital circuit design from an input pin of the second current circuit level to an input pin of a second fanout circuit level of the digital circuit design that is connected to an output of the second current circuit level to generate a second propagation event representing a logical transition at the input pin of the second fanout circuit level; and cancel the second propagation event based on determining that the second propagation event does not cause a change in the logical condition at the input pin of the second fanout circuit level.

[0019] The memory may further store instructions that, when executed, cause the processor to simulate the first arc of the digital circuit design by: searching for other events on one or more other input pins of the current circuit level within a multi-input switching window around the trigger event timestamp; and in response to detecting one or more other events, applying all events in the multi-input switching window in the simulation of the first arc.

[0020] The memory may further store instructions that, when executed, cause the processor to: identify a second propagation event representing a logical transition different from the logical transition of the propagation event at the input pin of the fanout circuit level, and the second propagation event having a second propagation event timestamp earlier than the propagation event timestamp; and detect runt interference based on: the difference between the propagation event timestamp and the second propagation event timestamp; and the inertial delay of the timing arc.

[0021] The memory may further store instructions that, when executed, cause the processor to: determine that the current circuit level associated with the trigger event is a volatile circuit level; and add the trigger event to an overflow queue for processing after emptying the priority queue.

[0022] The static analysis report may include an event tree that includes a parent node corresponding to the trigger event and a child node associated with the parent node corresponding to the propagation event.

[0023] According to one embodiment of the present disclosure, a non - transitory computer - readable medium stores instructions that, when executed by a processor, cause the processor to: receive a digital circuit design including a plurality of circuit levels among the plurality of circuit levels; derive initial logical conditions of a plurality of nets in the fan - out cone at an input port of the digital circuit design based on original events at the input port; initialize a priority queue of logical transition events prioritized by corresponding timestamps for the original events; determine a trigger event from the priority queue, wherein the trigger event has a trigger event timestamp that is equal to or earlier than the timestamps of all other logical transition events in the priority queue, and the trigger event represents a logical transition at an input pin of the current circuit level; the trigger event has the highest priority value among one or more priority values of one or more events in the priority queue, and the one or more priority values are calculated based on the corresponding timestamps of the one or more events in the priority queue; simulate a first arc of the digital circuit design from the input pin of the current circuit level to an input pin of a fan - out circuit level connected to an output of the current circuit level to generate a propagation event representing a logical transition at the input pin of the fan - out circuit level; calculate a propagation event timestamp of the propagation event based on: the trigger event timestamp; and a delay associated with the first arc connecting the current circuit level to the fan - out circuit level; enqueue the propagation event onto the priority queue according to the propagation event timestamp; and generate a static analysis report based on the propagation event timestamp, the static analysis report including a critical path of the digital circuit design including the current circuit level and the fan - out circuit level.

[0024] The critical path of the digital circuit design may include a critical power path of the digital circuit design, which represents a path with the highest power consumption.

[0025] The non - transitory computer - readable medium may further store instructions that, when executed, cause the processor to simulate the first arc of the digital circuit design by: searching for other events on one or more other input pins of the current circuit level in a multi - input switching window around the trigger event timestamp; and in response to detecting one or more other events, applying all events in the multi - input switching window in the simulation of the first arc, wherein the path with the highest power consumption includes the current circuit level, and wherein the power consumption of the current circuit level is calculated based on the events in the multi - input switching window.

[0026] The non - transitory computer - readable medium may further store instructions that, when executed, cause the processor to: detect short - pulse interference behavior in the digital circuit design by detecting two events on the same output pin in the digital circuit design; and suppress the short - pulse interference behavior by canceling the two events on the same output pin in the digital circuit design. Description of the Drawings

[0027] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of the embodiments of the present disclosure. The drawings are provided to provide an understanding of the embodiments of the present disclosure and do not limit the scope of the present disclosure to these specific embodiments. In addition, the drawings are not necessarily drawn to scale.

[0028] Figure 1A is a circuit diagram of a small digital circuit annotated to illustrate an embodiment of the present disclosure.

[0029] Figure 1B is a circuit diagram of a small digital circuit annotated to illustrate an embodiment of the present disclosure for detecting false paths.

[0030] Figure 2 is a flowchart of a method for performing static timing analysis of a digital circuit design according to an embodiment of the present disclosure.

[0031] Figure 3A Illustrates the fan - out cone of a sub - circuit that is downstream of the original event located at the input port within the circuit design.

[0032] Figure 3B Graphically illustrates a portion of a digital circuit design, where input pins and / or input and output ports at the circuit level are represented as vertices in the graph and the edges connecting the nodes are represented by arcs at the circuit level, as well as a data structure that tracks the causal relationship of events at each vertex.

[0033] Figure 4A Illustrates an example of a self - timed clock circuit.

[0034] Figure 4B Illustrates generated based on depth - first - search - based static timing analysis and event - based static timing analysis according to an embodiment of the present disclosure Figure 4A of the signal waveforms of the signals in the circuit shown in

[0035] Figure 5A Illustrates multi - input switching on a NAND gate.

[0036] Figure 5B is a flowchart of a method for simulating a circuit level with multiple inputs according to an example of the present disclosure.

[0037] Figure 5C Illustration of a portion of a digital circuit design according to an embodiment of the present disclosure and detection and simulation of multi-input switching.

[0038] Figure 5D Depiction of a portion of a digital circuit design according to an embodiment of the present disclosure and illustration of a signal timing diagram for detecting glitch interference using event-based static timing analysis.

[0039] Figure 6A An example of a digital circuit according to an embodiment of the present disclosure that includes a volatile net in the form of the output of a multiplexer, where the digital circuit can be statically analyzed.

[0040] Figure 6B A flowchart of a method according to an embodiment of the present disclosure for handling transition events at a volatile net of a circuit design in event-based static timing analysis.

[0041] Figure 6C A flowchart of a method according to an embodiment of the present disclosure for handling overflow events from an overflow queue.

[0042] Figure 7A Illustration of the fan-out cone of a sub-circuit downstream of multiple primitive events (e.g., a sequence of three primitive events) located at an input port within a circuit design.

[0043] Figure 7B Depiction of an example of a portion of a circuit or cell according to an embodiment of the present disclosure that can exhibit undesired behavior in response to a sequence of transition events, and Figure 7C is to Figure 7B a signal timing diagram of an input signal to the circuit shown in, for illustrating the performance of static analysis using multiple primitive events on an input port.

[0044] Figure 8 Depiction of a digital circuit design according to an embodiment of the present disclosure having multiple input ports with overlapping fan-out cones and supplying primitive events to the multiple input ports.

[0045] Figure 9 Flowcharts of various processes used during the design and manufacture of an integrated circuit according to some embodiments of the present disclosure.

[0046] Figure 10 Diagram of an example computer system in which embodiments of the present disclosure can operate. Detailed Description

[0047] Aspects of the present disclosure relate to event-driven tracing in static timing analysis of digital circuit designs. Aspects of the present disclosure also relate to applying event-driven tracing to static power analysis of digital circuit designs.

[0048] The design process of a digital electronic circuit includes timing verification for determining the clock frequency range within which the design can operate without signals arriving at undesirable times (e.g., too early or too late). Incorrect signal arrival times can cause the circuit to operate in a manner inconsistent with its specified behavior, resulting in incorrect outputs. For example, if the data input to a latch (a type of memory) arrives after the falling edge of the clock (setup violation), or if the data input changes before the falling edge of the previous clock (hold violation), the latch may not store the data correctly. Similar to functional violations, hold violations cannot be resolved by adjusting the clock frequency and must be addressed when redesigning part of the circuit.

[0049] Timing analysis detects potential timing violations (or violations of timing constraints) in the circuit design as well as at the input and output interfaces. Different paths through the circuit can have different lengths, and some combinations of input signals cause these signals to take different paths through the circuit. Thus, some sets of input signals can cause the output signal to be generated too early, while other sets of input signals can cause the output signal to be generated too late. In other words, there is a timing margin within which variation is allowed (e.g., the time window between the falling edge of the previous clock signal and the falling edge of the current clock signal), and timing analysis can be used to detect whether the circuit will operate within this timing margin.

[0050] In addition, the clock signal itself travels through the digital circuit along wires that introduce propagation delays, and the clock signal may also interact with subcircuits that also change the timing of the clock signal. These timing delays and timing differences can limit the maximum clock rate of the circuit because higher clock rates have smaller or tighter timing margins and are thus more difficult to absorb the timing differences between different paths through the circuit. Moreover, some specific use cases of the circuit may require operation at a specific clock rate (e.g., higher clock rates generally provide higher computational performance while lower clock rates generally provide lower power consumption), such as to meet the minimum data processing bandwidth for data communication (e.g., on a serial link), or to meet the frame rate requirements for outputting data to a display device.

[0051] After using timing analysis to detect potential timing violations in the circuit design, an engineer can modify or redesign the circuit design to prevent these timing violations from occurring. Failure to detect and correct timing violations in the circuit design can result in the circuit design only being able to operate at a slow clock rate or may not work at all (e.g., unable to operate at a high enough clock rate to meet the design goals of the circuit).

[0052] One method of timing analysis is dynamic simulation, in which a computer system simulates the propagation of signal values through a circuit design, starting from the values supplied at the input ports of the analog circuit and the input vectors of clock transitions. The simulation takes into account the propagation delays along the wires connecting the pins of the cells in the design, and the timing delays associated with the cells in the circuit design (which can be pre-characterized or determined at runtime by simulating the cells at the transistor level) (e.g., transistor switching delays). The transitions of signal values propagating through the circuit design will be referred to herein as transition events or events.

[0053] However, due to the complexity of digital circuit designs, and since the number of possible input vectors is exponential in the number of inputs (e.g., for a sub-circuit with n input ports, the possible inputs are 2 n to the power of n) and the number of state elements (e.g., flip-flops, latches, registers, etc.), dynamic simulation can be very time-consuming. This means that only a small fraction of all possible inputs can be simulated within a reasonable amount of time, and the design cannot be exhaustively checked. In addition, human engineers must use their judgment to select this small set of input vectors to run (e.g., test cases) to try to uncover the critical paths of the design.

[0054] In contrast, static timing analysis (STA) decomposes a circuit design into timing paths and searches each of these timing paths for timing violations. A timing path is a sequence of causal propagation levels that propagates a signal transition at a source to a subsequent signal transition at a sink. Static timing analysis does not simulate the operation of the circuit in response to a given set of input vectors, and thus does not depend on user-generated input vectors for the input signals.

[0055] In some embodiments, the STA process analyzes a given circuit design as a graph and performs a search for timing violations (critical paths representing paths that cause a signal to arrive too early or too late) by applying graph traversal methods such as depth-first search (DFS) or breadth-first search (BFS) and employing a three-state (0, 1, or X) logic implication system to track the transition of signals from a source and cascading through conductive stages to a sink. For example, in the DFS method, the search begins at an input port of the circuit design and propagates the transitions through the circuit, first following the paths leading deeper into the circuit (e.g., towards downstream circuit elements) at each branch point. Once a path has reached an end point (e.g., a memory element or an output port), the DFS method backs up to the nearest branch in the search and continues to follow the next unexplored path. As a result, DFS or BFS tracks the timing paths in the topological order in which they appear in the circuit design, regardless of the timing of the transition events. This means that DFS- or BFS-based methods do not maintain temporal logic at all nets during the tracking process and cannot avoid false paths (e.g., paths that are never sensitized due to logic configuration, expected data sequences, or operating modes). Additionally, some static timing analysis techniques are unable to accurately model some types of clock networks (e.g., pulsers and shaper clock circuits and self-timed clock circuits) without user intervention. However, manual intervention in the form of default behaviors that cover the modeling of clock circuits (e.g., manually specifying false paths or manually disabling some checks) is error-prone. Thus, using DFS and BFS for static timing analysis is insufficient to automatically analyze clock networks, which include, for example, self-timed loops and clock shaping (which enables the output clock waveform of a signal at the input of a cell to be different from the input clock waveform, e.g., such that the output clock waveform can be stretched or truncated). Some techniques for overcoming the drawbacks of DFS and BFS with respect to clock networks include dynamic clock simulation (DCS), in which the clock portions of the circuit are simulated together to generate accurate clock events for the static analysis of the other (logic) portions of the circuit.

[0056] Accordingly, aspects of embodiments of the present disclosure relate to event-driven static timing analysis that tracks timing paths through a circuit design based on the chronological order of transition events.

[0057] Event-driven static timing analysis according to embodiments of the present disclosure introduces primitive events (PEs) at the input ports of a design, such as a transition from logic 0 to logic 1, or vice versa. The timing of the primitive events is controlled by the clock waveform and delays at the clock and data ports as defined by parts of the design. The primitive events propagate from the input ports to downstream circuit elements, tracking the propagation delay of the wires on their way to the input pins of the cells in the circuit. When arriving at the input pin of the current cell, new or additional events are generated for each subsequent input pin of the current cell (e.g., each input pin of a downstream cell connected to the output of the current cell), and each new event is timestamped based on the time required to reach the corresponding subsequent input pin. These new events are then added to a priority queue sorted by timestamp, where the event with the earliest timestamp appears first or at the head of the priority queue. Event-driven timing analysis proceeds by selecting the next event to process from the head of the priority queue. Thus, events are processed in chronological order, rather than in the topological order in which the circuit elements are connected in the overall circuit design.

[0058] Technical advantages of the event-driven method according to the present disclosure include (but are not limited to): accurate tracking of the timing logic at switching pins and nets compared to DFS- or BFS-based techniques; accurate handling of multi-input switches; faster performance (e.g., shorter runtimes) than comparable DFS- and DCS-based techniques; exhaustive path coverage without the use of input vectors; tracking of multiple paths through the same vertex for a given input primitive event; improved ease of use for engineers (e.g., no need to manually perform control path tracing (e.g., manually mark false paths) and no need to specify input vectors for simulation); and the ability to perform, for example, noise analysis, power analysis, and glitch detection using event-driven static analysis.

[0059] Figure 1A is a circuit diagram of a digital circuit annotated to illustrate embodiments of the present disclosure. Figure 1A The circuit shown in is chosen to illustrate various features according to the present disclosure. In fact, embodiments of the present disclosure are applicable to larger digital circuits, which may include combinational circuit elements (e.g., logic gates) as well as sequential circuit elements (e.g., registers, latches, flip-flops, and memories).

[0060] Figure 1AThe example digital circuit design 100 shown therein includes an input port 110, and the input port 110 is connected to the input pin 121 of an inverter 120. The output of the inverter 120 is connected to the first input pin 131 of a NAND (negative AND) gate 130. The input port 110 is also connected to the second input pin 132 of the NAND gate 130. The NAND gate 130 generates an output 133 in response to the values at its input pins 131 and 132. The output 133 can be connected to a register 140 or other timing circuit elements controlled by a clock signal (CLK), and thus, the static timing analysis of the circuit can determine whether there is a timing path through the digital circuit design 100 that causes a timing violation (e.g., setup violation or hold violation) based on the timing of the clock signal CLK reaching the register 140 or other timing circuit elements controlled by the clock signal CLK.

[0061] Figure 2 is a flowchart illustrating a method 200 for performing static timing analysis of a digital circuit design according to an embodiment of the present disclosure. The digital circuit design is supplied to a software program running on a computer system (e.g., the computer system 1000 described below with reference to Figure 10 and is configured to perform static analysis. The computer system includes a processor and a memory, where the memory stores the software program, and the processor executes the instructions of the computer program such that the software program configures the computer system to operate as a dedicated device for performing static timing analysis according to the present disclosure. In some instances, the digital circuit design is represented as a netlist (e.g., a netlist format consistent with the netlist formats used with SPICE, CDL, Verilog, etc.).

[0062] At 210, the processor of the computer system initializes a priority queue of logic transition events for the primitive events at the input ports of the digital circuit design. The priority queue is a data structure, where each data element added to the priority queue has a priority or priority value associated with it. The data elements can be added or enqueued to the priority in any order and are removed or dequeued from the priority queue based on their priority values. Implementations of the priority queue can use a heap data structure (but are not limited to this), and can be implemented using a linked list or an array, with different trade-offs for different implementations.

[0063] In the event-driven static timing analysis according to an example of the present disclosure, an event is a signal transition at an input or output port at the circuit level. These events are associated with timestamps that represent the time at which a logical transition (e.g., from logic 0 to logic 1 or from logic 1 to logic 0) occurs at a location (e.g., an input pin at the circuit level) in the digital circuit when the input transition (or primitive event) propagates through the digital circuit.

[0064] AtFigure 1A In the example shown, the original event 141 has a timestamp of 0 nanoseconds (ns), which is selected as the base timestamp for the static analysis of the digital circuit design 100. The original event does not necessarily have a timestamp of 0 ns, and in the case where multiple original events are supplied at different input ports of the circuit, different original events may have different timestamps (e.g., 0 ns, 1 ns, 4 ns, etc.). Additionally, an event may have a negative timestamp. Nevertheless, it may be more convenient for the earliest event to have a timestamp of 0 ns (e.g., where the lowest timestamp is 0 ns).

[0065] In embodiments of the present disclosure, the timestamp of an event is used to calculate a priority or a priority value, which is used to sort the events in a priority queue, where an earlier timestamp (e.g., a smaller timestamp value) has precedence over a later timestamp. For example, the priority queue is configured such that performing a dequeue operation on the priority queue will dequeue the event with the lowest or earliest timestamp among all events in the priority queue. In the case where two or more events have the same timestamp (e.g., a timestamp tie), the priority is further determined based on, for example, the following (i.e., breaking the tie): the order in which the events are inserted into the priority queue; the depth of the event within the circuit (e.g., the number of nodes away from the input port where the original event is supplied); a random selection based on a random number generator; etc. As used herein, when referring to the event with the highest priority in a priority queue sorted by the earliest timestamp, the highest priority event may have the same timestamp as one or more other events in the queue, where its priority value is further determined based on one or more factors other than the timestamp. While aspects of embodiments of the present disclosure relate to using a priority queue to store events to be executed, the term is used herein to refer to the functionality where events are added to the queue without considering the timestamp and where the processor dequeues events from the priority queue based on a causal order (e.g., based on the timestamp or the chronological order). As mentioned above, the priority queue can be implemented using various different underlying data structures, such as a heap, an array, a linked list, a tree, a hash table, etc.

[0066] In Figure 1A the example shown, the original event 141 is enqueued onto an empty priority queue such that it is the only event on the priority queue.

[0067] At 220, the processor derives the initial logic condition of the fan - out cone of the input port to be consistent with that before the execution of the original event. Figure 3AIllustrate the fan - out cone 302 of a sub - circuit downstream of the original event 341 located at input port 351 within a circuit design. The fan - out cone includes nets having logical states that can be affected by the state transition associated with the original event. For example, a sub - circuit (or circuit level) with an input directly connected to input port 351 will be included in the fan - out cone. Similarly, sub - circuits directly connected to the outputs of those sub - circuits will also be included in the fan - out cone 302. Circuit elements within the fan - out cone 302 can also receive side inputs (e.g., side inputs 361 and 362) originating from outside the fan - out cone 302, where the logical states of these side inputs can be controlled by other external events occurring at different input ports of the circuit (the term original event may be used herein to refer to the external event currently being traced). In some embodiments, the side inputs from outside the fan - out cone and / or other external events are automatically set such that the values facilitate the propagation of events within the fan - out cone, thereby exploring various possible paths. In some embodiments, some or all of the values of the side inputs and other external events are manually set or specified by the user.

[0068] Reference Figure 1A , the fan - out cone of the original event 141 at input port 110 includes all the circuit elements shown in the example digital circuit design 100. When deriving the initial logic conditions, the net (first net n1) connected to input port 110 is set to the logical value that makes the event effective. Since the original event 141 in the example shown in FIG. 1 is a rising logic transition from logic 0 to logic 1 (or low to high), the processor sets the initial state at the first net n1 to logic 0 (denoted as IC0) so that after the execution of the original event 141, the original event has the effect of transitioning from the initial state of logic 0 to a new state of logic 1.

[0069] Since the first net connected to the input pin 121 of the inverter 120 has an initial state of logic 0, the inverter 120 outputs logic 1, and thus the second net n2 has an initial state of logic 1. Since logic 1 is supplied to the first input pin 131 of the NAND gate 130 and logic 0 is supplied to the second input pin 132 of the NAND gate 130, the output of the NAND gate is logic 1, and thus the third net n3 has an initial state of logic 1, consistent with the operation of the circuit levels (e.g., logic gates) in the example digital circuit.

[0070] Thus, the processor determines that the initial states of the nets of the digital circuit design 100 are consistent with the initial states of the nets connected to the input port before applying the original event 141 based on the behavior of the circuit elements in the fan - out cone of the original event 141.

[0071] At 230, 240, 250, 260, and 270, the processor iteratively performs event propagation through digital circuit designs by concurrently tracking multiple signal timing paths. For example, multiple different timing paths can all be stored in a partially completed state, and events along these timing paths are executed from a priority queue based on chronological order. In contrast, a depth-first search (DFS) method for searching timing paths evaluates a single potential timing path at a time.

[0072] At 230, the processor determines whether the priority queue of events is empty. If the priority queue of events is empty, then the propagation of the original event through the digital circuit design is complete, and the process continues at 280 to analyze the results of the event-based static analysis process, as described in more detail below. If the priority queue of events is not empty (e.g., there is at least one event on the priority queue), then the processor continues at 240 by determining the triggering event from the priority queue sorted by earliest timestamp (breaking ties as necessary, as discussed above). For example, in some embodiments, determining the triggering event includes dequeuing the triggering event from the priority queue, where the determined triggering event is the event having a timestamp equal to or earlier than all other events in the priority queue, and where ties in timestamps are automatically broken as part of the determination (e.g., equal timestamps) (e.g., by using randomness or based on other factors, such as a unique event identifier associated with each event).

[0073] In Figure 1A the example, the priority queue initially stores only the original event 141, and thus the original event is dequeued at 240. The event dequeued from the priority queue and currently being processed is referred to as the triggering event.

[0074] In some examples of the present disclosure, the processor determines at 245 whether the triggering event causes a change in the logic value at the input pin it supplies. Based on determining that the triggering event does not cause a change in the logic value at its input pin (e.g., if the input pin already has a logic value of 0 and the event is a transition from logic 1 to logic 0, or if the input pin already has a logic value of 1 and the triggering event is a transition from logic 0 to logic 1), then the triggering event is discarded (since it does not produce any meaningful change), and the processor returns to 230 to select the next event from the priority queue as the next triggering event.

[0075] At 250, based on determining that the trigger event did cause a change in the logic value at the input pin, the processor traverses the fan-out of the current circuit level corresponding to the trigger event. In the example shown in FIG. 1, the original event 141 is connected to the current circuit level that includes only the first net n1, and the first net n1 has two fan-outs - one fan-out to the input pin 121 of the inverter 120 and one fan-out to the first input pin 131 of the NAND gate 130.

[0076] At 260, the processor simulates the arcs from the input pins of the current circuit level to the input pins of the fan-out circuit levels in the remaining fan-outs of the current circuit level. For example, the processor may first simulate the arc from the input port 110 to the input pin 121 of the inverter 120. Since this arc contains only a wire, the same logic transition event is directly propagated to the input pin 121 of the inverter 120 (e.g., no logical operation is required on the transition direction). Similarly, if the processor first simulates the arc from the input port 110 to the second input pin 132 of the NAND gate 130, then the same logic transition event as the original event 141 will be propagated to the second input pin 132 of the NAND gate 130. In some examples of the present disclosure, the simulation of the arcs of the current circuit level is performed using a fast SPICE (Simulation Program with Integrated Circuit Emphasis) simulator.

[0077] In the simplified example of FIG. 1, there is no timing delay caused by the wires (e.g., the wire connecting the input port 110 to the input pin 121 of the inverter 120 and the wire connecting the input port 110 to the second input pin 132 of the NAND gate 130). However, the present disclosure is not limited thereto and also includes embodiments in which the wires (or interconnects) are modeled as causing timing delays, in which case the timestamp of the event arriving at the input port is increased (e.g., moved to a later time) based on the timing delay caused by the wire. For example, the wire causes a timing delay based on factors such as resistance (R), inductance (L), and capacitance (C), which may depend on the length and cross-sectional area of the wire, the material composition of the wire, and potential wire-to-wire coupling (e.g., crosstalk).

[0078] At 270, the processor queues the propagation events (if any) generated based on the execution of the trigger event and the associated simulation at 260, where the propagation event is a transition at the input pin of the fan-out circuit level. In Figure 1A the example shown, the input pin 121 of the inverter 120 is an input pin of the first fan-out circuit level, and the second input pin 132 of the NAND gate 130 is an input pin of the second fan-out circuit level. At 270, the processor queues the logic transition event corresponding to this transition.

[0079] Then, the processor returns to operation 250 to repeat simulating the arcs at 260 and enqueueing any propagation events at 270 until all the fan-outs of the current circuit level have been analyzed, at which point the processor returns to 230 to determine whether the priority queue of events is empty, and if not, then continues to dequeue trigger events from the priority queue.

[0080] In this simplified example, since it is assumed that there is zero delay along the wire, and thus both the first propagation event 142 on the input pin 121 of the inverter 120 and the second propagation event 143 on the second input pin 132 of the NAND gate 130 have a timestamp of 0 ns, the same as the original event 141. In this case, the first propagation event 142 and the second propagation event 143 are enqueued onto the priority queue according to their timestamps, which are the same (0 ns), such that they will be dequeued according to a tiebreaker (e.g., the order in which they were enqueued or the depth in the circuit, etc.). However, the present disclosure is not limited to this. For example, the wire can be modeled as introducing a propagation delay such that the first propagation event 142 on the input pin 121 of the inverter 120 has a timestamp of 0.25 ns and the second propagation event 143 on the second input pin 132 of the NAND gate 130 has a timestamp of 0.75 ns. In this case, the first propagation event 142 and the second propagation event 143 are enqueued onto the priority queue according to their priority values (e.g., where the priority value of an event is calculated based on its timestamp, and where ties between events with equal timestamps can be broken based on other factors), such that the first propagation event 142 with a timestamp of 0.25 ns dequeues before the second propagation event 143 with a timestamp of 0.75 ns. Although events dequeue from the priority queue in causal order (e.g., based on timestamps), propagation events are not necessarily added to the priority queue in chronological order, but rather based on the order in which those propagation events were generated when their corresponding trigger events were executed.

[0081] Continuing with operation 230, where the first propagation event 142 and the second propagation event 143 are on the priority queue, and assuming the first propagation event 142 dequeues at 240. The first propagation event 142 is applied (as a trigger) at the input pin 121 of the inverter 120, and the inverter has only one fan-out, which is connected to the first input pin 131 of the NAND gate 130. Thus, the arc to be simulated at 260 passes through the inverter 120 and the wire connecting the output pin of the inverter 120 to the first input pin 131 of the NAND gate 130.

[0082] In some embodiments, events are attached to pins of a cell, where the pins are attached to nets. Execution of an event first changes the logic value of a pin, which is then transmitted to the net. As an event is simulated or executed, the current logic at its corresponding affected pin is updated based on the transition associated with the event, which then causes the net connected to the pin to be updated. In this manner, the present disclosure tracks the current logic of all nets in the fan-out cone of a start port (or start ports). Since events are processed in chronological order, the net logic can be kept consistent with all logic constants. In contrast, when net logic is processed according to a depth-first search (DFS) or breadth-first search (BFS), events may not be processed in chronological order, such that the logic values at individual nets may not be consistent with the expected actual behavior of the digital circuit design. In this example, a first propagation event 142 corresponding to a transition from logic 0 to logic 1 (logical low to logical high) at the input pin 121 of the inverter 120 is executed, which causes the output of the inverter to transition from logic high to logic low (or logic 1 to logic 0).

[0083] In a corresponding manner, via the simulation arc, the processor generates a third propagation event 145 at the first input pin 131 of the NAND gate 130. When the third propagation event 145 is executed, since the third propagation event 145 is a falling transition event (logic 1 → logic 0), the logic state of the second net n2 is updated to logic 0 (or logical low). In the example shown in FIG. 1, the inverter 120 introduces a delay of 2 ns, and thus the third propagation event 145 has a timestamp calculated based on the timestamp of its parent event (the first propagation event 142 supplied at the input pin 121 of the inverter 120) and the delay along the simulation arc (here, assuming only the 2 ns delay caused by the inverter, simplified such that the wire does not cause additional delay), such that the third propagation event 145 has a timestamp of 2 ns. Enqueue this third propagation event 145 onto the priority queue at 270. Additionally, in some embodiments, the executed trigger event is added to an event history that stores the executed events, where the event history can also be implemented as a priority queue (e.g., a history priority queue), a first-in first-out (FIFO) queue, or other data structure. Since there is no additional fan-out from the inverter 120 to process, the processor loops back to 230.

[0084] At 230, the processor determines that the priority queue is not empty because it contains the second propagation event 143 and the third propagation event 145 in order. Thus, during this loop, the second propagation event 143 dequeues from the priority queue as a trigger event. At 250, the processor determines that there is a single fan-out from the current stage to the input pin of the register 140. At 260, the processor simulates the arc of the circuit design from the second input pin 132 of the NAND gate 130 to the input pin of the register 140.

[0085] When simulating the second propagation event 143 with a timestamp of 0 ns, the second network n2 still has a logic 1 value. Thus, transitioning the logic level at the second input pin 132 of the NAND gate 130 causes the NAND gate 130 to output logic 0. Therefore, at 270, the processor enqueues a fourth propagation event 147 at the input pin of the register 140, indicating a transition from logic 1 to logic 0 (1→0). The fourth propagation event 147 has a timestamp calculated based on the delay introduced by the arc through the circuit to the next input pin (in other words, through the wire or interconnect that connects the output pin of the circuit level and the input pin of the downstream circuit level). In this case, this includes the delay introduced by the NAND gate 130 and the wire (e.g., the third network n3). As mentioned above, wire delay can be modeled based on, for example, the resistance, capacitance, and inductance characteristics of the wire. The delay introduced by a circuit level or cell can be loaded from a pre-characterized model of the cell (e.g., from a standard cell library), where the delay is looked up based on the logical conditions of the cell (e.g., the inputs to the cell, the operating voltage, and other parameters such as process dimensions), or can be calculated in a transistor-level simulation of the circuit level based on factors including the slope of the circuit level, the input and output capacitances of the circuit level, the size of the transistors, etc., where some of these factors are inherent to the design of the cell (e.g., the transistor-level parameters of the cell), and other factors can be based on the layout of the circuit (e.g., the connections between the cell and the interconnect). Assuming the NAND gate 130 introduces a 4 ns delay, the fourth propagation event 147 thus has a timestamp of 4 ns.

[0086] At this time, the processor determines at 230 that the priority queue is not empty because it contains two transition events: the third propagation event 145 with a timestamp of 2 ns and the fourth propagation event with a timestamp of 4 ns, and at 240, the processor dequeues the third propagation event 145 with a timestamp of 2 ns, where the third propagation event 145 is at the first input pin 131 of the NAND gate 130. Executing the third propagation event 145 causes the second network n2 to update to logic 0, such that the inputs to the NAND gate 130 are now logic 0 (at the first input pin 131) and logic 1 (at the second input pin 132). This causes the output of the NAND gate 130 to change from logic 0 to logic 1, resulting in the generation of a fifth propagation event 149 at the input pin of the register 140. Since the triggering event of the fifth propagation event 149 is the third propagation event 145 with a timestamp of 2 ns, and since it is assumed that the NAND gate 130 has a 4 ns delay, the timestamp on the fifth propagation event 149 is 6 ns (2 ns + 4 ns).

[0087] At this time, at Figure 1AIn the event-driven static analysis of the circuit shown, the priority queue holds two events, both of which are at the input pins of register 140. These events are the fourth propagation event 147 at 4 ns and the fifth propagation event 149 at 6 ns. These events are executed in causal order in a manner similar to that described above for other events propagating through circuit design 100 (e.g., starting from the earliest timestamp). In short, executing these events involves simulating the arc from the output pin of NAND gate 130 to register 140, including setting the logic value at the third net n3 to an appropriate value (e.g., where the fourth propagation event 147 sets the third net n3 to logic 0 and the fifth propagation event 149 sets the third net n3 to logic 1).

[0088] Continue Figure 1A In the example of, after executing the fourth propagation event 147 and the fifth propagation event 149, the processor returns to 230 to check if the priority queue is empty. When the processor detects that the priority queue is empty, at 280, the processor analyzes the causality of the events to generate a static analysis report of the circuit, where the analysis may include the longest and shortest path reports, thereby detecting timing violations in the digital circuit design based on the timestamps of the events (e.g., in Figure 1A the example of, comparing the timestamps of the fourth propagation event 147 and the fifth propagation event 149 with the timestamp of the clock event, or based on the clock signal CLK supplied to the clock input pin of register 140), presenting the critical timing paths of the circuit, generating an event dependency tree, generating a report on power consumption, generating a report on static noise analysis, and generating a representation of the switching waveforms at various points in the design based on the traced timing paths of the circuit (where the switching waveforms can be graphically displayed for the user to view). More specifically, static noise analysis involves using the timing windows of the aggressor nets to align them to have the worst impact on the victim net. The method according to the present disclosure provides more accurate timing windows without the false path problem. For example, power analysis involves using the switching activity to determine the transition frequency of the logic values on the net, and aspects of the present disclosure provide more accurate switching activity. Thus, noise and power analysis can be combined into the timing analysis aspect of the present disclosure.

[0089] The generated report can be displayed to the engineer on a display device connected to the processor, or the report can be transmitted through a computer network.

[0090] Some aspects of the present disclosure relate to canceling the propagation of events that do not result in a change in logic value, in which case, at 260, no propagation events to be queued at 270 are generated. Figure 1B is a circuit diagram of a small digital circuit annotated to illustrate an embodiment of the present disclosure for detecting false paths. Figure 1B Shows related to Figure 1AThe digital circuit design 100b is the same as the digital circuit design 100 shown in Figure 1A The initial difference between Figure 1B is that the original event 141b supplied to the input port 110b in Figure 1B is a falling transition, while the original event 141 supplied to the input port 110 in Figure 1A is a rising transition. Since the inverter 120b has an input pin 121b connected to the first net n1b and an output pin connected to the second net n2b, this difference in the original event means that the initial state of the first net n1b is set to logic 1, which also means that the initial state of the second net n2b is set to logic 0. However, since the initial value on the first input pin 131b of the NAND gate 130b is logic 0 and the initial value on the second input pin 132b of the NAND gate 130b is logic 1, the NAND gate 130b has an output 133b set to logic 1, and the third net n3b is initialized to logic 1 (the same as the initial state of the third net n3 in Figure 1A ), which is the initial value supplied to the input pin of the register 140b.

[0091] When the original event 141b propagates through the circuit design 100b, a first propagation event 142b is generated on the input pin 121b of the inverter 120b in a manner similar to that described above for Figure 1A and a second propagation event 143b is generated on the second input pin 132b of the NAND gate 130b. Similarly, the first propagation event 142b is simulated to execute the arc through the inverter 120b, and a third propagation event 145b with a timestamp of 2 ns is generated at the first input pin 131b of the NAND gate 130b.

[0092] However, different from Figure 1AContrary to the example shown in , when simulating the arc between the second input pin 132b of the NAND gate 130b and the input pin of the register 140b, the processor may determine that assuming the logical value at the first input pin 131b is logic 0 at the current time (based on the timestamp of the triggering event, which is the second propagation event 143b with a timestamp of 0 ns at this iteration), then the transition from logic 1 to logic 0 at the second input pin 132b of the NAND gate 130b means that the output 133b of the NAND gate 130b should be logic 1 (since both inputs to the NAND gate 130b have the value logic 0). However, the third net n3b already has a value of logic 1, and thus the fourth propagation event 147b from logic 0 to logic 1 (or low to high) will not cause any change. In some examples of the present disclosure, when it is determined that a propagation event will not cause any change, the event is prevented from propagating through the cell (e.g., at time 0 ns, the propagation of the second propagation event 143 at the second input pin 132 of the NAND gate 130 is blocked by the logic 0 value at the first input pin 131 of the NAND gate 130, such that the fourth propagation event 147 is not generated), so that the simulation does not generate this propagation event, and thus such a propagation event 147b is not added to the priority queue at 270.

[0093] In some cases, when a propagation event generated by simulating an arc is supplied as an input to a sequential circuit element (e.g., the register 140b) or to an output port, then, in some examples of the present disclosure, the propagation event is not added to the priority queue, e.g., because there are no additional downstream circuit elements to propagate the event for the purpose of detecting timing violations in the supplied portion of the circuit design.

[0094] Continuing with the example, since only one fanout is considered for the second propagation event 143b, the processor returns to 230, determines that the queue is not empty, and dequeues the next (and only remaining) event, which is the third propagation event 145b. The third propagation event 145b has a timestamp of 2 ns, and thus the current time of propagation is advanced to 2 ns. In the example of FIG. 1, the second propagation event 143b previously sensitized the second input pin 132b of the NAND gate 130b to logic 0. Thus, there is no possible event at the first input pin 131b that would change the output of the NAND gate 130b from its current logic 1 state to logic 0 (since both inputs need to be logic 1 for the output of the NAND gate 130 to be logic 0). Thus, at 260, the processor determines that the third propagation event 145b is blocked due to infeasible side input logic, and the processor does not generate a propagation event to be enqueued at 270. Here, the processor can determine infeasible side input logic by attempting to logically sensitize the circuit level to propagate the input transition to the expected output transition. The processor is free to set those side inputs that do not have any known logic to any beneficial logic (e.g., a set of logic values for the side inputs can be searched to sensitize the circuit such that the input transition generates the expected output transition, where the search can be a brute force search or can be performed using, for example, a satisfiability solver or SAT solver). Only those inputs that have known logic from event simulation are restricted to taking only their known logic values. If no valid sensitization of the non-triggering inputs can be selected (e.g., there is no valid sensitization for these non-triggering inputs or side inputs), then the triggering event (e.g., a transition at an input port of the circuit level) is considered blocked.

[0095] Since events that do not cause a change in the input logic level are cancelled during event execution and by blocking events that encounter infeasible side input logic, spurious propagation paths through the circuit can be avoided and static analysis time can be reduced because these events that do not contribute to determining potential timing violations are not processed during the event-driven static timing analysis process.

[0096] Although Figure 2 presented in the case of a single original event added to the queue at 210, the present disclosure is not limited thereto. In some examples of the present disclosure, multiple original events are added to the priority queue, where these different original events can correspond to logic level transitions occurring at different input ports of a digital circuit or at the same port of the digital circuit. In the case where there are multiple original events at the same port of the digital circuit, these can include a sequence of three events (e.g., 0→1, 1→0, and then 0→1 or 1→0, 0→1, and then 1→0), as will be described below with respect to Figure 7A 、 7Band 7C is described in more detail (where, at 220, the initial logic condition is set based on the earliest primitive event (in other words, the primitive event with the earliest timestamp). In the case where there are multiple primitive events on different input ports of a digital circuit, these multiple primitive events may have the same timestamp, or may have different timestamps and dequeue from a priority queue according to these timestamps, as will be described in more detail below with respect to Figure 8 In the same way, at 220, the processor determines the initial logic condition of the fan - out cone of all input ports supplied with the corresponding primitive event. (In some embodiments, there is only one primitive event such that all initial logic is related to this one primitive event. In other embodiments, there are multiple primitive events on multiple input ports such that the initial logic is determined with respect to the earliest primitive event among one or more primitive events at each input port.) Although there are multiple primitive events, Figure 2 the remaining operations of method 200 shown in

[0097] can continue as described above, and these primitive events are scheduled to execute on the priority queue like other events. Figure 3B Some aspects of the present disclosure relate to methods for tracking the causal relationships of events generated and executed through a circuit design via event propagation for event - driven static timing analysis. Figure 3B The example shown in

[0098] contains a vertex Vi with two fan - outs to a first fan - out vertex Vj and a second fan - out vertex Vk. Figure 3B To illustrate the relationship between, for example,

[0099] the graphical representation shown in Figure 3B and a circuit diagram such as that shown in FIG. 1, various parts of FIG. 1 are annotated with vertex labels - input port 110 is labeled V1, the input pin 121 to inverter 120 is labeled V2, the first input pin 131 of NAND gate 130 is labeled V3, and the second input pin 132 of NAND gate 130 is labeled V4.

[0099] In the Figure 3B example shown in Figure 2When 260 simulations of the outgoing arcs are performed and the downstream input pins or downstream ports are reachable (e.g., as shown for the first fan-out vertex Vj and the second fan-out vertex Vk), the stack [Va,..., Vi] at the current node is cloned and the fan-out vertices are pushed onto the top of the stack. Thus, the first fan-out vertex Vj is associated with the stack [Va,..., Vi, Vj], and the second fan-out vertex Vk is associated with the stack [Va,..., Vi, Vk]. Each event pushed onto the stack contains a backward pointer to its causal event (e.g., the immediately upstream event that caused the creation of the event). Thus, the stack at each vertex tracks the causality of the events and the vertices feeding into that vertex. This allows paths to be generated based on the pins and nets of the circuit design. As mentioned above, if an event does not cause a logic change, it is skipped and the corresponding vertex is not pushed onto the stack.

[0100] Figure 4A An example of a self-timed clock circuit is illustrated. As mentioned above, some static timing analysis tools based on DFS are unable to accurately model some types of clock networks (e.g., self-timed clock circuits).

[0101] Figure 4B Illustrating the signal waveform diagrams of the signals in the circuit generated according to embodiments of the present disclosure based on static timing analysis using depth-first search and event-based static timing analysis Figure 4A The numbers located at the transitions represent the timestamps of the transition events. The dotted lines in the waveforms of the signals stclk and rstclk represent the incorrect waveforms generated by static timing analysis using the depth-first search method, where the corresponding timestamps are shown in bold and underlined. The desired waveforms of stclk and rstclk generated by event-based static timing analysis according to embodiments of the present disclosure are shown as solid lines. Thus, as Figure 4B shown, the method according to the present disclosure produces more accurate results than other static timing analysis techniques.

[0102] Another aspect of the present disclosure relates to constructing an analog stage with multi-input switching. Some logic gates (e.g., the NAND gate 130 shown in FIG. 1) have multiple inputs, and the multiple inputs can switch or transition during a given clock cycle. Figure 5A Illustrating the multi-input switching on the NAND gate.

[0103] For example, inputs A and B to a NAND gate each have corresponding events that switch them from logic 0 to logic 1 (0→1) and from logic 1 to logic 0 (1→0), respectively. If the 0→1 event on input A arrives first, making both inputs high, then the output z of the NAND gate will switch from logic 1 to logic 0. If inputs A and B arrive almost simultaneously, it is difficult to determine whether there will be an output change, depending on the implementation details of the cell and how the input waveforms corresponding to the events overlap.

[0104] In addition, when inputs other than the flip-flop of an analog cell are close in time to the flip-flop switching, it can affect the delay from the flip-flop. Some aspects of the present disclosure relate to handling such effects based on performing and scheduling events that are temporally close to flip-flop events. Accordingly, some aspects of the present disclosure relate to handling multi-input switching when simulating arcs (e.g., Figure 2 at 260 in

[0105] Figure 5B is a flowchart of a method 500 for simulating a circuit level with multiple inputs according to an example of the present disclosure. When simulating an arc (e.g., at 260 in method 200 shown in Figure 2 ), the processor simulates the operation of the circuit level in response to a current transition event at an input pin of the circuit level. The transition event dequeues from the priority queue and thus represents the earliest timestamp event in the priority queue.

[0106] Figure 5C Illustrates a portion of a digital circuit design according to an embodiment of the present disclosure and the detection and simulation of multi-input switching. Figure 5C The example circuit design 580 of

[0107] In Figure 5CIn the example shown, the first NAND gate 583 introduces a delay of 5 ns, and the second NAND gate 584 introduces a delay of 4 ns. Thus, the first propagation event 586 output by the first NAND gate 583 and the second propagation event 587 output by the second NAND gate 584 have timestamps of 5 ns and 4 ns, respectively. These events are applied to the first input pin and the second input pin of the fourth NAND gate 588, but have timestamps that differ by 1 nanosecond. These propagation events are added to the priority queue and dequeued and processed in timestamp order, such that the second propagation event 587 is dequeued before the first propagation event 586 (4 ns and 5 ns, respectively). In this example, the first propagation event 586 is marked as the trigger event.

[0108] At 510, the processor searches the event history for previous input transition events (e.g., previously executed events) on other input pins of the current circuit level within a lookback window. At 515, the processor determines whether any such previous input transition events were detected in the search performed at 510. If any other previous input transition events are found in the history, then the processor continues at 540 to apply all the detected input transition events found within the multi-input transition window, as described in more detail below. If no previous input transition events are found in the lookback window, then the processor proceeds to 520.

[0109] If no previous input transition events are detected, then at 520, the processor searches the priority queue for upcoming transition events on other input pins of the current level within a lookahead time window. As mentioned above, based on the invariant maintained by the priority queue, that the timestamps of all events stored in the priority queue are greater than or equal to the timestamp of the event at the head of the priority queue, all remaining events on the queue are scheduled to occur after the trigger event.

[0110] More specifically, at 520, the processor identifies unexecuted events on other input pins of the current circuit level in the priority queue that have timestamps within a lookahead window defined based on the midpoint time of the current transition event and a lookahead offset. Figure 5A The lookahead time and lookahead offset are similarly depicted, where the lookahead time is calculated based on a lookahead time offset before the midpoint time of the trigger event.

[0111] In some examples of the present disclosure, the look-ahead offset and the look-back offset are user-configurable values and, in some cases, are set to default values calculated based on a 25% threshold offset from a 50% switching threshold of the triggering event. The midpoint or 50% switching threshold refers to the point at which the signal has completed 50% of its voltage transition (e.g., for a rising transition, from a voltage representing logic 0 to a voltage representing logic 1, or for a falling transition, from a voltage representing logic 1 to a voltage representing logic 0). The threshold offset is calculated based on a percentage offset from the midpoint voltage. More specifically, assuming that logic 0 is represented by 0V and logic 1 is represented by 4V, the midpoint or 50% switching threshold is 2V. Assuming a 25% threshold offset from the 50% threshold, the lower voltage will be 50% - 25% = 25% (e.g., 1V), and the higher voltage will be 50% + 25% = 75% (e.g., 3V). Thus, for a rising transition, the look-back offset and the look-back time will be the time at which the transition rises to 1V, and the look-ahead offset and the look-ahead time will be the time at which the transition rises to 3V. Since the rise time and the fall time of the transition event can be different, the look-ahead offset and the look-back offset can be different, depending on whether the transition event is a rising transition from logic 0 to logic 1 or a falling transition from logic 1 to logic 0. Additionally, the rise time and the fall time of the transition event can be different at different inputs, e.g., based on the output slope of the driving net of the gate and / or the input slope of the pin at which the event occurs, resulting in differences, and thus the look-back offset and the look-ahead offset will depend on the characteristics of the transition (e.g., its duration based on the slope).

[0112] At 530, the processor determines whether searching for future events at 520 results in detecting other input switches that occur within a multi-input switching window (look-ahead window plus look-back window) around the midpoint time of the triggering event. In the case where the processor determines that there are other events, then, at 540, the processor performs a circuit-level simulation by applying all the detected transition events to the respective corresponding input pins at the circuit level (keeping the other input pins constant based on the recorded state of their nets). In the case where the processor determines that there are no other events, then at 550, it applies only the current transition event in the circuit-level simulation. The circuit-level simulation result is generated and returned, whether calculated based on a multi-input switching event or a single transition event (e.g., at 270 of method 200 shown in Figure 2 ).

[0113] Although Figure 5BDisclosed is an example embodiment where searching for previous transition events in the event history takes precedence over searching for upcoming or future transition events, but the present disclosure is not limited thereto. For example, in some embodiments, future events have precedence over past events such that the processor first looks for future switching events within a look-ahead window (e.g., in a priority queue), and if no match is found in the look-ahead window, then only looks for previous switching events in the event history within a backtrack window. In still other embodiments, the processor always searches for events in both the look-ahead window and the backtrack window, simulates all events found in both windows along with the trigger event, and in some embodiments, the processor selects the event with a greater impact when considering the look-ahead window and the backtrack window. For example, the impact of a side input detected in a window can be determined based on which side input in the window provides more extreme or critical behavior. As a more specific example, in the case of an earlier signal, it is detected which window contains a side input event that results in a shorter delay (closer to the minimum delay path), and in the case of a later signal, it is detected which window contains a side input event that results in a longer delay (closer to the maximum delay path).

[0114] In Figure 5C the example shown, assuming the backtrack offset is greater than 1 ns, the processor identifies the second propagation event 587 with a timestamp of 4 ns on the second input pin of the fourth NAND gate 588 as an event that falls within the multi-input switching window (since the first propagation event 586 has a timestamp of 5 ns, and thus the backtrack offset must be at least 1 ns for the backtrack time to be earlier than the 4 ns timestamp of the second propagation event 587). Thus, when performing a simulation on the circuit level that includes the fourth NAND gate 588, both the first propagation event 586 and the second propagation event 587 are applied.

[0115] Figure 5CThe example with two inputs to the fourth NAND gate 588 shown has symmetry because treating the second propagation event 587 as the trigger event will capture the first propagation event 586 as a side event of the multi-input switching condition, and subsequently treating the first propagation event 586 as the trigger event will also capture the second fan-out as a side event of another multi-input switching condition. Although the output events generated (e.g., downstream of the fourth NAND gate 588) from the first propagation event 586 and the second propagation event 587 will be generated and scheduled, the output events scheduled later will be cancelled because the output has not changed. Nevertheless, this does not mean that the first propagation event 586 should be removed from the priority queue when it is a side event of the execution of the second propagation event 587. For example, if the fourth NAND gate 588 has more than two inputs, then a third propagation event supplied at the third input pin of the fourth NAND gate 588 may have a timestamp outside the multi-input switching window (4 ns) of the second propagation event 587 but within the multi-input switching window (5 ns) of the first propagation event 586.

[0116] In some embodiments, multi-input switching determination ensures reciprocity between multiple events on different inputs. For example, if an event on input A overlaps with an event on input B, then the event on B should also overlap with the event on input A. In some embodiments, this is implemented by applying the multi-input switching technique (e.g., as described above) a second time by switching the inputs (e.g., switching the event on input A with the event on input B). This occurs when the transition times of the two events are different, resulting in the look-ahead window and the look-back window of one of the events being larger than the look-ahead and look-back windows of the other event. For example, if the event at A completes its transition faster than the event at B, then the look-ahead or look-back window of the event at A will be relatively small, such that the event at B will be outside the window associated with the event at A, thus missing this multi-input switching scenario. Therefore, in some embodiments, the analysis is also performed as if the event at B were the trigger event, such that the window is calculated based on its transition time. In this case, the event at A may be captured within the look-back or look-ahead window of the event at B, which allows the processor to determine that the event at B should be included in the multi-input switching (MIS) analysis of the trigger event at A.

[0117] Accordingly, aspects of the present disclosure relate to incorporating side input events based on a multi-input switching window around a trigger event (or current event) into the simulation at the circuit level, which provides the benefit of improving the accuracy of the calculation of stage delays. Additionally, an event-based tracking method for multi-input switching allows switching events to occur in the same direction (e.g., all from logic 1 to logic 0 or all from logic 0 to logic 1) or in opposite directions (e.g., a mix of transitions from logic 1 to logic 0 and from logic 0 to logic 1). Further, aspects of the present disclosure relate to simulating the circuit level based only on events occurring within the multi-input switching window, rather than forcing all switching events expected to occur at the input pins of the circuit level or taking the earliest or latest side input (as in DFS or BFS), which would result in an overly pessimistic simulation and potentially lead to false alarms (e.g., reporting potential problems that will not actually occur).

[0118] Another aspect of the present disclosure relates to the static detection and suppression of short pulse wave interference. For example, due to closely spaced input events, short pulse wave interference occurs at the output of the circuit level. Again considering Figure 5A the NAND gate shown in, prior to the trigger event arriving at input pin A and the side event arriving at input pin B, the inputs to the NAND gate are logic 0 and logic 1 respectively, such that the output of the NAND gate is logic 1.

[0119] If the side event (input pin B transitioning from logic 1 to logic 0) arrives long after the trigger event has fully transitioned input pin A to logic 1, then there will be a period of time prior to the arrival of the side event during which both inputs to the NAND gate are logic 1. In an ideal logic gate without switching delay, when both inputs to the NAND gate are logic 1, the NAND gate will immediately output logic 0, and then when the side input completes the transition of input pin B to logic 0, the NAND gate will immediately output logic 1 again.

[0120] However, in a logic gate with switching delay, the response of the logic gate or cell depends on the slope of the logic gate or cell. For example, if the difference in the arrival times of the trigger event and the side event is greater than the slope of the cell (e.g., output rise time, output fall time, or their average), then the timing of the input events may result in short pulse wave interference or a temporary switch in the output of the circuit cell (e.g., logic gate) - assuming the combination of input states during that period will cause a logic change in the output of the cell.

[0121] Accordingly, some aspects of the present disclosure relate to automatically detecting a short pulse wave interference event based on detecting two close transition events on a single net. In some embodiments, short pulse wave interference detection occurs when a new event is scheduled. If a previous event in the opposite direction is detected on the same net (e.g., on the same input pin of a fan-out stage), and the time interval between the new event and the previous event (e.g., the difference in the timestamps of the events) is less than the delay through the cell (e.g., the inertial delay of an arc through the circuit), then the two events form a short pulse wave interference, provided that they are generated by different causal events. In some embodiments, whether the short pulse wave interference is propagated, fully suppressed, or partially suppressed (e.g., scaled) depends on the electrical characteristics at the circuit level and can be modeled as a function of the difference between the inertial delay at the circuit level (e.g., an arc between input pins or a timing arc) and the timestamps of the events.

[0122] Figure 5D Depicts a portion of a digital circuit design and a signal timing diagram illustrating detection of short pulse wave interference using event-based static timing analysis in accordance with embodiments of the present disclosure. In Figure 5D the example shown, a portion or cell 590 of the digital circuit design includes three input signals labeled ckpb, rst, and rstg, and one output signal labeled ckpbh_c. As shown in timing diagram 592, a rising transition event at input ckpb of cell 590 generates a first falling event 593 at output ckpbh_c. Falling transition events at the rst and rstg inputs generate corresponding first rising transition events 595 at output pin ckpbh_c. Then, a rising transition event at input rst causes a second falling transition event 597 at output pin ckpbh_c, and a falling transition event at input ckpb causes a second rising transition event 599 at output pin ckpbh_c. Here, the time difference between the first falling event 593 and the first rising event 595 is greater than the delay through cell 590, and thus these two events are not short pulse wave interference. However, the time difference between the second falling event 597 and the second rising event 599 is less than the delay through cell 590, and thus this pair of transitions is classified as short pulse wave interference. In some circuit designs, the upper limit on the width of a pulse considered to be short pulse wave interference is 10 picoseconds (ps).

[0123] In some examples of the present disclosure, the processor generates a report of all such pins or vertices where multiple transitions occur. In some additional examples, the causality stack associated with each vertex or pin (as shown in the example of 3B) is presented with the pin containing the glitch to show the causality path leading to the glitch. For example, the report may indicate that the glitch on the net ckpbh_c is caused by a specific input event (e.g., events on ckpb and rst indicated by the arrows), and may also include an identification of the causality path leading to the glitch.

[0124] As discussed above, some aspects of the embodiments relate to detecting glitches having a pulse width with an inertial delay less than the circuit level. If so, then the pulse will not propagate, and events corresponding to the glitches (e.g., events in the opposite direction) can be canceled, thereby reducing the number of events propagated through the system to perform static timing analysis.

[0125] Some aspects of the embodiments of the present disclosure relate to capturing multiple timing paths through volatile nets of a circuit (e.g., nets corresponding to the outputs of multiplexers (muxes)). The volatile nets are connected to the output pins of the unit, which have independent paths to them from the inputs.

[0126] Figure 6A is an example of a digital circuit design 600 that includes a volatile net in the form of a multiplexer, where the digital circuit can be statically analyzed according to an embodiment of the present disclosure. In Figure 6A the example shown, the input port 610 is connected to the multiplexer 620 through a first timing path 631 (shown as a dotted line) connected to the first input pin 621 of the multiplexer 620 and a second timing path 632 (shown as a dashed line) connected to the second input pin 622 of the multiplexer 620. The first timing path 631 and the second timing path 632 are connected through different logic gates of the circuit design 600 and thus experience different timing delays (e.g., based on the switching delay at the circuit level and the propagation delay along the wires). The multiplexer 620 is shown to be controlled by the mux select signal.

[0127] A raw event 641 is supplied at an input port, and as discussed above, the event is propagated to reach the input of the multiplexer 620. In this instance, the mux select is outside the fanout cone of the raw event 641 and can thus be set to the logical value X. Accordingly, it cannot be determined based on the raw event 641 which input the multiplexer 620 will select, and thus which timing path will be propagated to the output of the circuit design 600. Consequently, two timing paths will be analyzed because either one of them could be the critical timing path through the circuit design 600 (e.g., the maximum delay path or the minimum delay path).

[0128] Accordingly, aspects of embodiments of the present disclosure relate to processing events at a volatile net of a circuit design to track the propagation of different events based on different possible selections of signals through the volatile net. Some signals reaching the volatile net will be stored as overflow events on an overflow queue or a shadow queue for analysis after completion of the analysis of another event that previously passed through the volatile net.

[0129] Figure 6B is a flowchart of a method 650 for processing transition events at a volatile net of a circuit design in event-based static timing analysis according to one embodiment of the present disclosure. Figure 6B The method 650 shown in Figure 2 is similar to the method 200 shown in Figure 2 but some of the details regarding, for example, handling fanout at the circuit level at 250, 260, and 270 are shown at a higher level to reduce duplication and focus on Figure 2 additional functionality not shown in

[0130] At 651, the processor initializes a priority queue of logical transition events for a raw event at an input port of a digital circuit design, and at 652, the processor derives the initial logical condition of the fanout cone of the input port to be consistent with that before the raw event is executed.

[0131] At 653, the processor determines whether the priority queue of events is empty. If not (e.g., there is at least one event on the priority queue), then the processor proceeds at 654 to dequeue the event on the priority queue that is sorted by the earliest timestamp (breaking ties as necessary, as discussed above).

[0132] At 655, the processor determines whether the current circuit level associated with the trigger event is a volatile circuit level (e.g., whether the current circuit level is a non-volatile circuit level (such as combinational logic gates) or a volatile circuit level (such as a multiplexer)). In the case where the current circuit level is not a volatile circuit level, then the processor continues at 656 to simulate the propagation of the trigger event through each of the fan-outs of the circuit level (e.g., perform the operations at 250, 260, and 270 described above for method 200 as illustrated in Figure 2 ).

[0133] In the case where the current circuit level is a volatile circuit level, then the processor at 657 detects whether the execution event will result in a situation where there is no logical change at the volatile net connected to the output pin of the volatile circuit level (e.g., the logical state of the volatile net does change).

[0134] Based on determining at 657 that the trigger event at the volatile circuit level results in a logical change, the processor at 656 simulates the execution of the trigger event through each fan-out of the volatile circuit level.

[0135] On the other hand, if the processor detects at 657 that executing the trigger event will result in a situation where there is no logical change (where the logical state of the volatile net connected to the output pin of the volatile circuit level will not change), then at 659, the processor adds the trigger event to the overflow event queue for later processing. The events propagated from the volatile circuit level itself may propagate to other downstream volatile circuit levels (in the fan-out cone of the events passing through the volatile circuit level). For example, Figure 6A the fan-out circuit level 625 shown in is shown as having a dual-input multiplexer controlled by a second mux select signal (mux select 2) outside the fan-out cone of the original event 641. Thus, the fan-out circuit level 625 is also a volatile circuit level and similarly processes the events arriving at its first input pin 626 or its second input pin 627 as overflow events, which is done by storing the overflow events on the overflow queue.

[0136] After simulating the trigger event at 656 or adding the trigger event to the overflow queue at 659, the processor then returns to 653 to process the next event from the priority queue.

[0137] Thus, the processor continues to propagate events through the digital circuit design, only processing one of the events entering the volatile nodes until the priority queue of events is empty. At this point, the processor has calculated the timing paths through the circuit based on the selected events passing through these volatile nodes.

[0138] At 660, the processor determines whether the overflow queue is empty. If the overflow queue is not empty, there are overflow events to be processed, as Figure 6C shown (continuing from label A in Figure 6B ).

[0139] Figure 6C is a flowchart of a method for processing overflow events from an overflow queue according to an embodiment of the present disclosure. The overflow events can be processed in a manner similar to the original events, but are supplied to the inputs of the volatile network where they occurred before being added to the overflow queue. More specifically, at 661, the processor adds the overflow events from the overflow queue to the priority queue, and then, at 662, resets the values of the networks to the states of those networks at the timestamp of the overflow event (e.g., determined according to history), thereby resetting the simulation time to the timestamp of the overflow event. Then, the processor continues to A' to dequeue the newly added overflow events at 654 and continue the propagation of the events starting from the removed overflow events.

[0140] Thus, the processor continues to process the overflow events and add the overflow events to the overflow queue until all timing paths have been analyzed, such that the overflow queue is detected to be empty at 660.

[0141] In the case where the overflow queue is empty, there are no additional events to process, and the processor generates a static analysis report of the digital circuit design at step 670 based on the timestamps of the events that occurred in the event history, and then outputs the report to the user (e.g., displayed on a display device, saved to a storage device, or transmitted over a computer network to an end-user device). In some embodiments, the static analysis report includes a path report that includes a plurality of critical timing paths. Each such critical timing path is a sequence of circuits (or circuit levels) through which a signal propagates from a source to a sink, showing pins, nets, delays, etc. that form the critical timing path (e.g., minimum delay path and maximum delay path). In some embodiments, the static analysis report includes a report of the clock arrival time at the clock network. In some embodiments, the static analysis report includes the history of each event executed by the system, where the history of the events may be presented in chronological order (e.g., sorted by the timestamp of each event). Each event is associated with a unique event identifier (or event id) and identifies, for example, the direction of the transition (e.g., whether it is a rising transition or a falling transition) and the input pin on which the event is executed. Each event may also indicate the result of executing the event, such as whether it was blocked (e.g., due to an infeasible side input) or whether it propagated through the circuit level or cell into which it was input. In the case where an event propagates through a circuit level, the static analysis report further includes propagated events generated by this event at one or more outputs of the circuit level or cell, where these propagated events are also identified by unique event identifiers. These propagated events may then appear elsewhere in the static analysis report to present the results of executing these propagated events, or may be indicated as cancelled (e.g., because it does not cause a logic change at the input port to which it is applied). In some embodiments, the static analysis report is presented using a visualization tool, such as by providing a visual highlighting between the events and the corresponding locations in the circuit design and the corresponding or transition in the signal waveforms associated with various pins and / or nets (again, in some embodiments, selecting a transition in the signal waveform presents the associated information about the corresponding transition event). In some embodiments, selecting a propagated event from the current event presents the information associated with the propagated event (e.g., by scrolling the static analysis report to the section representing the propagated event, or by showing a pop-up window, or by expanding a branch of a tree representation of the relationship between the event and the propagated event, where the original event may be the root of the tree).

[0142] Some aspects of embodiments of the present disclosure further relate to pruning events from an overflow queue. For example, when performing static analysis to determine critical paths of a circuit design (e.g., critical in terms of timing or power, as described in more detail below), a processor may determine that some overflow events are not part of a critical path and thus prune them from the analysis. By pruning the overflow events, these overflow events do not need to propagate through the circuit design, thereby reducing the overall runtime for performing event-driven static analysis of the circuit design. More specifically, when selecting the next overflow event to execute (assuming the regular priority queue is empty), the processor selects the most critical event on the same vertex, thereby pruning other less critical events. The most critical event will depend on the type of analysis being performed. For example, to determine the maximum path, the most critical event is the latest event. To determine the minimum path, the earliest event is the most critical event. For power consumption or noise, the most critical event may be the event that results in the highest or lowest power consumption or the most or least amount of noise.

[0143] As mentioned above, some aspects of embodiments of the present disclosure relate to multiple primitive events on the same port of a digital circuit design. This technique can be used to capture error conditions that may occur due to, for example, rising-to-falling or falling-to-rising conditions. To test both conditions, it is sufficient to introduce three primitive events, which can be: a falling transition event, a rising transition event, and a falling transition event (falling-rising-falling); or a rising transition event, a falling transition event, and a rising transition event (rising-falling-rising).

[0144] Figure 7A Illustrates the fan-out cone of a sub-circuit downstream of multiple primitive events (e.g., a sequence of three primitive events) located at an input port within a circuit design. Figure 7A Depicts a specific instance of a falling-rising-falling sequence of primitive events, which includes a falling transition event 701 (1→0), a rising transition event 702 (0→1), and another falling transition event 703 (1→0), which are supplied to an input port 721 (labeled V1) having a fan-out cone 710. Thus, the falling transition event 701 and the rising transition event 702 cover the falling-to-rising condition, and the rising transition event 702 together with another falling transition event 703 cover the rising-to-falling condition. As discussed above, there may be side inputs to the fan-out cone 710, such as a first side input 731 and a second side input 732. The multiple primitive events have different timestamps such that one primitive event is executed at a time on the input port 721. Thus, all these primitive events are initially added to a priority queue (e.g., based on their timestamps) and executed when they dequeue from the priority queue in order to maintain the expected causal relationship of the events propagating through the fan-out cone 710 of the digital circuit. When initializing the fan-out cone of an input port (e.g., at Figure 2At 220), the initial logic condition at each of the nets in the fan - out cone is set based on the earliest primitive event (e.g., the primitive event with the earliest timestamp), which may be referred to herein as the earliest primitive event on the input port or the earliest primitive event of the fan - out cone.

[0145] Figure 7B Depicts an example of a portion of a circuit or cell 740 according to an embodiment of the present disclosure, which may exhibit undesired behavior in response to a sequence of transition events, and Figure 7C is the Figure 7B signal timing diagram of the input signal to the circuit shown in, to illustrate performing static analysis using multiple primitive events on the input port. More specifically, assume that cell 740 is supplied with a rising primitive event, followed by a falling primitive event. Cell 740 obtains an input clock signal (clk) and receives a feedback signal (clkext_adr) generated by the rising primitive event and driven by another circuit 741. As Figure 7C shown in, this feedback signal (clkext_addr) interacts with the falling primitive event because when clk is low and clkext_adr is also low, the output of the gate can be pulled up through the PMOS transistor stack. These types of interactions between the propagation events of multiple primitive events cannot be handled unless they are included in the same trace. Thus, supplying multiple primitive events enables the detection of such situations, while a single primitive event would not be able to detect such situations (because after a single primitive event, there are no additional events on the input clock signal).

[0146] Figure 8 Depicts a digital circuit design according to an embodiment of the present disclosure having a multi - input port 820 with overlapping fan - out cones (e.g., fan - out cones 800 and 810) and supplying primitive events to the multi - input port. In some embodiments, the multiple different input ports 820 are input ports for different clock signals (e.g., for tracking all clock signals in the circuit design). In some embodiments, the multiple different input ports 820 are different input ports for logic signals (e.g., data). In some embodiments, the multiple different input ports 820 include one or more input ports for clock signals and one or more input ports for logic signals. As Figure 8As shown, the first input port 821 receives one or more raw events (e.g., three raw events 801, 802, and 803), and the second input port 822 receives one or more raw events (e.g., three raw events 811, 812, and 813). The fan-out cones of the multi-input port 820 overlap such that an event propagating from one of the input ports (e.g., the first input port 821) is transmitted to a unit that is also downstream of another input port (e.g., the second input port 822). As described above, side inputs can also provide inputs of external events from outside the fan-out cones 800 and 810 of the raw events. In the case where different ones of the input ports are clock input ports, this can result in clock merging to create a new clock. When initializing the fan-out cones of multiple different input ports 820 (e.g., at Figure 2 220 of), the initial logic condition at each net in each fan-out cone is set based on the earliest raw event at the input port corresponding to the fan-out cone (e.g., the raw event with the earliest timestamp or the initial raw event of each fan-out cone). A given net may be located in the overlapping region of the fan-out cones of multiple different input ports. In this case, the earliest raw events at each of the multiple different input ports may result in the same value (consistent value) or different values (e.g., conflicting values) being derived for the initial logical state of the net in the overlapping region. In the case where the net in the overlapping region is derived as a consistent value based on all the earliest raw events of the overlapping fan-out cones in the overlapping region, the initial logic condition at the net is set to the consistent value. However, in the case where the net in the overlapping region of the two fan-out cones has two different possible values based on the earliest raw events of the two fan-out cones, the initial logic condition of the net is set to a logical value representing an unknown state (e.g., the X logic state in a logical value system, which may include, for example, the logical 0 state, the logical 1 state, and the logical X state).

[0147] Although Figure 8 an example is shown where the raw events are located at two different input ports, the present disclosure is not limited thereto, and raw events can be supplied to more than two different input ports (e.g., n different input ports, as indicated by the ellipsis between the first input port V1 821 and the second input port Vn 822). The fan-out cones of these two or more input ports can overlap according to the connections between the units downstream of these input ports in the circuit design.

[0148] In some cases, the original events are supplied to all the inputs of a digital circuit design. This increases the flexibility of design partitioning, as its implementation tracks from multiple inputs that are exposed by the design cut during partitioning, making it easier to perform accurate static analysis on portions of the overall circuit design. This also improves the ease of use for circuit designers, as the circuit designer would otherwise need to include more design upstream of the portion of the circuit of interest to facilitate tracking from a common input (which is not always possible). Tracking from data ports also provides improved accuracy, especially when performing static analysis with the multi-input switching techniques described above.

[0149] Accordingly, some aspects of embodiments of the present disclosure relate to finding critical paths, which are in turn used to determine the timing window (or minimum and maximum timing envelopes) of nets in a circuit design. This timing window is important for signal integrity analysis (crosstalk delay and noise calculations) and power analysis.

[0150] Some aspects of embodiments of the present disclosure relate to power analysis. A given circuit stage can consume a certain amount of power in response to a signal propagating to the input pins of the circuit stage. The amount of power consumed can vary depending on intrinsic factors such as the size of the transistors, the applied voltage, etc., and extrinsic factors such as whether the input transition is from logic 0 to logic 1 or from logic 1 to logic 0, and the state of the nets at other input pins of the circuit stage, and whether the event causes the output of the circuit stage to change. Thus, in some embodiments, when the simulation executes a triggering event through a circuit stage, the processor further calculates the power consumption of the circuit stage in response to the triggering event. By summing the power consumption of each circuit stage of a timing path, the processor calculates the power consumption of the path through the circuit (e.g., based on switching activity), and can thus determine, for example, critical power paths corresponding to maximum and minimum power consumption, and / or calculate the detailed power consumption values for each path through the circuit.

[0151] As discussed above, after performing event-driven static timing analysis on a circuit design, the processor generates a report of the analysis results and presents the report to the user, e.g., by displaying the report on a display device, transmitting the report over a network, or storing the report in a persistent storage device (e.g., a solid-state drive or a network-accessible cloud storage device). For example, embodiments of the present disclosure implement extracting timing models to generate library files (e.g.,.lib files) that contain the timing, noise, and power abstractions of the circuit for feeding into a hierarchical analysis flow.

[0152] Some aspects of embodiments of the present disclosure relate to generating an event tree and initial logic conditions. An event tree according to some embodiments is a representation of events and their causal relationships, traced back to the original event. This event tree can be represented in text or graphical form, e.g., stored as a collection of linked nodes in a graphical data structure.

[0153] In some examples of the present disclosure, an event tree is tracked by associating each event with a unique event identifier (or event ID). When propagating an event and generating fan-out events based on a corresponding triggering event, the processor stores the fan-out event ID in association with its corresponding triggering event or parent event (or, in the case of multi-input switching, multiple triggering events or parent events).

[0154] Additionally, in some embodiments, events that are blocked, pruned, cancelled, etc. are presented in the event tree along with their parent events on the trace path back to the original event. This allows a user to view the causal paths that led to an event being blocked, pruned, or cancelled when analyzing the behavior of a circuit design.

[0155] Accordingly, aspects of embodiments of the present disclosure relate to event-driven static timing analysis of digital circuit designs to trace timing paths through a circuit. The event-driven approach provides more accurate results than other techniques for static timing analysis based on depth-first search and provides an exhaustive analysis of all timing paths, rather than just sampling the behavior of a circuit based on a small selection of possible input vectors to the circuit. Aspects of embodiments of the present disclosure also relate to performing power analysis using event-driven static analysis of digital circuit designs. When tested on ten real circuit designs of different sizes, the event-driven method according to the present disclosure was also on average approximately 4.75 times faster than a comparable method based on dynamic clock simulation (DCS).

[0156] Figure 9 A set of example processes 900 are described for use during the design, verification, and fabrication of a work in progress (e.g., an integrated circuit) to transform and verify design data and instructions representing the integrated circuit. Each of these processes may be structured and implemented as multiple modules or operations. The term 'EDA' represents the term 'electronic design automation'. These processes begin with creating a product idea 910 from information supplied by a designer, which is transformed to create a work in progress using a set of EDA processes 912. When the design is complete, the design is taped out 934, at which time the artwork of the integrated circuit (e.g., geometric patterns) is sent to a fabrication plant to manufacture a mask set, which is then used to manufacture the integrated circuit. After tape out, a semiconductor die 936 is fabricated, and packaging and assembly processes 938 are performed to produce a finished integrated circuit 940.

[0157] The scope of the specification of a circuit or electronic structure can range from low-level transistor material layout to high-level description languages. High-level representations can be used to design circuits and systems using hardware description languages (‘HDLs’) such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. The HDL description can be transformed into a logic-level register transfer level (‘RTL’) description, a gate-level description, a layout-level description, or a mask-level description. Each lower representation level as a more detailed description adds more useful details to the design description, for example, more details of the modules containing the description. The lower representation levels as more detailed descriptions can be computer-generated, exported from a design library, or created by another design automation process. An example of a specification language for a lower-level representation language for specifying a more detailed description is SPICE, which is used to detail circuits with many analog components. Enable the description of each representation level to be used by the corresponding system (e.g., a formal verification system) of the layer. The design process can use Figure 9 the sequence depicted in Figure 9 The process described by

[0158] During system design 914, specify the functionality of the integrated circuit to be manufactured. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction, etc. At this stage, the design can be divided into different types of modules or components.

[0159] During logic design and functional verification 916, specify the modules or components in the circuit in one or more description languages and check the functional accuracy of the specification. For example, the components of the circuit can be tested to generate an output that matches the specification requirements of the designed circuit or system. Functional verification can use simulators and other programs such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, a special system of components called an ‘emulator’ or ‘prototyping system’ is used to accelerate functional verification.

[0160] During synthesis and test design 918, the HDL code is transformed into a netlist. In some embodiments, the netlist can be a graphical structure where the edges of the graphical structure represent the components of the circuit and where the nodes of the graphical structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical artifacts that can be used by EDA products to verify whether the integrated circuit performs according to the specified design when manufactured. The netlist can be optimized for the target semiconductor manufacturing technology. Additionally, the finished integrated circuit can be tested to verify whether the integrated circuit meets the specification requirements.

[0161] During netlist verification 920, the netlist is checked for compliance with timing constraints, which may include applying event-driven static timing analysis according to embodiments of the present disclosure, and for correspondence with the HDL code. During design planning 922, an overall floorplan of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0162] During placement or physical implementation 924, physical placement (e.g., positioning of circuit components such as transistors or capacitors) and routing (connecting circuit components via multiple conductors) are performed, and units may be selected from a library to implement a particular logic function. As used herein, the term 'unit' may designate a set of transistors, other components, and interconnections that provide a Boolean logic function (e.g., AND, OR, NOT, XOR) or a storage function (e.g., flip-flop or latch). As used herein, a circuit 'block' may refer to two or more units. Both units and circuit blocks may be referred to as modules or components and are enabled both as physical structures and in simulation. Parameters, such as size, are specified for selected units (based on'standard cells') and made accessible in a database for use by EDA products.

[0163] During analysis and extraction 926, the circuit function is verified at the layout level, which allows for improvement of the layout design. During physical verification 928, the layout design is checked to ensure that manufacturing constraints (e.g., DRC constraints, electrical constraints, lithography constraints) are correct and that the circuit function matches the HDL design specifications. During resolution enhancement 930, the geometry of the layout is transformed to improve the way the circuit design is manufactured.

[0164] During tape-out, data is created for the production of lithography masks (after applying lithography enhancements, where appropriate). During mask data preparation 932, the 'tape-out' data is used to generate lithography masks for the production of the finished integrated circuit.

[0165] A storage subsystem of a computer system (e.g., Figure 10 computer system 1000) may be used to store programs and data structures for use by some or all of the EDA products described herein and products for developing units for libraries and physical and logical designs using the libraries.

[0166] Figure 10 An example machine of computer system 1000 is described, within which a set of instructions may be executed to cause the machine to perform any one or more of the methods discussed herein. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0167] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network device, a server, a network router, a switch, or a bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specify actions to be taken by the machine. Further, although a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein.

[0168] Example computer system 1000 includes a processing device 1002, a main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM))), a static memory 1006 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 1018, which communicate with each other via a bus 1030.

[0169] Processing device 1002 represents one or more processors, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or multiple processors implementing a combination of instruction sets. Processing device 1002 can also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 1002 can be configured to execute instructions 1026 for performing the operations and steps described herein.

[0170] Computer system 1000 can further include a network interface device 1008 to communicate via a network 1020. Computer system 1000 can also include a video display unit 1010 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1012 (e.g., a keyboard), a cursor control device 1014 (e.g., a mouse), a graphics processing unit 1022, a signal generation device 1016 (e.g., a speaker), a graphics processing unit 1022, a video processing unit 1028, and an audio processing unit 1032.

[0171] The data storage device 1018 may include a machine-readable storage medium 1024 (also referred to as a non-transitory computer-readable medium) having stored thereon one or more sets of instructions 1026 or software embodying any one or more of the methods or functions described herein. During execution of instructions 1026 by the computer system 1000, the instructions 1026 may also reside completely or at least partially within the main memory 1004 and / or within the processing device 1002, which also constitutes a machine-readable storage medium.

[0172] In some embodiments, the instructions 1026 include instructions that implement functionality corresponding to the present disclosure. Although the machine-readable storage medium 1024 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and that causes the machine and the processing device 1002 to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0173] Some of the foregoing detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is a series of operations that results in a desired result. The operations are those requiring physical manipulation of physical quantities. These quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0174] However, it should be borne in mind that all such and similar terms are to be associated with appropriate physical quantities and are merely convenient labels applied to these quantities. As is apparent from the present disclosure, unless otherwise expressly specified, it should be understood that throughout the description, certain terms refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the computer system memory or registers or other such information storage devices.

[0175] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0176] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various other systems may be used with the programs according to the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein.

[0177] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.

[0178] In the foregoing disclosure, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. Obviously, various modifications can be made thereto without departing from the broader spirit and scope of the present disclosure as set forth in the appended claims. In cases where the present disclosure refers to some elements in the singular, more than one element may be described in the figures and the same numerals are used to label the same elements. Therefore, the present disclosure and the figures should be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method, comprising: Receiving a digital circuit design including a plurality of circuit levels; Deriving, by a processing device, initial logic conditions of a plurality of nets in a fan - out cone of an input port based on original events at the input port of the digital circuit design; Initializing, for the original event, a priority queue of logic transition events prioritized by corresponding timestamps; Determining a trigger event from the priority queue, wherein the trigger event has a trigger event timestamp equal to or earlier than the timestamps of all other logic transition events in the priority queue, and the trigger event represents a logic transition at an input pin of a current circuit level among the plurality of circuit levels; Simulating a first arc of the digital circuit design from the input pin of the current circuit level to an output pin of a fan - out circuit level of the digital circuit design connected to the output of the current circuit level to generate a propagation event representing a logic transition at the input pin of the fan - out circuit level; Calculating a propagation event timestamp of the propagation event based on: The trigger event timestamp; And A delay associated with the first arc connecting the current circuit level to the fan - out circuit level; Enqueuing, by the processing device, the propagation event onto the priority queue according to the propagation event timestamp; And Generating a static analysis report of the digital circuit design based on the propagation event timestamp.

2. The method according to claim 1, further comprising: Determining a second trigger event from the priority queue, the second trigger event having a second trigger event timestamp equal to or earlier than the timestamps of all other logic transition events in the priority queue, and the second trigger event being associated with a second current circuit level among the plurality of circuit levels; Simulating a second arc of the digital circuit design from an input pin of the second current circuit level to an input pin of a second fan - out circuit level of the digital circuit design connected to the output of the second current circuit level to generate a second propagation event representing a logic transition at the input pin of the second fan - out circuit level; Calculating a second propagation event timestamp of the second propagation event based on: The second trigger event timestamp; And A delay associated with the second arc connecting the second current circuit level to the second fan - out circuit level; And Enqueuing the second propagation event onto the priority queue according to the second propagation event timestamp, wherein the first arc and the second arc are on different timing paths through the digital circuit design.

3. The method according to claim 1, further comprising: Determining a second trigger event from the priority queue, the second trigger event having a second trigger event timestamp equal to or earlier than the timestamps of all other logic transition events in the priority queue, and the second trigger event being associated with a second current circuit level among the plurality of circuit levels; And Blocking the second trigger event based on determining infeasible sensitization according to logic conditions of side - inputs of the second current circuit level.

4. The method according to claim 1, further comprising: Determine a second trigger event from the priority queue, the second trigger event having a second trigger event timestamp that is equal to or earlier than all other logical transition events in the priority queue, the second trigger event being associated with a second current circuit level among the plurality of circuit levels; Simulate a second arc of the digital circuit design from an input pin of the second current circuit level to an input pin of a second fanout circuit level of the digital circuit design that is connected to an output of the second current circuit level to generate a second propagation event representing a logical transition at the input pin of the second fanout circuit level; Determine that the second propagation event does not cause a change in the logical condition at the input pin of the second fanout circuit level; and Cancel the second propagation event.

5. The method according to claim 1, wherein simulating the first arc of the digital circuit design comprises: Search for other events on one or more other input pins of the current circuit level in a multi-input switching window around the trigger event timestamp; and In response to detecting one or more other events, apply all events in the multi-input switching window when simulating the first arc.

6. The method according to claim 1, further comprising: Identify a second propagation event representing a logical transition different from the logical transition of the propagation event at the input pin of the fanout circuit level, the second propagation event having a second propagation event timestamp earlier than the propagation event timestamp; and Detect runt interference based on the following function: The difference between the propagation event timestamp and the second propagation event timestamp; and The inertial delay of the timing arc.

7. The method according to claim 1, further comprising: Determine that the current circuit level associated with the trigger event is a volatile circuit level; and Add the trigger event to an overflow queue for processing after emptying the priority queue.

8. The method according to claim 1, further comprising: Enqueue one or more additional primitive events at the input port of the digital circuit design onto the priority queue, the one or more additional primitive events having a timestamp later than the primitive event.

9. The method according to claim 1, further comprising: Derive additional initial logical conditions for a plurality of nets in one or more additional fanout cones of the one or more additional input ports according to the earliest primitive event among the one or more primitive events at each of the one or more additional input ports of the digital circuit design; and Enqueue the one or more primitive events at each of the one or more additional input ports onto the priority queue.

10. A non-transitory computer-readable medium comprising stored instructions that, when executed by a processor, cause the processor to perform the method according to any one of claims 1 to 9.

11. A system comprising: A memory that stores instructions; and A processor coupled to the memory and executing the instructions, the instructions when executed causing the processor to: Receive a digital circuit design including a plurality of circuit levels among the plurality of circuit levels; Derive initial logic conditions for a plurality of nets in the fan - out cone at the input port based on the original event at the input port of the digital circuit design; Initialize a priority queue of logic transition events sorted by corresponding timestamps for the original event; Determine a trigger event from the priority queue, where the trigger event has a trigger event timestamp equal to or earlier than the trigger event timestamps of all other logic transition events in the priority queue, and the trigger event represents a logic transition at an input pin of the current circuit level; The trigger event has the highest priority value among one or more priority values of one or more events in the priority queue, and the one or more priority values are calculated based on the corresponding timestamps of the one or more events in the priority queue; Simulate a first arc of the digital circuit design from the input pin of the current circuit level to the input pin of a fan - out circuit level connected to the output of the current circuit level to generate a propagation event representing a logic transition at the input pin of the fan - out circuit level; Calculate the propagation event timestamp of the propagation event based on: The trigger event timestamp; And The delay associated with the first arc connecting the current circuit level to the fan - out circuit level; Enqueue the propagation event onto the priority queue according to the propagation event timestamp; And Generate a static analysis report based on the propagation event timestamp, the static analysis report including critical timing paths of the digital circuit design including the current circuit level and the fan - out circuit level.

12. The system according to claim 11, wherein the memory further stores instructions that, when executed, cause the processor to: Determine a second trigger event from the priority queue, the second trigger event having a second trigger event timestamp equal to or earlier than the second trigger event timestamps of all other logic transition events in the priority queue, and the second trigger event being associated with a second current circuit level among the plurality of circuit levels; and Block the second trigger event based on determining infeasible sensitization according to the logic conditions of side inputs of the second current circuit level.

13. The system according to claim 11, wherein the memory further stores instructions that, when executed, cause the processor to: Determine a second trigger event from the priority queue, the second trigger event having a second trigger event timestamp equal to or earlier than the second trigger event timestamps of all other logic transition events in the priority queue, and the second trigger event being associated with a second current circuit level among the plurality of circuit levels; Simulate a second arc of the digital circuit design from the input pin of the second current circuit level to the input pin of a second fan - out circuit level of the digital circuit design connected to the output of the second current circuit level to generate a second propagation event representing a logic transition at the input pin of the second fan - out circuit level; And Cancel the second propagation event based on determining that the second propagation event does not cause a change in the logic conditions at the input pin of the second fan - out circuit level.

14. The system according to claim 11, wherein the memory further stores instructions that, when executed, cause the processor to simulate the first arc of the digital circuit design by: Searching for other events on one or more other input pins of the current circuit level in a multi-input switching window around the trigger event timestamp; and In response to detecting one or more other events, applying all events in the multi-input switching window in the simulation of the first arc.

15. The system according to claim 11, wherein the memory further stores instructions that, when executed, cause the processor to: Identify a second propagation event representing a logic transition different from the logic transition of the propagation event on the input pin of the fan-out circuit level, and the second propagation event has a second propagation event timestamp earlier than the propagation event timestamp; and Detect runt interference based on the following function: The difference between the propagation event timestamp and the second propagation event timestamp; and The inertial delay of the timing arc.

16. The system according to claim 11, wherein the memory further stores instructions that, when executed, cause the processor to: Determine that the current circuit level associated with the trigger event is a volatile circuit level; and Add the trigger event to an overflow queue for processing after emptying the priority queue.

17. The system according to claim 11, wherein the static analysis report includes an event tree that includes a parent node corresponding to the trigger event and child nodes associated with the parent node corresponding to the propagation event.

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