Chip packaging structure and electronic equipment

Abstract

The embodiment of the invention discloses a chip packaging structure and electronic equipment. According to the chip packaging structure, a resin material is constructed outside a chip to form overall protection, a first packaging resin layer is located on the back side of the chip, a second packaging resin layer is located on the front side of the chip, and the first packaging resin layer and the second packaging resin layer are jointed to form a packaging body; and an external pin of the chip packaging structure is arranged on the second packaging resin layer, and the external pin is electrically connected with a pin located on the front surface of the chip through a metallization structure, so that a substrate-free chip packaging scheme is constructed and formed. Through the arrangement, stress caused by temperature change is effectively reduced, and the production reliability is improved; and the interconnection path between the chip pin and the external pin is shorter, so that the influence of parasitic parameters on the product performance can be reduced. On the basis of improving the reliability and performance of the product, the product size can be reduced, and the manufacturing cost is reduced.

Description

Technical Field

[0001] Embodiments of the present application relate to the technical field of chip packaging, and in particular, to a chip packaging structure and an electronic device. Background Art

[0002] Research on sensors fabricated based on micro-electromechanical systems (MEMS) technology has been continuously developing. For example, but not limited to, sensors such as inertial measurement units (IMUs), gyroscopes, and accelerometers, and have been widely used in related products in fields such as automotive and consumer (mobile phones, smart wearables, etc.).

[0003] MEMS device-level packaging generally includes key basic processes such as micro-sensor chip bonding, wire bonding, capping, and hermetic welding. Due to the complex interaction between packaging and harsh environments, the stress introduced during the packaging process is likely to cause sensor structure failures, such as chip cracks, bond wire fractures, and chip-substrate delamination. Therefore, reducing the stress introduced by the packaging process can effectively improve the output performance (accuracy, resonant frequency, quality factor, etc.) and reliability of the sensor. Summary of the Invention

[0004] Embodiments of the present application provide a chip packaging structure and an electronic device, which reduce packaging stress by optimizing the packaging architecture and improve the impact of stress deformation on chip performance and reliability.

[0005] In the first aspect of the embodiments of the present application, a chip packaging structure is provided. The chip packaging structure includes a chip, a first encapsulation resin layer, and a second encapsulation resin layer. Among them, the first encapsulation resin layer is located on the back side of the chip, the second encapsulation resin layer is located on the front side of the chip, and the first encapsulation resin layer and the second encapsulation resin layer are joined to form an encapsulation body; a resin material is used to construct an overall protection outside the chip. The external pins of the chip packaging structure are arranged on the second encapsulation resin layer, and the external pins are electrically connected to the pins located on the front side of the chip through a metallization structure, thereby constructing a substrate-less chip packaging solution. By setting it like this, it is possible to avoid the packaging stress caused by chips and substrates or carrier plates with different coefficients of thermal expansion due to temperature changes during the packaging process, as well as the stress that may be generated due to temperature changes during use, and avoid phenomena such as cracks in the chip, broken bonding wires, or delamination caused by excessive stress, thereby improving production reliability; moreover, the interconnection path from the chip pins to the external pins is shorter, the parasitic parameters are smaller, which is beneficial to improving product performance; based on this substrate-less chip packaging solution, the stress generated due to temperature changes can be controlled and adjusted by the thickness or material formula of the first encapsulation resin layer or the second encapsulation resin layer, thereby improving the impact caused by stress deformation. While improving product reliability, the product size can be further reduced and the manufacturing cost can be lowered.

[0006] In addition, compared with the traditional substrate packaging including a chip, a substrate, and packaging materials, due to the mechanical stress introduced by different material properties, this solution uses encapsulation resin to form an encapsulation body, reducing the possibility of introducing mechanical stress due to material differences. In addition, the substrate-less chip packaging structure is directly mounted on a single board, and the heat transfer path formed between the two has a relatively low thermal resistance, which can improve the heat dissipation performance, thereby reducing the temperature gradient of the chip in the use state and reducing the stress impact that may be generated due to temperature changes, further improving the use reliability.

[0007] At the same time, the encapsulation body formed based on the encapsulation resin material can, to a certain extent, relieve the mechanical stress from the external environment and effectively reduce the impact of mechanical shock or vibration on the packaging structure; in particular, for MEMS sensors, they may be subject to greater mechanical vibration and temperature changes in the actual scenario, and the above-mentioned advantages of stress reduction and buffer capacity improvement are more significant.

[0008] Exemplarily, the resin material for making the first encapsulation resin layer and the second encapsulation resin layer can be made of epoxy resin, silica gel, or phenolic resin, and can also be made of epoxy resin composite material.

[0009] In practical applications, at least one of the first encapsulation resin layer and the second encapsulation resin layer is made of epoxy resin, silica gel, or phenolic resin.

[0010] Based on the first aspect, the embodiments of the present application further provide a first implementation manner of the first aspect: The first encapsulation resin layer and the second encapsulation resin layer are made of the same material. For example, both are made of epoxy resin material, so as to have good bonding compatibility, thereby achieving seamless bonding on the outer periphery of the chip and improving the bonding reliability. Alternatively, the first encapsulation resin layer and the second encapsulation resin layer can also be made of different materials. For example, the first encapsulation resin layer is made of epoxy resin, and the second encapsulation resin layer is made of thermally conductive silica gel, so as to adjust the stress deformation of both sides of the chip under the strain environment as needed, and avoid affecting the chip performance and service reliability.

[0011] Based on the first aspect, or the first implementation manner of the first aspect, the embodiments of the present application further provide a second implementation manner of the first aspect: There are multiple chips in the chip packaging structure, and the multiple chips are arranged in a tiled manner. That is, they are laid along the extension direction of the chip body, and the thickness dimension can be reasonably controlled; in practical applications, at least two chips are electrically connected by leads to meet different product performance requirements.

[0012] Based on the first aspect, or the first implementation manner of the first aspect, the embodiments of the present application further provide a third implementation manner of the first aspect: There are multiple chips in the chip packaging structure, and the multiple chips are arranged in a stacked manner in sequence, that is, stacked along a direction perpendicular to the extension direction of the chip body, and the board area can be reasonably controlled; the multiple chips are electrically connected by leads, and the chip arranged closer to the external pins among the multiple chips is electrically connected to the external pins through a metallization structure.

[0013] Based on the first aspect, or the first implementation manner of the first aspect, the embodiments of the present application further provide a fourth implementation manner of the first aspect: There are multiple chips in the chip packaging structure, and the multiple chips are arranged in a stacked manner to form multiple stacked layers, and at least two chips are arranged in a tiled manner in at least one stacked layer; the chip arranged closer to the external pins among the multiple chips is electrically connected to the external pins through a metallization structure; the other chips among the multiple chips are electrically connected to the chip arranged closer to the external pins by leads. In this way, a multi-chip packaging structure is constructed by using a combined layout method of tiling and stacking, and the chip layout can be realized as needed to meet the usage requirements of high-density scenarios.

[0014] Based on the third implementation manner of the first aspect, or the fourth implementation manner of the first aspect, the embodiments of the present application further provide a fifth implementation manner of the first aspect: In the stacking direction, adjacent two chips are fixed with an adhesive. The structure is stable and reliable.

[0015] Based on the first aspect, or the first implementation manner of the first aspect, or the second implementation manner of the first aspect, or the third implementation manner of the first aspect, or the fourth implementation manner of the first aspect, or the fifth implementation manner of the first aspect, the embodiments of the present application further provide a sixth implementation manner of the first aspect: The metallized structure is a lead, a stud, a solder ball, a via hole or a conductive post.

[0016] Exemplarily, the metallized structure can be fabricated first and then the encapsulation resin layer can be fabricated. For example, a lead for electrically connecting the chip pins and the external pins can be vertically formed by using a wire bonding process. For another example, a stud for electrically connecting the chip pins and the external pins can be formed by using a stud bumping process.

[0017] Other exemplarily, the encapsulation resin layer can be fabricated first and then the metallized structure can be fabricated. For example, holes are formed at positions corresponding to the chip pins on the second encapsulation resin layer, and a conductive material is coated in the holes by using an electroplating process to form conductive vias; for another example, holes are formed at positions corresponding to the chip pins on the second encapsulation resin layer, and a conductive post is formed in the holes by using a silver paste hole filling process.

[0018] Based on the first aspect, or the first implementation manner of the first aspect, or the second implementation manner of the first aspect, or the third implementation manner of the first aspect, or the fourth implementation manner of the first aspect, or the fifth implementation manner of the first aspect, or the sixth implementation manner of the first aspect, the embodiments of the present application further provide a seventh implementation manner of the first aspect: The external pins of the chip package structure are pads located on the surface of the second encapsulation resin layer.

[0019] In practical applications, the external pins of the pad structure can be fabricated by using an electroplating process to be welded to the corresponding interfaces of the external single board to achieve electrical connection.

[0020] Based on the first aspect, or the first implementation manner of the first aspect, or the second implementation manner of the first aspect, or the third implementation manner of the first aspect, or the fourth implementation manner of the first aspect, or the fifth implementation manner of the first aspect, or the sixth implementation manner of the first aspect, or the seventh implementation manner of the first aspect, the embodiments of the present application further provide an eighth implementation manner of the first aspect: The external pins of the chip package structure are solder balls electrically connected to the metallized structure. Exemplarily, the solder ball structure can be arranged in a grid array form to improve the processability of the upper board soldering and assembly.

[0021] Based on the eighth embodiment of the first aspect, the embodiment of the present application also provides a ninth embodiment of the first aspect: the second encapsulating resin layer is provided with a surface pad electrically connected to the metallization structure, and the external pins of the solder ball structure can be made on the corresponding surface pad, which has good processability. The second encapsulating resin layer is provided with a redistribution layer electrically connected to the metallization structure, and the external pins of the solder ball structure can be welded to the surface pad or the redistribution layer to achieve electrical connection. In this way, based on the redistribution layer, a small pitch layout of the external pins can be achieved, which can be adapted for use in high-density scenarios.

[0022] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, or the third embodiment of the first aspect, or the fourth embodiment of the first aspect, or the fifth embodiment of the first aspect, the embodiment of the present application further provides a tenth embodiment of the first aspect: the metallization structure is a solder ball, and the solder ball is exposed in the second encapsulation resin layer and forms an external pin. This embodiment has good processability.

[0023] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, or the third embodiment of the first aspect, or the fourth embodiment of the first aspect, or the fifth embodiment of the first aspect, or the sixth embodiment of the first aspect, or the seventh embodiment of the first aspect, or the eighth embodiment of the first aspect, or the ninth embodiment of the first aspect, or the tenth embodiment of the first aspect, the embodiment of the present application further provides an eleventh embodiment of the first aspect: the chip packaging structure further includes a protective layer arranged on the outside of the package body, the protective layer covering the surface of the package body away from the side where the external pins are located, and part of the outer peripheral surface of the package body. In this way, further protection can be provided and the reliability of the product can be improved.

[0024] For example, the protective layer may be made of a metal material to shield and isolate the influence of interference signals. For another example, the protective layer may be made of a ceramic material.

[0025] A second aspect of an embodiment of the present application provides an electronic device comprising a motherboard and the aforementioned chip packaging structure, the chip packaging structure being disposed on the motherboard. This substrate-less, low-stress chip packaging structure mitigates the effects of stress and deformation on chip performance and reliability, improving product reliability. Furthermore, the interconnection path from chip pins to external pins is shortened, thereby improving product performance. Overall, this provides technical support for ensuring the operational reliability of electronic equipment.

[0026] Based on the second aspect, the embodiments of the present application further provide a first implementation manner of the second aspect: The chip packaging structure is a MEMS device of an electronic device. Exemplarily, the MEMS device can be a MEMS mechanical sensor, a MEMS electrical sensor, or a MEMS acoustic sensor, or the MEMS device can also be a MEMS micromirror.

[0027] In practical applications, the electronic device can be a vehicle-mounted device, a mobile phone, a tablet computer, a smart wearable device, a medical device, a micro-projector, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a cross-sectional view of a chip packaging structure provided by an embodiment of the present application;

[0029] Figure 2 is Figure 1 a top view of the chip packaging structure shown in

[0030] Figure 3 is Figure 1 a bottom view of the chip packaging structure shown in

[0031] Figure 4 is Figure 1 a schematic diagram of the manufacturing process of the chip packaging structure shown in

[0032] Figure 5 is Figure 1 a schematic diagram of the simulation effect of the chip warping performance formed by the change in the thickness of the second encapsulation resin layer shown in

[0033] Figure 6 is Figure 1 a schematic diagram of the simulation effect of the chip warping performance formed by the change in the material of the second encapsulation resin layer shown in

[0034] Figure 7 is a cross-sectional view of another chip packaging structure provided by an embodiment of the present application;

[0035] Figure 8 is a cross-sectional view of yet another chip packaging structure provided by an embodiment of the present application;

[0036] Figure 9 is a cross-sectional view of another chip packaging structure provided by an embodiment of the present application;

[0037] Figure 10 is a cross-sectional view of yet another chip packaging structure provided by an embodiment of the present application.

[0038] Figure 11 is a cross-sectional view of another chip packaging structure provided by an embodiment of the present application;

[0039] Figure 12A cross-sectional view of another chip packaging structure provided by an embodiment of the present application;

[0040] Figure 13 A cross-sectional view of another chip packaging structure provided by an embodiment of the present application;

[0041] Figure 14 A cross-sectional view of another chip packaging structure provided by an embodiment of the present application;

[0042] Figure 15 A cross-sectional view of another chip packaging structure provided by an embodiment of the present application;

[0043] Figure 16 A cross-sectional view of another chip packaging structure provided by an embodiment of the present application;

[0044] Figure 17 A schematic structural diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0045] The embodiments of the present application provide a substrate-free low-stress chip packaging implementation solution to effectively improve the influence of packaging stress.

[0046] Generally, there are many factors causing packaging stress. An important factor is the physical properties of packaging materials. For example, the stiffness of the material. A harder material may generate greater stress during temperature changes, especially in the case of rapid cooling. Another example is the brittleness of the material. Higher brittleness causes the material to be more prone to cracking during temperature changes. Another important factor is the stress introduced by the packaging process. The related technology uses a packaging substrate as the basic structure of chip packaging, involving but not limited to processes such as bonding, wire bonding, capping, and soldering. When the coefficient of thermal expansion (CTE) between the packaging substrate and the chip and other structures with contact connection relationships is quite different, during the temperature change in the process, different materials may undergo relative displacement based on the difference in the coefficient of thermal expansion, thus generating stress. When the temperature changes during use, stress also exists based on the difference in the coefficient of thermal expansion between materials.

[0047] This kind of stress will affect the performance and reliability of the chip, especially for devices such as microstructures or sensitive sensors. For example, MEMS sensor chips used in accelerometers, gyroscopes, and pressure sensors can measure and detect physical quantities such as acceleration, angular velocity, and pressure. The MEMS sensor contains tiny moving parts inside, and the microstructure is more sensitive to stress. In addition, the tiny structural deformation or performance degradation caused by packaging directly affects the measurement accuracy of the sensor. Therefore, during the packaging process, it is necessary to focus on the influence or damage of packaging stress.

[0048] Based on this, an embodiment of the present application provides a chip packaging structure. The chip packaging structure includes a chip, a first encapsulation resin layer, and a second encapsulation resin layer. Among them, the first encapsulation resin layer is located on the back side of the chip, and the second encapsulation resin layer is located on the front side of the chip. The first encapsulation resin layer and the second encapsulation resin layer are joined to form a package body; the external pins of the chip packaging structure are arranged on the second encapsulation resin layer, and the external pins are electrically connected to the pins on the front side of the chip through a metallization structure. Here, "encapsulation" means that the first encapsulation resin layer and the second encapsulation resin layer are used to seal and form a package body with a definite structural form. For example, but not limited to, the package body is a plate-like structure. Here, the "external pins" can be electrically connected to a single board, so as to realize the connection between the chip and an external circuit; in addition, the chip can also be electrically connected to other external devices through the traces on the single board.

[0049] With such a setting, a substrate-free chip packaging solution is constructed. On the one hand, it can avoid the packaging stress caused by the different thermal expansion coefficients of the chip and the substrate or carrier board due to the temperature change during the packaging process, and the stress that may be generated during use due to temperature change, and avoid the possible structural failures such as cracks in the chip, broken bonding wires or delamination caused by excessive stress, thereby improving the production reliability; and the interconnection path from the chip pins to the external pins is shorter, and the parasitic parameters are smaller, which is beneficial to improving the product performance. On the other hand, based on this substrate-free chip packaging solution, the stress generated due to temperature change can be controlled and adjusted by the thickness or material formula of the first encapsulation resin layer or the second encapsulation resin layer, so as to improve the influence caused by stress deformation; while improving the product reliability, the product size can be further reduced, and the manufacturing cost can be lowered.

[0050] In addition, compared with the mechanical stress introduced between the chip, the substrate and the packaging material due to different material properties in the traditional substrate packaging, this solution uses encapsulation resin to form a package body, reducing the possibility of mechanical stress introduced by material differences. In addition, the substrate-free chip packaging structure is connected to a single board, and the thermal resistance of the heat transfer path between the two is relatively low, which can improve the heat dissipation performance. Therefore, the temperature gradient of the chip in the use state can be reduced, and the stress that may be generated due to temperature change can be further reduced.

[0051] At the same time, the package body formed based on the encapsulation resin material can relieve the mechanical stress from the external environment to a certain extent, effectively reducing the influence of mechanical shock or vibration on the packaging structure; in particular, for MEMS sensors, which are mainly used in application scenarios such as vehicles and consumer electronics products, they may be subjected to greater mechanical vibration and temperature change in the actual scenario. Therefore, the advantages of stress reduction and buffer capacity improvement are more significant.

[0052] To better understand the technical solutions and effects of the present application, without loss of generality, specific embodiments will be described in detail below with reference to the accompanying drawings. Please refer to Figure 1 , Figure 2 and Figure 3 , wherein, Figure 1 is a cross-sectional view of a chip packaging structure provided by an embodiment of the present application, Figure 2 is Figure 1 a top view of the chip packaging structure shown in Figure 3 is Figure 1 a bottom view of the chip packaging structure shown in

[0053] As Figure 1 shown, the chip packaging structure 10 includes a chip 1, and both sides and the outer periphery of the chip 1 are coated with a resin material. The first encapsulation resin layer 21 is located on the back side of the chip 1, and the second encapsulation resin layer 22 is located on the front side of the chip 1, that is, the side where the pins 11 of the chip 1 are located, and the first encapsulation resin layer 21 and the second encapsulation resin layer 22 are joined to form an encapsulation body 2. Combining Figure 2 and Figure 3 shown, the first encapsulation resin layer 21 forms a protection on the back of the chip 1, the second encapsulation resin layer 22 forms a protection on the front of the chip 1, and the two are joined on the outer periphery of the chip 1. In this way, a overall protection is constructed outside the chip 1 using a resin material.

[0054] In a specific implementation, the resin material used to form the first encapsulation resin layer 21 and the second encapsulation resin layer 22 can be selected according to the overall design requirements of the product, such as but not limited to epoxy resin, silica gel, or phenolic resin, etc. In addition, the resin material used to form the first encapsulation resin layer 21 and the second encapsulation resin layer 22 can also be a composite material, such as but not limited to an epoxy resin composite material. Combining epoxy resin with glass fiber, carbon fiber, etc. can further improve the strength and rigidity of the packaging structure and is suitable for application scenarios that require higher mechanical properties.

[0055] In addition, the resin material used to form the first encapsulation resin layer 21 and the second encapsulation resin layer 22 can also be a thermally conductive silica gel with good thermal conductivity to achieve rapid heat dissipation of the chip 1.

[0056] In a possible implementation, the first encapsulation resin layer 21 and the second encapsulation resin layer 22 are made of the same resin material. For example, both the first encapsulation resin layer 21 and the second encapsulation resin layer 22 are made of epoxy resin, and there is good bonding compatibility between them. In this way, seamless bonding can be achieved on the outer periphery of the chip 1, and the bonding reliability is relatively high. In other possible implementation manners, the first encapsulation resin layer 21 and the second encapsulation resin layer 22 are made of different resin materials. For example, the first encapsulation resin layer 21 is made of epoxy resin, and the second encapsulation resin layer 22 is made of thermally conductive silica gel, so as to adjust the stress deformation of both sides of the chip 1 in a strain environment as needed, and avoid affecting the performance and use reliability of the chip 1.

[0057] For another example Figure 1 As shown, the external pin 4 of the chip package structure 10 is located on the second encapsulation resin layer 2, and the external pin 4 is a pad structure; the external pin 4 is electrically connected to the pin 11 on the front of the chip 1 through the metallization structure 3, and the metallization structure 3 is a lead structure. In a specific implementation, the lead (metallization structure 3) can be formed on the pin on the front of the chip 1 first, and then the encapsulation resin layer is made; then a pad (external pin 4) electrically connected to the lead is formed on the surface of the second encapsulation resin layer 2. For example but not limited to, a pad exposed on the second encapsulation resin layer 2 is formed by metal deposition for welding to the corresponding interface on the single board side.

[0058] Next, in combination with Figure 4 , briefly describe Figure 1 the manufacturing process of the chip package structure shown in

[0059] Step S401, a glue layer 4-2 is adhered to the carrier board 4-1.

[0060] Step S402, the chip 1 is mounted on the carrier board 4-1. The chips 1 are arranged at intervals on the carrier board 4-1. In a specific implementation, on the basis of meeting the requirements of subsequent manufacturing processes, the chips 1 can be arranged with a small pitch to improve production efficiency.

[0061] Step S403, the metallization structure 3 is made. On the pins of each chip 1, the metallization structure 3 is respectively formed. In a specific implementation, the metallization structure 3 can be vertically formed based on the WB (Wire bonding) process, or formed by the needle implantation process. The embodiments of the present application do not make limitations.

[0062] Step S404, the second encapsulation resin layer 22 is made. The second encapsulation resin layer 22 is formed on the front of the chip 1. In a specific implementation, it can be formed by coating a resin material, or can be formed by injecting a resin material using a mold, or formed by the growth of a film.

[0063] Step S405: Remove the carrier board and remove the glue.

[0064] Step S406: Fabricate the first encapsulation resin layer 21. Form the first encapsulation resin layer 21 on the back surface of the chip 1. In specific implementation, it can be formed by coating a resin material, or by injection molding the resin material using a mold, or by growing a film.

[0065] Here, the first encapsulation resin layer 21 and the second encapsulation resin layer 22 can be made of the same material or different materials.

[0066] Step S407: Grind. Grind off a layer of the surface of the material of the second encapsulation resin layer 22 to expose the metallization structure 3 outside the second encapsulation resin layer 22.

[0067] Step S408: Fabricate the external pin 4. In specific implementation, the external pin 4 of the pad structure can be made by plating to be welded to the corresponding interface of the external single board to achieve electrical connection.

[0068] In other specific implementations, a sputter process or a laser direct structuring (LDS) is used to form the pad; for example, based on the sputter process, a metal (such as copper) layout is sputtered on the surface of the encapsulation resin layer to form a pad, or a pad is directly formed; for another example, based on the laser direct structuring process, through process steps such as laser etching and copper plating, the circuit wiring and the pad structure pattern are directly written on the surface of the encapsulation resin layer.

[0069] Step S409: Final cutting. Perform the final cutting process according to the product design requirements to obtain the substrate - free low - stress chip package structure 10.

[0070] For different application scenarios, the warping deformation of the chip can be improved by adjusting the thickness of the encapsulation resin layer (the first encapsulation resin layer 21 and the second encapsulation resin layer 22). Taking Figure 1 the described chip package structure 10 as the simulation test object, on the basis of the same structure on the side of the chip 1, adjust the thickness of the second encapsulation resin layer 22 on the front side of the chip 1, and the chip warping performance obtained is as Figure 5 shown. Figure 5 In it, the abscissa shows the thickness of the second encapsulation resin layer 22 (unit: mm), and the ordinate shows the maximum warping size of the chip (unit: μm).

[0071] From Figure 5From the test simulation results, it can be seen that when the thickness of the second encapsulation resin layer 22 varies from 0.13 mm to 0.16 mm, the warpage deformation shows a gradually decreasing trend; when the thickness of the second encapsulation resin layer 22 varies from 0.16 mm to 0.19 mm, the warpage deformation shows a gradually increasing trend. Based on this simulation test condition, when the thickness of the second encapsulation resin layer 22 is 0.16 mm, the maximum warpage deformation of the chip is the smallest. Thus, it can be determined that in this implementation scheme, the generation of stress can be reasonably controlled by adjusting the thickness of the second encapsulation resin layer, enabling the chip to maintain a relatively small warpage deformation and improving the stress and deformation of the chip during the manufacturing process and use. Similarly, the stress can also be reasonably controlled by adjusting the thickness of the first encapsulation resin layer, or by adjusting the thicknesses of the first encapsulation resin layer and the second encapsulation resin layer simultaneously.

[0072] In addition, for different application scenarios, the warpage deformation of the chip can also be improved by adjusting the material formula of the encapsulation resin layer (the first encapsulation resin layer 21 and the second encapsulation resin layer 22). Taking Figure 1 the described chip packaging structure 10 as the simulation test object, on the basis of the same structure on the side of the chip 1, adjust the material ratio of the second encapsulation resin layer 22 on the front side of the chip 1. For example, but not limited to, adjust the filler ratio in the material formula, and the chip warpage performance obtained is as Figure 6 shown. Figure 6 In [figure], the abscissa shows different material formulas (five material formulas), and the ordinate shows the chip warpage size (unit: μm).

[0073] Among them, Figure 6 the five formulas shown in [figure] are determined with a filler change gradient of 4%: the filler of formula 1 is 72%, the filler of formula 2 is 76%, the filler of formula 3 is 80%, the filler of formula 4 is 84%, the filler of formula 5 is 88%, the thermal expansion system of formula 1 → formula 5 decreases, and the modulus of formula 1 → formula 5 increases.

[0074] From Figure 6 the test simulation results, it can be seen that for the material formula corresponding to the position indicated by the mark A, the chip warpage approaches zero. Thus, it can be determined that in this implementation scheme, the stress generated due to temperature changes can be reasonably controlled by adjusting the material formula of the second encapsulation resin layer, ensuring the chip performance and reliability. Similarly, the stress and deformation of the chip during the manufacturing process and use can also be improved by adjusting the material formula of the first encapsulation resin layer, or by adjusting the material formulas of the first encapsulation resin layer and the second encapsulation resin layer simultaneously.

[0075] In addition, taking an inertial measurement unit (IMU) with the same performance parameters encapsulated by a traditional substrate as a comparative example, while improving the product reliability, by applying the substrate-free chip packaging structure provided by this solution, the thickness can be reduced by about 20%, and the board area can be reduced by about 25%, meeting the trend design requirements of product miniaturization.

[0076] In the foregoing embodiments, the metallization structure 3 is a lead or a pin structure. In other specific implementations, the metallization structure may adopt other structural forms, for example, stacked balls or solder balls.

[0077] Please refer to Figure 7 , which is a cross-sectional view of another chip packaging structure provided by an embodiment of the present application. To clearly show the differences and connections between this implementation and the foregoing Figure 1 described embodiments, components or structures with the same function are denoted by the same reference numeral in the figure.

[0078] As Figure 7 shown, the metallization structure 3a of the chip packaging structure 10a is a stacked ball structure. Similarly, stacked balls (metallization structure 3a) can be formed on the pins 11 on the front surface of the chip 1 first, and then the encapsulation resin layer is made; then pads (external pins 4) electrically connected to the stacked balls are formed on the surface of the second encapsulation resin layer 2. Other components and connection relationships may be the same as those in the foregoing embodiments and will not be elaborated here.

[0079] Please refer to Figure 8 , which is a cross-sectional view of yet another chip packaging structure provided by an embodiment of the present application. To clearly show the differences and connections between this implementation and the foregoing embodiments, components or structures with the same function are denoted by the same reference numeral in the figure.

[0080] As Figure 8 shown, the metallization structure 3b of the chip packaging structure 10b is a solder ball structure. Similarly, solder balls (metallization structure 3b) can be formed on the pins 11 on the front surface of the chip 1 first, and then the encapsulation resin layer is made; the pads (external pins 4) exposed outside the second encapsulation resin layer 2 can be integrally formed based on the solder ball forming process. Other components and connection relationships may be the same as those in the foregoing embodiments and will not be elaborated here.

[0081] In a possible implementation, pads electrically connected to the solder balls are independently formed on the surface of the second encapsulation resin layer 2. The specific forming process can be implemented by using the prior art, and the embodiments of the present application do not make any limitations.

[0082] The foregoing Figure 1 , Figure 7 and Figure 8In the described embodiments, the structure form is to fabricate the metallization structure first and then the encapsulation resin layer. In other implementation solutions, the structure form of fabricating the encapsulation resin layer first and then the metallization structure can also be adopted. For example, the metallization structure 3 can also adopt other structure forms, such as, via opening electroplating, Through Molding Via (TMV), silver paste filling holes, etc.

[0083] Please refer to Figure 9 , which is a cross-sectional view of another chip packaging structure provided by an embodiment of the present application. To clearly show the differences and connections between this embodiment and the foregoing embodiments, components or structures with the same functions are denoted by the same reference numerals in the figure.

[0084] As Figure 9 shown, the metallization structure 3c of the chip packaging structure 10c is a via structure formed by the via opening electroplating process. In a specific implementation, the encapsulation resin layer can be fabricated first, and then holes are formed at positions corresponding to the pins 11 of the chip 1 on the second encapsulation resin layer 2, and a conductive material is coated in the holes by electroplating, for example, but not limited to, forming a conductive via (metallization structure 3c) by electroplating copper. Then, pads (external pins 4) electrically connected to the via are fabricated on the surface of the second encapsulation resin layer 2. Other components and connection relationships can be the same as those in the foregoing embodiments. Details are not described herein again.

[0085] Please refer to Figure 10 , which is a cross-sectional view of yet another chip packaging structure provided by an embodiment of the present application. To clearly show the differences and connections between this embodiment and the foregoing embodiments, components or structures with the same functions are denoted by the same reference numerals in the figure.

[0086] As Figure 10 shown, the metallization structure 3d of the chip packaging structure 10d is a columnar structure formed by the silver paste filling hole process. Similarly, the encapsulation resin layer can be fabricated first, and then holes are formed at positions corresponding to the pins 11 of the chip 1 on the second encapsulation resin layer 2, and a conductive column (metallization structure 3d) is formed in the holes by the silver paste filling hole process. Then, pads (external pins 4) electrically connected to the via are fabricated on the surface of the second encapsulation resin layer 2. Other components and connection relationships can be the same as those in the foregoing embodiments. Details are not described herein again.

[0087] In the foregoing embodiments, the external pin 4 is a flat pad structure. In other specific implementations, the external pin can also be a solder ball structure, for example, but not limited to, arranging the solder ball structure in the form of a Land Grid Array (LGA) package to improve the board mounting and assembly processability.

[0088] Please refer to Figure 11, This figure is a cross-sectional view of another chip packaging structure provided by an embodiment of the present application. To clearly show the differences and connections between this implementation and the previous embodiments, components or structures with the same function are denoted by the same reference numeral in the figure.

[0089] As Figure 11 shown, the external pins 4e of the chip packaging structure 10e are in the form of solder balls, and these solder balls can be formed on the surface metal pads 41e of the second encapsulation resin layer 22 by the ball mounting process. Other components and connection relationships may be the same as those in the previous embodiments and will not be elaborated here.

[0090] Please refer to Figure 12 , This figure is a cross-sectional view of yet another chip packaging structure provided by an embodiment of the present application. To clearly show the differences and connections between this implementation and the previous embodiments, components or structures with the same function are denoted by the same reference numeral in the figure.

[0091] As Figure 12 shown, the external pins 4f of the chip packaging structure 10f are in the form of solder balls, and these solder balls can be formed on the redistribution layer (Re-Distribution Layer, RDL) 41f of the second encapsulation resin layer 22 by the ball mounting process. The redistribution layer 41f is formed on the second encapsulation resin layer 2 and is electrically connected to the metallization structure 3; in this way, based on the redistribution layer 41f, a small pitch layout of the external pins 4f can be achieved, which is suitable for high-density scenarios. Other components and connection relationships may be the same as those in the previous embodiments and will not be elaborated here.

[0092] The aforementioned Figure 11 and Figure 12 described chip packaging structures, the external pins 4e of the solder ball structure are all welded to the surface metal of the second encapsulation resin layer 22, having good processability. In other possible implementation manners, the external pins 4e of the solder ball structure can be formed on the second encapsulation resin layer 22 by the ball mounting process and are directly electrically connected to the metallization structure 3 (not shown in the figure).

[0093] In the aforementioned embodiments, each chip packaging structure encapsulates a single chip. In other specific implementations, the chip packaging structure can also encapsulate multiple chips to meet the requirements of different product functions.

[0094] Please refer to Figure 13 , This figure is a cross-sectional view of another chip packaging structure provided by an embodiment of the present application. To clearly show the differences and connections between this implementation and the previous embodiments, components or structures with the same function are denoted by the same reference numeral in the figure.

[0095] As Figure 13As shown, the chip packaging structure 10g includes two chips 1, and the two chips 1 are arranged in a horizontally tiled manner. Here, the horizontal direction is also the extending direction of the chip body shown in the figure. The pins 11 on the front of each chip 1 are electrically connected to the corresponding external pins 4 through a metallization structure 3.

[0096] It can be understood that the structural forms of the metallization structure 3 and the external pin 4 can both be determined according to the overall design requirements of the product. For example, but not limited to, the metallization structure 3 can be a structure such as a lead, a planted pin, a stacked ball, a solder ball, a via hole, or a conductive post, and the external pin 4 can be a pad or a solder ball structure, or can be integrally formed based on the metallization structure 3. The embodiments of the present application do not make limitations.

[0097] In addition, wire bonding is also used to achieve electrical connection between the two chips 1. Specifically, as Figure 13 shown, the two chips 1 are connected by a lead 12g and encapsulated by a second encapsulation resin layer 22. It should be understood that for the electrical interconnection between the two chips 1, it is not limited to a single lead in the figure, and can be specifically determined according to actual functional needs. The embodiments of the present application do not make limitations.

[0098] For the horizontally tiled manner, it can also be arranged as other multiple chips (not shown in the figure) according to needs, rather than being limited to Figure 13 the two shown in the figure. In specific implementation, multiple chips can be in an array layout or a staggered layout. In specific implementation, according to the device function design requirements, some of the multiple chips can be electrically interconnected, or all the chips can be electrically interconnected separately. The embodiments of the present application do not make limitations.

[0099] Please refer to Figure 14 , which is a cross-sectional view of another chip packaging structure provided by the embodiment of the present application. In order to clearly show the differences and connections between this implementation and the foregoing embodiments, components or structures with the same function are denoted by the same reference numeral in the figure.

[0100] As Figure 14 shown, the chip packaging structure 10h includes two chips 1: a first chip 1A and a second chip 1B. The two chips 1 are stacked in the vertical direction. Here, the vertical direction is perpendicular to the extending direction of the chip body shown in the figure, and the chips 1 can be fixed by an adhesive. Among them, the first chip 1A is arranged on the side close to the external pin among the two stacked chips 1, and the pins 11 on the front are electrically connected to the corresponding external pins 4 through a metallization structure 3. The second chip 1B is connected to the first chip 1A through a lead 12h to achieve electrical connection, and the lead 12h is encapsulated by a second encapsulation resin layer 22.

[0101] Of course, in specific implementations, for the electrical interconnection between two chips 1, it is not limited to a single lead shown in the figure, and can be determined specifically according to actual functional requirements. The embodiments of this application do not make any limitations.

[0102] For the vertically stacked manner, it can also be arranged with other multiple chips as needed (not shown in the figure), rather than being limited to Figure 14 the two shown in []. In specific implementations, multiple chips can be arranged in a sequential stacking manner. In the stacking direction, adjacent chips are fixed with adhesive. The embodiments of this application do not make any limitations.

[0103] In addition, for a chip package structure that packages multiple chips, a combination of laying and stacking can also be used for arrangement. Taking two - layer stacking as an example, two chips are arranged in a laying manner in one layer, and one chip is arranged in a laying manner in the other layer. Please refer to Figure 15 This figure is a cross - sectional view of another chip package structure provided by the embodiments of this application. To clearly show the differences and connections between this implementation and the foregoing embodiments, components or structures with the same function are indicated by the same label in the figure.

[0104] As Figure 15 shown, this chip package structure 10i includes three chips 1: the first chip 1A, the second chip 1B, and the third chip 1C. The second chip 1B and the third chip 1C are located in the same stacking layer and are arranged in a laying manner, and the second chip 1B and the third chip 1C are respectively fixed to the first chip 1A with adhesive. Among them, the pins 11 on the front of the first chip 1A are electrically connected to the corresponding external pins 4 through the metallization structure 3. The second chip 1B and the third chip 1C are respectively connected to the first chip 1A through leads 12i, and the leads 12i are encapsulated by the second encapsulation resin layer 22.

[0105] In other specific implementations, multiple chips in the chip package structure can also be stacked into other multiple layers, and in at least one stacking layer, multiple chips are arranged in a laying manner. Among them, the chip arranged closer to the external pin side among the multiple chips is electrically connected to the external pin through the metallization structure, and other chips among the multiple chips can be electrically connected to the chip arranged closer to the external pin side through leads. That is to say, for the arrangement method using a combination of laying and stacking, it is not limited to arranging multiple chips in a laying manner in each stacking layer. In addition, the number of chips laid in each stacking layer can be the same or different. The embodiments of this application do not make any limitations.

[0106] To further improve the reliability of the product, in specific implementations, a protection structure can be provided outside the chip package structure. Please refer to Figure 16, This figure is a cross-sectional view of another chip packaging structure provided by an embodiment of the present application. To clearly show the differences and connections between this implementation and the foregoing embodiments, components or structures with the same functions are denoted by the same reference numerals in the figure.

[0107] As Figure 16 shown, the chip packaging structure 10j includes a protective layer 5j that covers the outer periphery of the package 2 and the outer surface of the package 2 on the side facing away from the external pins 4. In this way, further protection can be provided to improve the reliability of the product.

[0108] In a specific implementation, the protective layer 5j can be made of a metal material to achieve shielding and isolation of interference signals and further improve the reliability of the product. At the same time, based on the setting of the metal protective layer 5j, the self-heat dissipation ability of the chip packaging structure 10j can also be improved. In other specific implementations, the protective layer 5j can also be made of a ceramic material, which is not limited in the embodiments of the present application.

[0109] In other possible implementations, the protective layer can also cover a part of the outer peripheral surface of the package 2 and the outer surface of the package 2 on the side facing away from the external pins 4, rather than being limited to completely covering the outer peripheral surface of the package 2 as shown in the figure, and can also provide an effective protective effect.

[0110] In addition to the foregoing chip packaging structure, this embodiment also provides an electronic device. Please refer to Figure 17 , This figure is a schematic structural diagram of an electronic device provided by an embodiment of the present application.

[0111] As Figure 17 shown, the electronic device 100 includes a housing 20 and a main board 30 disposed inside the housing 20. The main board 30 is provided with the chip packaging structure 10 described in the foregoing embodiments. The chip packaging structure 10 can be a MEMS device of the electronic device 100, for example, but not limited to, a MEMS mechanical sensor, a MEMS electrical sensor, a MEMS acoustic sensor, or it can also be a MEMS micromirror, etc. This is not limited in the embodiments of the present application.

[0112] In a specific implementation, the electronic device can be a vehicle-mounted device, a mobile phone, a tablet computer, a smart wearable device, a medical device, a micro-projector, etc., which is not limited in the embodiments of the present application. It should be understood that the other functional components of the electronic device are not the core inventive points of the present application, and those skilled in the art can implement them according to the prior art, so they will not be elaborated herein.

[0113] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A chip packaging structure, characterized in that, The package comprises a chip, a first encapsulating resin layer and a second encapsulating resin layer, wherein the first encapsulating resin layer is located on the back side of the chip, the second encapsulating resin layer is located on the front side of the chip, and the first encapsulating resin layer and the second encapsulating resin layer are bonded to form a package; The external pins of the chip packaging structure are arranged on the second encapsulation resin layer, and the external pins are electrically connected to the pins located on the front side of the chip through a metallization structure.

2. The chip packaging structure according to claim 1, wherein The first encapsulating resin layer and the second encapsulating resin layer are made of the same material or different materials.

3. The chip packaging structure according to claim 1 or 2, characterized in that At least one of the first encapsulating resin layer and the second encapsulating resin layer is made of epoxy resin, silica gel or phenolic resin.

4. The chip packaging structure according to any one of claims 1 to 3, characterized in that, There are multiple chips, and the multiple chips are arranged in a flat manner.

5. The chip packaging structure according to claim 4, wherein, At least two of the chips are electrically connected via leads.

6. The chip packaging structure according to any one of claims 1 to 3, characterized in that, There are multiple chips, and the multiple chips are arranged in a stacked manner; the multiple chips are electrically connected through leads, and the chip arranged close to the external pin side among the multiple chips is electrically connected to the external pin through the metallization structure.

7. The chip packaging structure according to any one of claims 1 to 3, characterized in that, There are multiple chips, and the multiple chips are arranged into a multi-layer stacking layer in a stacking manner, and at least two chips are arranged in a flat manner in at least one stacking layer; the chip arranged near the external pin side among the multiple chips is electrically connected to the external pin through the metallization structure; the other chips among the multiple chips are electrically connected to the chip arranged near the external pin side through leads.

8. The chip packaging structure according to claim 6 or 7, characterized in that In the stacking direction, two adjacent chips are fixed with adhesive.

9. The chip packaging structure according to any one of claims 1 to 8, characterized in that, The metallization structure is a lead, a implant needle, a stacked ball, a through hole or a conductive column.

10. The chip packaging structure according to any one of claims 1 to 9, characterized in that, The external pins are pads located on the surface of the second encapsulating resin layer.

11. The chip packaging structure according to any one of claims 1 to 9, characterized in that, The external pins are solder balls electrically connected to the metallization structure.

12. The chip packaging structure according to claim 11, wherein, A surface pad or a redistribution layer electrically connected to the metallization structure is provided on the second encapsulating resin layer, and the solder ball is electrically connected to the surface pad or the redistribution layer.

13. The chip packaging structure according to any one of claims 1 to 8, characterized in that, The metallization structure is a solder ball, and the solder ball is exposed from the second encapsulation resin layer and forms the external pin.

14. The chip packaging structure according to any one of claims 1 to 13, characterized in that, The invention also includes a protection layer arranged outside the package body, wherein the protection layer covers the surface of the package body away from the external pins and a part of the outer peripheral surface of the package body.

15. The chip package structure according to claim 14, wherein The protective layer is made of metal material or ceramic material.

16. An electronic device, characterized in that, The invention comprises a mainboard and the chip packaging structure according to any one of claims 1 to 15, wherein the chip packaging structure is arranged on the mainboard.

17. The electronic device according to claim 16, wherein The chip packaging structure is a device of the electronic device formed based on a micro-electromechanical system.

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