Holographic element and preparation method thereof

Abstract

The invention belongs to the technical field of optical elements, and particularly relates to a holographic element and a preparation method thereof. The preparation method of the holographic element comprises the following steps: providing a pretreated silicon-based substrate; forming a mask layer with a first pattern on the upper surface of the pretreated silicon-based substrate by adopting a laser printing technology; and carrying out gray scale etching on the pretreated silicon-based substrate by using ICP-RIE (Inductively Coupled Plasma-Reactive Ion Etching) equipment by utilizing the mask layer to form a silicon-based substrate with a second pattern so as to obtain the holographic element. According to the technical scheme, the preparation method of the holographic element is simple in process and accurate in etching, and the structural precision, the optical performance and the reliability of the holographic element can be improved.

Description

Technical Field

[0001] This application belongs to the technical field of optical elements, and particularly relates to a holographic element and a preparation method thereof. Background Art

[0002] With the continuous development of optical technology, researchers have gradually applied holographic optical technology to the preparation of components. Currently, in the preparation process of holographic elements, the mask transfer combined with gray-scale lithography technology usually uses multiple etching or complex process combinations to achieve stepped structures with different heights. This process has the following disadvantages: 1) Multiple mask alignments and etching are required, and the process is relatively complex, resulting in low production efficiency and high costs; 2) Multiple etching is prone to introducing errors, and the etching ratio is unstable, affecting the consistency of the step height; 3) Due to process parameter changes, the etching rate is unstable, making it difficult to control the structural accuracy; 4) It is impossible to conveniently and accurately control the manufactured optoelectronic devices through the mask height to cope with different working wavelengths. Summary of the Invention

[0003] Embodiments of this application provide a holographic element and a preparation method thereof to solve or alleviate the above-mentioned technical problems. The preparation method of the holographic element in the technical solution of this application has a simple process and accurate etching, and can improve the structural accuracy, optical performance and reliability of the holographic element.

[0004] In a first aspect, embodiments of this application provide a preparation method of a holographic element, including: Providing a pretreated silicon-based substrate; Using laser printing technology to form a mask layer with a first pattern on the upper surface of the pretreated silicon-based substrate; Using the mask layer, using an ICP-RIE device to perform gray-scale etching on the pretreated silicon-based substrate to form a silicon-based substrate with a second pattern, and obtaining a holographic element.

[0005] Optionally, using laser printing technology to form a mask layer with a first pattern on the upper surface of the silicon-based substrate includes: Loading the pretreated silicon-based substrate in a two-photon lithography system; Coating a two-photon photoresist on the pretreated silicon-based substrate; Using a laser to perform photolithography on the two-photon photoresist; Developing the two-photon photoresist after photolithography in a developer to form the mask layer with the first pattern.

[0006] Optionally, when using the laser to perform photolithography on the two-photon photoresist, the shadow line distance is 0.03 - 0.07 μm.

[0007] Optionally, the laser power of the laser is 16 - 20 mW; and / or The scanning speed of the laser is 8000 - 12000 μm / s.

[0008] Optionally, a gray-scale etching is performed on the pre-treated silicon-based substrate using an ICP-RIE device, including: Placing the pre-treated silicon-based substrate with the mask layer in the etching chamber of the ICP-RIE device, introducing an etching gas and an auxiliary etching gas, and etching the pre-treated silicon-based substrate; Wherein, the etching gas is CHF3, and the auxiliary etching gas is O2.

[0009] Optionally, the flow rate of the etching gas is 30 - 50 sccm; and / or The flow rate of the auxiliary etching gas is 5 - 15 sccm.

[0010] Optionally, the flow rate ratio of the etching gas to the auxiliary etching gas is 3 - 5.

[0011] Optionally, the power of the ICP source is 1100 - 1300 W; the radio frequency power is 80 - 120 W; the chamber pressure is 10 - 30 mTorr.

[0012] Optionally, the etching ratio of the material of the mask layer to the material of the pre-treated silicon-based substrate is 2.2 - 2.4.

[0013] Optionally, the height gradient of the mask layer with the first pattern is 0.29 - 0.32 μm, and the height gradient of the silicon-based substrate with the second pattern is 0.13 - 0.14 μm.

[0014] In a second aspect, an embodiment of the present application provides a holographic element, including: prepared by using the preparation method of the holographic element provided in any one of the above embodiments.

[0015] The technical solution of the present application may include the following advantages: In the technical solution of the present application, first, a mask layer with a first pattern is formed by laser printing technology, and then a gray-scale etching is performed using an ICP-RIE device to form a silicon-based substrate with a second pattern. High-precision patterning and etching are achieved through laser printing technology to form a patterned mask layer, reducing etching errors. Gray-scale etching is performed using an ICP-RIE device, and the high-precision transfer of the gray-scale mask can be achieved in a single etching, avoiding errors caused by multiple processes. Moreover, the formed step structure can achieve high-resolution optical imaging and high-efficiency optical modulation, improving the performance of the holographic element. In addition, the preparation of a holographic element with different height step structures can be achieved through one mask and etching process, greatly simplifying the process flow, improving production efficiency, and reducing production costs. Description of the Drawings

[0016] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the several views denote the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0017] Figure 1 is a process structure diagram of a method for preparing a holographic element provided by an embodiment of the present application; Figure 2 is a schematic structural diagram of a holographic element provided by an embodiment of the present application; Figure 3 is a surface topography diagram of a holographic element provided by an embodiment of the present application; Figure 4 is a peak signal-to-noise ratio diagram of the holographic elements of Example 1 and Comparative Example 1; Figure 5 is a topography diagram of the holographic elements of Example 1 and Comparative Example 1.

[0018] Description of reference numerals: 10. Pretreated silicon-based substrate; 11. Silicon-based substrate; 20. Mask layer. Detailed description of the specific implementation

[0019] The embodiments of the present application will be described in detail below. The examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, for clarity, the dimensions of layers, regions, and elements, as well as their relative dimensions, may be exaggerated. Among them, the same or similar reference numerals throughout denote the same or similar elements or elements having the same or similar functions. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present application and should not be construed as limiting the present application. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other.

[0020] As Figures 1 to 3 shown, an embodiment of the present application provides a method for preparing a holographic element, including: S100: Provide a pretreated silicon-based substrate 10; S200: Adopt a laser printing technique to form a mask layer 20 with a first pattern on the upper surface of the pretreated silicon-based substrate; S300: Use the mask layer and an ICP-RIE device to perform gray-scale etching on the pretreated silicon-based substrate to form a silicon-based substrate 11 with a second pattern, thereby obtaining a holographic element.

[0021] In the technical solution of this application, first, a mask layer with a first pattern is formed by laser printing technology, and then an ICP-RIE device is used for grayscale etching to form a silicon-based substrate with a second pattern. High-precision patterning and etching are achieved through laser printing technology to form a patterned mask layer, reducing etching errors. Grayscale etching is performed using an ICP-RIE device, and high-precision transfer of the grayscale mask can be achieved in a single etching, avoiding errors caused by multiple processes. Moreover, the formed stepped structure can achieve high-resolution optical imaging and high-efficiency optical modulation, improving the performance of holographic elements. In addition, holographic elements with stepped structures of different heights can be prepared through a single mask and etching process, greatly simplifying the process flow, improving production efficiency, and reducing production costs.

[0022] The silicon-based substrate can be a quartz silicon substrate or a silicon wafer. The size of the silicon-based substrate can be 1 - 1.5 inches, and the thickness is 0.5 - 1 mm.

[0023] In some embodiments, step S200, using laser printing technology to form a mask layer with a first pattern on the upper surface of the silicon-based substrate, includes: S210: Load the pretreated silicon-based substrate in a two-photon lithography system; S220: Coat a two-photon photoresist on the pretreated silicon-based substrate; S230: Use a laser to perform photolithography on the two-photon photoresist; S240: Develop the two-photon photoresist that has undergone photolithography in a developer to form a mask layer with a first pattern.

[0024] Load the pretreated silicon-based substrate in a two-photon lithography system and coat a two-photon photoresist on it. Use a laser to perform photolithography on the photoresist, causing a chemical reaction in a specific area of the photoresist to form an exposed area corresponding to the desired pattern. Then, put the photoresist that has undergone photolithography into a developer for development to remove the unexposed or under-exposed parts, thereby forming a mask layer with a first pattern. Two-photon lithography technology can achieve high-resolution patterning, which helps to manufacture holographic elements with complex structures and high precision, improving the performance of holographic elements.

[0025] In the two-photon lithography system, the laser can be a femtosecond laser, the wavelength of the laser is 780 nm, and the frequency is 80 MHz. Photolithography can be performed using a femtosecond laser in the galvanometer scanning mode. The laser is focused on the photoresist through an objective lens. Due to the two-photon absorption effect, the photoresist polymerizes at the focus to form nanostructures.

[0026] In the two-photon lithography system, an immersion objective lens with a high numerical aperture (Plan-Apochromat 63× / 1.40 oil phase difference) can be used to improve the resolution.

[0027] In an alternative embodiment, before performing photolithography on a two-photon photoresist using a laser, a pattern can be designed through a diffraction phase plate. The resolution of the diffraction phase plate can be 100×100 pixels, and the pixel area can be 1 μm 2 .

[0028] In an alternative embodiment, the two-photon photoresist (IP-Dip) includes an organic polymer. Specifically, the two-photon photoresist includes a resin, a solvent, and a photoinitiator.

[0029] In some embodiments, when performing photolithography on a two-photon photoresist using a laser, the shadow line distance is 0.03 - 0.07 μm.

[0030] The shadow line distance refers to the distance between the shadow region formed on the photoresist and the actual exposure region during the photolithography process due to factors such as diffraction and scattering of the laser beam. The shadow line distance plays a crucial role in ensuring the accuracy and consistency of the pattern. Controlling the shadow line distance between 0.03 - 0.07 μm helps to achieve more refined nano-patterns, reduce pattern errors and defects, and improve the optical performance and stability of the holographic element.

[0031] In some embodiments, the laser power of the laser is 16 - 20 mW. In some embodiments, the scanning speed of the laser is 8000 - 12000 μm / s.

[0032] During the laser photolithography process, controlling the laser power and / or scanning speed of the laser within a reasonable range helps to improve the stability and reliability of photolithography, ensure the quality of the mask layer pattern, and thus improve the preparation quality of the holographic element.

[0033] In an alternative embodiment, before performing photolithography on a two-photon photoresist using a laser, photolithography parameters need to be set. In a specific embodiment, the shadow line distance can be set to 0.03 - 0.07 μm (e.g., 0.03 μm, 0.05 μm, 0.07 μm), the laser power can be set to 16 - 20 mW (e.g., 16 mW, 17 mW, 18 mW, 19 mW, 20 mW), and the scanning speed can be set to 8000 - 12000 μm / s (e.g., 8000 μm / s, 9000 μm / s, 10000 μm / s, 11000 μm / s, 12000 μm / s).

[0034] The lithographed silicon-based substrate is developed in a developer to remove the unexposed photoresist. Among them, the developer is propylene glycol monomethyl ether acetate (PGMEA), and the development time is 20 - 30 minutes (for example, 20 minutes, 25 minutes, 30 minutes). After the development is completed, a cleaning solution can be used for cleaning to remove the developer remaining on the surface of the mask layer. The cleaning time is 5 - 10 minutes, and then drying is performed to obtain a mask layer with the first pattern.

[0035] In some embodiments, in step S300, the pre-treated silicon-based substrate is subjected to gray-scale etching using an ICP-RIE device, including: S310: Place the pre-treated silicon-based substrate with the mask layer in the etching chamber of the ICP-RIE device, introduce an etching gas and an auxiliary etching gas, and etch the pre-treated silicon-based substrate. Among them, the etching gas is CHF3, and the auxiliary etching gas is O2.

[0036] In the embodiments of the present application, CHF3 is used as the etching gas, and O2 is used as the auxiliary etching gas. Among them, the fluorine content of CHF3 is relatively low, so that the etching rate of the first pattern is slower. The lower etching rate makes the required first pattern thinner when reaching the same substrate etching depth, which helps to reduce the lateral etching of the first pattern and achieve a more refined pattern transfer. Since physical ion bombardment may cause cross-linking of the first pattern, making it more difficult to remove, and thus introducing etching instability, while O2 can alleviate the cross-linking problem of the first pattern caused by physical ion bombardment during the etching process, making the etching process more stable.

[0037] In some embodiments, the flow rate of the etching gas is 30 - 50 sccm (for example, 30 sccm, 35 sccm, 40 sccm, 45 sccm, 50 sccm). In some embodiments, the flow rate of the auxiliary etching gas is 5 - 15 sccm (for example, 5 sccm, 8 sccm, 10 sccm, 12 sccm, 15 sccm). In some embodiments, the flow rate ratio of the etching gas to the auxiliary etching gas is 3 - 5 (for example, 3, 3.5, 4, 4.5, 5).

[0038] In some embodiments, the power of the ICP (Inductively Coupled Plasma) source is 500 - 1400 W. Preferably, the power of the ICP source is 1100 - 1300 W (for example, 1100 W, 1150 W, 1200 W, 1250 W, 1300 W); the radio frequency power is 80 - 120 W (for example, 80 W, 90 W, 100 W, 110 W, 120 W); the chamber pressure is 10 - 30 mTorr (for example, 15 mTorr, 20 mTorr, 25 mTorr, 30 mTorr).

[0039] During the gray-scale etching process, by reasonably controlling at least one of the etching gas flow rate, the auxiliary etching gas, and the equipment operation parameters (for example, the power of the ICP source, the RF power, and the chamber pressure), the stability and uniformity of the plasma can be improved, the etching accuracy and quality can be enhanced, the structural accuracy and consistency of the holographic element can be ensured, and the optical performance and reliability of the holographic element can be improved.

[0040] In some embodiments, the etching ratio of the material of the mask layer to the material of the pre-treated silicon-based substrate is 2.2 - 2.4 (for example, 2.2, 2.25, 2.3, 2.35, 2.4).

[0041] By adjusting the materials of the mask layer and the pre-treated silicon-based substrate, the etching ratio of the material of the mask layer to the material of the pre-treated silicon-based substrate is controlled to be 2.2 - 2.4, the etching ratio and the etching rate are stably controlled, and the height consistency of the stepped structure on the silicon-based substrate after pattern transfer is ensured.

[0042] In some embodiments, as Figure 1 shown, the height gradient of the mask layer 20 with the first pattern is 0.29 - 0.32 μm. In some embodiments, as Figure 2 shown, the height gradient of the silicon-based substrate with the second pattern is 0.13 - 0.14 μm.

[0043] In the embodiments of the present application, the mask height is accurately designed according to the etching ratio, so that the height gradient of the mask layer with the first pattern is 0.29 - 0.32 μm (for example, 0.290 μm, 0.295 μm, 0.300 μm, 0.306 μm, 0.310 μm, 0.315 μm, 0.320 μm), and the height gradient of the silicon-based substrate with the second pattern is 0.13 - 0.14 μm (for example, 0.130 μm, 0.132 μm, 0.133 μm, 0.135 μm, 0.138 μm, 0.140 μm). Holographic element structures corresponding to different working wavelengths can be manufactured. For example, it can correspond to a 1 / 4π phase modulation at a working wavelength of 532 nm, improving the versatility and adaptability of the holographic element and meeting the requirements of different application fields.

[0044] In an alternative embodiment, the method for preparing a holographic element further includes: before placing the pre-treated silicon-based substrate with the mask layer in the etching chamber of the ICP-RIE equipment, first place a 6-inch silicon wafer in the etching chamber and clean it with oxygen plasma for 30 minutes. The 6-inch silicon wafer can remove the impurity gas in the etching chamber through adsorption, clean the etching chamber, and ensure process stability. Then perform an environmental treatment step for 15 minutes to further confirm the chamber cleanliness, using the same parameters as those used in the actual etching process.

[0045] In an alternative embodiment, the method for preparing a holographic element further includes: S320: After forming the silicon-based substrate with the second pattern, perform ultrasonic cleaning of the silicon-based substrate with ethanol for 30 minutes to remove the impurities adhered during the etching process. During the etching process, the mask layer will be completely removed, so there is no need to remove the mask layer.

[0046] In an alternative embodiment, during the gray-scale etching process, a thermally conductive adhesive can be used to bond the pre-treated silicon-based substrate to the silicon wafer to prevent overheating.

[0047] An embodiment of the present application provides a holographic element, which is prepared by using the method for preparing a holographic element provided in any one of the above embodiments.

[0048] The following specific embodiments further illustrate the present application in detail, but should not be construed as a limitation to the present application. Without departing from the spirit and essence of the present application, any modification or replacement of the methods, steps or conditions of the present application belongs to the scope of the present application.

[0049] Embodiment 1 As Figure 1 and Figure 2 shown, the method for preparing a holographic element in Embodiment 1 includes: S100a: Provide a pre-treated silicon-based substrate 10 (quartz silicon substrate); S210a: Load the pre-treated silicon-based substrate 10 in a two-photon lithography system; S220a: Coat a two-photon photoresist on the pre-treated silicon-based substrate; wherein, the two-photon photoresist includes an organic polymer; S230a: In the galvanometer scanning mode, use a laser to perform lithography on the two-photon photoresist; wherein, the laser can be a femtosecond laser, the wavelength of the laser is 780 nm, the frequency is 80 MHz, the shadow line distance is 0.05 μm, the laser power is 18 mW, and the scanning speed is 10000 μm / s; S240a: Develop the lithographed two-photon photoresist in a developer to form a mask layer 20 with a first pattern on the upper surface of the pre-treated silicon-based substrate; wherein, the developer is propylene glycol monomethyl ether acetate (PGMEA), the development time is 25 minutes, and the height gradient of the mask layer is 0.306 μm; S310a: Place the preprocessed silicon-based substrate 10 with the mask layer 20 in the etching chamber of the ICP-RIE equipment, introduce the etching gas and the auxiliary etching gas, perform gray-scale etching on the preprocessed silicon-based substrate to form a silicon-based substrate 11 with a second pattern, and obtain a holographic element; wherein, the etching gas is CHF3, the auxiliary etching gas is O2, the flow rate of the etching gas is 40 sccm, the flow rate of the auxiliary etching gas is 10 sccm, the power of the ICP source is 1200 W, the radio frequency power is 100 W, the chamber pressure is 120 mTorr, the etching ratio of the material of the mask layer to the material of the preprocessed silicon-based substrate is 2.3, and the height gradient of the silicon-based substrate is 0.13 - 0.14 μm.

[0050] To more clearly illustrate the technical effects of the embodiments of the present application, the holographic element of Comparative Example 1 is also pointed out in the present application.

[0051] Comparative Example 1 The base material of the holographic element of Comparative Example 1 is photoresist, and the two-photon lithography process is used to cure the photoresist to form the base.

[0052] Next, the holographic elements of Example 1 and Comparative Example 1 of the present application are subjected to performance testing, and the peak signal-to-noise ratio (PSNR) with the designed hologram under different high-temperature annealings is tested. The test results are shown in Table 1, and the peak signal-to-noise ratio diagrams of the holographic elements of Example 1 and Comparative Example 1 are as Figure 4 shown. Figure 5 are the morphology diagrams of the holographic elements of Example 1 and Comparative Example 1. Figure 4 and Figure 5 The photoresist in represents Example 1, and SiO2 represents Example 1.

[0053] Table 1

[0054] From the data in Table 1 and Figure 4 it can be seen that compared with Comparative Example 1, the holographic element of Example 1 of the present application has better stability. Although the initial display quality and peak signal-to-noise ratio (PSNR) of the hologram of Comparative Example 1 (photoresist) are higher. However, after high-temperature annealing, the performance of the hologram of Comparative Example 1 deteriorates significantly. For annealing at 400 °C, the holographic image of Comparative Example 1 almost disappears, while the hologram of Example 1 (quartz silicon) remains stable. Moreover, according to the image of Figure 5 , it can be seen that compared with Comparative Example 1, the morphology diagram of the holographic element of Example 1 of the present application is clearer, indicating that the etching accuracy of the holographic element of Example 1 of the present application is higher.

[0055] In summary, in the technical solution of this application, first, a mask layer with a first pattern is formed through a laser printing technique, and then an ICP-RIE device is used for grayscale etching to form a silicon-based substrate with a second pattern. High-precision patterning and etching are achieved through the laser printing technique to form a patterned mask layer, reducing etching errors. Grayscale etching is performed using an ICP-RIE device, and high-precision transfer of the grayscale mask can be achieved in a single etching, avoiding errors caused by multiple processes. Moreover, the formed step structure can achieve high-resolution optical imaging and high-efficiency optical modulation, improving the performance of the holographic element. In addition, the preparation of a holographic element with different-height step structures can be achieved through a single mask and etching process, greatly simplifying the process flow, improving production efficiency, and reducing production costs.

[0056] It should be noted that the terms "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to this application. The orientation terms "inner" and "outer" refer to the inside and outside relative to the contour of each component itself. For example, if the device in the drawing is inverted, the device described as "above other devices or structures" or "on top of other devices or structures" will be positioned as "below other devices or structures" or "beneath other devices or structures" afterwards. Thus, the exemplary term "above..." can include both the orientations of "above..." and "below...". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and corresponding interpretations are made for the relative spatial descriptions used here.

[0057] It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, so that the embodiments of this application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0058] It should also be noted that the "one embodiment", "another embodiment", "embodiment", etc. mentioned in this application refer to the specific features, structures or characteristics described in connection with that embodiment being included in at least one embodiment generally described in this application. The same expression appearing in multiple places in the specification does not necessarily refer to the same embodiment. Further, when describing a specific feature, structure or characteristic in connection with any one embodiment, it is intended that the implementation of such feature, structure or characteristic in combination with other embodiments also falls within the scope of this application.

[0059] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0060] It should also be noted that the above are only the preferred embodiments of this application, and do not limit the scope of patent protection of this application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of this application, or directly or indirectly applied in other related technical fields, shall be similarly included in the scope of patent protection of this application.

Claims

1. A method for preparing a holographic element, characterized in that, Including: Providing a pre-treated silicon-based substrate; Adopting a laser printing technique to form a mask layer with a first pattern on the upper surface of the pre-treated silicon-based substrate; Utilizing the mask layer, using an ICP-RIE device to perform gray-scale etching on the pre-treated silicon-based substrate to form a silicon-based substrate with a second pattern, thereby obtaining a holographic element.

2. The method for preparing a holographic element according to claim 1, wherein Adopting a laser printing technique to form a mask layer with a first pattern on the upper surface of the silicon-based substrate, including: Loading the pre-treated silicon-based substrate in a two-photon lithography system; Coating a two-photon photoresist on the pre-treated silicon-based substrate; Using a laser to perform photolithography on the two-photon photoresist; Developing the photolithographed two-photon photoresist in a developer to form the mask layer with the first pattern.

3. The method for preparing a holographic element according to claim 2, wherein When using the laser to perform photolithography on the two-photon photoresist, the shadow line distance is 0.03 - 0.07 μm.

4. The method for preparing a holographic element according to claim 2, wherein, The laser power of the laser is 16 - 20 mW; and / or The scanning speed of the laser is 8000 - 12000 μm / s.

5. The method for preparing a holographic element according to claim 1, wherein Using an ICP-RIE device to perform gray-scale etching on the pre-treated silicon-based substrate, including: Placing the pre-treated silicon-based substrate with the mask layer in the etching chamber of the ICP-RIE device, introducing an etching gas and an auxiliary etching gas to etch the pre-treated silicon-based substrate; Wherein, the etching gas is CHF3, and the auxiliary etching gas is O2.

6. The method for preparing a holographic element according to claim 5, wherein, The flow rate of the etching gas is 30 - 50 sccm; and / or The flow rate of the auxiliary etching gas is 5 - 15 sccm.

7. The method for preparing a holographic element according to claim 5, characterized in that, The flow rate ratio of the etching gas to the auxiliary etching gas is 3 - 5.

8. The method for preparing a holographic element according to claim 5, wherein The power of the ICP source is 1100 - 1300 W; the radio frequency power is 80 - 120 W; the chamber pressure is 10 - 30 mTorr.

9. The method for preparing a holographic element according to claim 5, characterized in that, The etching ratio of the material of the mask layer to the material of the pre-treated silicon-based substrate is 2.2 - 2.

4.

10. The method for preparing a holographic element according to any one of claims 1 to 9, characterized in that, The height gradient of the mask layer with the first pattern is 0.29 - 0.32 μm, and the height gradient of the silicon-based substrate with the second pattern is 0.13 - 0.14 μm.

11. A holographic element, characterized in that, Prepared and formed by using the method for preparing a holographic element according to any one of claims 1 to 10.

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