Control circuit for SOC and control method thereof

Abstract

The invention discloses a control circuit for an SOC and a control method thereof. The control circuit comprises an SOC and power supply module, a watchdog control module, a watchdog module, an RTC domain delay reset module and an AP domain enable and delay reset module. Wherein the SOC and power supply module is used for outputting an RTC domain power supply signal, an AP domain power supply signal and a digital signal according to an external power supply signal; the reset module is used for resetting an RTC domain or an AP domain according to an RTC domain reset signal or an AP domain reset signal; the watchdog control module is used for outputting a watchdog circuit enable signal; the watchdog module is used for outputting a power supply under-voltage protection reset signal and a watchdog timer overtime reset signal in an enabled state; the RTC domain delay reset module is used for outputting an RTC domain reset signal; the AP domain enabling and delay reset module is used for enabling an AP domain and generating an AP domain reset signal. According to the invention, the possibility that the SOC is awakened can be improved, and the operation reliability of the SOC circuit is enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of SOC chip control, and particularly to a control circuit and a control method for an SOC. Background Art

[0002] SOC chips have a very high integration level, can include almost all digital circuits and analog circuits, support complex calculations and processing, and at the same time can also provide high performance and reliability, supporting various applications such as high-speed networks, multimedia, artificial intelligence, and graphics processing.

[0003] In the prior art, the system basic control circuit of an SOC mainly uses an RC delay circuit as the reset circuit of the SOC, and uses the watchdog inside the SOC as the deadlock reset circuit. Under special working conditions, such as when the voltage is slightly interrupted during the connection of the automotive battery, the SOC freezes due to the inability to be normally reset and cannot recover by itself. In the case of program anomalies, such as when the program enters an infinite loop before the watchdog is turned on and after it is turned off, it will cause the SOC to freeze and cannot recover by itself. Under harsh working conditions, such as extreme power supply voltage or strong electromagnetic interference, the SOC freezes because it cannot be powered on according to the required timing and cannot recover by itself. Under harsh working conditions, such as extreme ambient temperature or strong electromagnetic interference, the SOC cannot be awakened, resulting in freezing and cannot recover by itself. Under harsh working conditions, such as extreme ambient temperature or strong electromagnetic interference, the SOC cannot be normally put into sleep or is frequently awakened, resulting in excessive dark current in the vehicle and battery discharge. The current system basic control circuit is only suitable for simple applications of the SOC, resulting in the incomplete performance of the SOC and unstable system performance, greatly increasing the failure rate of the vehicle. Summary of the Invention

[0004] The main purpose of the present invention is to provide a control circuit and a control method for an SOC to improve the reliability of the SOC during operation.

[0005] The technical solution adopted by the present invention is: a control circuit for an SOC, including an SOC and a power supply module, a watchdog control module, a watchdog module, an RTC domain delay reset module, and an AP domain enable and delay reset module;

[0006] Wherein: the SOC and the power supply module include an AP domain and an RTC domain, which are respectively connected to the watchdog control module, the watchdog module, the RTC domain delay reset module, and the AP domain enable and delay reset module, and are put into sleep or awakened by receiving an external wake-up signal during normal operation; used to output an RTC domain power signal, an AP domain power signal, and a digital signal according to an external power signal; used to reset the RTC domain or the AP domain according to an RTC domain reset signal or an AP domain reset signal;

[0007] The watchdog control module is connected to the watchdog module and is used to output a watchdog circuit enable signal according to an external wake-up signal, an RTC domain power signal, and an AP domain power signal;

[0008] The watchdog module is connected to the RTC domain delay reset module and is enabled or disabled by the watchdog circuit enable signal and the AP domain power signal. It is used to output a power supply undervoltage protection reset signal and a watchdog timer timeout reset signal according to the RTC domain power signal, the AP domain power signal, and a digital signal in the enabled state;

[0009] The RTC domain delay reset module is used to output an RTC domain reset signal according to the RTC domain power signal, the output power supply undervoltage protection reset signal, and the watchdog timer timeout reset signal;

[0010] The AP domain enable and delay reset module is used to enable the AP domain and generate an AP domain reset signal.

[0011] According to the above technical solution, the RTC domain power signal includes a first RTC domain power signal, a second RTC domain power signal, and a third RTC domain power signal; the AP domain power signal includes a first AP domain power signal, a second AP domain power signal, a third AP domain power signal, and a fourth AP domain power signal.

[0012] According to the above technical solution, the SOC and the power module are further used to receive an AP domain power enable signal, and the AP domain power enable signal includes a first AP domain power enable signal and a fourth AP domain power enable signal from the AP domain of this module, and a second AP domain power enable signal and a third AP domain power enable signal from the AP domain enable and delay reset module;

[0013] The SOC and the power module are further used to output an AP domain power status indication signal, and the AP domain power status indication signal includes an AP domain power on signal, a first AP domain power status indication signal, and a second AP domain power status indication signal;

[0014] The SOC and the power module are further used to output an RTC domain power status indication signal.

[0015] According to the above technical solution, the AP domain power on signal is connected to the fourth AP domain power enable signal; the second AP domain power status indication signal is connected to the first AP domain power enable signal.

[0016] According to the above technical solution, when the external power signal input changes from 0V to a preset value:

[0017] After delaying a preset time, the SOC and the power module make the RTC domain power status indication signal output a high level;

[0018] Delay for a preset time, and the SOC and the power supply module make the AP domain power-on signal and the fourth AP domain power signal both output high levels;

[0019] Delay for a preset time, and the SOC and the power supply module make the second AP domain power status indication signal and the first AP domain power signal both output high levels;

[0020] Delay for a preset time, and the SOC and the power supply module make the first AP domain power status indication signal, the second AP domain power signal, and the third AP domain power signal all output high levels, and the second AP domain power enable signal and the third AP domain power enable signal both output high levels;

[0021] Delay for a preset time, and the SOC and the power supply module make a square wave with a digital signal output frequency within a preset range, a duty cycle within a preset range, a low level within a preset range, and a high level within a preset range.

[0022] According to the above technical solution, the watchdog control module includes a first chip, a first triode, a second triode, and a third triode;

[0023] Among them, the first chip is a dual D trigger integrated circuit with set and reset functions. The first triode is used for signal inversion and isolation. The second triode is used for signal inversion and switch control. The third triode is used for signal inversion and amplification;

[0024] The pin D, pin CLR, and pin PRE of the first chip are connected to the second RTC domain power signal, and the pin Q is connected to the watchdog circuit enable signal; the collector of the first triode is connected to the second RTC domain power signal, and the base is connected to the external wake-up signal; the collector of the second triode is connected to the second RTC domain power signal, and the base is connected to the third AP domain power signal; the collector and the base of the third triode are connected to the second RTC domain power signal.

[0025] According to the above technical solution, when the second RTC domain power signal outputs a high level and the external wake-up signal changes from a high level to a low level: the watchdog control module makes the watchdog enable signal output a high level;

[0026] When the second RTC domain power signal outputs a high level and the external wake-up signal changes from a low level to a high level: if the third AP domain power signal changes from a high level to a low level, the watchdog control module makes the watchdog enable signal output a low level; if the third AP domain power signal changes from a low level to a high level, the watchdog control module makes the watchdog enable signal output a high level;

[0027] When the second RTC domain power signal and the third AP domain power signal output low levels, and the external wake-up signal is high or low: the watchdog control module causes the watchdog enable signal to output a low level.

[0028] According to the above technical solution, the watchdog module includes a second chip, a first diode, a second diode, and a first switch; the second chip is used to monitor the circuit voltage and enable and detect the watchdog module; the first diode and the second diode are used to isolate signals; the first switch is used to forcibly open and close the watchdog module;

[0029] Among them, the pin VCC of the second chip is connected to the second RTC domain power signal, the pin SET is connected to the watchdog enable signal and the third AP domain power signal, the pin WDI is connected to the digital signal, the pin nWDO is connected to the power supply undervoltage protection reset output signal, and the pin nRESET is connected to the watchdog timer timeout reset signal; the anode of the first diode is connected to the third AP domain power signal; the anode of the second diode is connected to the watchdog enable signal; the first switch is connected to the watchdog enable signal.

[0030] According to the above technical solution, when the third AP domain power signal outputs a high level or the watchdog enable signal outputs a high level, the watchdog module is enabled; when the third AP domain power signal outputs a high level and the watchdog enable signal outputs a low level, the watchdog module is disabled.

[0031] According to the above technical solution, when the watchdog module is enabled, if the voltage value of the second RTC domain power signal is less than the preset low voltage threshold, the watchdog module causes the power supply undervoltage protection reset signal to output a low level, and if the voltage value of the second RTC domain power signal is greater than the preset low voltage threshold by a certain multiple, the watchdog module causes the power supply undervoltage protection reset signal to output a high level;

[0032] When the watchdog module is disabled, the watchdog module causes the watchdog timer timeout reset signal to output a high level; when the watchdog module is enabled, if the pulse period of the digital signal is within the preset range and less than the preset watchdog timeout reset period, the watchdog module causes the watchdog timer timeout reset signal to output a high level, and if the pulse period of the digital signal is within the preset range and greater than the preset watchdog timeout reset period, the watchdog module causes the watchdog timer timeout reset signal to output a low level.

[0033] According to the above technical solution, the RTC domain delay reset module includes a fourth triode, a fifth triode, and a third diode; among them, the fourth triode is used to conduct and cut off signals, the fifth triode is used to invert and switch control signals, and the third diode is used to step down the base of the fourth triode and isolate signals;

[0034] The collector of the fourth triode is connected to the second RTC domain power supply signal, the base is connected to the output ends of the output power supply undervoltage protection reset signal, the watchdog timer timeout reset signal, and the external reset signal; the collector of the fifth triode is connected to the second RTC domain power supply signal, the RTC domain power status indication signal, and the RTC domain reset signal.

[0035] According to the above technical solution, when the RTC domain power status indication signal outputs a high level or a low level, the RTC domain delay reset module causes the RTC domain reset signal to output a high level or a low level correspondingly;

[0036] When the second RTC domain power supply signal outputs a preset value: if any one of the power supply undervoltage protection reset signal, the watchdog timer timeout reset signal, or the external reset signal outputs a low level, the RTC domain delay reset module causes the RTC domain reset signal to output a low level; if the power supply undervoltage protection reset signal, the watchdog timer timeout reset signal, and the external reset signal all output high levels, the RTC domain delay reset module causes the RTC domain reset signal to output a high level; if the power supply undervoltage protection reset signal, the watchdog timer timeout reset signal, or the external reset signal jumps from any one outputting a low level to all outputting high levels, the RTC domain delay reset module causes the RTC domain reset signal to initially output a low level and jump to a high level after a preset delay; if the power supply undervoltage protection reset signal, the watchdog timer timeout reset signal, or the external reset signal jumps from all outputting high levels to any one outputting a low level, the RTC domain delay reset module causes the RTC domain reset signal to jump from a high level to a low level.

[0037] According to the above technical solution, the AP domain enable and delay reset module includes a discharge delay circuit for the fourth AP domain power supply signal, a discharge delay circuit for the first AP domain power status indication signal, a voltage rise delay circuit and a voltage drop delay circuit for the AP domain reset signal;

[0038] The AP domain enable and delay reset module is also connected to the second AP domain power enable signal, the third AP domain power enable signal, and the second AP domain power supply signal;

[0039] When the fourth AP domain power supply signal and the second AP domain power supply signal output high levels:

[0040] If the first AP domain power status indication signal outputs a high level, the second AP domain power enable signal, the third AP domain power enable signal, and the AP domain reset signal output high levels;

[0041] If the first AP domain power status indication signal outputs a low level, the second AP domain power enable signal, the third AP domain power enable signal, and the AP domain reset signal output low levels;

[0042] If the first AP domain power status indication signal jumps from low level to high level, the second AP domain power enable signal and the third AP domain power enable signal jump from low level to high level, and the AP domain reset signal rises from low level to high level after a preset time;

[0043] If the first AP domain power status indication signal jumps from high level to low level, the second AP domain power enable signal and the third AP domain power enable signal jump from high level to low level, and the AP domain reset signal rises from high level to low level after a preset time.

[0044] According to the above technical solution, the AP domain enable and delay reset module includes a sixth triode and a seventh triode; the sixth triode and the seventh triode are used for inverting and amplifying signals;

[0045] The emitter of the sixth triode is connected to the second AP domain power signal, and the collector is connected to the AP domain reset signal; the collector of the seventh triode is connected to the second AP domain power signal, and the base is connected to the fourth AP domain power signal, the second AP domain power enable signal, the third AP domain power enable signal, and the first AP domain power status indication signal.

[0046] According to the above technical solution, the AP domain enable and delay reset module includes a third chip; the third chip is a voltage monitoring integrated circuit with programmable delay;

[0047] The pin VDD and the pin SENSE of the third chip are connected to the second AP domain power signal, and the pin VDD and the pin nRESET of the third chip are connected to the AP domain reset signal.

[0048] Another aspect of the present invention provides a control method for a control circuit for an SOC based on the above, including:

[0049] The SOC and the power supply module output an RTC domain power signal and an AP domain power signal according to the received external power signal;

[0050] The RTC domain delay reset module outputs an RTC domain reset signal according to the received RTC domain power signal, and the RTC domain of the SOC and the power supply module performs a reset for a preset time according to the RTC domain reset signal; the AP domain enable and delay reset module enables the AP domain of the SOC and the power supply module according to the received AP domain power signal and outputs an AP domain reset signal, and the AP domain of the SOC and the power supply module performs a reset for a preset time according to the AP domain reset signal;

[0051] After the reset of the RTC domain and the AP domain is completed, the SOC and the power supply module work normally, output digital signals to the watchdog module, and sleep or be woken up according to the received external wake-up signal; the watchdog module is enabled or disabled by the watchdog control module and the AP domain power signal. In the enabled state, the watchdog module outputs a power supply undervoltage protection reset signal and a watchdog timer timeout reset signal according to the RTC domain power signal, the AP domain power signal, and the digital signal;

[0052] The RTC domain delay reset module outputs an RTC domain reset signal according to the received RTC domain power signal, the output power supply undervoltage protection reset signal, and the watchdog timer timeout reset signal, and the SOC and the power supply module reset the RTC domain according to the received RTC domain reset signal.

[0053] The beneficial effects of the present invention are as follows: The present invention provides a control circuit and a control method for an SOC, wherein the control circuit includes an SOC and a power supply module, a watchdog control module, a watchdog module, an RTC domain delay reset module, and an AP domain enable and delay reset module. In the present invention, the external wake-up signal is used both to wake up the SOC and to realize the reset and restart of the SOC, improving the reliability of the SOC being woken up. The watchdog module in the present invention is enabled jointly by the watchdog circuit enable signal and the AP domain power signal, improving the reliability of the watchdog circuit being turned on. Based on the above effects, the control circuit of the present invention has high reliability and is applicable to controllers with high functional safety requirements.

[0054] Furthermore, the control circuit of the present invention is applicable to various SOCs and various MCUs, having strong versatility;

[0055] Furthermore, the control circuit of the present invention is implemented by discrete devices and general logic devices, having a low implementation cost;

[0056] Furthermore, the control circuit of the present invention uses resistors and capacitors to implement delay setting, with flexible timing setting;

[0057] Furthermore, the control circuit of the present invention uses low-power chips and pulse wake-up methods, having low dark current;

[0058] Furthermore, the control circuit of the present invention can be expanded or trimmed, and can also be recombined to adapt to different control requirements, having a wide application range.

[0059] Of course, it is not necessary for any product implementing the present invention to achieve all the above-mentioned advantages simultaneously. Description of the Drawings

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0061] Figure 1 It is a schematic structural diagram of the control circuit for SOC in the embodiment of the present invention;

[0062] Figure 2 It is a circuit connection diagram of the control circuit for SOC in the embodiment of the present invention;

[0063] Figure 3 It is a schematic connection diagram between SOC and the power supply module in the control circuit for SOC in the embodiment of the present invention;

[0064] Figure 4 It is a schematic connection diagram of the watchdog module in the control circuit for SOC in the embodiment of the present invention;

[0065] Figure 5 It is a schematic connection diagram of the RTC domain delay reset module in the control circuit for SOC in the embodiment of the present invention;

[0066] Figure 6 It is a schematic connection diagram of the AP domain enable and delay reset module in the control circuit for SOC in the embodiment of the present invention;

[0067] Figure 7 It is a schematic connection diagram of another AP domain enable and delay reset module in the control circuit for SOC in the embodiment of the present invention;

[0068] Figure 8 It is a flowchart of the control method of the control circuit for SOC in the embodiment of the present invention.

[0069] Reference numerals: 1, SOC and the power supply module; 2, watchdog control module; 3, watchdog module; 4, RTC domain delay reset module; 5, AP domain enable and delay reset module. Detailed implementation manners

[0070] In order to make the objectives, technical solutions and advantages of the present invention clearer, the following further elaborates on the present invention in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0071] It should be noted that the illustrations provided in the embodiments of the present invention only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0072] In the present invention, it should also be noted that when terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings. This is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation to the present application. In addition, when terms such as "first" and "second" appear, they are only used for descriptive and distinguishing purposes, and cannot be understood as indicating or implying relative importance.

[0073] For the convenience of understanding the present application document, the following keywords need to be explained as follows:

[0074] SOC: It is an integrated circuit with a dedicated target, including a complete system and all the content of the embedded software. At the same time, it is also a technology used to realize the entire process from determining the system function, to software / hardware partitioning, and to completing the design. The SOC chip has a very high integration level, can include almost all digital circuits and analog circuits, can support complex calculations and processing, is suitable for running operating systems, and can also provide high performance and reliability, supporting various applications such as high-speed networks, multimedia, artificial intelligence, and graphics processing.

[0075] MCU: The MCU chip usually only includes basic controllers, such as counters, timers, GPIO, serial communication interfaces, etc., and also has some analog circuit interfaces. They usually do not require an external processor or controller, and generally do not support operating systems, but can run bare-metal programs and can quickly respond to real-time tasks and control systems.

[0076] Watchdog circuit: Essentially a timer circuit, mainly used to monitor and manage the operating state of the CPU, and perform a reset operation on the CPU in an abnormal state to enable it to work again.

[0077] SOC_RTC domain: The real-time clock module of the SOC, which is isolated from other modules, and its power supply is also isolated.

[0078] SOC_AP domain: The general application module and security control module of the SOC.

[0079] Embodiment 1

[0080] This embodiment provides a control circuit for an SOC. The connection manner between each module is as Figure 1 shown, and the circuit connection manner is as Figure 2 shown, including an SOC, a power supply module, a watchdog control module, a watchdog module, an RTC domain delay reset module, and an AP domain enable and delay reset module.

[0081] Among them, the SOC and the power supply module include an SOC_RTC domain and an SOC_AP domain, and are connected to the output end of an external power supply signal V_BAT, the output end of an external wake-up signal SOC_SYS_WAKE0, the input end of an RTC domain 3.3V power supply signal V_RTC_3V3, the input end of an RTC domain 0.8V power supply signal V_RTC_0V8, the input end of an RTC domain 1.8V power supply signal V_RTC_1V8, the input end of an AP domain 5.0V power supply signal V_APSAFE_5V0, the input end of an AP domain 0.8V power supply signal V_APSAFE_0V8, the input end of an AP domain 1.8V power supply signal V_APSAFE_1V8, the input end of an AP domain 3.3V power supply signal V_APSAFE_3V3, the output end of an AP domain reset signal SOC_APSAFE_RESET, the output end of an RTC domain reset signal SOC_RTC_RESET, the input end of an RTC domain 3.3V power supply status indication signal V_RTC_3V3_PG, the input end of a digital signal SOC_GPIO1, the input end of an AP domain power-on signal V_APSAFE_PowerOn, the input end of an AP domain 5.0V power supply status indication signal V_APSAFE_5V0_PG, the output end of an AP domain 1.8V power supply enable signal V_APSAFE_1V8_EN, and the output end of an AP domain 3.3V power supply enable signal V_APSAFE_3V3_EN.

[0082] The SOC_AP domain of this module outputs an AP domain 5.0V power supply enable signal V_APSAFE_5V0_EN and an AP domain 0.8V power supply enable signal V_APSAFE_0V8_EN.

[0083] The AP domain power-on signal V_APSAFE_PowerOn is directly connected to the AP domain 5.0V power supply enable signal V_APSAFE_5V0_EN, and the AP domain 5.0V power supply status indication signal V_APSAFE_5V0_PG is directly connected to the AP domain 0.8V power supply enable signal V_APSAFE_0V8_EN.

[0084] The negative electrode of the power supply in the SOC and the power supply module is grounded.

[0085] The control method of the SOC and the power supply module includes:

[0086] When the external power supply signal V_BAT changes from 0V to (8V - 16V): The RTC domain 3.3V power supply signal V_RTC_3V3 outputs a power supply voltage of (3.2V - 3.4V), the RTC domain 0.8V power supply signal V_RTC_0V8 outputs a power supply voltage of (0.78V - 0.86V), and the RTC domain 1.8V power supply signal V_RTC_1V8 outputs a power supply voltage of (1.7V - 1.9V).

[0087] The AP domain 5.0V power supply signal V_APSAFE_5V0, the AP domain 0.8V power supply signal V_APSAFE_0V8, the AP domain 1.8V power supply signal V_APSAFE_1V8, and the AP domain 3.3V power supply signal V_APSAFE_3V3 all output 0V.

[0088] The AP domain power-on signal V_APSAFE_PowerOn, the AP domain 5.0V power status indication signal V_APSAFE_5V0_PG, the AP domain 0.8V power status indication signal V_APSAFE_0V8_PG, the AP domain reset signal SOC_APSAFE_RESET, and the RTC domain 3.3V power status indication signal.

[0089] V_RTC_3V3_PG, the RTC domain reset signal SOC_RTC_RESET, and the digital signal SOC_GPIO1 all output a low level of (0V - 0.3V).

[0090] The AP domain 5.0V power enable signal V_APSAFE_5V0_EN, the AP domain 0.8V power enable signal V_APSAFE_0V8_EN, the AP domain 1.8V power enable signal V_APSAFE_1V8_EN, and the AP domain 3.3V power enable signal V_APSAFE_3V3_EN all input a low level of (0V - 0.3V).

[0091] When the external wake-up signal SOC_SYS_WAKE0 inputs a high level of (1.7V - 1.9V) or a low level of (0V - 0.3V):

[0092] After a delay of the set time, the RTC domain 3.3V power status indication signal V_RTC_3V3_PG outputs a high level of (1.7V - 1.9V), and the RTC domain reset signal SOC_RTC_RESET outputs a high level of (1.7V - 1.9V).

[0093] After the time of the delay setting, the high level of the AP domain power-on signal V_APSAFE_PowerOn is output (1.7V - 1.9V), that is, the high level of the input of the 5.0V power enable signal V_APSAFE_5V0_EN for the AP domain (1.7V - 1.9V), and the power supply voltage of the 5.0V power signal V_APSAFE_5V0 for the AP domain is output (4.8V - 5.2V).

[0094] After the time of the delay setting, the high level of the 5.0V power enable signal V_APSAFE_5V0_PG for the AP domain is output (4.8V - 5.2V), that is, the high level of the input of the 0.8V power enable signal V_APSAFE_0V8_EN for the AP domain (4.8V - 5.2V), and the power supply voltage of the 0.8V power signal V_APSAFE_0V8 for the AP domain is output (0.78V - 0.86V).

[0095] After the time of the delay setting, the high level of the 0.8V power status indication signal V_APSAFE_0V8_PG for the AP domain is output (4.8V - 5.2V), the high levels of the inputs of the 1.8V power enable signal V_APSAFE_1V8_EN and the 3.3V power enable signal V_APSAFE_3V3_EN for the AP domain (4.8V - 5.2V), the power supply voltage of the 1.8V power signal V_APSAFE_1V8 for the AP domain is output (1.7V - 1.9V), and the power supply voltage of the 3.3V power signal V_APSAFE_3V3 for the AP domain is output (3.2V - 3.4V).

[0096] After the time of the delay setting, the high level of the AP domain reset signal SOC_APSAFE_RESET is output (1.7V - 1.9V), and the digital signal SOC_GPIO1 outputs a square wave with a frequency of (200 ± 50) Hz, a duty cycle of (50 ± 20)%, a low level of (0V - 0.3V), and a high level of (3.2V - 3.4V).

[0097] If the SOC meets the sleep condition and the external wake-up signal SOC_SYS_WAKE0 is at a high level of (1.7V - 1.9V), the SOC enters the sleep state.

[0098] The power supply voltage of the 3.3V power signal V_RTC_3V3 for the RTC domain is output (3.2V - 3.4V), the power supply voltage of the 0.8V power signal V_RTC_0V8 for the RTC domain is output (0.78V - 0.86V), and the power supply voltage of the 1.8V power signal V_RTC_1V8 for the RTC domain is output (1.7V - 1.9V).

[0099] The 5.0V power supply signal V_APSAFE_5V0, 0.8V power supply signal V_APSAFE_0V8, 1.8V power supply signal V_APSAFE_1V8, and 3.3V power supply signal V_APSAFE_3V3 in the AP domain all output 0V.

[0100] The AP domain power-on signal V_APSAFE_PowerOn, 5.0V power supply status indication signal V_APSAFE_5V0_PG, 0.8V power supply status indication signal V_APSAFE_0V8_PG, AP domain reset signal SOC_APSAFE_RESET, RTC domain 3.3V power supply status indication signal V_RTC_3V3_PG, RTC domain reset signal SOC_RTC_RESET, and digital signal SOC_GPIO1 all output a low level of (0V - 0.3V).

[0101] The 5.0V power supply enable signal V_APSAFE_5V0_EN, 0.8V power supply enable signal V_APSAFE_0V8_EN, 1.8V power supply enable signal V_APSAFE_1V8_EN, and 3.3V power supply enable signal V_APSAFE_3V3_EN in the AP domain all input a low level of (0V - 0.3V).

[0102] When the external wake-up signal SOC_SYS_WAKE0 changes from a high level of (1.7V - 1.9V) to a low level of (0V - 0.3V), the SOC is woken up.

[0103] The AP domain power-on signal V_APSAFE_PowerOn outputs a high level of (1.7V - 1.9V), that is, the 5.0V power supply enable signal V_APSAFE_5V0_EN in the AP domain inputs a high level of (1.7V - 1.9V), and the 5.0V power supply signal V_APSAFE_5V0 in the AP domain outputs a power supply voltage of (4.8V - 5.2V).

[0104] After delaying for the set time, the 5.0V power supply status indication signal V_APSAFE_5V0_PG in the AP domain outputs a high level of (4.8V - 5.2V), that is, the 0.8V power supply enable signal V_APSAFE_0V8_EN in the AP domain inputs a high level of (4.8V - 5.2V), and the 0.8V power supply signal V_APSAFE_0V8 in the AP domain outputs a power supply voltage of (0.78V - 0.86V).

[0105] After the time of the delay setting, the high level of the power status indication signal V_APSAFE_0V8_PG of the AP domain 0.8V power supply outputs (4.8V - 5.2V), the high level of the power enable signal V_APSAFE_1V8_EN of the AP domain 1.8V power supply and the high level of the power enable signal V_APSAFE_3V3_EN of the AP domain 3.3V power supply input (4.8V - 5.2V), the power supply voltage of the power supply signal V_APSAFE_1V8 of the AP domain 1.8V outputs (1.7V - 1.9V), and the power supply voltage of the power supply signal V_APSAFE_3V3 of the AP domain 3.3V outputs (3.2V - 3.4V).

[0106] After the time of the delay setting, the high level of the reset signal SOC_APSAFE_RESET of the AP domain outputs (1.7V - 1.9V), and the digital signal SOC_GPIO1 outputs a square wave with a frequency of (200 ± 50) Hz, a duty cycle of (50 ± 20)%, a low level of (0V - 0.3V), and a high level of (3.2V - 3.4V).

[0107] When the external power supply signal V_BAT is (0V - 1V): all power supplies and signals are 0V;

[0108] When the external power supply signal V_BAT is not (0V - 1V) and not (8V - 16V), all output signals are uncertain;

[0109] When the absolute value of the external power supply signal V_BAT exceeds 28V, it may cause damage to the circuit.

[0110] The watchdog control module is used to receive the external wake-up signal, the AP domain power supply signal and the RTC domain power supply signal, and output a watchdog circuit enable signal.

[0111] The connection mode of the watchdog control module is as Figure 3 shown, including chip U1, resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, capacitors C1, C2, C3, C4, C5, C6, and transistors Q1, Q2, Q3.

[0112] The chip U1 selects RS1G74XVS8, which is a dual D flip-flop integrated circuit with set and reset functions; C1 is selected as 1uF, which is the energy storage capacitor for the power supply of U1; C2 is selected as 10nF, which is the filter capacitor for the power supply of U1; R1 is selected as 10kΩ, which is the pull-up resistor for the set of U1; R3 is selected as 20kΩ, which is the load resistor for the inverting output of U1; Q1 selects the triode BC807-25HE3-TP, which is a low-power PNP triode for inverting and isolation functions; C4 is selected as 1nF, which is the filter capacitor between the base and emitter of Q1; R5 is selected as 39kΩ, which is the parallel resistor between the base and emitter of Q1; R7 is selected as 20kΩ, which is the current-limiting resistor for the base of Q1; the resistance ratio of R5 and R7 determines the input signal for Q1 to conduct and cut off, that is, the voltage threshold of the external wake-up signal SOC_SYS_WAKE0; R10 is selected as 20kΩ, which is the load resistor for the collector of Q1; Q2 selects the triode BC817-25HE3-TP, which is a low-power NPN triode for inverting and switch control functions; C8 is selected as 1nF, which is the filter capacitor between the base and emitter of Q2; R9 is selected as 10kΩ, which is the parallel resistor between the base and emitter of Q2; R6 is selected as 10kΩ, which is the current-limiting resistor for the base of Q2; the resistance ratio of R9 and R6 determines the input signal for Q2 to conduct and cut off, that is, the voltage threshold of the 3.3V power supply signal V_APSAFE_3V3 in the AP domain; R4 is selected as 10kΩ, which is the load resistor for the collector of Q2; Q3 selects the triode BC817-25HE3-TP, which is a low-power NPN triode for inverting and amplifying functions; R8 is selected as 20kΩ, which is the parallel resistor between the base and emitter of Q3; C6 is selected as 10nF, which is the filter capacitor between the base and emitter of Q3; C3 is selected as 1uF, which is the input capacitor for the AC signal of the base of Q3.

[0113] Among them, the pin CLK of the chip U1 is connected to the ground after connecting the resistor R10, the pin CLK of the chip U1 is connected to the collector of the triode Q1, the base of the triode Q1 is connected to the resistor R7, the other end of the resistor R7 is connected to the output end of the external wake-up signal SOC_SYS_WAKE0, a resistor R5 is connected between the base and the emitter of the triode Q1, the capacitor C4 is connected in parallel across the resistor R5, and the emitter of the triode Q1 is connected to the output end of the 1.8V power supply signal V_RTC_1V8 in the RTC domain.

[0114] The pin D of the chip U1 is connected to the output end of the 1.8V power supply signal V_RTC_1V8 in the RTC domain.

[0115] The pin of the chip U1 is connected to the ground after connecting the resistor R3.

[0116] The pin GND of the chip U1 is grounded.

[0117] The pin Q of the chip U1 is connected to the input end of the watchdog circuit enable signal SET_WD.

[0118] Pins of chip U1 After connecting resistor R2, it is connected to the output terminal of the 1.8V power supply signal V_RTC_1V8 of the RTC domain. The pins of chip U1 Is connected to the collector of transistor Q3. The base of transistor Q3 is connected to capacitor C3. The other end of capacitor C3 is connected to the collector of transistor Q2. A capacitor C6 is connected between the base and emitter of transistor Q3. Resistor R8 is connected in parallel across capacitor C6. The emitter of transistor Q3 is grounded. The emitter of transistor Q2 is grounded. The collector of transistor Q2 is connected to resistor R4. The other end of resistor R4 is connected to the output terminal of the 3.3V power supply signal V_APSAFE_3V3 of the AP domain. A capacitor C5 is connected in parallel between the emitter and base of transistor Q2. Resistor R9 is connected in parallel across capacitor C5. The base of transistor Q2 is connected to resistor R6. The other end of resistor R6 is connected to the output terminal of the 3.3V power supply signal V_APSAFE_3V3 of the AP domain.

[0119] Pins of chip U1 After connecting resistor R1, it is connected to the output terminal of the 1.8V power supply signal V_RTC_1V8 of the RTC domain.

[0120] The VCC pin of chip U1 is grounded after connecting capacitors C1 and C2 in parallel. The VCC pin of chip U1 is connected to the output terminal of the 1.8V power supply signal V_RTC_1V8 of the RTC domain.

[0121] When the 1.8V power supply signal V_RTC_1V8 of the RTC domain is (1.7V - 1.9V):

[0122] If the external wake-up signal SOC_SYS_WAKE0 changes from a high level of (1.7V - 1.9V) to a low level of (0V - 0.3V), the watchdog circuit enable signal SET_WD outputs a high level of (1.7V - 1.9V), and the watchdog circuit is enabled.

[0123] When the external wake-up signal SOC_SYS_WAKE0 changes from a low level of (0V - 0.3V) to a high level of (1.7V - 1.9V), the watchdog circuit enable signal SET_WD maintains its original output state. If the 3.3V power supply signal V_APSAFE_3V3 of the AP domain changes from (3.2V - 3.4V) to (0V - 0.3V), the watchdog circuit enable signal SET_WD outputs a low level of (0V - 0.3V), and the watchdog circuit is disabled. If the 3.3V power supply signal V_APSAFE_3V3 of the AP domain changes from (0V - 0.3V) to (3.2V - 3.4V), the watchdog circuit enable signal SET_WD maintains its original output state.

[0124] When the RTC domain 1.8V power supply signal V_RTC_1V8 is (0V - 0.3V):

[0125] The watchdog circuit enable signal SET_WD outputs a low level of (0V - 0.3V), and the AP domain 3.3V power supply signal V_APSAFE_3V3 inputs (0V - 0.3V).

[0126] When the RTC domain 1.8V power supply signal V_RTC_1V8 is not (0V - 0.3V) and not (1.7V - 1.9V): All output signals are uncertain.

[0127] When the absolute value of the RTC domain 1.8V power supply signal V_RTC_1V8 exceeds 2.1V: It may cause circuit damage.

[0128] The connection method of the watchdog module is as Figure 4 shown, including chip U2, diode D1, diode D2, capacitor C7, capacitor C8, capacitor C9, capacitor C10, capacitor C11, resistor R11, resistor R12, resistor R13, resistor R14, resistor R15, switch S1.

[0129] U2 selects the chip SGM820A - 1.6QTGS8G / TR, which is an integrated circuit with functions of detecting voltage, enabling the watchdog circuit, and detecting the watchdog circuit; C7 takes 1uF and is the energy storage capacitor for the power supply of U1; C8 takes 10nF and is the filtering capacitor for the power supply of U1; D1 selects the diode BAV21W; D2 selects the diode BAV21W, and D2 is the diode for isolating the input signal; R12 takes 20kΩ, R13 takes 1kΩ, and both R12 and R13 are input current - limiting resistors; R11 takes 20kΩ and is the input load resistor; C9 takes 4.7nF and is the input filtering capacitor; The resistance ratios of R12 to R11 and R13 to R11 determine the corresponding input signals for turning on and off the watchdog circuit, that is, the voltage thresholds of the AP domain 3.3V power supply signal V_APSAFE_3V3 and the watchdog circuit enable signal SET_WD; S1 is the forced - off switch of the watchdog circuit; R14 takes 10kΩ and is the input current - limiting resistor; R15 takes 15kΩ and is the input load resistor; C10 takes 1nF and is the input filtering capacitor; The resistance ratio of R14 to R15 determines the feeding - dog input signal of the watchdog circuit, that is, the voltage threshold of the digital signal SOC_GPIO1; C11 takes 220nF, and the capacitance value of C11 determines the timeout reset period of the watchdog circuit timer.

[0130] Among them, the pin VCC of chip U2 is connected to the parallel - connected capacitors C7 and C8 and then grounded, and the pin VCC of chip U2 is connected to the output terminal of the RTC domain 1.8V power supply signal V_RTC_1V8.

[0131] The pin CWD of chip U2 is grounded after being connected to capacitor C11.

[0132] The pin nMR of chip U2 is left floating.

[0133] The pins GND and EP of chip U2 are grounded.

[0134] The pin SET of chip U2 is grounded after being connected to the parallel combination of resistor R11 and capacitor C9. The pin SET of chip U2 is connected to the negative electrode of diode D2 after being connected to resistor R13. The positive electrode of diode D2 is connected to the output end of the watchdog circuit enable signal SET_WD. The pin SET of chip U2 is connected to the negative electrode of diode D1 after being connected to resistor R12. The positive electrode of diode D1 is connected to the output end of the 3.3V power supply signal V_APSAFE_3V3 in the AP domain. The pin SET of chip U2 is grounded after being connected to switch S1.

[0135] The pin WDI of chip U2 is grounded after being connected to the series combination of capacitor C10 and resistor R15. The pin WDI of chip U2 is connected to the output end of the digital signal SOC_GPIO1 after being connected to resistor R14.

[0136] The pin nWDO of chip U2 is connected to the input end of the power supply undervoltage protection reset output signal SOC_RTC_RST1.

[0137] The pin nRESET of chip U2 is connected to the input end of the watchdog timer timeout reset signal SOC_RTC_RST2.

[0138] When the RTC domain 1.8V power supply signal V_RTC_1V8 is within the range of (1.7V - 1.9V): If the AP domain 3.3V power supply signal V_APSAFE_3V3 is within the range of (3.2V - 3.4V) or the watchdog circuit enable signal SET_WD is within the range of (1.7V - 1.9V), the watchdog circuit is enabled. If the AP domain 3.3V power supply signal V_APSAFE_3V3 is within the range of (0V - 0.3V) and the watchdog circuit enable signal SET_WD is within the range of (0V - 0.3V), the watchdog circuit is disabled. In the enabled state of the watchdog circuit, if the falling edge of the digital signal SOC_GPIO1 appears on time within the period of the watchdog circuit timer, the watchdog timer timeout reset signal SOC_RTC_RST2 continuously outputs a high level of (1.7V - 1.9V). Otherwise, the watchdog timer timeout reset signal SOC_RTC_RST2 outputs a low level of (0V - 0.3V) at the overflow moment of the timer. The duration of the low level can be set and then jumps to a high level of (1.7V - 1.9V) after the elapsed duration of the low level. If the digital signal SOC_GPIO1 never outputs a falling edge, the watchdog timer timeout reset signal SOC_RTC_RST2 outputs continuous low pulses with the timer overflow period as the cycle until the digital signal SOC_GPIO1 resumes outputting a falling edge on time, and the watchdog timer timeout reset signal SOC_RTC_RST2 also resumes continuous output of the high level. In the disabled state of the watchdog circuit enable, the watchdog timer timeout reset signal SOC_RTC_RST2 continuously outputs a high level of (1.7V - 1.9V).

[0139] When the RTC domain 1.8V power supply signal V_RTC_1V8 is within the range of (1.60V - 1.69V), the watchdog timer timeout reset signal SOC_RTC_RST2 continuously outputs a high level of (1.7V - 1.9V), and the output power supply undervoltage protection reset signal SOC_RTC_RST1 continuously outputs a low level of (0V - 0.3V).

[0140] When the RTC domain 1.8V power supply signal V_RTC_1V8 rises to within the range of (1.70V - 1.90V), the low level output by the output power supply undervoltage protection reset signal SOC_RTC_RST1 jumps to a high level of (1.7V - 1.9V) after the set time;

[0141] When the RTC domain 1.8V power supply signal V_RTC_1V8 is neither within the range of (0V - 0.3V) nor within the range of (1.7V - 1.9V), all output signals are uncertain;

[0142] When the absolute value of the RTC domain 1.8V power supply signal V_RTC_1V8 exceeds 2.1V, it may cause circuit damage.

[0143] The connection method of the RTC domain delay reset module is as follows Figure 5 shown, including transistor Q4, transistor Q5, diode D3, resistor R16, resistor R17, resistor R18, resistor R19, resistor R20, resistor R21, resistor R22, resistor R23 and capacitor C12.

[0144] Q4 selects the transistor C807-25HE3-TP, which is a low-power PNP transistor for inverting and switch control; R19 takes 20 kΩ, which is the parallel resistor between the base and emitter of Q4; R21 takes 4.7 kΩ; R16 takes 1 kΩ, R17 takes 1 kΩ, and R16 and R17 are the base current-limiting resistors of Q4; D3 selects the diode BAV21W, which is a diode for base voltage reduction and input signal isolation; the resistance ratios of R19 to (R21+R16) and R19 to (R21+R17) determine the corresponding input signals for Q4 to conduct and cut off, that is, the voltage thresholds of the output power supply undervoltage protection reset signal SOC_RTC_RST1 and the watchdog timer timeout reset signal SOC_RTC_RST2; the resistance ratio of R19 to R21 and the conduction voltage value of D3 determine the input signal for Q4 to conduct and cut off, that is, the voltage threshold of the external reset signal SOC_RTC_RST3; Q5 selects the transistor BC817-25HE3-TP, which is a low-power NPN transistor for inverting and switch control; R20 takes 10 kΩ, which is the parallel resistor between the base and emitter of Q5; R23 takes 10 kΩ, which is the base current-limiting resistor of Q5; the resistance ratio of R20 and R23 determines the voltage threshold of the input signal for Q5 to conduct and cut off; R18 takes 10 kΩ, which is the collector load resistor of Q5, C12 takes 100 nF, which is the output delay and filter capacitor, and R22 is the reserved output series resistor.

[0145] Among them, a resistor R19 is connected between the base and emitter of the transistor Q4, the base of the transistor Q4 is connected to the resistor R21, the resistor R21 is respectively connected to the resistor R16, the resistor R17 and the diode D3, the resistor R16 is connected to the output end of the power supply undervoltage protection reset signal SOC_RTC_RST1, the resistor R17 is connected to the output end of the watchdog timer timeout reset input signal SOC_RTC_RST2, the negative electrode of the diode D3 is connected to the output end of the external reset signal SOC_RTC_RST3, the emitter of the transistor Q4 is connected to the output end of the RTC domain 1.8V power supply signal V_RTC_1V8, and the collector of the transistor Q4 is connected to the resistor R23 and then connected to the base of the transistor Q5.

[0146] A resistor R20 is connected between the emitter and the base of the triode Q5. The emitter of the triode Q5 is grounded. The collector of the triode Q5 is connected to the output terminal of the 1.8V power supply signal of the RTC domain after connecting the resistor R18. The collector of the triode Q5 is connected to the input terminal of the RTC domain reset signal SOC_RTC_RESET after connecting the resistor R22. The collector of the triode Q5 is connected to the 3.3V power supply status indication signal V_RTC_3V3_PG of the RTC domain. The base of the triode Q5 is grounded after connecting the resistor R20. A capacitor C12 is connected between the collector and the emitter of the triode Q5.

[0147] When the 3.3V power supply status indication signal V_RTC_3V3_PG of the RTC domain is (1.7V - 1.9V), the RTC domain reset signal SOC_RTC_RESET is (1.7V - 1.9V).

[0148] When the 3.3V power supply status indication signal V_RTC_3V3_PG of the RTC domain is (0V - 0.3V), the RTC domain reset signal SOC_RTC_RESET is (0V - 0.3V). When the 1.8V power supply signal V_RTC_1V8 of the RTC domain is (1.7V - 1.9V), if the power supply undervoltage protection reset signal SOC_RTC_RST1 or the watchdog timer timeout reset signal SOC_RTC_RST2 or the external reset signal SOC_RTC_RST3 is a low level of (0V - 0.3V), the RTC domain reset signal SOC_RTC_RESET is a low level of (0V - 0.3V). If the power supply undervoltage protection reset signal SOC_RTC_RST1, the watchdog timer timeout reset signal SOC_RTC_RST2, and the external reset signal SOC_RTC_RST3 are all high levels of (1.7V - 1.9V), the RTC domain reset signal SOC_RTC_RESET is a high level of (1.7V - 1.9V). If the power supply undervoltage protection reset signal SOC_RTC_RST1 or the watchdog timer timeout reset signal SOC_RTC_RST2 or the external reset signal SOC_RTC_RST3 jumps from a low level of (0V - 0.3V) to a high level of (1.7V - 1.9V) where the power supply undervoltage protection reset signal SOC_RTC_RST1, the watchdog timer timeout reset signal SOC_RTC_RST2, and the external reset signal SOC_RTC_RST3 are all high levels of (1.7V - 1.9V), the RTC domain reset signal SOC_RTC_RESET is initially a low level of (0V - 0.3V).

[0149] After the time of the delay setting, the RTC domain reset signal SOC_RTC_RESET jumps to a high level of (1.7V - 1.9V). If the output power supply undervoltage protection reset signal SOC_RTC_RST1, the watchdog timer timeout reset signal SOC_RTC_RST2, and the external reset signal SOC_RTC_RST3 jump from a high level of (1.7V - 1.9V) to a low level of (0V - 0.3V) for the output power supply undervoltage protection reset signal SOC_RTC_RST1 or the watchdog timer timeout reset signal SOC_RTC_RST2 or the external reset signal SOC_RTC_RST3, the RTC domain reset signal SOC_RTC_RESET immediately jumps from a high level of (1.7V - 1.9V) to a low level of (0V - 0.3V); when the RTC domain 1.8V power supply signal V_RTC_1V8 is not (1.7V - 1.9V), all output signals are indeterminate.

[0150] The connection mode of the AP domain enabling and delay reset module is as Figure 6 shown, and includes a triode Q6, a triode Q7, a diode D4, a capacitor C13, a capacitor C14, a resistor R24, a resistor R25, a resistor R26, a resistor R27, a resistor R28, a resistor R29, a resistor R30, a resistor R31, a resistor R32, a resistor R33, a resistor R34.

[0151] Transistor BC817-25HE3-TP is selected as a low-power NPN transistor for inverting and amplifying functions; R32 is taken as 30 kΩ, which is a parallel resistor between the base and emitter of Q7; R30 is taken as 30 kΩ, which is the base current-limiting resistor of Q7; the resistance ratio of R32 and R30 determines the voltage threshold of the AP domain reset signal VIN_APSAFE_RESET for Q7 to turn on and off; C13 is taken as 10 nF, which is the input signal delay and filter capacitor; R29 is taken as 1 kΩ, R25 is taken as 30 kΩ, and R29 and R25 are input signal delay resistors; R28 is taken as 100 Ω, which is the input isolation resistor; R33 is taken as 100 Ω, which is the output isolation resistor; R34 is taken as 100 Ω, which is the output isolation resistor; C13 and (R25 + R29) form a charging delay circuit for the AP domain 5.0 V power supply signal V_APSAFE_5V0; C13 and (R28 + R29) form a discharging delay circuit for the AP domain 0.8 V power supply enable signal V_APSAFE_0V8_PG; Transistor BC807-25HE3-TP is selected as a low-power PNP transistor for inverting and amplifying functions; R26 is taken as 10 kΩ, which is the base current-limiting resistor of Q6; R27 is taken as 10 kΩ, which is the base current-limiting resistor of Q7; the resistance ratio of R26 and R27 determines the voltage threshold of the AP domain 1.8 V power supply signal V_APSAFE_1V8 for Q6 to turn on and off; R24 is taken as 510 Ω, which is the collector load resistor of Q6 and the discharging resistor of C14; R31 is taken as 200 kΩ, which is the charging resistor of C14; Diode SMD110PL-TP is selected as the Schottky diode for the discharging circuit of C14; C14 is taken as 47 nF, which is the delay charge and discharge capacitor for the AP domain reset signal SOC_APSAFE_RESET; R31 and C14 form a voltage rising delay circuit for the AP domain reset signal SOC_APSAFE_RESET; R24, D4 and C14 form a voltage falling delay circuit for the AP domain reset signal SOC_APSAFE_RESET.

[0152] Among them, a resistor R26 is connected between the base and emitter of transistor Q6, the emitter of transistor Q6 is connected to the output terminal of the AP domain 1.8 V power supply signal V_APSAFE_1V8, the collector of transistor Q6 is connected to the input terminal of the AP domain reset signal SOC_APSAFE_RESET after connecting resistor R31, the collector of transistor Q6 is connected to the negative pole of diode D4, diode D4 is in parallel with resistor R31, the negative pole of diode D4 is connected to resistor R24 and then grounded, the positive pole of diode D4 is connected to capacitor C14 and then grounded, and the base of transistor Q6 is connected to resistor R27 and then connected to the collector of transistor Q7.

[0153] A resistor R32 is connected between the base and the emitter of the triode Q7. The emitter of the triode Q7 is grounded. The base of the triode Q7 is connected to the resistor R30. The other end of the resistor R30 is respectively connected to the resistor R29 and the capacitor C13. The other end of the capacitor C13 is grounded. The other end of the resistor R29 is connected to the resistor R25 and then to the output end of the 5.0V power supply signal V_APSAFE_5V0 in the AP domain. The other end of the resistor R29 is connected to the resistor R28 and then to the output end of the 0.8V power supply status indication signal V_APSAFE_0V8_PG in the AP domain. The other end of the resistor R29 is connected to the resistor R33 and then to the input end of the 1.8V power supply enable signal V_APSAFE_0V8_PG in the AP domain. The other end of the resistor R29 is connected to the resistor R34 and then to the input end of the 3.3V power supply enable signal V_APSAFE_3V3_EN in the AP domain.

[0154] When the AP domain 5.0V power supply signal V_APSAFE_5V0 is within (4.8V - 5.2V) and the AP domain 1.8V power supply signal V_APSAFE_1V8 is within (1.7V - 1.9V), if the AP domain 0.8V power supply status indication signal V_APSAFE_0V8_PG is within (4.8V - 5.2V), the AP domain 1.8V power supply enable signal V_APSAFE_1V8_EN and the AP domain 3.3V power supply enable signal V_APSAFE_3V3_EN are both within (4.8V - 5.2V), and the AP domain reset signal SOC_APSAFE_RESET is within (1.7V - 1.9V), if the AP domain 0.8V power supply status indication signal V_APSAFE_0V8_PG is within (0V - 0.3V), the AP domain 1.8V power supply enable signal V_APSAFE_1V8_EN, the AP domain 3.3V power supply enable signal V_APSAFE_3V3_EN, and the AP domain reset signal SOC_APSAFE_RESET are all within (0V - 0.3V), if the AP domain 0.8V power supply status indication signal V_APSAFE_0V8_PG jumps from (0V - 0.3V) to (4.8V - 5.2V), the AP domain 1.8V power supply enable signal V_APSAFE_1V8_EN and the AP domain 3.3V power supply enable signal V_APSAFE_3V3_EN both jump from (0V - 0.3V) to (4.8V - 5.2V), and the AP domain reset signal SOC_APSAFE_RESET slowly rises from (0V - 0.3V) to (1.7V - 1.9V), and the slow rise time can be set. If the AP domain 0.8V power supply status indication signal V_APSAFE_0V8_PG jumps from (4.8V - 5.2V) to (0V - 0.3V), the AP domain 1.8V power supply enable signal V_APSAFE_1V8_EN and the AP domain 3.3V power supply enable signal V_APSAFE_3V3_EN both jump from (4.8V - 5.2V) to (0V - 0.3V), and the AP domain reset signal SOC_APSAFE_RESET quickly drops from (1.7V - 1.9V) to (0V - 0.3V), and the quick drop time can be set.

[0155] When the AP domain 5.0V power supply signal V_APSAFE_5V0 is not within (4.8V - 5.2V) or the AP domain 1.8V power supply signal V_APSAFE_1V8 is not within (1.7V - 1.9V), all output signals are uncertain.

[0156] Preferably, the triode in this embodiment can be replaced by a Mosfet with the same function.

[0157] Preferably, the chip in this embodiment can be replaced by other models of chips that achieve the same function.

[0158] Embodiment 2

[0159] This embodiment provides a control circuit for an SOC based on Embodiment 1, including an SOC, a power supply module, a watchdog control module, a watchdog module, an RTC domain delay reset module, and an AP domain enable and delay reset module. The difference between the control circuit of this embodiment and that of Embodiment 1 is that the AP domain enable and delay reset module of this embodiment uses a chip to implement its structure and function.

[0160] The connection method of the AP domain enable and delay reset module of this structure is as Figure 7 shown, including chip U3, capacitor C15, capacitor C16, capacitor C17, resistor R35, resistor R36, resistor R37, resistor R38, resistor R39, resistor R40.

[0161] R38 is taken as 100 Ω, which is an input isolation resistor; R40 is taken as 100 Ω, which is an output isolation resistor; R35 is taken as 100 Ω, which is an output isolation resistor; R37 is taken as 100 kΩ, which is an input pull-up resistor; C15 is taken as 10 nF, which is an input signal delay and filtering capacitor; R39 is taken as 1 kΩ, which is an input signal delay resistor. C15 and (R37 + R39) form an input signal, that is, a charging delay circuit for the AP domain 5.0V power supply signal V_APSAFE_5V0. C15 and (R38 + R39) form an input signal, that is, a discharging delay circuit for the AP domain 0.8V power supply status indication signal V_APSAFE_0V8_PG. Chip U3 is selected as the voltage monitoring integrated circuit SGM836-ADJXN6G / TR with programmable delay. C17 is taken as 100 nF, which is a filtering capacitor for the input power supply. C16 is taken as 4.7 nF, which is a reset output delay capacitor. R36 is taken as 10 kΩ, which is a pull-up resistor for the reset output signal.

[0162] The pin VDD of chip U3 is connected to the output end of the AP domain 1.8V power supply signal. A resistor R36 is connected between the pin VDD and the pin nRESET of chip U3. The pin VDD of chip U3 is connected to the pin SENSE.

[0163] The pin SENSE of chip U3 is connected to capacitor C17 and then grounded.

[0164] The pin CT of chip U3 is connected to capacitor C16 and then grounded.

[0165] The pin nMR of chip U3 is set floating.

[0166] The pin GND of chip U3 is grounded.

[0167] The pin nRESET of chip U3 is connected to the input end of the AP domain reset signal SOC_APSAFE_RESET.

[0168] The resistor R39 is connected to the capacitor C15 and then grounded. The other end of the resistor R39 is respectively connected to the resistors R37, R38, R40, and R35. The other end of the resistor R37 is connected to the output terminal of the 5.0V power supply signal in the AP domain. The other end of the resistor R38 is connected to the output terminal of the 0.8V power supply status indication signal V_APSAFE_0V8_PG in the AP domain. The other end of the resistor R40 is connected to the input terminal of the 1.8V power supply enable signal V_APSAFE_1V8_EN in the AP domain. The resistor R35 is connected to the input terminal of the 3.3V power supply enable signal V_APSAFE_3V3_EN in the AP domain.

[0169] Preferably, the triode in this embodiment can be replaced by a Mosfet with the same function.

[0170] Preferably, the chip in this embodiment can be replaced by other models of chips with the same function.

[0171] Embodiment 3

[0172] Another aspect of this embodiment provides a control method for a control circuit for SOC described in Embodiment 1 or Embodiment 2. The process is as Figure 8 shown, including the steps:

[0173] S1. The SOC and the power supply module output an RTC domain power supply signal, an RTC domain power supply status indication signal, an AP domain power supply signal, and an AP domain power supply status indication signal according to the received external power supply signal.

[0174] S2. The RTC domain delay reset module outputs an RTC domain reset signal according to the received RTC domain power supply signal and RTC domain power supply status indication signal, and the RTC domain of the SOC and the power supply module is reset for a preset time; the AP domain enable and delay reset module outputs an AP domain power supply enable signal and an AP domain reset signal according to the received AP domain power supply signal and AP domain power supply status indication signal, and the AP domain of the SOC and the power supply module is enabled and reset for a preset time.

[0175] S3. After the RTC domain and the AP domain are reset, the SOC and the power supply module work normally, output digital signals to the watchdog module, and sleep or be woken up according to the received external wake-up signal.

[0176] S4. After the SOC and the power supply module work properly, the watchdog module monitors the working state of the SOC, and outputs a power undervoltage protection reset signal and a watchdog timer timeout reset signal to the RTC domain delay reset module according to the received RTC domain power signal, AP domain power signal, and digital signal; the RTC domain delay reset module outputs an RTC domain reset signal according to the received RTC domain power signal, RTC domain power status indication signal, output power undervoltage protection reset signal, watchdog timer timeout reset signal, and external reset signal, and the SOC and the power supply module perform a reset of the RTC domain according to the received RTC domain reset signal.

[0177] Specifically, when the external power signal V_BAT is 0V, all the power supplies and signals of the control circuit for the SOC are at 0V voltage. When the external power signal V_BAT changes from 0V to 12V, the RTC domain 3.3V power signal V_RTC_3V3 outputs 3.3V voltage, the RTC domain 0.8V power signal V_RTC_0V8 outputs 0.8V voltage, the RTC domain 1.8V power signal V_RTC_1V8 outputs 1.8V voltage, the RTC domain reset signal SOC_RTC_RESET and the RTC domain 3.3V power status indication signal V_RTC_3V3_PG are both at a low level of 0V, and the SOC_RTC domain enters the reset state.

[0178] After the SOC_RTC domain is reset for 1.1 ms, the RTC domain 3.3V power status indication signal V_RTC_3V3_PG and the RTC domain reset signal SOC_RTC_RESET both output a high level of 1.8V, and the SOC_RTC domain exits the reset state, that is, the RTC domain power-on is completed and enters the normal working state. After a further delay of 75 us, the AP domain power-on signal V_APSAFE_PowerOn and the AP domain 5.0V power enable signal V_APSAFE_5V0_EN both output a high level of 1.8V. The AP domain 5.0V power signal V_APSAFE_5V0 outputs a power voltage of 5V. After a further delay of 30 us, the AP domain 5.0V power status indication signal V_APSAFE_5V0_PG and the AP domain 0.8V power enable signal V_APSAFE_0V8_EN output a high level of 5V. The AP domain 0.8V power signal V_APSAFE_0V8 outputs a power voltage of 0.82V. After a further delay of 0.1 ms, the AP domain 0.8V power status indication signal V_APSAFE_0V8_PG, the AP domain 1.8V power enable signal V_APSAFE_1V8_EN, and the AP domain 3.3V power enable signal V_APSAFE_3V3_EN all output a high level of 5V. The AP domain 1.8V power signal V_APSAFE_1V8 outputs a power voltage of 1.8V. The AP domain 3.3V power signal V_APSAFE_3V3 outputs a power voltage of 3.3V. The AP domain reset signal SOC_APSAFE_RESET is at a low level of 0V, and the SOC_APSAFE domain enters the reset state.

[0179] After the SOC_APSAFE domain is reset for 2.0 ms, the AP domain reset signal SOC_APSAFE_RESET outputs a high level of 1.8V, and the SOC_APSAFE domain exits the reset state, that is, the SOC power-on is completed and enters the normal working state. The program starts running. The digital signal SOC_GPIO1 outputs a square wave with a frequency of 200 Hz, a duty cycle of 50%, a low level of 0V, and a high level of 3.3V, which is used as the watchdog circuit's dog feeding signal, and other tasks are executed according to the software strategy.

[0180] When the SOC meets the sleep condition and the external wake-up signal SOC_SYS_WAKE0 is at a high level of 1.8V, after a delay of 1s, if the SOC still meets the sleep condition and the external wake-up signal SOC_SYS_WAKE0 is still at a high level of 1.8V, the AP domain reset signal SOC_APSAFE_RESET outputs a low level of 0V. After a delay of 1.8ms, the AP domain power-on signal V_APSAFE_PowerOn outputs a low level of 0V. Immediately afterwards, the AP domain 1.8V power signal V_APSAFE_1V8, the AP domain 3.3V power signal V_APSAFE_3V3, the AP domain 0.8V power signal V_APSAFE_0V8, and the AP domain 5.0V power signal V_APSAFE_5V0 all output 0V. The RTC domain 3.3V power signal V_RTC_3V3 still outputs a voltage of 3.3V, the RTC domain 0.8V power signal V_RTC_0V8 still outputs a voltage of 0.8V, the RTC domain 1.8V power signal V_RTC_1V8 still outputs a voltage of 1.8V, the RTC domain reset signal SOC_RTC_RESET still outputs a high level of 1.8V, and the SOC enters the sleep state with a standby current of approximately 50uA.

[0181] When the external wake-up signal SOC_SYS_WAKE0 changes from a high level of 1.8V to a low level of 0V, the SOC is awakened. The AP domain power-on signal V_APSAFE_PowerOn outputs a high level of 1.8V, and the AP domain 5.0V power signal V_APSAFE_5V0 outputs a power voltage of 5V. After a delay of 30us, the AP domain 0.8V power signal V_APSAFE_0V8 outputs a power voltage of 0.8V. After a delay of 0.1ms, the AP domain 1.8V power signal V_APSAFE_1V8 outputs a power voltage of 1.8V, the AP domain 3.3V power signal V_APSAFE_3V3 outputs a power voltage of 3.3V. After a delay of 2.0ms, the AP domain reset signal SOC_APSAFE_RESET outputs a high level of 1.8V, and the SOC_APSAFE domain exits the reset state, that is, the SOC wake-up is completed and it enters the normal working state, the program starts to run, and the digital signal SOC_GPIO1 outputs a square wave with a frequency of 200Hz, a duty cycle of 50%, a low level of 0V, and a high level of 3.3V, which is used as a watchdog circuit's feeding signal, and other tasks are executed according to the software strategy.

[0182] This embodiment also provides a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that when the processor executes the computer program, it implements the steps of the above control method for the control circuit of the SOC.

[0183] This embodiment also provides a computer-readable storage medium, such as a flash memory, a hard disk, a multimedia card, a card-type memory (e.g., SD or DX memory, etc.), a random access memory (RAM), a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, an optical disk, a server, an App application store, etc., on which a computer program is stored, and when the program is executed by a processor, corresponding functions are implemented. When the computer-readable storage medium of this embodiment is executed by a processor, the above control method for the control circuit of the SOC is implemented.

[0184] In summary, the present invention provides a control circuit and a control method for an SOC, which wake up the SOC based on an external wake-up signal or implement the reset and restart of the SOC, improving the reliability of waking up the SOC. Among them, the watchdog module is enabled by both the watchdog circuit enable signal and the AP domain power signal, improving the reliability of turning on the watchdog circuit.

[0185] It should be noted that according to the needs of implementation, the various steps / components described in this application can be split into more steps / components, or two or more steps / components or partial operations of steps / components can be combined into new steps / components to achieve the purpose of the present invention.

[0186] In the above embodiments, the magnitudes of the sequence numbers of the steps do not mean the order of execution. The execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of this application.

[0187] It should be understood that those of ordinary skill in the art can make improvements or transformations according to the above description, and all such improvements and transformations should fall within the protection scope of the appended claims of the present invention.

Claims

1. A control circuit for an SOC, characterized in that, It includes an SOC and a power supply module, a watchdog control module, a watchdog module, an RTC domain delay reset module, and an AP domain enable and delay reset module; Among them: the SOC and power supply module includes an AP domain and an RTC domain, which are respectively connected to the watchdog control module, the watchdog module, the RTC domain delay reset module, and the AP domain enable and delay reset module, and sleep or are woken up according to an external wake-up signal during normal operation; it is used to output an RTC domain power signal, an AP domain power signal, and a digital signal according to an external power signal; it is used to reset the RTC domain or the AP domain according to an RTC domain reset signal or an AP domain reset signal; The watchdog control module is connected to the watchdog module and is used to output a watchdog circuit enable signal according to an external wake-up signal, an RTC domain power signal, and an AP domain power signal; The watchdog module is connected to the RTC domain delay reset module, and is enabled or disabled by the watchdog circuit enable signal and the AP domain power signal. It is used to output a power supply undervoltage protection reset signal and a watchdog timer timeout reset signal according to the RTC domain power signal, the AP domain power signal, and the digital signal in the enabled state; The RTC domain delay reset module is used to output an RTC domain reset signal according to the RTC domain power signal, the output power supply undervoltage protection reset signal, and the watchdog timer timeout reset signal; The AP domain enable and delay reset module is used to enable the AP domain and generate an AP domain reset signal.

2. The control circuit for the SOC according to claim 1, wherein, The RTC domain power signal includes a first RTC domain power signal, a second RTC domain power signal, and a third RTC domain power signal; the AP domain power signal includes a first AP domain power signal, a second AP domain power signal, a third AP domain power signal, and a fourth AP domain power signal.

3. The control circuit for the SOC according to claim 2, wherein, The SOC and power supply module is further used to receive an AP domain power enable signal, and the AP domain power enable signal includes a first AP domain power enable signal and a fourth AP domain power enable signal from the AP domain of this module, and a second AP domain power enable signal and a third AP domain power enable signal from the AP domain enable and delay reset module; The SOC and power supply module is further used to output an AP domain power status indication signal, and the AP domain power status indication signal includes an AP domain power on signal, a first AP domain power status indication signal, and a second AP domain power status indication signal; The SOC and power supply module is further used to output an RTC domain power status indication signal.

4. The control circuit for SOC according to claim 3, characterized in that, The AP domain power on signal is connected to the fourth AP domain power enable signal; the second AP domain power status indication signal is connected to the first AP domain power enable signal.

5. The control circuit for the SOC according to claim 4, wherein, When the input of the external power signal changes from 0V to a preset value: After delaying a preset time, the SOC and power supply module makes the RTC domain power status indication signal output a high level; After delaying a preset time, the SOC and power supply module makes both the AP domain power on signal and the fourth AP domain power signal output a high level; After delaying a preset time, the SOC and power supply module makes both the second AP domain power status indication signal and the first AP domain power signal output a high level; Delay for a preset time, and the SOC and the power supply module cause the first AP domain power status indication signal, the second AP domain power signal, and the third AP domain power signal to all output high levels, and the second AP domain power enable signal and the third AP domain power enable signal to all output high levels; Delay for a preset time, and the SOC and the power supply module cause a square wave with a digital signal output frequency within a preset range, a duty cycle within a preset range, a low level within a preset range, and a high level within a preset range.

6. The control circuit for the SOC according to claim 4, wherein The watchdog control module includes a first chip, a first triode, a second triode, and a third triode; Wherein, the first chip is a dual D trigger integrated circuit with set and reset functions. The first triode is used for inverting and isolating signals. The second triode is used for inverting and switching control of signals. The third triode is used for inverting and amplifying signals; The pin D, pin CLR, and pin PRE of the first chip are connected to the second RTC domain power signal, and the pin Q is connected to the watchdog circuit enable signal; the collector of the first triode is connected to the second RTC domain power signal, and the base is connected to the external wake-up signal; the collector of the second triode is connected to the second RTC domain power signal, and the base is connected to the third AP domain power signal; the collector and the base of the third triode are connected to the second RTC domain power signal.

7. The control circuit for the SOC according to claim 6, wherein When the second RTC domain power signal outputs a high level and the external wake-up signal changes from a high level to a low level: the watchdog control module causes the watchdog enable signal to output a high level; When the second RTC domain power signal outputs a high level and the external wake-up signal changes from a low level to a high level: if the third AP domain power signal changes from a high level to a low level, the watchdog control module causes the watchdog enable signal to output a low level; if the third AP domain power signal changes from a low level to a high level, the watchdog control module causes the watchdog enable signal to output a high level; When the second RTC domain power signal and the third AP domain power signal output low levels and the external wake-up signal is at a high level or a low level: the watchdog control module causes the watchdog enable signal to output a low level.

8. The control circuit for the SOC according to claim 4, characterized in that, The watchdog module includes a second chip, a first diode, a second diode, and a first switch; the second chip is used for monitoring the circuit voltage and enabling and detecting the watchdog module; the first diode and the second diode are used for isolating signals; the first switch is used for forcibly opening and closing the watchdog module; Wherein, the pin VCC of the second chip is connected to the second RTC domain power signal, the pin SET is connected to the watchdog enable signal and the third AP domain power signal, the pin WDI is connected to the digital signal, the pin nWDO is connected to the power supply undervoltage protection reset output signal, and the pin nRESET is connected to the watchdog timer timeout reset signal; the anode of the first diode is connected to the third AP domain power signal; the anode of the second diode is connected to the watchdog enable signal; the first switch is connected to the watchdog enable signal.

9. The control circuit for an SOC according to claim 8, wherein When the third AP domain power signal outputs a high level or the watchdog enable signal outputs a high level, the watchdog module is enabled; when the third AP domain power signal outputs a high level and the watchdog enable signal outputs a low level, the watchdog module is disabled.

10. The control circuit for SOC according to claim 8, wherein, When the watchdog module is enabled, if the voltage value of the second RTC domain power signal is less than a preset low voltage threshold, the watchdog module causes the power undervoltage protection reset signal to output a low level; if the voltage value of the second RTC domain power signal is greater than the preset low voltage threshold by a certain multiple, the watchdog module causes the power undervoltage protection reset signal to output a high level. When the watchdog module is disabled, the watchdog module causes the watchdog timer timeout reset signal to output a high level; when the watchdog module is enabled, if the pulse period of the digital signal is within a preset range and less than the preset watchdog timeout reset period, the watchdog module causes the watchdog timer timeout reset signal to output a high level; if the pulse period of the digital signal is within a preset range and greater than the preset watchdog timeout reset period, the watchdog module causes the watchdog timer timeout reset signal to output a low level.

11. The control circuit for SOC according to claim 4, wherein the RTC domain delay reset module includes a fourth triode, a fifth triode, and a third diode; the fourth triode is used to conduct and cut off signals, the fifth triode is used to perform inversion and switch control on signals, and the third diode is used to step down the base of the fourth triode and isolate signals. The collector of the fourth triode is connected to the second RTC domain power signal, the base is connected to the output terminal of the power undervoltage protection reset signal, the watchdog timer timeout reset signal, and an external reset signal; the collector of the fifth triode is connected to the second RTC domain power signal, the RTC domain power status indication signal, and the RTC domain reset signal.

12. The control circuit for SOC according to claim 11, wherein when the RTC domain power status indication signal outputs a high level or a low level, the RTC domain delay reset module causes the RTC domain reset signal to output a high level or a low level correspondingly. When the second RTC domain power supply signal outputs a preset value: If any of the power supply undervoltage protection reset signal, watchdog timer timeout reset signal, or external reset signal outputs a low level, the RTC domain delay reset module causes the output of the RTC domain reset signal to be at a low level; if the power supply undervoltage protection reset signal, watchdog timer timeout reset signal, and external reset signal all output high levels, the RTC domain delay reset module causes the RTC domain reset signal to output a high level; if the power supply undervoltage protection reset signal, watchdog timer timeout reset signal, or external reset signal jumps from any output of a low level to all outputting high levels, the RTC domain delay reset module causes the RTC domain reset signal to initially output a low level and jump to a high level after a preset time delay; if the power supply undervoltage protection reset signal, watchdog timer timeout reset signal, or external reset signal jumps from all outputting high levels to any output of a low level, the RTC domain delay reset module causes the RTC domain reset signal to jump from a high level to a low level.

13. The control circuit for the SOC according to claim 4, wherein, The AP domain enable and delay reset module includes a discharge delay circuit for the fourth AP domain power supply signal, a discharge delay circuit for the first AP domain power status indication signal, a voltage rise delay circuit for the AP domain reset signal, and a voltage drop delay circuit. The AP domain enable and delay reset module is also connected to the second AP domain power enable signal, the third AP domain power enable signal, and the second AP domain power supply signal. When the fourth AP domain power supply signal and the second AP domain power supply signal output high levels: If the first AP domain power status indication signal outputs a high level, the AP domain enable and delay reset module causes the second AP domain power enable signal, the third AP domain power enable signal, and the AP domain reset signal to output high levels. If the first AP domain power status indication signal outputs a low level, the AP domain enable and delay reset module causes the second AP domain power enable signal, the third AP domain power enable signal, and the AP domain reset signal to output low levels. If the first AP domain power status indication signal jumps from a low level to a high level, the AP domain enable and delay reset module causes the second AP domain power enable signal and the third AP domain power enable signal to jump from a low level to a high level, and the AP domain reset signal rises from a low level to a high level after a preset time. If the first AP domain power status indication signal jumps from a high level to a low level, the AP domain enable and delay reset module causes the second AP domain power enable signal and the third AP domain power enable signal to jump from a high level to a low level, and the AP domain reset signal drops from a high level to a low level after a preset time.

14. The control circuit for the SOC according to claim 13, characterized in that, The AP domain enable and delay reset module includes a sixth triode and a seventh triode; the sixth triode and the seventh triode are used for inverting and amplifying signals. The emitter of the sixth triode is connected to the second AP domain power supply signal, and the collector is connected to the AP domain reset signal; the collector of the seventh triode is connected to the second AP domain power supply signal, and the base is connected to the fourth AP domain power supply signal, the second AP domain power enable signal, the third AP domain power enable signal, and the first AP domain power status indication signal.

15. The control circuit for an SOC according to claim 13, wherein The AP domain enabling and delay reset module includes a third chip; the third chip is a voltage monitoring integrated circuit with programmable delay; Pin VDD and pin SENSE of the third chip are connected to the second AP domain power signal, and pin VDD and pin nRESET of the third chip are connected to the AP domain reset signal.

16. A control method for a control circuit for an SOC according to any one of claims 1-15, characterized in that, It includes: The SOC and the power module output the RTC domain power signal and the AP domain power signal according to the received external power signal; The RTC domain delay reset module outputs the RTC domain reset signal according to the RTC domain power signal, and the RTC domain of the SOC and the power module is reset for a preset time according to the RTC domain reset signal; the AP domain enabling and delay reset module enables the AP domain of the SOC and the power module according to the AP domain power signal and outputs the AP domain reset signal, and the AP domain of the SOC and the power module is reset for a preset time according to the AP domain reset signal; After the RTC domain and the AP domain are reset, the SOC and the power module work normally, output digital signals to the watchdog module, and are put to sleep or woken up by an external wake-up signal; the watchdog module is enabled or disabled by the watchdog circuit enabling signal output by the watchdog control module and the AP domain power signal; the watchdog control module outputs the watchdog circuit enabling signal according to the external wake-up signal, the RTC domain power signal and the AP domain power signal; In the enabled state, the watchdog module outputs a power undervoltage protection reset signal and a watchdog timer timeout reset signal according to the RTC domain power signal, the AP domain power signal and the digital signal; The RTC domain delay reset module outputs the RTC domain reset signal according to the RTC domain power signal, outputs the power undervoltage protection reset signal and the watchdog timer timeout reset signal, and the SOC and the power module reset the RTC domain according to the RTC domain reset signal.

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