Hardware simulation tool, interface adapter and hardware simulation system

Abstract

The invention provides a hardware simulation tool which is used for being connected with a first host and a daughter card to simulate logic system design, and the hardware simulation tool comprises a programmable logic device used for realizing the logic system design; the first interface is connected with the programmable logic device and the first host; and the interface adapter is connected with the programmable logic device and the daughter card, and the interface adapter is also connected to a second host.

Description

Technical Field

[0001] This application relates to the field of chip verification technology, and particularly to a hardware simulation tool, an interface adapter, and a hardware simulation system. Background Art

[0002] A hardware simulation tool (e.g., a prototype verification board or an emulator) can prototype and debug a logic system design including one or more modules. The logic system design can be, for example, a design for an Application Specific Integrated Circuit (ASIC) or a System-On-Chip (SOC) for a specific application. Therefore, the logic system design to be tested in the simulation tool can also be referred to as the Design Under Test (DUT). The simulation tool can simulate the DUT through one or more configurable components (e.g., a Field Programmable Gate Array (FPGA)), including performing various operations of the DUT, so as to test and verify the functions of each module of the DUT before manufacturing. By externally connecting various peripheral daughter cards to the simulation tool, the running effect of the DUT and various peripherals as a complete system can also be tested.

[0003] There are also many software supporting the hardware simulation tool, such as compilers, synthesizers, debuggers, etc.

[0004] The compiler is used to compile the source code of the logic system design, the synthesizer is used to synthesize the logic system design into a netlist form and burn it into the FPGA, and the debugger is used to implement some simple debugging functions. It can be understood that the above software runs on a host connected to the hardware simulation tool.

[0005] When a hardware simulation tool externally connects various peripheral daughter cards, a cable connection error may occur. This cable connection error may be an error generated by the user during connection, or may be caused by a configuration error when the logic system design configures the pins. Summary of the Invention

[0006] A first aspect of this application provides a hardware simulation tool for connecting to a first host and a daughter card to simulate a logic system design. The hardware simulation tool includes: a programmable logic device for implementing the logic system design; a first interface connecting the programmable logic device and the first host; and an interface adapter connecting the programmable logic device and the daughter card, and the interface adapter is also connected to a second host.

[0007] A second aspect of the present application provides a hardware simulation system, including: a hardware simulation tool for connecting to a first host and a daughter card to simulate a logic system design, the hardware simulation tool including: a programmable logic device for implementing the logic system design; and a first interface connecting the programmable logic device and the first host; and an interface adapter connecting the hardware simulation tool and the daughter card, the interface adapter also being connected to a second host.

[0008] A third aspect of the present application provides an interface adapter for connecting to a daughter card and a hardware simulation tool, the interface adapter including: a plurality of first pins for connecting to a programmable logic device of the hardware simulation tool, a plurality of second pins for connecting to the daughter card, and at least one third pin for reading values of the plurality of first pins or the plurality of second pins; and a memory for storing a connection relationship configuring connections between the plurality of first pins, the plurality of second pins, and the at least one third pin. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the present application or related technologies, the following will briefly introduce the drawings required for use in the embodiments or related technology descriptions. Obviously, the drawings in the following description are only embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0010] Figure 1 The structural schematic diagram of an exemplary host according to an embodiment of the present application is shown.

[0011] Figure 2 The schematic diagram of a simulation system according to an embodiment of the present application is shown.

[0012] Figure 3 The schematic diagram of another simulation system according to an embodiment of the present application is shown.

[0013] Figure 4 The schematic diagram of an interface adapter according to an embodiment of the present application is shown.

[0014] Figure 5 The schematic diagram of another exemplary interface adapter according to an embodiment of the present application is shown.

[0015] Figure 6 The schematic diagram of yet another exemplary interface adapter according to an embodiment of the present application is shown.

[0016] Figure 7 The schematic diagram of a hardware simulation system according to an embodiment of the present application is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] In order to make the objectives, technical solutions and advantages of this application more clear, this application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0018] It should be noted that, unless otherwise defined, the technical or scientific terms used in this application should have the usual meaning understood by people with ordinary skills in the field to which this application belongs. The "first", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0019] As mentioned above, cable connection errors may occur when connecting multiple peripheral daughter cards to the hardware emulation tool. These cable connection errors may be caused by errors made by the user when connecting cables (typically there can be dozens of cables, making them very error-prone) (for example, incorrect cable connections) or by pin configuration errors in the logic system design.

[0020] Generally, when an error occurs due to a user connection error, the hardware emulation system may require the user to reconnect; when a configuration pin error occurs, the hardware emulation system may require the user to reconfigure and recompile.

[0021] This shows that once an error occurs, users need to spend a lot of time adjusting the physical connection or pin configuration.

[0022] How to facilitate users to adjust cable connection errors is a technical problem that needs to be solved urgently.

[0023] Figure 1 FIG1 shows a schematic diagram of the structure of the host 100 according to an embodiment of the present application. The host 100 may be an electronic device running a simulation system. Figure 1 As shown, the host 100 may include a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. The processor 102, the memory 104, the network interface 106, and the peripheral interface 108 are connected to each other via the bus 110 within the electronic device.

[0024] The processor 102 can be a Central Processing Unit (CPU), an image processor, a Neural Network Processor (NPU), a Microcontroller Unit (MCU), a programmable logic device, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits. The processor 102 can be used to execute functions related to the technologies described in this application. In some embodiments, the processor 102 can also include multiple processors integrated as a single logic component. As Figure 1 shown, the processor 102 can include multiple processors 102a, 102b, and 102c.

[0025] The memory 104 can be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In some embodiments, the simulation test system for simulating a test design can be a computer program stored in the memory 104. As Figure 1 shown, the data stored in the memory can include program instructions (e.g., program instructions for implementing the method of positioning errors in this application) and data to be processed (e.g., the memory can store temporary code generated during the compilation process). The processor 102 can also access the program instructions and data stored in the memory and execute the program instructions to operate on the data to be processed. The memory 104 can include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 can include a Random Access Memory (RAM), a Read-Only Memory (ROM), an optical disc, a magnetic disk, a hard disk, a Solid State Drive (SSD), a flash memory, a memory stick, etc.

[0026] The network interface 106 can be configured to provide communication with other external devices to the host 100 via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, Near Field Communication (NFC), etc.), a cellular network, the Internet, or a combination of the above. It can be understood that the type of the network is not limited to the above specific examples. In some embodiments, the network interface 106 can include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.

[0027] The peripheral interface 108 can be configured to connect the host 100 to one or more peripheral devices to achieve information input and output. For example, the peripheral devices can include input devices such as a keyboard, a mouse, a touchpad, a touch screen, a microphone, various sensors, etc. and output devices such as a display, a speaker, a vibrator, an indicator light, etc.

[0028] The bus 110 can be configured to transfer information among various components of the host 100, such as the processor 102, the memory 104, the network interface 106, and the peripheral interface 108, such as an internal bus (e.g., a processor-memory bus), an external bus (USB port, PCI-E bus), etc.

[0029] It should be noted that although the above electronic device architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in the specific implementation process, this electronic device architecture may also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above electronic device architecture may also only include the components necessary to implement the solution of the embodiments of the present application, and does not necessarily include all the components shown in the figure.

[0030] Figure 2 A schematic diagram of a simulation system 200 according to an embodiment of the present application is shown.

[0031] As Figure 2 shown, the simulation system 200 may include a simulation tool 202 and a host 100 connected to the simulation tool 202.

[0032] The simulation tool 202 is a hardware system for simulating a design under test (DUT). The simulation tool 202 may be a prototype verification board or a hardware emulator. A design under test may include multiple modules. The design under test may be a combinational logic circuit, a sequential logic circuit, or a combination of the two. The simulation tool 202 may include one or more configurable circuits (e.g., FPGA) for simulating the design under test.

[0033] The simulation tool 202 may include an interface unit 2022 for communicatively coupling with the host 100 to enable communication between the host 100 and the simulation tool 202. In some embodiments, the interface unit 2022 may include one or more interfaces with electrical connection capabilities. For example, the interface unit 2022 may include an RS232 interface, a USB interface, a LAN port, an optical fiber interface, an IEEE1394 (FireWire interface), etc. In some embodiments, the interface unit 2022 may be a wireless network interface. For example, the interface unit 2022 may be a WIFI interface, a Bluetooth interface, etc.

[0034] The host 100 may transmit the compiled DUT, debug instructions, etc. to the simulation tool 202 via the interface unit 2022. The simulation tool 202 may also transmit simulation data, etc. to the host 100 via the interface unit 2022.

[0035] The simulation tool 202 may further include a memory 2024 for storing simulation data (e.g., various signal values) generated by the design under test during the simulation process. In some embodiments, the signal values generated by the design under test during the simulation process can be directly read by the host 100. It can be understood that the memory 2024 can also be independent of the simulation tool 202, for example, using an external memory.

[0036] The simulation tool 202 may further include a programmable logic device (e.g., FPGA) 2026 for hardware-implementing a logic system design onto the programmable logic device. It can be understood that the simulation tool 202 may include multiple programmable logic devices, and only an example is shown in the figure.

[0037] In addition to being connected to the host 100, the simulation tool 202 may also be connected to one or more daughter cards 204 via the interface unit 2022.

[0038] The daughter card is used to provide peripherals to the DUT to form a complete electronic system when using the simulation tool 202 for prototype verification. Prototype verification refers to a verification method that, before the chip is taped out, tries to restore the real usage scenario of the chip as much as possible to verify whether the chip functions accurately and completely. The daughter card 204 may include a memory daughter card (e.g., providing a DDR memory interface), a communication daughter card (e.g., providing multiple network interfaces or a wireless network card interface), etc. The daughter card 204 can refer to all peripherals.

[0039] The host 100 can be used to configure the simulation tool 202 to simulate a design under test. The design under test can be a complete logic system design or one or more modules of a complete logic system design. In some embodiments, the host 100 can be a virtual host in a cloud computing system. A logic system design (e.g., ASIC or System-On-Chip) can be designed by a hardware description language (e.g., Verilog, VHDL, System C, or System Verilog). The host 100 configuring the simulation tool 202 may include configuring the simulation environment (e.g., the connection relationship between multiple simulation tools 202 or the connection relationship between the simulation tool and the daughter card), etc.

[0040] The host 100 can compile a logic system design in source code form into an executable file. From a design perspective, a logic system design can include a design under test and a test bench corresponding to the design under test.

[0041] From a comprehensive perspective, the design of a logic system can include synthesizable parts and non-synthesizable parts. The synthesizable parts usually correspond to the actual physical design (e.g., a chip), while the non-synthesizable parts usually include initialization modules, test benches, etc. The executable file formed after compiling the non-synthesizable parts can usually be run by the host 100. The synthesizable parts still need to be synthesized after compilation to form a bit file. The bit file can be used to configure the FPGA 2026 to run according to the design requirements of the synthesizable parts.

[0042] The host 100 can receive a request from the user to debug the design under test. As described above, the design under test can include one or more modules. The description of the design under test can be completed in a hardware description language. The host 100 can perform synthesis based on the description of the design under test to generate, for example, a gate-level circuit netlist (not shown) of the design under test. The gate-level circuit netlist of the design under test can be loaded into the simulation tool 202 to run, and then a circuit structure corresponding to the design under test can be formed in the simulation tool 202. Therefore, the circuit structure of the design under test can be obtained according to this description, and correspondingly, the circuit structure of each block in the design under test can also be obtained similarly.

[0043] As described above, when the daughter card 204 is connected to the simulation tool 202, a cable connection error may occur due to a wiring error or a configuration error.

[0044] In view of the above problems, an embodiment of the present application provides a novel structure of a simulation tool.

[0045] Figure 3 A schematic diagram of another simulation system 300 according to an embodiment of the present application is shown.

[0046] The simulation system 300 can include a hardware simulation tool 302, a daughter card 204, a host 100, and a host 304.

[0047] Different from the general structure, in addition to the interface unit 2022, the memory 2024, and the programmable logic device 2026, the simulation tool 302 further includes an interface adapter 3022.

[0048] The interface adapter 3022 is connected to the daughter card 204, the programmable logic device 2026, and the host 304. The host 304 and the host 100 can be the same host or different hosts. Here, for the sake of distinction, different hosts are taken as an example for illustration.

[0049] Figure 4 A schematic diagram of the interface adapter 3022 according to an embodiment of the present application is shown.

[0050] As Figure 4As shown, after the logic system design is configured into the FPGA 2026, n + 1 leads of the FPGA 2026 are configured as n + 1 pins pin_00, pin_01, pin_02, …, pin_0n of the logic system design. n can be a positive integer greater than 1. It can be understood that the FPGA 2026 has at least n + 1 leads, and the configured leads are only at least a part of all the leads of the FPGA 2026. Generally, the pins pin_00, pin_01, pin_02, …, pin_0n are used as inputs or outputs of the logic system design. It can be understood that the n + 1 pins pin_00, pin_01, pin_02, …, pin_0n of the logic system design can be connected to the interface adapter 3022 via the interface 202 of the hardware simulation tool 302. That is to say, the connection of the interface adapter 3022 to the programmable logic device (such as, FPGA) 2026 can be indirect (such as, via an additional interface). It can be understood that in the description of the embodiments of the present application, any connection includes a direct connection or an indirect connection.

[0051] The interface adapter 3022 can include a plurality of first pins A0, A1, A2, …, An for connecting to the programmable logic device 2026 and a plurality of second pins B0, B1, B2, …, Bn for connecting to the daughter card 204. The interface adapter 3022 can also include a third pin Am, Bo, etc.

[0052] In some embodiments, the pins Am, etc. and the plurality of first pins A0, A1, A2, …, An are arranged on one side of the interface adapter 3022 for connecting to the hardware simulation tool 302. Therefore, the pins A0, A1, A2, …, An, …Am can be referred to as internal connection pins. The pins Bo, etc. and the plurality of second pins B0, B1, B2, …, Bn are arranged on the other side of the interface adapter 3022 for connecting to the daughter card 204. Therefore, the pins B0, B1, B2, …, Bn can be referred to as external connection pins. It can be understood that the arrangement of the pins is not necessarily limited to two sides.

[0053] It can be seen that the number m + 1 of the internal connection pins can be a positive integer greater than or equal to n + 1; the number o + 1 of the external connection pins can be a positive integer greater than or equal to n + 1.

[0054] The third pins Am, Bo can be used to read the values of the plurality of first pins or the plurality of second pins. Specifically, it will be further described later.

[0055] The interface adapter 3022 can include a memory 3024 for storing the connection relationship between the plurality of first pins and the plurality of second pins. The connection relationship is, for example, that pin A0 is connected to pin B0.

[0056] The interface adapter 3022 can configure the connection between the first pin and the second pin of the interface adapter 3022 according to the above connection relationship.

[0057] Corresponding to the FPGA 2026, the daughter card 204 may also include n + 1 pins pin_10, pin_11, pin_12, …, pin_1n.

[0058] In Figure 4 In the embodiment of

[0059] As stated in this application, the cable connection error may be caused by configuration errors and physical lead connection errors (e.g., ribbon cable connection errors).

[0060] Figure 5 FIG. shows a schematic diagram of another exemplary interface adapter 3022 according to an embodiment of this application.

[0061] In some embodiments, as Figure 5 shown, due to user configuration errors, the pin that should have been configured as pin_00 is configured as pin_01, and the pin that should have been configured as pin_01 is configured as pin_00. For the existing connection method (i.e., the pins of the FPGA 2026 are directly connected to the corresponding pins of the daughter card 204), pin_01 will be connected to pin_10, and pin_00 will be connected to pin_11. Compared with the correct connection where pin_00 is connected to pin_10 and pin_01 is connected to pin_11, a connection error occurs. In the prior art, it is necessary to reconfigure the logic system design, generate a new bit file, and accordingly reconfigure the FPGA 2026, which consumes a lot of time. Figure 5 The embodiment of

[0062] After the user locates the configuration errors of pin_00 and pin_01, the user can dynamically modify the connection relationship between multiple first pins and multiple second pins in the interface adapter 3022 via the host 304. In some embodiments, the user can implement the modification of the connection relationship in the memory 3024 in the host 304. For example, compared with the default connection where the first pin A0 is connected to the second pin B0 and the first pin A1 is connected to the second pin B1, the connection relationship can be modified to the first pin A0 is connected to the second pin B1 and the first pin A1 is connected to the second pin B0.

[0063] In this way, the misconfigured pin_01 can be connected to the second pin B1 after passing through the first pin A0 of the interface adapter 3022, and finally connected to the pin pin_11 of the daughter card 204 to form a correct connection.

[0064] Similarly, the misconfigured pin_00 can also be correctly connected to the pin pin_10.

[0065] In this way, the user can correct the incorrect connection without recompiling and configuring the FPGA 2026, improving the efficiency.

[0066] The above embodiments are described by taking configuration errors as examples. It can be understood that other types of connection errors can be corrected similarly.

[0067] Figure 6 FIG. shows a schematic diagram of another exemplary interface adapter 3022 according to an embodiment of the present application.

[0068] In some embodiments, one first pin of the interface adapter 3022 can be connected to more than two second pins, and one second pin can be connected to more than two first pins.

[0069] For example, as Figure 6 shown, the first pin An can be connected to the second pin Bn and the third pin Bo. In this way, without affecting the normal verification of the logic system design, the user can also read the value of the first pin An through the pin Bo, and then read the value of Pin_0n connected to the first pin An. That is to say, without affecting the normal verification of the logic system design, the user can directly observe the output of the FPGA 2026 by using the interface adapter 3022, thus reducing the additional occupation of the limited IO resources of the FPGA.

[0070] Similarly, the second pin Bn can be connected to the first pin An and the third pin Am. In this way, the user can also read the value of the second pin Bn through the third pin Am, and then read the value of Pin_1n connected to the second pin Bn.

[0071] In some embodiments, the interface adapter can be independent of the hardware simulation tool.

[0072] Figure 7 FIG. shows a schematic diagram of a hardware simulation system 700 according to an embodiment of the present application.

[0073] As Figure 7As shown, the hardware emulation system 700 can be used to connect to the first host 100 and the daughter card 204 to emulate a logic system design, and includes: a hardware emulation tool 702 for connecting to the first host 100 and the daughter card 204 to emulate a logic system design; and an interface adapter 704 connecting the hardware emulation tool 702 and the daughter card 204.

[0074] The hardware emulation tool 702 can include: a programmable logic device for implementing the logic system design (e.g., Figure 7 the FPGA 2026 in); and a first interface 2022 connecting the programmable logic device and the first host 100.

[0075] The interface adapter 704 is also connected to the second host 304.

[0076] The interface adapter 704 further includes: a plurality of first pins for connecting to the first interface (e.g., Figure 4 A0 to An of), a plurality of second pins for connecting to the daughter card (e.g., Figure 4 B0 to Bn of), and at least one third pin for reading the plurality of first pins or the plurality of second pins (e.g., Figure 4 Am or Bo of, etc.); a memory (e.g., Figure 4 3024 in), for storing a connection relationship configuring the connection between the plurality of first pins, the plurality of second pins, and the at least one third pin (e.g., Figure 5 the connection relationship shown). It can be understood that although Figure 4 and Figure 5 the described interface adapter is integrated with the hardware emulation tool, the structure of the interface adapter is the same.

[0077] In addition, in some embodiments, the first host 100 and the second host 304 can be the same host or different hosts, and they are described separately here only for distinction.

[0078] By providing a separate interface adapter 704 to the hardware emulation tool 702 in the hardware emulation system 700, the hardware emulation system 700 can be flexibly adjusted Embodiments of the present application also provide a hardware emulation tool (e.g., Figure 3 the hardware emulation tool 302 in). The hardware emulation tool can be used to connect to a first host (e.g., Figure 3 the host 100 in) and a daughter card (e.g., Figure 3 the daughter card 204 in) to emulate a logic system design (not shown). The hardware emulation tool includes: a programmable logic device for implementing the logic system design (e.g., Figure 2the FPGA 2026); a first interface connecting the programmable logic device and the first host. For example, Figure 2 the interface 2022; and an interface adapter connecting the first interface and the daughter card (for example, Figure 3 the interface adapter 3022). The interface adapter is also connected to a second host (for example, Figure 3 the host 304).

[0079] The interface adapter further includes: a plurality of first pins for connecting to the first interface (for example, Figure 4 A0 to An), a plurality of second pins for connecting to the daughter card (for example, Figure 4 B0 to Bn), and at least one third pin for reading the plurality of first pins or the plurality of second pins (for example, Figure 4 Am or Bo, etc.); a memory (for example, Figure 4 3024) for storing the connection relationship configuring the connection between the plurality of first pins, the plurality of second pins, and the at least one third pin (for example, Figure 5 the connection relationship shown).

[0080] In addition, in some embodiments, the first host 100 and the second host 304 may be the same host or different hosts, and they are separately described here only for distinction.

[0081] An embodiment of the present application also provides an interface adapter for connecting to a first interface of a daughter card and a hardware emulation tool. The interface adapter includes: a plurality of first pins for connecting to the first interface (for example, Figure 4 A0 to An), a plurality of second pins for connecting to the daughter card (for example, Figure 4 B0 to Bn), and at least one third pin for reading the plurality of first pins or the plurality of second pins (for example, Figure 4 Am or Bo, etc.); a memory (for example, Figure 4 3024) for storing the connection relationship configuring the connection between the plurality of first pins, the plurality of second pins, and the at least one third pin (for example, Figure 5 the connection relationship shown).

[0082] Some embodiments of the present application have been described above. Other embodiments are within the scope of the appended claims. In some cases, the acts or steps recited in the claims may be performed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0083] Those of ordinary skill in the art should understand that the discussion of any embodiment above is merely exemplary and is not intended to imply that the scope of the present application (including the claims) is limited to these examples; within the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the present application as described above, which are not provided in detail for the sake of brevity.

[0084] Although the present application has been described in connection with specific embodiments of the present application, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art based on the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0085] The present application is intended to cover all such alternatives, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A hardware simulation tool for connecting to a first host and a daughter card to simulate a logic system design, the hardware simulation tool comprising: A programmable logic device for implementing the logic system design; A first interface connecting the programmable logic device and the first host; And An interface adapter connecting the programmable logic device and the daughter card, the interface adapter also being connected to a second host.

2. The hardware simulation tool according to claim 1, wherein, The interface adapter further comprises: A plurality of first pins for connecting to the programmable logic device, a plurality of second pins for connecting to the daughter card, and at least one third pin for reading values of the plurality of first pins or the plurality of second pins; A memory for storing a connection relationship configuring connections between the plurality of first pins, the plurality of second pins, and the at least one third pin.

3. The hardware simulation tool according to claim 1, wherein The first host and the second host are the same host.

4. A hardware simulation system, comprising: A hardware simulation tool for connecting to a first host and a daughter card to simulate a logic system design, the hardware simulation tool comprising: a programmable logic device for implementing the logic system design; and a first interface connecting the programmable logic device and the first host; and An interface adapter connecting the hardware simulation tool and the daughter card, the interface adapter also being connected to a second host.

5. The hardware simulation system according to claim 2, wherein The interface adapter further comprises: A plurality of first pins for connecting to the programmable logic device of the hardware simulation tool, a plurality of second pins for connecting to the daughter card, and at least one third pin for reading values of the plurality of first pins or the plurality of second pins; A memory for storing a connection relationship configuring connections between the plurality of first pins, the plurality of second pins, and the at least one third pin.

6. The hardware simulation system according to claim 1, wherein, The first host and the second host are the same host.

7. An interface adapter for connecting to a daughter card and a hardware simulation tool, the interface adapter comprising: A plurality of first pins for connecting to the programmable logic device of the hardware simulation tool, a plurality of second pins for connecting to the daughter card, and at least one third pin for reading values of the plurality of first pins or the plurality of second pins; And A memory for storing a connection relationship configuring connections between the plurality of first pins, the plurality of second pins, and the at least one third pin.

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