Methods, apparatuses, media, and products for data processing

Abstract

The application discloses a method, device, medium and product for data processing, relates to the technical field of data storage, and comprises the following steps: assigning the same input / output queue to multiple controllers; and each controller exclusively controls the queue item assigned to the controller. By commonly assigning the same input / output queue to multiple controllers, hardware overhead can be significantly reduced, dynamic allocation of the input / output queue between the multiple controllers is supported, and system requirements of different scales can be adapted. In addition, the combination of polling scheduling and weight priority can guarantee the fairness of the controllers and also take into account the real-time performance of high-priority tasks. Therefore, the technical problems of high latency and resource waste of an arbitration mechanism in processing large-scale queues can be solved, and the technical effects of reducing hardware overhead, reducing latency and improving resource utilization can be achieved.

Description

Technical Field

[0001] This application relates to the field of data storage technology, and in particular to methods, apparatus, media and products for data processing. Background Technology

[0002] Non-Volatile Memory Express (NVMe) is a high-performance, low-latency storage protocol designed for flash-based storage devices. For example, NVMe can be applied to solid-state drives (SSDs). In the NVMe protocol, command submission and completion status are implemented through queue pairs. The NVMe protocol supports multiple queue pairs, each capable of independently handling input / output requests, thus achieving parallel processing and high throughput.

[0003] Arbitration mechanisms in related technologies suffer from high latency and resource waste when dealing with large-scale queues. Summary of the Invention

[0004] This application provides methods, apparatus, media, and products for data processing to at least address the problems of high latency and resource waste in the related art when processing large-scale queues.

[0005] This application provides a method for data processing, comprising: creating an input / output queue, wherein the attributes of the input / output queue include a first attribute, based on which the controller to which each queue item in the input / output queue belongs, or whether a queue item is not assigned to a controller; traversing the input / output queue based on instructions for configuring queue items of each controller to determine the queue items assigned to each controller; if there are requests from multiple controllers, determining the target controller corresponding to the next request to be processed through round-robin scheduling; determining the queue item to be processed from the multiple queue items of the target controller based on the weight priority of each queue item; and performing data processing based on the attributes of the queue item to be processed.

[0006] This application also provides a computer device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described methods for data processing when executing the computer program.

[0007] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described methods for data processing.

[0008] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described methods for data processing.

[0009] This application assigns the same input / output queue to multiple controllers, with each controller exclusively controlling its assigned queue items. By having multiple controllers jointly allocate the same input / output queue, hardware overhead can be significantly reduced. Furthermore, it supports dynamic allocation of input / output queues among multiple controllers, adapting to system requirements of different scales. In addition, the combination of round-robin scheduling and weighted priority ensures fairness among controllers while also taking into account the real-time performance of high-priority tasks. Therefore, it can solve the technical problems of high latency and resource waste that exist in arbitration mechanisms when handling large-scale queues, achieving the technical effects of reducing hardware overhead, reducing latency, and improving resource utilization. Attached Figure Description

[0010] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This diagram illustrates the structure of a read submission queue command in related technologies.

[0012] Figure 2 This diagram illustrates the structure of a write-complete queue command in related technologies.

[0013] Figure 3 A flowchart illustrating the data processing method provided in this application is shown;

[0014] Figure 4 A schematic diagram of the structure of the controller description table of multiple controllers provided in this application is shown;

[0015] Figure 5 This paper illustrates an application scenario diagram of the command to retrieve the submission queue provided in this application;

[0016] Figure 6 This paper illustrates an application scenario diagram of the write completion queue completion command provided in this application;

[0017] Figure 7 A schematic diagram of the structure of the data processing apparatus provided in this application is shown;

[0018] Figure 8 A schematic diagram of the structure of the electronic device provided in this application is shown. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0020] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0021] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] The NVMe protocol includes two queue pairs: the submission queue and the completion queue. The submission queue (SQ) is used by the host to submit input / output (I / O) commands to the SSD controller. These I / O commands can be read or write. The host is the computing device running an operating system and applications, such as a server or a personal computer (PC). The completion queue (CQ) is used by the SSD controller to return the execution results of the commands to the host.

[0023] In SSD controller chip designs using the Peripheral Component Interconnect Express (PCIe) interface, the Physical Function (PF) controller or Virtual Function (VF) controller typically manages its own submission or completion queue independently, leading to low hardware resource utilization and poor scheduling efficiency. As SSD controller chip size increases, the number of submission and completion queues also increases, significantly raising hardware overhead and scheduling complexity. Especially in multi-controller environments, the efficiency of command scheduling and processing directly impacts SSD performance and response speed.

[0024] In related technologies, each controller exclusively occupies a fixed queue resource, such as a submit queue or a completion queue in the I / O queue, and each controller has an independent module for obtaining and processing commands. Figure 1 A schematic diagram of the structure of a read commit queue command in related technologies is shown. For example... Figure 1 As shown, the queue resources owned by the first controller 10 include the first controller's submission queue request retrieval sequence 101. The queue resources owned by the second controller 11 include the second controller's submission queue request retrieval sequence 111. The queue resources owned by the third controller 12 include the third controller's submission queue request retrieval sequence 121.

[0025] The first polling scheduling module 13 is used to obtain and perform polling scheduling based on the submission queue request acquisition sequence 101 of the first controller, the submission queue request acquisition sequence 111 of the second controller, and the submission queue request acquisition sequence 121 of the third controller.

[0026] The command prompt FIFO module 14 receives I / O commands from the submission queue request sequence and sends them to each weighted round-robin scheduling module. Specifically, it sends the submission queue request of the first controller to the first weighted round-robin scheduling module 15; the first weighted round-robin scheduling module 15 then sends the submission queue request of the first controller to the processing module 151 of the first controller for processing. The submission queue request of the second controller is sent to the second weighted round-robin scheduling module 16; the second weighted round-robin scheduling module 16 then sends the submission queue request of the second controller to the processing module 161 of the second controller for processing. The submission queue request of the third controller is sent to the third weighted round-robin scheduling module 17; the third weighted round-robin scheduling module 17 then sends the submission queue request of the third controller to the processing module 171 of the third controller for processing.

[0027] Figure 2 A schematic diagram of the write-complete queue command structure in related technologies is shown. For example... Figure 2 As shown, the command prompt completion module 20 obtains the first hardware completion queue 21, the first firmware completion queue 22, and the first direct storage access completion queue 23, and sends each completion queue to the first first-in-first-out module 24, the second first-in-first-out module 25, or the third first-in-first-out module 26 indicated by the controller identification information, according to the controller identification information in each completion queue.

[0028] The queue resources possessed by the first controller 10 also include the completion queue processing resources of the first controller. Based on the first FIFO module 24, the completion queue 241 of the target first controller is determined. The queue resources possessed by the second controller 11 also include the completion queue processing resources of the second controller. Based on the second FIFO module 25, the completion queue 251 of the target second controller is determined. The queue resources possessed by the third controller 12 also include the completion queue processing resources of the third controller. Based on the third FIFO module 26, the completion queue 261 of the target third controller is determined.

[0029] The completion queue write arbitrator 27 determines the write signal 271 in the completion queues 241, 251, and 261 of the first target controller, the second target controller, and the third target controller. The completion queue read arbitrator 28 determines the read signal 281 in the completion queues 241, 251, and 261 of the first target controller, the second target controller, and the third target controller.

[0030] The specific implementation is as follows: Each controller has its own independent I / O Submission Queue (SQ) and I / O Completion Queue (CQ), and these queue resources are not shared. The controller includes register resources such as a Doorbell register, CQ / SQ base addresses, and registers indicating whether the CQ / SQ are consecutive. The Doorbell register is used by the host to notify the controller that a new command has been submitted to the SQ, or that a completion status needs to be read from the CQ. Each controller is also equipped with an independent command acquisition module and a command processing module. The command acquisition module interacts with the host through the Doorbell register to read commands from the SQ. The command processing module performs preliminary analysis and verification of the read commands. Through analysis and verification, it determines whether the command conforms to the format specified by the protocol. If the command does not conform to the format specified by the protocol, it is placed in the hardware completion queue; if the command conforms to the format specified by the protocol, it is delivered to the software for processing.

[0031] The technical solutions in related technologies have the following problems:

[0032] First, having each controller exclusively control a fixed queue resource leads to low resource utilization. For example, the queue resources of some controllers may not be fully utilized, while the queue resources of other controllers may be insufficient. Because resources cannot be shared, hardware overhead is significant, especially in multi-controller environments, where redundant queue resource design increases chip area and power consumption.

[0033] Secondly, a controller may be unable to process a new command due to insufficient queue resources, while the queue resources of other controllers may be idle. Due to the lack of a resource sharing mechanism, the overall system scheduling efficiency is low, and hardware resources cannot be fully utilized.

[0034] Furthermore, queue resources are statically allocated during initialization and cannot be dynamically adjusted according to actual needs. For example, when the load on a controller increases, more queue resources cannot be dynamically allocated. Due to the lack of a dynamic resource allocation mechanism, the system cannot adapt to I / O requests of different scales, resulting in poor flexibility.

[0035] The specific application environment architecture or specific hardware architecture on which the execution of the methods used for data processing depends is described herein.

[0036] The data processing method provided in this application relies on a collaborative design of a multi-controller parallel architecture, two-layer arbitration hardware, and a shared input / output queue. It accelerates scheduling decisions through a hardware-level arbitrator and achieves efficient allocation using hardware encoding of queue attributes. It can be applied to scenarios requiring concurrent processing by multiple controllers and with clear requirements for scheduling fairness and priority, such as high-end storage systems, multi-core computing platforms, or high-speed network devices.

[0037] Embodiments of this application provide a method for data processing. Figure 3 A flowchart illustrating the data processing method provided in this application is shown, such as... Figure 3 As shown, the methods used for data processing include:

[0038] Step S301: Create an input / output queue, wherein the attributes of the input / output queue include a first attribute, which represents the controller to which each queue item in the input / output queue belongs, or whether the queue item has not been assigned to a controller.

[0039] In this step, the I / O queues of multiple controllers are merged, allowing multiple controllers to share a created input / output queue. Based on the created input / output queue, a shared resource pool is represented. The attributes of the input / output queue include queue item identification information, which can be used to distinguish different queue items by numbering the input / output queues.

[0040] Specifically, the input / output queue includes multiple queue items, such as the first queue item, the second queue item, ..., the Nth queue item. The first queue item can be a submission queue, and the second queue item can be a completion queue. The submission queue in the input / output queue can be represented by `local_sqn`, and the completion queue can be represented by `local_cqn`, where `n` can represent a number, such as 0, 1, or 2. The input / output queue can also include pairs of queues, such as the first queue pair, the second queue pair, ..., the Mth queue pair. The first queue pair includes a first queue item and a second queue item, where the first queue item can be a submission queue and the second queue item can be a completion queue. The submission queue number (sqn) is used to identify a specific submission queue. The completion queue number (cqn) is used to identify a specific completion queue.

[0041] In addition to the first attribute, the attributes of input / output queues also include the doorbell register, the base address of the submission queue, the base address of the completion queue, whether the submission queue is consecutive, and whether the completion queue is consecutive. If the value of the first attribute of a queue item is empty or NULL, it indicates that the queue item has not been assigned to a controller; if the value of the first attribute of a queue item is controller identification information, such as the controller identifier (controller_id), it indicates that the queue item has been assigned to the controller represented by the controller identifier.

[0042] Step S302: Based on the instructions for configuring queue items for each controller, traverse the input / output queues to determine the queue items assigned to each controller.

[0043] In this step, upon receiving a "Set Feature" command, the controller iterates through the first attributes of the input / output queues. The "Set Feature" command can be FID 07h from the NVMe protocol. If the first controller receives the "Set Feature" command, it iterates through the first attributes of the input / output queues. The first attribute of the first queue item in the input / output queue indicates that the first queue item has not yet been allocated. The identifier information of the first queue item can be written to the controller's controller description table until the number of queues specified by the "Set Feature" command is obtained, or until all queues in the input / output queues have been iterated through. The allocation status of the input / output queues is then sent to the host. The "Set Feature" command is used to configure the number, function, or attributes of the NVMe device's queues.

[0044] Step S303: If there are requests from multiple controllers, the target controller corresponding to the next request to be processed is determined by round-robin scheduling. Among the multiple queues of the target controller, the queue to be processed is determined based on the weight and priority of each queue. Data processing is performed based on the attributes of the queue to be processed.

[0045] In this step, if there are requests from multiple controllers, a round-robin (RR) scheduling algorithm can be used to select the target controller for request processing. Then, multiple submission queue requests within the target controller are arbitrated using a weighted round-robin (WRR) scheduling algorithm. Based on the weighted round-robin scheduling result, the target submission queue request for the read command operation is determined, and the corresponding data processing operation is performed based on the target submission queue request.

[0046] In this way, the same input / output queue is allocated to multiple controllers, with each controller having exclusive control over its assigned queue item. By having multiple controllers jointly allocate the same input / output queue, hardware overhead can be significantly reduced. By determining the target controller through polling scheduling and then processing queue items based on weighted priorities, the complex cross-queue scheduling judgments in related technologies are avoided, thus improving resource utilization. When multiple controllers request simultaneously, the polling mechanism allocates processing rights in sequence, and the weighted priorities ensure that high-priority tasks are executed first, thereby achieving resource optimization.

[0047] In some optional implementations, determining the queue items assigned to each controller by traversing the input / output queues based on the instructions for configuring queue items for each controller includes: after obtaining the instructions for configuring queue items for the target controller, traversing the first attribute of the input / output queues; if the first attribute indicates that the queue item is in a state of not being assigned to a controller, writing the identification information of the target controller into the first attribute of the queue item; if the first attribute indicates that the queue item has been assigned to another controller, traversing the next queue item based on the order of queue items in the input / output queues, until the number of queues specified by the instructions is obtained or the input / output queues have been traversed.

[0048] In this embodiment, when the host initializes the controller, configuration commands are sent via the admin queue to allocate input / output queue resources to the controller. The allocation of each queue item in the input / output queue can be determined by iterating through the values ​​of the first attribute. If the first attribute indicates that the queue item is not allocated, the identifier information of that queue item can be written into the controller description table of the controller to be initialized, establishing a mapping relationship between queue items in the input / output queue and the controller, until the number of requests in the admin queue is reached, or the input / output queue iteration is complete.

[0049] When adding a new controller, simply allocate an idle queue item from the input / output queue; no hardware architecture modification is required, enabling seamless expansion.

[0050] In this way, operations are performed only on unallocated queue items, avoiding duplicate allocation or invalid traversal; at the same time, unallocated queue items can be dynamically allocated to any controller, which can solve the problem of idle dedicated input / output queues in related technologies; in addition, the ability to modify the allocation strategy at runtime can improve the system's flexibility and scalability.

[0051] In some optional implementations, the aforementioned method for data processing further includes creating a controller description table: after determining the queue items allocated to each controller, establishing a correspondence between the allocated queue item identification information, the allocated controller identification information, and the controller request queue identification information; and characterizing the controller description table based on the correspondence.

[0052] In this implementation, a corresponding controller description table (QueueMap) and an allocated queue item count register can be created for each controller. Based on the allocated queue item count register, the identification information of the queue items allocated to the controller and the total number of queue items are recorded. The controller description table can store the identification information of queue items or the identification information of queue pairs.

[0053] Figure 4 A schematic diagram of the structure of the controller description table of the multiple controllers provided in this application is shown. Figure 4 The method for data processing in this application is illustrated using ten queue items and three controllers as an example. Figure 4 As shown, the input / output queue 400 includes the following queue entries: first queue item (local_sq0) 4001, second queue item (local_sq1) 4002, third queue item (local_sq2) 4003, fourth queue item (local_sq3) 4004, fifth queue item (local_sq4) 4005, sixth queue item (local_sq5) 4006, seventh queue item (local_sq6) 4007, eighth queue item (local_sq7) 4008, ninth queue item (local_sq8) 4009, and tenth queue item (local_sq9) 4010. The system includes a first controller, a second controller, and a third controller. The first controller can be controller0, the second controller can be controller1, and the third controller can be controller3.

[0054] The queue items assigned to the first controller include first queue item 4001, fourth queue item 4004, fifth queue item 4005, sixth queue item 4006, and seventh queue item 4007. The queue items assigned to the second controller include second queue item 4002 and third queue item 4003.

[0055] In response to the configuration and management command issued by the host to the third controller, the third controller traverses the first attributes of the input / output queues 400. The first attributes of queue items 4001 to 4007 all indicate that the queue items have been assigned to the controller. The first attribute of queue item 4008 indicates that queue item 4008 has not been assigned and can be assigned to the third controller. Similarly, the first attributes of queue items 4009 and 4010 indicate that queue items 4009 and 4010 have not been assigned and can be assigned to the third controller.

[0056] The first controller includes a first controller first request (sq1) 4021, a first controller second request (sq2) 4022, a first controller third request (sq3) 4023, a first controller fourth request (sq4) 4024, and a first controller fifth request (sq5) 4025. The second controller includes a second controller first request 4031 and a second controller second request 4032. The third controller includes a third controller first request 4041, a third controller second request 4042, and a third controller third request 4043.

[0057] The controller description table 402 of the first controller includes the correspondence between the first queue item 4001 and the first request 4021 of the first controller; and the correspondence between the fourth queue item 4004 and the second request 4022 of the first controller. The controller description tables 403 and 404 of the second and third controllers are as follows: Figure 4 As shown, details will not be elaborated here. Input / output queue 400 can be either a submission queue or a completion queue. Both the submission queue and the completion queue can have their controller description tables created using the methods described above.

[0058] In this way, by supporting bidirectional queries between controller identifier and queue item identifier, or between queue item identifier and controller identifier, through the controller description table, repeated traversal of the global queue can be avoided, significantly reducing scheduling latency. At the same time, it is convenient to monitor the load status of each controller in real time, providing data support for dynamic load balancing. In addition, by managing the allocation relationship through a unified description table, there is no need to maintain queue item allocation information independently in each controller, which can reduce memory consumption and data synchronization overhead, and further reduce hardware costs.

[0059] In some optional implementations, the attributes of queue items in the input / output queues also include the doorbell register address, and the aforementioned data processing method further includes: determining the address offset of the doorbell register based on the difference between the base address and the doorbell register address; determining the queue item index offset corresponding to the address offset based on the address offset; determining the queue item index based on the queue item index offset; and establishing a mapping relationship between the doorbell register address and the queue item identification information based on the controller description table and the queue item index.

[0060] In this embodiment, the mapping relationship between the doorbell register address and the identifiers of each queue item in the input / output queue can be represented in the following way;

[0061] Map[(address - base address of the doorbell register) / 8 - 1]

[0062] The doorbell register address can be allocated based on the NVMe protocol; the base address of the doorbell register can be determined based on the different types of doorbell registers, for example, it could be 0x1000 or 0x1004. Dividing the address offset by 8 indicates that each doorbell register occupies eight bytes of address space. Subtracting one converts the queue item index to start from 0.

[0063] The mapping between sequence numbers and serial numbers in the submission queue of each controller's input / output queue on the host side is: Map[sqn-1]. The mapping between sequence numbers and serial numbers in the completion queue is: Map[cqn-1]. Map is used to represent the controller description table.

[0064] When submitting or completing a queue request, if the queue index needs to be submitted or completed, the above mapping relationship can be used to obtain the identification information of the queue items in the input and output queues, and then obtain the configuration information of the queue items, thereby completing the corresponding submit or complete queue request.

[0065] In this way, resources can be located directly through simple mathematical calculations without the need for traversal searches; at the same time, queue information can be obtained with a single address calculation, avoiding multi-level pointer references; in addition, linear address mapping is highly compatible with the NVMe controller hardware implementation, which can accelerate command processing.

[0066] In some optional implementations, the aforementioned method for data processing further includes determining whether a controller request exists: if the head pointer and tail pointer of a queue item point to different positions, and the first attribute of the queue item indicates that the queue item has been assigned to the target controller, it is determined that a request exists from the target controller.

[0067] In this embodiment, it can be determined whether the controller corresponding to a queue item has a command read request based on the head and tail pointers and the value of the first attribute of the queue item in the controller descriptor. For example, if the head and tail pointer attributes of the queue item numbered local_sq1 are not equal, and the value of the first attribute of the queue item is 1, it indicates that the queue item has been assigned to the first controller, and the first controller currently has a read command request.

[0068] Specifically, read request signals for the controller can be generated using the controller descriptor and the head and tail pointers of the queue items. For example, if the head and tail pointers of the second queue item 4002 corresponding to the 0th position of the controller descriptor of the second controller (controller1) are not equal, it indicates that the second controller's first request 4031 has a read request. According to the above rules, if each controller may have a maximum of ten request signals, the total maximum number of request signals is 3*10.

[0069] In this way, by verifying both pointer state and attribute flags, misjudgments of controller requests can be avoided; at the same time, each controller only checks the requests assigned to it and will not interfere with other controllers. If a controller fails, it will not affect the system's processing of requests from other controllers.

[0070] In some optional implementations, if there are requests from multiple controllers, the target controller corresponding to the next request to be processed is determined by round-robin scheduling. Among the multiple queues of the target controller, the queue to be processed is determined based on the weight priority of each queue. This includes: after determining the target controller, determining the queue to be processed based on the number of queues allocated to the target controller, the weight priority of each queue in the target controller, and the requests in each queue.

[0071] In this implementation, when multiple controllers have requests, a round-robin scheduling algorithm (RR) can be used to obtain the round-robin scheduling result and determine the target controller for command reading. The number of queue items allocated to the target controller, the weight and priority of each queue item in the target controller, and the requests in the queue items can be passed to the weighted round-robin scheduling arbitration module. The weighted round-robin scheduling arbitration module is set up to arbitrate based on NVMe protocol requirements and the weight and priority of queue items, thereby determining the request to execute the read command operation and the number of read commands.

[0072] To handle the maximum number of arbitration requests, the weighted round-robin scheduling arbitration module should be able to process the maximum number of arbitration requests. In the case of sequential logic arbitration, methods in related technologies require consuming a maximum number of clock cycles of queues to traverse all requests. Since the number of queues for each controller is dynamically changing—for example, the first controller might have 250 requests while the second controller only has 6—methods in related technologies lead to a large amount of meaningless traversal.

[0073] In this way, based on the polling scheduling results obtained by RR, the number of queue items allocated to the target controller is transmitted to the weighted polling scheduling arbitration module. If the number of requests traversed by the weighted polling scheduling arbitration module reaches the number of queue items allocated to the target controller, the requests are traversed again from the lower sequence number, reducing the time spent traversing meaningless requests and thus reducing arbitration latency.

[0074] In some optional implementations, after determining the target controller, the queue item to be processed is determined based on the number of queue items allocated to the target controller, the weight and priority of each queue item in the target controller, and the requests in each queue item. This includes: based on the number of queue items, traversing the queue items of the target controller to determine whether there are any requests in the queue items of the target controller; and in the queue items where there are requests, determining the queue item to be processed based on the maximum number of requests to be acquired by the target controller, the amount of free space in the first first-in-first-out cache, and the number of commands to be processed in the queue item.

[0075] In this embodiment, Figure 5 This paper illustrates an application scenario diagram of the retrieval and submission queue command provided in this application, such as... Figure 5 As shown, when a controller submits a queue read request, for example, if there are a first controller submitting a queue request 5011, a second controller submitting a queue request 5012, and a third controller submitting a queue request 5013, the polling scheduling module 501 first determines which controller's request signal to process.

[0076] After determining the selected target controller, target controller information 5017 is obtained from multiple controller information sources. This information includes the number of queue items assigned to the target controller, the weight and priority of each queue item in the target controller, and the requests in each queue item. Each controller information source includes the number of assigned queue items, the weight and priority of each queue item in the target controller, and the requests in each queue item. The multiple controller information sources include first controller information 5014, second controller information 5015, and third controller information 5016.

[0077] The acquired target controller information is transmitted to the weighted round-robin scheduling module 502. The weighted round-robin scheduling module 502, based on the number of queue items allocated to the target controller, traverses each submission queue of the target controller, determines whether there is a read request signal, and performs weighted round-robin scheduling arbitration. At the same time, based on the target controller's maximum request acquisition quantity (arbitration burst, ab), the amount of free space in the first first-in-first-out cache 503, and the number of commands to be processed in the queue items, it determines the weighted round-robin scheduling result 5021, which is the number of commands that should be read in this weighted round-robin scheduling arbitration.

[0078] Then, the target controller's identification information, the request (sqn) in the target controller, the queue item (local_sqn) allocated in the target controller, and the number of commands to be read in this weighted round-robin scheduling arbitration are stored in the first FIFO cache 503. The weight consumption of each queue item in the target controller is updated in the target controller's weighted round-robin scheduling weight register. At the same time, the pseudo-head pointer 504 is updated to prevent the value of the head pointer that has participated in the arbitration from being reused. The pseudo-head pointer is used to represent the head pointer of the actual command that has not yet been read from the host memory. It should be noted that round-robin scheduling can only be performed if there is free space in the first FIFO cache 503, that is, if the first FIFO cache 503 is not full, so that the round-robin scheduling arbitration result can be saved.

[0079] In this way, by first checking whether a request exists in the queue and skipping the processing of empty queues, invalid processing can be avoided; at the same time, the processing volume can be dynamically adjusted based on the free space of the cache to prevent request loss caused by cache overflow and ensure the reliability of data processing.

[0080] In some optional implementations, data processing based on the attributes of the queue items being processed includes: obtaining attribute information of the queue items based on the queue item identification information in the queue items being processed; reading command information from the host memory based on the attribute information; and storing the command information, the target controller identification information, and the queue item identification information being processed into a second first-in-first-out cache.

[0081] In this embodiment, such as Figure 5As shown, the command acquisition module 507 is used to read command information from the host memory. Based on the value of the processing queue item (local_sqn) obtained from the first first-in-first-out cache 503, the command acquisition module 507 determines the attribute information of the processing queue item (local_sqn), that is, in the attribute information of the first queue item 505, the second queue item 505, ... the tenth queue item 506, the target queue item attribute information 5031 is determined. Based on the target queue item attribute information 5031, the base address, size, whether it is continuous, head pointer and tail pointer and other information of the corresponding submission queue (SQ) are obtained. Then, the command acquisition module 507 reads the command information from the specified location in the host memory according to this information. After the command information is read, the head pointer 512 is updated. The update of the head pointer indicates that the command has been read from the host. The read command information, the identification information of the target controller and the identification information of the processing queue item are stored in the second first-in-first-out cache 508.

[0082] When the number of command messages read reaches the number indicated by the first first-in-first-out buffer 503, update the output value of the first first-in-first-out buffer 503 to proceed with reading the next commit queue (SQ) command.

[0083] The processor module 509 reads commands from the second first-in-first-out cache 508 and performs operations such as command format checks. Based on the command type, it stores the command in the firmware read queue 510, or places the command processing result in the hardware completion queue 511. The firmware read queue (FWRQ) 510 stores commands for firmware read operations. Firmware refers to the software running on the solid-state drive controller, responsible for managing hardware resources and executing commands submitted by the host.

[0084] In this way, attribute information can be obtained based on queue item identification information, and the unique identifier can be used to directly locate the attributes of queue items, avoiding traversing the entire data and reducing retrieval time overhead; at the same time, command information in host memory can be read in a targeted manner based on attribute information, avoiding invalid memory addressing.

[0085] In some optional implementations, the aforementioned method for data processing further includes: if there are hardware completion queue requests, firmware completion queue requests, and direct memory access requests, performing polling scheduling based on the hardware completion queue request, the controller request queue identifier information corresponding to the hardware completion queue request, the firmware completion queue request, the controller request queue identifier information corresponding to the firmware completion queue request, the direct memory access request, and the controller request queue identifier information corresponding to the direct memory access request to determine the target controller; determining the target queue item identifier information based on the target controller and the controller description table of the target controller; and obtaining the attribute information corresponding to the target queue item identifier information based on the target queue item identifier information and performing data writing processing.

[0086] In this embodiment, Figure 6 This paper illustrates an application scenario of the write completion queue completion command provided in this application, such as... Figure 6 As shown, when executing the write completion queue completion command, the instruction completion module 601 performs preprocessing based on the information obtained in the hardware completion queue 511, firmware completion queue 603, and direct memory access completion queue 604. According to the controller identification information in each hardware completion queue 511, firmware completion queue 603, and direct memory access completion queue 604, it sends each completion queue to the third first-in-first-out buffer 605, the fourth first-in-first-out buffer 606, or the fifth first-in-first-out buffer 607 indicated by the controller identification information.

[0087] The polling arbitrator 608, based on the contents of the third FIFO buffer 605, the fourth FIFO buffer 606, and the fifth FIFO buffer 607, performs polling scheduling arbitration to determine the target controller 609 to perform the sending operation. The completion command sending module 610 is used to place the completion command into the completion queue specified by the host.

[0088] The mapping module 611, based on the identification information of the target controller 609, the completion queue identifier (cqn), and the controller description table of the target controller, obtains the value of the target queue item (local_cqn), i.e., the target queue item attribute information 5031, from the attribute information of the first queue item 505, the attribute information of the second queue item, ..., the attribute information of the tenth queue item 506. Then, it obtains the attribute information such as the base address, size, whether it is continuous, head pointer, and tail pointer of the completion queue to be written. The completion command sending module 610 writes the aforementioned attribute information into the completion queue (CQ) based on the write enable module 613 or the read enable module 614.

[0089] In this way, by integrating hardware-completed queue requests, firmware-completed queue requests, and direct memory access requests, and employing a round-robin scheduling algorithm to determine the target controller, we can avoid a single queue from occupying resources for a long time and achieve fair scheduling of different types of requests. Simultaneously, storing the completion queue commands and requests from different controllers in independent First-In-First-Out (FIFO) caches (such as the third to fifth FIFO caches) can prevent request interference between controllers. Furthermore, the independent FIFO cache design provides inherent fault isolation capabilities. If a controller malfunctions, only its corresponding cache is affected, without impacting other controllers.

[0090] In some optional implementations, the aforementioned method for data processing further includes configuring a controller weight information register and recording the controller's arbitration weight information based on the controller weight information register.

[0091] In this implementation, since only one weighted round-robin arbitrator (WRR arbitrator) is used, and the arbitration configuration and consumption of each controller are different, a weight information register can be set up for each controller to record the arbitration weight consumption of each controller. After obtaining the preliminary RR arbitration result, the weight consumption of the WRR arbitrator is dynamically configured to ensure that the WRR arbitration weight of each controller is correct. The weight information register is updated after each arbitration is completed to prevent weight information loss.

[0092] In this way, the weights are dynamically updated based on the real-time arbitration consumption of the controller, achieving adaptive scheduling. At the same time, a single WRR arbitrator combined with the weight information register improves efficiency while ensuring scheduling fairness. Compared with static polling, weighted polling can allocate time slices according to the actual processing capacity of the controller. In addition, the independent configuration of the weight information register ensures that anomalies in a single controller will not affect other controllers.

[0093] In some optional implementations, the aforementioned method for data processing further includes: after polling scheduling, writing the target controller's identification information, the queue items allocated by the target controller, the target controller's request queue, and the number of commands into a first first-in-first-out cache; and updating the head pointer of the queue items to be processed.

[0094] In this embodiment, after the target controller is determined by polling and scheduling, the target controller's identification information, the queue items allocated to the target controller, the target controller's request queue, and the number of commands are extracted, and the extracted information is written into the first first-in-first-out cache. Then, the head pointer is updated, that is, the pseudo-head pointer 504 is updated, so that the value of the head pointer that has participated in arbitration is not reused. The pseudo-head pointer is used to represent the head pointer that the actual command has not yet been read from the host memory.

[0095] In this way, the first FIFO buffer acts as an intermediate buffer between the scheduling module and the execution module, decoupling the polling scheduling from the actual processing logic. For example, the scheduling module can continue to the next round of scheduling without waiting for the current command to complete. The execution module can process commands continuously according to the cache order, reducing the time overhead of waiting for scheduling. This mode improves the system's concurrent processing capability, especially under high-load scenarios.

[0096] In some alternative implementations, the aforementioned method for data processing further includes, after determining the queue item to be processed, storing the attributes of the queue item to be processed based on a second first-in-first-out cache.

[0097] In this embodiment, the target controller sends a host read request through the command acquisition module 507 based on the arbitration result, and stores the read command information, the target controller's identification information, and the identification information of the processed queue item into the second first-in-first-out cache 508. Since there is a delay in reading the command, this delay may be greater than the arbitration speed. If arbitration is performed after data reading is completed, a waiting period for the arbitration result will occur. Therefore, adding a second first-in-first-out module 508 between the arbitration and command acquisition modules to cache the arbitration result can reduce latency.

[0098] The data processing method provided in this application can be applied to data transmission systems based on the high-speed serial computer extended bus standard (peripheral component interconnect express, or PCIe) interface and conforming to the NVMe protocol.

[0099] The data processing method provided in this application addresses the issue of non-shared queue resources and redundant logical functions among multiple controllers. It establishes a queue resource pool (input / output queues) and uses a controller description table to map physical queue resources to controller logical queues, thereby enabling queue sharing among controllers. Furthermore, based on the changing characteristics of the number of controller queues, the arbitration method is optimized to shorten the arbitration cycle and improve arbitration efficiency. A FIFO mechanism is also introduced to further enhance arbitration efficiency and reduce command retrieval latency.

[0100] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0101] Embodiments of this application also provide an apparatus for data processing. Figure 7 A schematic diagram of the structure of the data processing apparatus provided in this application is shown, such as... Figure 7As shown, the apparatus for data processing includes:

[0102] Shared module 701 is used to create input / output queues, wherein the attributes of the input / output queues include a first attribute, which represents the controller to which each queue item in the input / output queue belongs, or whether the queue item is not assigned to a controller.

[0103] The configuration module 702 is used to traverse the input and output queues based on the instructions for configuring the queue items of each controller, and determine the queue items to be allocated to each controller.

[0104] The processing module 703 is used to determine the target controller corresponding to the next request to be processed by polling and scheduling if there are requests from multiple controllers. Among the multiple queue items of the target controller, the processing queue item is determined based on the weight and priority of each queue item. Data processing is performed based on the attributes of the processing queue item.

[0105] In some alternative implementations, configuration module 702 includes:

[0106] The first unit of the configuration module is used to obtain the instruction for configuring the queue items of the target controller, and then traverse the first attribute of the input and output queues. If the first attribute indicates that the queue item is not assigned to a controller, the identification information of the target controller is written into the first attribute of the queue item. If the first attribute indicates that the queue item has been assigned to another controller, the next queue item is traversed based on the order of the queue items in the input and output queues until the number of queues specified by the instruction is obtained or the input and output queues have been traversed.

[0107] In some alternative embodiments, the aforementioned data processing apparatus further includes:

[0108] The first module is used to create a controller description table. After determining the queue items assigned to each controller, it establishes a correspondence between the assigned queue item identification information, the assigned controller identification information, and the controller request queue identification information; based on the correspondence, it characterizes the controller description table.

[0109] In some alternative embodiments, the aforementioned data processing apparatus further includes:

[0110] The second module is used to determine the address offset of the doorbell register based on the difference between the base address and the address of the doorbell register; determine the queue item index offset corresponding to the address offset; determine the queue item index based on the queue item index offset; and establish a mapping relationship between the doorbell register address and the queue item identification information based on the controller description table and the queue item index.

[0111] In some alternative embodiments, the aforementioned data processing apparatus further includes:

[0112] The third module is used to determine whether a request from the controller exists: if the head pointer and tail pointer of the queue item point to different positions, and the first attribute of the queue item indicates that the queue item has been assigned to the target controller, it is determined that a request from the target controller exists.

[0113] In some alternative implementations, the processing module 703 includes:

[0114] The first unit of the processing module is used to determine the queue items to be processed after determining the target controller, based on the number of queue items allocated to the target controller, the weight and priority of each queue item in the target controller, and the requests in each queue item.

[0115] In some optional implementations, the first processing module includes:

[0116] The first subunit of the processing module is used to traverse the queues of the target controller based on the number of queue items, and determine whether there are any requests in the queues of the target controller; in the queues where there are requests, the queue item to be processed is determined based on the maximum number of requests that the target controller can obtain, the amount of free space in the first first-in-first-out cache, and the number of commands to be processed in the queue item.

[0117] In some alternative implementations, the processing module 703 further includes:

[0118] The second processing module is used to obtain the attribute information of the queue item based on the queue item identification information in the queue item being processed; read the command information from the host memory based on the attribute information; and store the command information, the target controller identification information, and the queue item identification information being processed into the second first-in-first-out cache.

[0119] In some alternative embodiments, the aforementioned data processing apparatus further includes:

[0120] The fourth module is used to perform polling scheduling to determine the target controller if there are hardware completion queue requests, firmware completion queue requests, and direct memory access requests. Based on the hardware completion queue request, the controller request queue identifier information corresponding to the hardware completion queue request, the firmware completion queue request, the controller request queue identifier information corresponding to the firmware completion queue request, the direct memory access request, and the controller request queue identifier information corresponding to the direct memory access request, the module determines the target queue item identifier information based on the target controller and the target controller's controller description table. Based on the target queue item identifier information, the module obtains the attribute information corresponding to the target queue item identifier information and performs data writing processing.

[0121] In some alternative embodiments, the aforementioned data processing apparatus further includes:

[0122] The fifth module is used to configure the controller weight information register and record the arbitration weight information of the controller based on the controller weight information register.

[0123] In some alternative embodiments, the aforementioned data processing apparatus further includes:

[0124] The sixth module is used to write the target controller's identification information, the queue items allocated to the target controller, the target controller's request queue, and the number of commands into the first first-in-first-out cache after polling scheduling; and to update the head pointer of the queue items to be processed.

[0125] In some alternative embodiments, the aforementioned data processing apparatus further includes:

[0126] The seventh module is used to store the attributes of the queue items to be processed based on the second first-in-first-out cache after determining the queue items to be processed.

[0127] For a description of the features in the embodiment of the apparatus for data processing, please refer to the relevant description of the embodiment of the method for data processing, which will not be repeated here.

[0128] Embodiments of this application also provide an electronic device. Figure 8 A schematic diagram of the structure of the electronic device provided in this application is shown, such as... Figure 8 As shown, it includes a processor 81 and a memory 82, in which a computer program is stored, and the processor 81 is configured to run the computer program to perform the steps in any of the above-described method embodiments for data processing.

[0129] The electronic device also includes an input device 83 and an output device 84. The processor 81, memory 82, input device 83, and output device 84 can be connected via a bus or other means. Figure 8 Taking the example of a connection between China and Israel via a bus.

[0130] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described methods for data processing at runtime.

[0131] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0132] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described methods for data processing.

[0133] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in any of the above-described methods for data processing.

[0134] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0135] The foregoing has provided a detailed description of a method, apparatus, medium, and product for data processing provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for data processing, characterized in that, include: Create an input / output queue, wherein the attributes of the input / output queue include a first attribute, based on the first attribute, representing the controller to which each queue item in the input / output queue belongs, or whether the queue item is not assigned to a controller; After obtaining the instruction to configure the queue items of the target controller, the first attribute of the input / output queue is traversed; If the first attribute indicates that the queue item is in a state where it has not been assigned to a controller, the identification information of the target controller is written into the first attribute of the queue item; If the first attribute indicates that the queue item has been assigned to another controller, based on the order of the queue items in the input / output queue, traverse the next queue item until the number of queues specified by the instruction is obtained or the input / output queue has been traversed. If there are requests from multiple controllers, the target controller corresponding to the next request to be processed is determined by round-robin scheduling. Among the multiple queues of the target controller, the queue to be processed is determined based on the weight priority of each queue. Based on the queue item identifier information in the processed queue item, the attribute information of the queue item is obtained; Based on the attribute information, read command information from the host memory; The command information, the identification information of the target controller, and the identification information of the queue item being processed are stored in a second first-in-first-out cache. Configure the controller weight information register, and record the arbitration weight information of the controller based on the controller weight information register; After the polling scheduling, the identification information of the target controller, the queue items allocated to the target controller, the request queue of the target controller, and the number of commands are written into the first first-in-first-out cache; Update the head pointer of the queue item being processed; After determining the queue item to be processed, the attributes of the queue item to be processed are stored based on the second first-in-first-out cache.

2. The method for data processing according to claim 1, characterized in that, The method also includes creating a controller description table: After determining the queue items assigned to each controller, a correspondence is established between the assigned queue item identifier information, the assigned controller identifier information, and the controller request queue identifier information; Based on the aforementioned correspondence, the controller description table is characterized.

3. The method for data processing according to claim 2, characterized in that, The attributes of the queue items in the input / output queue also include the doorbell register address, and the method further includes: The address offset of the doorbell register is determined based on the difference between the base address of the doorbell register and the address of the doorbell register. Based on the address offset, determine the queue item index offset corresponding to the address offset; The queue item index is determined based on the queue item index offset; Based on the controller description table and the queue item index, a mapping relationship is established between the doorbell register address and the queue item identification information.

4. The method for data processing according to claim 1, characterized in that, The method further includes determining whether a request from the controller exists: If the head pointer and the tail pointer of the queue item point to different positions, and the first attribute of the queue item indicates that the queue item has been assigned to the target controller, it is determined that the target controller has the request.

5. The method for data processing according to claim 1, characterized in that, If there are requests from multiple controllers, the target controller corresponding to the next request to be processed is determined by round-robin scheduling. Among the multiple queues of the target controller, the queues to be processed are determined based on the weight priority of each queue. After determining the target controller, the queue item to be processed is determined based on the number of queue items allocated to the target controller, the weight priority of each queue item in the target controller, and the requests in each queue item.

6. The method for data processing according to claim 5, characterized in that, After determining the target controller, the queue items to be processed are determined based on the number of queue items allocated to the target controller, the weight priority of each queue item in the target controller, and the requests in each queue item: Based on the number of queue items, traverse the queue items of the target controller and determine whether there is a request in the queue items of the target controller; In the queue of the requested items, the queue to be processed is determined based on the maximum number of requests retrieved by the target controller, the amount of free space in the first first-in-first-out cache, and the number of commands to be processed in the queue.

7. The method for data processing according to claim 1, characterized in that, Also includes: If there are hardware completion queue requests, firmware completion queue requests, and direct memory access requests, the polling scheduling is performed based on the hardware completion queue request, the controller request queue identifier information corresponding to the hardware completion queue request, the firmware completion queue request, the controller request queue identifier information corresponding to the firmware completion request, the direct memory access request, and the controller request queue identifier information corresponding to the direct memory access request to determine the target controller. Based on the target controller and the controller description table of the target controller, determine the target queue item identification information; Based on the target queue item identification information, obtain the attribute information corresponding to the target queue item identification information, and perform data writing processing.

8. A computer device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the method for data processing as described in any one of claims 1 to 7 when executing the computer program.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method for data processing as described in any one of claims 1 to 7.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method for data processing as described in any one of claims 1 to 7.

Images