Data sequence number remapping method, electronic device and storage medium

By establishing a mapping relationship between Rtagi and Ctagi in collaborative simulation, the data serial number mismatch problem between cmodel and RTL is solved, the fallback logic in the verification process is simplified, and the development cycle is shortened.

CN120387409BActive Publication Date: 2025-09-19METAX INTEGRATED CIRCUITS (SHANGHAI) CO LTD
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Patent Information

Application Number
CN202510886958.3
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2025-06-27
Publication Date
2025-09-19
Estimated Expiration
2045-06-27

AI Technical Summary

Technical Problem

In co-simulation, due to the mismatch between the data sequence number tags of the cmodel and RTL, a large amount of additional logic overhead is required during the verification process to recycle and reuse the tags, resulting in a long development cycle.

Method used

By constructing the storage structure strck, a one-to-one mapping relationship between Rtagi and Ctagi is established, and Ctagi is replaced with Rtagi to achieve remapping of the data sequence number. The data sequence number is retrieved through the index to avoid the fallback logic caused by the data sequence number not being returned.

Benefits of technology

It simplifies the management of fallback logic during the verification process, shortens the development cycle, and saves time in processing fallback logic.

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Abstract

The present invention relates to the field of chip design technology, and in particular to a data sequence number remapping method, electronic device and storage medium, which uses the data sequence number Rtag bound to the i-th data sent by the second verification module to remap the data sequence number Rtag. i The data sequence number Ctag bound to the i-th data sent by the first verification module i Remapping: Build a storage structure to store Rtag i As a unique index identifier, Ctag i Store it in the storage structure as associated data and establish a mapping relationship; i Replaced by Rtag i , get the updated data, make the verification environment pass the verification based on the updated data; the verification environment returns Cdata to the first verification module i ´ response data, with Rtag i As the address index strc k Ctags saved in i Remove and Ctag i Returning to the first verification module avoids fallback logic problems and shortens the development cycle.
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Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a data sequence number remapping method, electronic equipment, and storage medium. Background Art

[0002] In co-simulation, complex hardware and software system design verification allows different simulation tools or models to work together. For example, a cmodel (software model) and RTL (Register-Transfer Level) can run together in the same simulation environment to jointly verify the system.

[0003] In the system simulation mechanism, each group of output interfaces I1-In has a corresponding data sequence number (tag) t1-tn. Tags have no practical meaning and are used only for recycling. For example, an interface issues a read or write request, which is associated with a tag. When the verification platform receives this read or write request, although the data is sent in order, it is returned out of order. When the data is returned, the tag is used to determine which request the interface issued corresponds to. The returned tag can be reused. During co-simulation, the tags of the cmodel and RTL must be exactly the same, meaning that the data in both must be the same. However, in complex scenarios, some anomalies may occur, resulting in different tags. For example, if the cmodel runs faster than the RTL, the cmodel may send more tags than the RTL, or if the hardware experiences an interrupt or reboot, the tags may not match, resulting in an error. Unused tags need to be recycled, and the code needs to be rolled back to the same tag location to restart verification. This requires a significant amount of additional logic overhead for both the cmodel and RTL to recycle tags. However, during the verification process, there are tens of thousands of data points, and tags are constantly recycled and reused. The rollback logic is quite complex, and each rollback can take two weeks or even longer, resulting in long development cycles. Therefore, a method is urgently needed to avoid the need to handle rollback logic due to unreturned tags. Summary of the Invention

[0004] In order to solve the above technical problems, the present invention adopts a technical solution: a data sequence number remapping method, which includes the following steps:

[0005] S100, the verification platform receives the data sent by the first verification module and stores it in the cache. When it receives the kth interface interface of the second verification module, k The i-th data Rdata sent iWhen the kth interface of the first verification module stored in the cache is searched, k The i-th data sent Cdata i .

[0006] S200, compared to Rdata i and Cdata i Are the data parts in the same? If they are the same, get Rdata i Bound data serial number Rtag i and Cdata i Bound data serial number Ctag i , and Rtag i and Ctag i Remapping is performed, wherein the remapping step comprises:

[0007] S210, build a storage structure strc k , Rtag i As a unique index identifier, Ctag i Stored as associated data in the strc k In the Rtag i For index, Ctag i A one-to-one mapping of associated values.

[0008] S220, Cdata i Bound data serial number Ctag i Replaced by Rtag i , get the updated Cdata i ´, so that the verification environment can be used for Rdata i and Cdata i Verification passed.

[0009] S230, the verification environment returns Cdata to the first verification module i ´ response data, with Rtag i As the address index strc k Ctags saved in i Take out and put the Ctag i Return to the first verification module.

[0010] In addition, the present invention also provides a non-transitory computer-readable storage medium, which stores at least one instruction or at least one program, and the at least one instruction or at least one program is loaded and executed by a processor to implement the above method.

[0011] In addition, the present invention also provides an electronic device including a processor and the above-mentioned non-transitory computer-readable storage medium.

[0012] The present invention has at least the following beneficial effects:

[0013] The present invention provides a data sequence number remapping method, electronic device and storage medium, which cleverly establish a mapping relationship between data sequence numbers through remapping and return the data sequence number through index retrieval to resolve the problem of data return. Compared with the existing technology, it is no longer required that the data sequence numbers must be exactly the same, and the data sequence number is no longer a condition for judging whether the verification is passed or not. Whether the data sequence number is returned or recycled will not affect the verification result. Therefore, it avoids the problem of needing to process fallback logic due to the failure of the data sequence number to be returned, saves a lot of time for processing fallback logic, and shortens the development cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 A flow chart of a data sequence number remapping method provided by an embodiment of the present invention;

[0016] Figure 2 A flowchart of the remapping steps provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0018] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present invention have the same meanings as commonly understood by those skilled in the art.

[0019] See also Figure 1 , which shows a flow chart of a data sequence number remapping method, the method comprising the following steps:

[0020] S100, the verification platform receives the data sent by the first verification module and stores it in the cache. When it receives the kth interface interface of the second verification module, kThe i-th data Rdata sent i When the kth interface of the first verification module stored in the cache is searched, k The i-th data sent Cdata i .

[0021] In one embodiment, the verification platform is a cosim verification platform that can combine different simulation environments to achieve collaborative simulation and testing between software and hardware. Other types of verification platforms that can combine two different verification platforms fall within the scope of protection of the present invention.

[0022] The first verification module and the second verification module are both models of the same chip to be tested. Therefore, the kth interface interface of the first verification module k and the kth interface of the second verification module k The interface number configuration and the data sent are the same.

[0023] In one embodiment, the second verification module is an RTL (Register Transfer Level model) or a VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language model). Other types of register transfer level verification modules fall within the scope of protection of the present invention.

[0024] In one embodiment, the first verification module is a Cmodel model, a SystemC model, a Python model, or a gate-level netlist verification model, etc. Other types of verification models also fall within the protection scope of the present invention.

[0025] When the second verification module is RTL or VHDL, the first verification module can be any one of a Cmodel model, a SystemC model, a Python model, or a gate-level netlist verification model. It should be noted that, in another embodiment, the second verification module is a Cmodel model, a SystemC model, a Python model, or a gate-level netlist verification model, and the first verification module is RTL or VHDL.

[0026] In one embodiment, Rdata i For read request data or write request data. Similarly, Cdata i Read request data or write request data.

[0027] In one embodiment, the cache is a first-in first-out (FIFO) queue.

[0028] S200, compared to Rdata i and Cdata i Are the data parts in the same? If they are the same, get Rdata i Bound data serial number Rtag i and Cdata i Bound data serial number Ctag i , and Rtag i and Ctag i Perform remapping.

[0029] Among them, when the data part is different, the verification platform will directly report an error. This error is caused by the actual difference in the data part. It is a real error and has nothing to do with the data sequence number.

[0030] It should be noted that the data sequence number is only used to identify the data that the current data is the number of data sent by the current interface, rather than the data part itself. Therefore, when comparing data, the data itself should be compared, rather than the data sequence number. Whether the data sequence number matches has no practical significance. Therefore, when the data part is the same, it has actually been verified. However, in order to match the verification mechanism of the verification platform and the correct return logic of the data, remapping is required.

[0031] Further, please combine Figure 2 , Figure 2 The remapping steps are shown, which include:

[0032] S210, build a storage structure strc k , Rtag i As a unique index identifier, Ctag i Stored as associated data in the strc k In the Rtag i For index, Ctag i A one-to-one mapping of associated values.

[0033] In one embodiment, the first verification module includes multiple interfaces, and a storage structure is configured for each interface. It should be noted that the data sequence number of each interface is independent, and there is no relationship between the data sequence numbers of different interfaces. Accordingly, the storage structure of each interface is also independent.

[0034] The storage structure includes an associative array or two lists, and other storage structures that establish mapping relationships also fall within the protection scope of the present invention.

[0035] In one embodiment, strc in S210 k is an associative array, where Rtag i For array index, Ctag i Store in associative array strc k [Rtag i ]middle.

[0036] Among them, an associative array, also known as a dictionary or hash table, is a data structure that can associate keys and values, allowing strings or other complex data types to be used as array indexes. i As the address index, Ctag i As data, Ctag i Stored as data in Rtag i In the associative array of address index, Rtag is actually established by associative array i and Ctag i The mapping relationship between them, that is, for each Rtag i Assigned a corresponding Ctag i Regardless of the size of the associative array, finding a specific Rtag i Corresponding Ctag i The time required remains basically unchanged, and the required data can be quickly located. The mapping relationship established not only has concise code, but also can clearly show the Rtag i and Ctag i The correspondence between them, the complexity of dynamically adding, deleting and modifying the mapping relationship is low.

[0037] In one embodiment, strc k For two lists, use two lists to store Rtag respectively i and Ctag i , create Rtag by the same index position i and Ctag i When searching, first find Ctag i The index in the Ctag list, and then get the Rtag from the Rtag list through the index i .

[0038] S220, Cdata i Bound data serial number Ctag i Replaced by Rtag i , get the updated Cdata i ´, so that the verification environment can be used for Rdata i and Cdata i Verification passed.

[0039] Among them, Cdata i Ctag i Replaced by Rtag i After that, you can make Cdata i The data sequence number in ´ is the same as Rdata i The data sequence number in is the same, that is, Rdata i and Cdata i The data part and data sequence number are the same, and the verification platform determines Rdata according to the original judgment logic. i and Cdata i The comparison results are the same, and the verification is passed. This method not only re-establishes the mapping relationship between the data sequence numbers in the second verification module and the first verification module, but also eliminates the interference of the data sequence number on the verification result, so that the verification result will no longer be rolled back due to data sequence number mismatch.

[0040] S230, the verification environment returns Cdata to the first verification module i ´ response data, with Rtag i As the address index strc k [Rtag i Ctag saved in ] i Take out and put the Ctag i Return to the first verification module.

[0041] When the verification environment returns the response data to the first verification module, the response data is returned to the inter k The number of data sent is determined by the data sequence number when the data is sent, so the original data sequence number needs to be returned. The original data sequence number is saved in strc k [Rtag i ], according to Ctag i It can ensure that the information is correctly returned to the first verification module.

[0042] It should be noted that, for the handling of abnormal situations, since the speed at which the first verification module sends data is greater than the speed at which the second verification module sends data, assuming that the first verification module sends 10 data and the second verification module sends 5 data, and the remaining 5 data of the second verification module have abnormal situations such as reset, then these 5 data with abnormal situations will be discarded; since the method provided by the present invention no longer requires the data sequence numbers to be equal, the data sequence numbers are no longer a condition for passing the verification, but a mapping relationship between the data sequence numbers is re-established, so the subsequent data of the first verification module can be numbered in sequence when it is sent again, and the data sequence number of the first verification module does not need to fall back to the 5th data of the second verification module, directly avoiding various fallback problems caused by whether the data sequence numbers are equal or not. In addition, since the data sequence number is no longer a condition for passing the verification, and it is no longer required that the data sequence numbers of two identical data be exactly the same, the data sequence number only needs to be numbered in sequence when sending the data, and the data sequence number can be reused after use, without the need for complex fallback management logic, thus simplifying the management logic of the original system.

[0043] In summary, the present invention provides a data sequence number remapping method, which re-establishes the mapping relationship between the data sequence numbers of two data, replaces the data sequence number of the first verification module with the data sequence number of the second verification module to pass the verification, and then retrieves and returns the data sequence number of the first verification module through the mapping relationship; this method cleverly resolves the problem of data return by remapping to establish a mapping relationship between data sequence numbers and retrieving data sequence numbers through indexes. It no longer requires that the data sequence numbers must be exactly the same, and the data sequence number is no longer a condition for judging whether the verification is passed or not. Whether the data sequence number is returned or recycled will not affect the verification result, thereby avoiding the problem of needing to process the fallback logic due to the failure of the data sequence number to be returned, saving a lot of time for processing the fallback logic, and shortening the development cycle.

[0044] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in a method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0045] An embodiment of the present invention further provides an electronic device including a processor and the aforementioned non-transitory computer-readable storage medium.

[0046] An embodiment of the present invention further provides a computer program product comprising program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0047] Those skilled in the art will clearly understand that for the sake of convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0048] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A data sequence number remapping method, characterized in that: The method comprises the following steps: S100, the verification platform receives the data sent by the first verification module and stores it in the cache. When it receives the kth interface interface of the second verification module, k The i-th data Rdata sent i When the kth interface of the first verification module stored in the cache is searched, k The i-th data sent Cdata i ; S200, compared to Rdata i and Cdata i Are the data parts in the same? If they are the same, get Rdata i Bound data serial number Rtag i and Cdata i Bound data serial number Ctag i , and Rtag i and Ctag i Remapping is performed, wherein the remapping step comprises: S210, build a storage structure strc k , Rtag i As a unique index identifier, Ctag i Stored as associated data in the strc k In the Rtag i For index, Ctag i A one-to-one mapping relationship for associated values; S220, Cdata i Bound data serial number Ctag i Replaced by Rtag i , get the updated Cdata i ´, so that the verification environment can be used for Rdata i and Cdata i Verification passed; S230, the verification environment returns Cdata to the first verification module i ´ response data, with Rtag i As the address index strc k Ctags saved in i Take out and replace the Ctag i Return to the first verification module.

2. The method according to claim 1, characterized in that The first verification module includes multiple interfaces, and a storage structure is configured for each interface.

3. The method according to claim 1, characterized in that strc in S210 k is an associative array, where Rtag i For array index, Ctag i Store in associative array strc k [Rtag i ]middle.

4. The method according to claim 1, wherein The second verification module is an RTL model or a VHDL model.

5. The method according to claim 1, wherein The first verification module is a Cmodel model, a SystemC model, a Python model or a gate-level netlist verification model.

6. The method according to claim 1, characterized in that The verification platform is a cosim verification platform.

7. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, characterized in that: The at least one instruction or the at least one program is loaded and executed by a processor to implement the method according to any one of claims 1 to 6.

8. An electronic device, characterized in that: The device comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 7.

Citation Information

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