Digital circuit engineering correction method and related equipment

Abstract

The present application belongs to the field of semiconductor design automation technology, and proposes a digital circuit engineering correction method and related equipment. The method includes: after the digital circuit wiring is completed, static timing analysis is performed based on the actual circuit resistance and capacitance parasitic parameters of the timing path in the digital circuit to obtain global timing information of the timing path, and based on the global timing information, abnormal timing paths containing abnormal logic units are screened out from the digital circuit; logic unit changes are performed on the abnormal timing paths containing abnormal logic units, and wiring changes are performed on the digital circuit after the logic unit changes; if there is no wiring violation in the digital circuit, the step of performing static timing analysis based on the actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit is returned to execution until there is no abnormal timing path in the digital circuit. The technical solution provided by the present application can improve the correction efficiency of digital circuit engineering.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor design automation technology, and in particular relates to a digital circuit engineering correction method and related equipment. Background Art

[0002] With the rapid advancement of semiconductor technology, the scale and complexity of digital circuits (such as digital integrated circuits) are constantly increasing. This has made routing a crucial component in the field of semiconductor design automation (EDA). Especially with FinFET processes, routing complexity in digital circuit design has increased significantly. Currently, anomalies such as timing violations often occur in the later stages of digital circuit design. Re-doing the entire layout and routing process not only consumes significant time and resources but may also introduce new anomalies. Therefore, improving the efficiency of digital circuit engineering revisions has become a pressing technical challenge. Summary of the Invention

[0003] The embodiments of the present application provide a digital circuit engineering correction method, apparatus, computer program product, computer-readable storage medium, and electronic device, which can improve the correction efficiency of digital circuit engineering to a certain extent.

[0004] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by practice of the present application.

[0005] According to a first aspect of an embodiment of the present application, a digital circuit engineering correction method is provided, the method comprising: after completing the wiring of the digital circuit, performing static timing analysis based on the actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit to obtain global timing information of each timing path; based on the global timing information of each timing path, screening out abnormal timing paths containing abnormal logic units from the digital circuit; performing logic unit changes on the abnormal timing paths containing the abnormal logic units, and performing wiring changes on the digital circuit after the logic unit changes; if the digital circuit after the wiring changes is checked based on a design rule checking engine and no wiring violations exist, returning to the step of performing static timing analysis based on the actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit until no abnormal timing paths exist in the digital circuit.

[0006] In some embodiments of the present application, based on the aforementioned scheme, static timing analysis is performed based on the actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit to obtain global timing information of each timing path, including: based on the actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit, calling a static timing analysis engine to calculate the timing parameter values ​​of each logic unit in each timing path in at least one dimension as the global timing information of each timing path.

[0007] In some embodiments of the present application, based on the aforementioned scheme, the screening out of abnormal timing paths including abnormal logic units from the digital circuit based on the global timing information of each timing path includes: obtaining a preset timing parameter threshold; if a timing parameter value of any logic unit in the digital circuit satisfies a preset size relationship with the timing parameter threshold, determining the any logic unit as an abnormal logic unit, and determining the timing path to which the abnormal logic unit belongs as an abnormal timing path.

[0008] In some embodiments of the present application, based on the aforementioned scheme, the logic unit change of the abnormal timing path containing the abnormal logic unit includes: obtaining a pre-built exception list and an alternative list, wherein the exception list is used to record the abnormal timing path screened out from the digital circuit and the abnormal logic units in the abnormal timing path, and the alternative list is used to record configurable logic units of different unit types, wherein the unit types include functional units and filler units; selecting a target abnormal timing path to be changed and a target abnormal logic unit in the target abnormal timing path from the exception list, determining a target change type of the logic unit, and selecting a logic unit to be placed from the alternative list; wherein the change type of the logic unit includes at least adding a logic unit, replacing a logic unit, and deleting a logic unit; based on the logic unit to be placed and the target abnormal logic unit, the logic unit change is performed on the target abnormal timing path according to the target change type.

[0009] In some embodiments of the present application, based on the aforementioned scheme, if the target change type is to add a logical unit, the logical unit to be placed is a first functional unit, and the logical unit change of the target abnormal timing path includes: placing the first functional unit in a target site area on the target abnormal timing path close to the target abnormal logical unit, wherein the site is a basic location unit on the timing path.

[0010] In some embodiments of the present application, based on the aforementioned scheme, placing the first functional unit in a target site area on the target abnormal timing path close to the target abnormal logic unit includes: determining the logical units within a preset radius centered on the target abnormal logic unit on the target abnormal timing path to obtain a logical unit list; traversing the sizes of the padding units in the logical unit list in sequence according to a set traversal order; when the size of any padding unit traversed is greater than or equal to the size of the first functional unit, or when the sum of the sizes of any group of consecutively adjacent padding units traversed is greater than or equal to the size of the first functional unit, determining the site area occupied by any one padding unit or the site area occupied by any group of consecutively adjacent padding units as the target site area; deleting the padding units in the target site area, and placing the first functional unit in the target site area.

[0011] In some embodiments of the present application, based on the aforementioned scheme, placing the first functional unit in the target site area includes: if the size of the target site area is larger than the size of the first functional unit, then based on the size difference between the size of the target site area and the size of the first functional unit, searching for one or more filling units from the alternative list according to the set search logic; combining the first functional unit with the one or more filling units to obtain a combined unit, the size of the target site area is equal to the size of the combined unit; and placing the combined unit in the target site area.

[0012] In some embodiments of the present application, based on the aforementioned scheme, the method further includes: if the first functional unit is a buffer unit, calculating a radius threshold based on a signal integrity analysis engine; determining the preset radius, and the preset radius is greater than or equal to the radius threshold.

[0013] In some embodiments of the present application, based on the aforementioned solution, if the target change type is replacing a logic unit, the logic unit to be placed is a second functional unit that is adapted to the size of the target abnormal logic unit, and changing the logic unit of the target abnormal timing path includes: deleting the target abnormal logic unit and placing the second functional unit in the site area occupied by the target abnormal logic unit.

[0014] In some embodiments of the present application, based on the aforementioned solution, if the target change type is deleting a logical unit, the logical unit to be placed is a padding unit or a combination of padding units that is adapted to the size of the target abnormal logical unit, and performing a logical unit change on the target abnormal timing path includes: deleting the target abnormal logical unit and placing the padding unit or the combination of padding units that is adapted to the size of the target abnormal logical unit in the site area occupied by the target abnormal logical unit.

[0015] In some embodiments of the present application, based on the aforementioned scheme, the wiring change of the digital circuit after the logic unit is changed includes: performing a local wiring change on the digital circuit after the logic unit is changed; or performing a global wiring change on the digital circuit after the logic unit is changed.

[0016] In some embodiments of the present application, based on the aforementioned scheme, the local wiring change of the digital circuit after the logic unit is changed includes: taking a memory snapshot of the wiring data of other timing paths except the abnormal timing path, and clearing the wiring data of the abnormal timing path; obtaining the wiring data of the other timing paths in the memory, and calling a three-dimensional wiring algorithm to rewire the abnormal timing path based on the wiring data of the other timing paths.

[0017] According to a second aspect of an embodiment of the present application, a digital circuit engineering correction device is provided, the device comprising: an analysis unit for performing static timing analysis based on actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit after the digital circuit is wired, to obtain global timing information of each timing path; a screening unit for screening out abnormal timing paths containing abnormal logic units from the digital circuit based on the global timing information of each timing path; a change unit for performing logic unit changes on the abnormal timing paths containing the abnormal logic units, and performing wiring changes on the digital circuit after the logic unit changes; and a checking unit for returning to the step of performing static timing analysis based on actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit, if a design rule checking engine checks that no wiring violations exist in the digital circuit after the wiring changes, until no abnormal timing paths exist in the digital circuit.

[0018] According to a third aspect of an embodiment of the present application, a computer program product is provided, which includes computer instructions, which are stored in a computer-readable storage medium and are suitable for being read and executed by a processor, so that a computer device having the processor executes to implement the operations performed by the method described in the first aspect above.

[0019] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which at least one computer program instruction is stored. The at least one computer program instruction is loaded and executed by a processor to implement the operations performed by the method described in the first aspect above.

[0020] According to a fifth aspect of an embodiment of the present application, an electronic device is provided, comprising one or more processors and one or more memories, wherein at least one computer program instruction is stored in the one or more memories, and the at least one computer program instruction is loaded and executed by the one or more processors to implement the operations performed by the method described in the first aspect above.

[0021] Based on the technical solution proposed in this application, the efficiency of correcting digital circuit engineering can be significantly improved. Specifically, first, after the wiring is completed, static timing analysis is performed based on the resistance and capacitance parasitic parameters of the actual circuit, which can obtain more real and accurate global timing information, avoiding the timing analysis deviation caused by inaccurate parameters before wiring in the traditional ECO method, thereby improving the accuracy of timing violation detection. Secondly, by changing the logic unit of the abnormal logic unit contained in the abnormal timing path, and combining incremental wiring and other means, only the local wiring is quickly changed without the need to re-do the global layout and wiring, which can greatly shorten the correction cycle of the digital circuit engineering and improve the iterative efficiency of the digital circuit. In addition, the present application verifies the digital circuit after the wiring change in real time through the design rule checking engine, ensuring that the wiring violation can be discovered and eliminated in time after each local correction, which can ensure the reliability and design quality of the digital circuit correction process. Iterative analysis and correction are repeated until all timing paths are free of abnormalities, which can further ensure that the timing performance of the final digital circuit meets the design requirements.

[0022] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are incorporated into and constitute a part of the specification, illustrating embodiments consistent with the present application and, together with the specification, explaining the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0024] Figure 1 A flow chart of a digital circuit engineering correction method according to an embodiment of the present application is shown;

[0025] Figure 2A first schematic diagram of adding a logic unit to a digital circuit in an embodiment of the present application is shown;

[0026] Figure 3 A second schematic diagram showing an embodiment of the present application in which a logic unit is added to a digital circuit is shown;

[0027] Figure 4 A block diagram of a digital circuit engineering correction device in an embodiment of the present application is shown;

[0028] Figure 5 A schematic structural diagram of an electronic device in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0030] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0031] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices. It should also be noted that in the accompanying drawings, certain components that do not affect the explanation of the technical solutions of this application have been omitted for clarity.

[0032] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0033] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0034] In order to enable those skilled in the art to better understand this application, the technical concepts and application background involved in this application are first briefly explained.

[0035] Digital Circuit (DC): A digital circuit is an electronic circuit that uses digital signals (i.e., signals that take on a finite number of discrete values, typically "0" and "1") as information carriers, processing, transmitting, and storing information through electronic devices such as logic gates. Based on Boolean algebra, digital circuits can perform various logical and arithmetic operations, data storage, and control functions, and are a core component of modern computer, communications, and automatic control systems.

[0036] Digital Circuit Routing (DCR): Digital circuit routing usually refers to the process of connecting various functional units, logic gates, and circuit blocks inside a chip (such as FPGA, CPU, GPU, etc.) through metal interconnects according to design requirements.

[0037] With the continuous advancement of semiconductor technology, the scale and complexity of digital circuits are increasing. Routing is a critical step in the digital circuit design process. This is especially true at advanced process nodes like FinFET, where changes in process physics lead to more complex parasitic parameters such as circuit impedance and capacitance. This significantly increases the difficulty of routing and the complexity of timing analysis.

[0038] In the later stages of digital circuit design, anomalies such as timing violations often arise. The traditional solution is to re-layout the entire digital circuit, but this not only consumes a significant amount of time and computing resources, but can also introduce new anomalies due to large-scale changes. In this context, this application proposes a digital circuit engineering correction scheme that improves the efficiency of digital circuit engineering corrections, allowing for rapid and efficient correction of abnormal timing paths in digital circuits while ensuring design correctness.

[0039] The following describes the implementation details of the technical solution of the embodiment of the present application:

[0040] Reference Figure 1, shows a flow chart of a digital circuit engineering correction method in an embodiment of the present application, which can be executed by a device with a computing and processing function. Figure 1 As shown, the digital circuit engineering correction method includes at least steps 110 to 140, which are described in detail as follows:

[0041] Reference Figure 1 In step 110, after the digital circuit is wired, static timing analysis is performed based on actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit to obtain global timing information of each timing path.

[0042] In this application, the digital circuit includes multiple timing paths (also referred to as timing paths, timing links, signal paths, signal / timing networks, etc.). Specifically, a timing path refers to the signal transmission path in a digital circuit from the output end of a clock trigger (such as a trigger, latch, register, storage unit, etc.), through several logic cells (Cell) and wiring, and finally to the input end of another clock trigger. Timing paths can generally be divided into data paths (Data Path), clock paths (Clock Path), input paths (Input Path), output paths (Output Path), cross-clock domain paths (Cross-Domain Path), etc. according to their starting and ending points.

[0043] In this application, after the digital circuit wiring is completed, the completed wiring data can be parasitically read using physical design tools to obtain the actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit. The circuit resistance and capacitance parasitic parameters, which can be referred to as RC parasitic parameters, refer to the parasitic resistance (R) and parasitic capacitance (C) that are inevitably generated during the physical implementation of the digital circuit due to metal interconnects, vias, metal layers, adjacent signal lines, etc. These parameters can reflect the additional electrical characteristics introduced by the physical structure and material properties in the actual physical circuit, in addition to the ideal logic cells.

[0044] During digital circuit design, after routing is complete, the actual physical characteristics of the circuit (such as routing length, metal layer distribution, and coupling relationships) directly affect the signal delay along each timing path. This means that the actual delay of each timing path depends not only on the delay of the logic gate itself but also significantly on parasitic parameters such as resistance (R) and capacitance (C) introduced by the routing. Therefore, after routing is complete, the global timing information for each timing path can be determined based on the extracted actual circuit resistance and capacitance parasitic parameters.

[0045] In the present application, static timing analysis is performed based on the actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit to obtain global timing information of each timing path. The steps 111 can be performed as follows:

[0046] Step 111: Based on the actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit, call a static timing analysis engine to calculate the timing parameter values ​​of each logic unit in each timing path in at least one dimension as the global timing information of each timing path.

[0047] In this application, the actual circuit resistance and capacitance parasitic parameters on each timing path can be associated with the logic netlist to form a real path model at the physical level. Afterwards, the static timing analysis (STA) engine can be called to load the netlist, process library and actual circuit resistance and capacitance parasitic parameters, and perform timing calculations on each timing path step by step to obtain the multi-dimensional timing parameter values ​​of each logic unit. Finally, the key timing parameters of all logic units on each timing path are summarized to form the global timing information of the path. Since the resistance and capacitance parasitic parameters obtained after the wiring is completed can truly reflect the additional electrical characteristics introduced by the digital circuit during the physical implementation process, the static timing analysis algorithm can be used to accurately estimate the global timing information of the timing path based on these resistance and capacitance parasitic parameter information, thereby providing an accurate basis for the subsequent correction of the digital circuit, thereby improving the correction efficiency of the digital circuit engineering.

[0048] In this application, the timing parameter value may specifically include at least one of the following dimensions:

[0049] Delay: Delay refers to the time it takes for a signal to travel from one point to another in a circuit. It reflects the time lag caused by a signal passing through logic gates, wires, and other components.

[0050] Setup Time: Setup time refers to the minimum time that the data signal must remain stable before the clock signal's valid edge (such as the rising or falling edge) arrives. Simply put, the data must be prepared in advance so that the clock signal can correctly sample stable data.

[0051] Arrival Time: Arrival time refers to the actual time it takes for a signal to arrive at a specific pin. It is the time it takes for a signal to travel from its source, through a series of logic gates and wires, to finally reach its destination pin.

[0052] Slack: Slack is the difference between the actual arrival time and the required arrival time. It reflects the margin of signal arrival time and is an important indicator for measuring whether the timing meets the requirements.

[0053] Required Time: The required time is the latest time that a signal must arrive at a specific pin. It is determined by the timing requirements of the circuit and the period of the clock signal.

[0054] Slew: Slew refers to the rate at which the signal voltage changes, indicating the time it takes for the signal to change from one level to another.

[0055] Load: A load is a device or component connected to a power or signal source in a circuit that consumes power or receives signals. The characteristics of the load affect the performance of the circuit, such as current, power, and signal integrity.

[0056] In a real-world design process, for example, a timing path is Register A → BUF1 → AND2 → INV3 → Register B. Assume that after extracting the actual circuit's RC parasitic parameters, the global timing information for this timing path is as follows: BUF1's delay is 50ps, its slew is 120ps, and its load is 0.2pF; AND2's delay is 80ps, its slew is 180ps, and its load is 0.35pF; and INV3's delay is 60ps, its slew is 110ps, and its load is 0.1pF. The wiring between BUF1 and AND2 has significant capacitance and coupling capacitance. Based on the actual circuit's RC parasitic parameter analysis, the STA engine finds that AND2's output slew is slow, which increases the delay of INV3 and ultimately results in a -30ps setup margin for the entire timing path.

[0057] Based on the technical solution of step 111 above, by introducing the parasitic parameters of actual circuit resistance and capacitance, the parasitic effects of actual circuit resistance and capacitance can be fully considered, avoiding the misjudgment of the ideal static timing analysis engine, achieving highly accurate timing analysis, and ensuring that the analysis results are highly consistent with the actual performance of the digital circuit after physical implementation. At the same time, by calling the static timing analysis engine to calculate the global timing information of each timing path, the timing performance of each logic unit can be finely analyzed, thereby providing an accurate basis for subsequent digital circuit corrections, thereby improving the correction efficiency of digital circuit engineering.

[0058] Overall, this step achieves accurate calculation and summary of the multi-dimensional timing parameters of each timing path and its internal logic units through static timing analysis based on the actual circuit's resistance and capacitance parasitic parameters. This provides a solid data foundation for subsequent timing anomaly detection, correction, and optimization, and is a key technical link in achieving high-quality, high-reliability digital circuit design.

[0059] Continue to refer to Figure 1 In step 120, based on the global timing information of each timing path, an abnormal timing path containing an abnormal logic unit is screened out from the digital circuit.

[0060] In the present application, specifically, the step of screening out abnormal timing paths including abnormal logic units from the digital circuit based on the global timing information of each timing path may be performed according to the following steps 121 to 122:

[0061] Step 121: Obtain a preset timing parameter threshold.

[0062] Step 122 : If the timing parameter value of any logic unit in the digital circuit satisfies a preset magnitude relationship with the timing parameter threshold, the any logic unit is determined as an abnormal logic unit, and the timing path to which the abnormal logic unit belongs is determined as an abnormal timing path.

[0063] In this application, timing parameter thresholds refer to the allowable ranges for various timing parameters (such as delay, slew, load, and timing margin), set based on design specifications, process requirements, empirical data, or simulation results. These thresholds can be set based on different logic cell types and timing path categories to accommodate the diverse needs of complex digital circuit design. For example, the delay threshold for a particular logic cell can be set to no more than 200ps, and the slew threshold can be set to no more than 150ps.

[0064] In the present application, the preset size relationship may include comparison symbols such as ">", "<", "≥", "≤", etc., which are used to define the judgment criteria between the timing parameter value and the corresponding timing parameter threshold.

[0065] During the screening process for abnormal logic units and abnormal timing paths, all logic units on each timing path are first traversed to check whether the values ​​of various timing parameters and their corresponding thresholds meet a preset size relationship. For example, this can determine whether the delay exceeds a threshold or whether the slew rate is too slow. Once a timing parameter value is detected to exceed its corresponding threshold, the logic unit is marked as an "abnormal logic unit." Subsequently, the entire timing path containing the abnormal logic unit is also marked as an "abnormal timing path."

[0066] In addition, this application also supports joint judgment of multiple timing parameter values. For example, it can be configured to determine an abnormality only when both delay and slew exceed corresponding thresholds, thus implementing a flexible abnormality judgment strategy. Furthermore, this application can also automatically and batch-screen abnormal logic units and abnormal timing paths in large-scale circuit design scenarios to improve design and verification efficiency.

[0067] Continue to refer to Figure 1 In step 130, a logic unit change is performed on the abnormal timing path including the abnormal logic unit, and a wiring change is performed on the digital circuit after the logic unit change.

[0068] In this application, the exception list and the alternative list can be pre-built and saved in memory.

[0069] The exception list can be used to record abnormal timing paths screened out from the digital circuit and abnormal logic units in the abnormal timing paths. Specifically, the exception list can include all screened abnormal timing paths and their corresponding abnormal logic units, as well as relevant timing parameter values ​​(such as delay, slew, etc.); the alternative list can be used to record configurable logic units of different unit types. Specifically, the alternative list includes optional logic units of different unit types, such as functional units and filler units.

[0070] Specifically, the functional unit, also known as the standard cell, refers to a basic circuit unit in digital circuit design that performs specific logic or storage functions. They are the "building blocks" that implement chip functions, such as AND gates, OR gates, NOT gates, flip-flops, latches, adders, etc. For example, the inverter INV_X1 has a drive capability of 1, the two-input AND gate AND2_X2 has a drive capability of 2, and the D flip-flop DFF_X1. The filler cell, also called the filler cell, is a cell that has no logical function and is used only for physical filling. Its main function is to fill the gaps between standard cells during the place and route process to ensure the integrity of the chip's physical structure and meet process requirements. For example, filler cells of different widths (sizes) FILL1, FILL2, and FILL4.

[0071] In the present application, the logic unit change of the abnormal timing path including the abnormal logic unit may be performed according to the following steps 131 to 133:

[0072] Step 131: Obtain a pre-built exception list and alternative list.

[0073] Step 132: Select a target abnormal timing path to be changed and a target abnormal logical unit in the target abnormal timing path from the abnormal list, determine a target change type for the logical unit, and select a logical unit to be placed from the candidate list. The change types for the logical unit include at least adding a logical unit, replacing a logical unit, and deleting a logical unit.

[0074] Step 133 : Based on the logic unit to be placed and the target abnormal logic unit, and according to the target change type, perform a logic unit change on the target abnormal timing path.

[0075] In the present application, the user may select the target abnormal timing path to be changed and the target abnormal logic unit in the target abnormal timing path from the abnormal list, determine the target change type of the logic unit, and select the logic unit to be placed from the alternative list. Alternatively, the user may automatically select the target abnormal timing path to be changed and the target abnormal logic unit in the target abnormal timing path from the abnormal list based on preset rules, determine the target change type of the logic unit, and select the logic unit to be placed from the alternative list. This application does not impose any additional restrictions on this.

[0076] In the present application, the selected target abnormal timing path may be any one or more abnormal timing paths in the digital circuit, or may be all abnormal timing paths in the digital circuit. In this regard, the present application does not make too many restrictions. Furthermore, the selected target abnormal logic unit may be any one (or the first in the timing direction) abnormal logic unit in the target abnormal timing path, or may be all abnormal logic units in the target abnormal timing path. In this regard, the present application does not make too many restrictions. If the selected target abnormal timing path is all abnormal timing paths in the digital circuit, batch changes to the abnormal timing paths can be implemented subsequently. If the selected target abnormal logic units are all abnormal logic units in the target abnormal timing path, batch changes to the abnormal logic units can be implemented subsequently.

[0077] In the present application, the target abnormal timing path and the target abnormal logic unit therein that need to be corrected first can also be selected from the abnormality list according to the priority (such as the smallest timing margin, the largest delay limit violation, etc.).

[0078] In this application, changes to logic units may include at least adding, replacing, and deleting logic units. For example, when drive capacity is insufficient or the load is excessive, a buffer or drive enhancement unit can be inserted (i.e., adding a logic unit). Another example is replacing a unit with a similar unit that offers greater drive, faster latency, or improved slew (i.e., replacing a logic unit). Another example is directly removing redundant gates or invalid buffers that can shorten the path (i.e., deleting a logic unit).

[0079] In this application, available logic units to be placed (such as logic units with different process sizes and different drive capabilities) can be screened from the alternative list based on the determined target change type, process compatibility of the logic unit, functional requirements, etc.

[0080] In the present application, after selecting a target abnormal logic unit, determining a target change type of the logic unit, and selecting a logic unit to be placed, a logic unit change can be performed on the target abnormal timing path based on the logic unit to be placed and the target abnormal logic unit according to the target change type.

[0081] For example, if insufficient drive capability is detected in an abnormal timing path for INV3 (inverter 3), resulting in a slow output slew rate, and a system analysis recommends "Replace Logic Unit," then a higher-drive-capable INV3 can be selected from the candidate list to replace the original INV3. Alternatively, if a long routing distance exists between BUF1 and AND2 on a certain path, causing signal attenuation, and a system analysis recommends "Add Logic Unit," then a buffer, BUF2, can be inserted between them.

[0082] In this application, by automatically selecting the target abnormal timing path, target abnormal logic unit, and appropriate target change type, and performing operations such as adding, replacing, or deleting logic units, efficient and accurate correction of timing anomalies can be achieved. This not only improves the efficiency and effectiveness of post-routing timing optimization of digital circuits, but also provides a solid foundation for subsequent automated design closed loops.

[0083] Specifically, in the present application, if the target change type is to add a logical unit, the logical unit to be placed is the first functional unit.

[0084] In the present application, the first functional unit may be a suitable functional unit (such as a buffer or an inverter) selected according to the abnormality type of the target abnormal unit (such as insufficient drive or excessive delay), and its parameters such as driving capability and size are determined.

[0085] Furthermore, the logic unit change of the target abnormal timing path may be performed according to the following step 1331:

[0086] Step 1331 : Place the first functional unit in a target site area on the target abnormal timing path close to the target abnormal logic unit, where a site is a basic location unit on the timing path.

[0087] In this application, a site is a basic location unit in layout and routing (i.e., on a sequential path), typically aligned with the cell library step (e.g., one site per 0.19μm). Based on the location of the target abnormal logic cell, combined with physical layout, congestion, power / ground line distribution, etc., you can prioritize the target site area close to the target abnormal logic cell, and place the first functional unit (such as BUF_X2) in the target site area upstream or downstream of the target abnormal logic cell. For example, if the first functional unit is a driver enhancement logic unit, the first functional unit can be placed upstream of the target abnormal logic unit. If the first functional unit is a signal shaping or timing adjustment logic unit, the first functional unit can also be placed downstream of the target abnormal logic unit.

[0088] In the present application, a specific site area may be directly set according to actual conditions to place the first functional unit.

[0089] It should be noted that before placing the first functional unit, physical and process verification is required. First, it is necessary to check whether there is enough space in the target site area to avoid the first functional unit overlapping with other functional units on the target abnormal timing path.

[0090] In some embodiments of the present application, placing the first functional unit in a target site area close to the target abnormal logic unit on the target abnormal timing path may also be performed according to the following steps 13311 to 13314:

[0091] Step 13311: determine the logical units within a preset radius centered on the target abnormal logical unit on the target abnormal timing path, and obtain a logical unit list.

[0092] Step 13312: traverse the sizes of the filling units in the logical unit list in sequence according to the set traversal order.

[0093] Step 13313, when the size of any filling unit traversed is greater than or equal to the size of the first functional unit, or when the sum of the sizes of any group of adjacent filling units traversed is greater than or equal to the size of the first functional unit, the site area occupied by any one filling unit or the site area occupied by any group of adjacent filling units is determined as the target site area.

[0094] Step 13314: Delete the filling unit in the target site area and place the first functional unit in the target site area.

[0095] In the present application, by finely screening and operating the area close to the target abnormal logic unit on the target abnormal timing path, the precise placement of the first functional unit can be achieved. First, within a preset radius centered on the target abnormal logic unit, the logic units within the range are determined and a list of logic units is generated. Next, the three-dimensional layout shape database of the digital circuit can be queried, and the sizes of each filling unit in the logic unit list can be checked in sequence according to the set traversal order. When it is found that the size of a filling unit is greater than or equal to the size of the first functional unit, or when it is found that the sum of the sizes of a group of adjacent filling units is greater than or equal to the first functional unit, the site area occupied by the filling unit or the group of adjacent filling units is determined as the target site area. Finally, the filling units in the target site area are deleted, and the first functional unit is accurately placed in the target site area, thereby making full use of the space reserved by the filling unit without affecting the normal layout of the functional unit, and realizing physical optimization of the abnormal timing path.

[0096] Steps 13311 to 13314 can significantly improve the efficiency and performance of digital circuit design. First, identifying the logical cells within a radius centered on the target abnormal logical cell helps quickly identify the logical cells to be analyzed, forming a list of logical cells and making subsequent processing more systematic. By setting a traversal order and checking the sizes of the filler cells one by one, it is possible to effectively identify those filler cells that can be replaced. After determining the target site area, unnecessary filler cells are deleted. This not only eliminates redundancy in the circuit design, but also creates space for possible subsequent cell combinations, thus providing a basis for design optimization.

[0097] In this application, the following steps 133111 to 133112 may also be performed:

[0098] Step 133111: If the first functional unit is a buffer unit (Buffer), a radius threshold is calculated based on a signal integrity analysis (SI) engine.

[0099] Step 133112: determine the preset radius, which is greater than or equal to the radius threshold.

[0100] In this application, for the special case where the first functional unit is a buffer unit (Buffer), the selection process of the preset radius centered on the target abnormal logic unit is further optimized. Specifically, the target abnormal timing path is first evaluated through the signal integrity analysis (SI) engine to calculate the minimum radius threshold that meets the signal integrity requirements, ensuring that the placement of the buffer unit can effectively improve the signal quality. Subsequently, based on the radius threshold, the preset radius is reasonably determined so that it is greater than or equal to the radius threshold, so that in the subsequent selection process of the target site area, the layout of the buffer unit is guaranteed to not only meet the space requirements, but also take into account the signal integrity optimization goals, ensuring that the physical location of the buffer helps to improve the signal transmission quality and system stability.

[0101] In the above step 13314, placing the first functional unit in the target site area may be performed according to the following step 133141:

[0102] Step 133141: If the size of the target site area is equal to the size of the first functional unit, the first functional unit can be directly placed in the target site area.

[0103] Furthermore, in the above step 13314, the placing of the first functional unit in the target site area may also be performed according to the following steps 133142 to 133144:

[0104] Step 133142: If the size of the target site area is larger than the size of the first functional unit, one or more filling units are searched from the alternative list according to the set search logic based on the size difference between the size of the target site area and the size of the first functional unit.

[0105] Step 133143: Combine the first functional unit with the one or more filling units to obtain a combined unit, and the size of the target site area is equal to the size of the combined unit.

[0106] Step 133144, placing the combined unit in the target site area.

[0107] In this application, in order to make those skilled in the art better understand this application, the following will be combined with Figure 2 and Figure 3 A specific embodiment is used for description.

[0108] See also Figure 2 and Figure 3 , respectively showing a first schematic diagram and a second schematic diagram of adding a logic unit to a digital circuit in an embodiment of the present application.

[0109] In practical applications, such as Figure 2 The target abnormal timing path shown includes at least a logic unit AN, wherein the timing direction of the logic unit AN is:

[0110] A→B→C→D→E→F→G→H→I→J→K→L→M→N.

[0111] In addition, in the target abnormal timing path, it is assumed that the functional unit G is a target abnormal logic unit and has insufficient driving capability.

[0112] In this case, the logical units within a preset radius φ centered on the functional unit G can be determined in the target abnormal timing path to obtain a logical unit list, wherein the logical unit list includes filling unit A, functional unit B, filling unit C, filling unit D, functional unit E, filling unit F, filling unit H, functional unit I, filling unit J, functional unit K, filling unit L, functional unit M, and functional unit N.

[0113] Furthermore, the sizes of the filling units in the logical unit list can be traversed in sequence according to the traversal order in the time sequence direction. Specifically, when any logical unit is traversed to be a filling unit, it can be determined whether the size of the filling unit is greater than or equal to the size of the first functional unit. If so, the site area occupied by the filling unit is determined as the target site area and the traversal is stopped. If not, it is determined whether the next logical unit adjacent to it is a filling unit. If so, it is determined whether the sum of the sizes of the filling unit and the next filling unit is greater than or equal to the size of the first functional unit. If so, the site area occupied by the filling unit and the next filling unit is determined as the target site area and the traversal is stopped. If not, it is determined whether the third logical unit is a filling unit. This cycle is repeated until the sum of the sizes of the adjacent filling units is greater than or equal to the size of the first functional unit, and the traversal is stopped, or when the traversed logical unit is a functional unit, the subsequent filling units are traversed again.

[0114] like Figure 2As shown, when traversing to the filling unit A, its size is 1 site, which is smaller than the size of the functional unit O to be placed, which is 8 site, so the traversal of the logical unit B continues. Since the logical unit B is a functional unit, the traversal of the logical unit C is re-performed. Since the logical unit C is a filling unit and its size is 5 site, which is smaller than the size of the functional unit O to be placed, which is 8 site, so the traversal of the logical unit D is continued. Since the logical unit D is a filling unit, the sum of the sizes of the logical unit C and the logical unit D is compared to be 7 site. Since 7 site is smaller than the size of the functional unit O to be placed, which is 8 site, so the traversal of the logical unit E is continued. Since the logical unit E is a functional unit, the traversal of the logical unit F is re-performed. Since the logical unit F is a filling unit and its size is 9 site, which is larger than the size of the functional unit O to be placed, which is 8 site, the site area occupied by the logical unit F can be determined as the target site area and the traversal is stopped.

[0115] After the target site area is determined, the fill cells of the target site area can be deleted.

[0116] Furthermore, if the size of the target site area is larger than the size of the first functional unit, one or more filling units are searched from the candidate list according to the set search logic based on the size difference between the size of the target site area and the size of the first functional unit. Figure 3 As shown, the target site area's size (9-site) is one site larger than the size (8-site) of the to-be-placed functional unit O. Therefore, a filler unit P with a size of 1 site can be found from the candidate list according to a predetermined search logic (e.g., by sorting filler unit sizes from largest to smallest). By combining the to-be-placed functional unit O and filler unit P, a combined unit with a size of 9 sites is obtained, which is equal to the target site area's size (9-site). Finally, this combined unit can be placed in the target site area.

[0117] Through the above steps 133142 to 133144, if the size of the target site area is larger than the size of the first functional unit, by searching the filling units in the alternative list and combining them, it is ensured that the size of the combined unit matches the size of the target site area, and the blank position in the target abnormal timing path can be effectively filled. In this way, the flexibility of the design can be improved and the potential problems caused by size mismatch can be reduced. In addition, this process enhances the controllability of the design, allowing designers to quickly respond and adjust the design in a complex digital circuit environment to meet timing requirements. This can shorten the design cycle, reduce design costs, and improve the stability and reliability of the circuit.

[0118] Overall, the above method enables fixed-point optimization of target abnormal logic cells in the target abnormal timing path, improving correction efficiency and effectiveness. This not only standardizes the placement process of the first functional unit, facilitating automated implementation in EDA tools, but also ensures that the placement of functional units does not compromise the physical and process integrity of the digital circuit. It effectively mitigates timing violations caused by insufficient drive capability or excessive load, improves the correction efficiency of digital circuit engineering, and accelerates the convergence and optimization of digital circuit designs.

[0119] In the present application, if the target change type is to replace a logic unit, the logic unit to be placed is a second functional unit that is adapted to the size of the target abnormal logic unit.

[0120] Furthermore, the logic unit change of the target abnormal timing path may be performed according to the following step 1332:

[0121] Step 1332: Delete the target abnormal logical unit and place the second functional unit in the site area occupied by the target abnormal logical unit.

[0122] In this application, when the target change type is to replace the logic unit, the optimization is mainly carried out for the situation where the target abnormal logic unit has performance or timing problems. First, a second functional unit that is compatible with the size of the target abnormal logic unit and functionally equivalent can be selected as the logic unit to be placed to ensure that no space conflict or functional loss is introduced after the replacement. Subsequently, by deleting the original target abnormal logic unit and placing the second functional unit directly in the site area originally occupied by it, a seamless replacement is achieved. In this way, not only the continuity and rationality of the physical layout can be guaranteed, but also the performance indicators of the target abnormal timing path can be effectively improved, and the timing and functional performance of the overall circuit can be optimized.

[0123] In the present application, if the target change type is deleting a logical unit, the logical unit to be placed is a filling unit or a combination of filling units that is adapted to the size of the target abnormal logical unit.

[0124] Furthermore, the logic unit change of the target abnormal timing path may be performed according to the following step 1333:

[0125] Step 1333: Delete the target abnormal logical unit, and place a filling unit or a combination of filling units that matches the size of the target abnormal logical unit in the site area occupied by the target abnormal logical unit.

[0126] In the present application, when the target change type is to delete a logic unit, in the case where the target abnormal logic unit needs to be removed from the target abnormal timing path, first, a filling unit or a combination of filling units that matches the size of the target abnormal logic unit can be selected as the logic unit to be placed to ensure that there will be no vacancies or layout chaos in the site area after deletion. Then, the deletion operation is performed to remove the target abnormal logic unit from its original site area, and the selected filling unit or combination of filling units is accurately placed in the area. Through this process, the effective removal of the target abnormal logic unit can be achieved, and the integrity of the physical structure of the digital circuit and the continuity of the layout can be maintained, preventing process or electrical problems caused by blank areas, thereby improving the reliability of the digital circuit design and the controllability of the manufacturing process.

[0127] In the present application, the wiring change of the digital circuit after the logic unit change can be performed according to the following step 134:

[0128] Step 134 , performing local wiring changes on the digital circuit after the logic unit is changed.

[0129] Specifically, the local wiring change of the digital circuit after the logic unit change can be performed according to the following steps 1341 to 1342:

[0130] Step 1341 , taking a memory snapshot of the wiring data of the other timing paths except the abnormal timing path, and clearing the wiring data of the abnormal timing path.

[0131] Step 1342 : Obtain the wiring data of the other timing paths in the memory, and based on the wiring data of the other timing paths, call a three-dimensional wiring algorithm to rewire the abnormal timing path.

[0132] In this application, first, a memory snapshot is taken of the wiring data of all other timing paths except the abnormal timing path, that is, the current wiring status of these timing paths is completely saved to ensure that subsequent operations will not affect the wiring integrity and correctness of the normal timing path. Subsequently, for the abnormal timing path, all its original wiring data is cleared. In this way, it can be ensured that only the abnormal timing path is corrected for wiring, avoiding unnecessary disturbances to the wiring of the entire circuit. In addition, by deleting only the wiring of the abnormal timing path, space is made for subsequent rewiring, eliminating congestion or conflicts that may be caused by the original wiring. At the same time, using the memory snapshot, it can be ensured that the wiring of other paths can be used as a constraint and reference for the subsequent wiring algorithm.

[0133] In the present application, further, the wiring data of other timing paths can be obtained and restored from the memory to ensure that the wiring information of these timing paths is visible and valid when the algorithm is executed. Based on these existing wirings, the abnormal timing paths are pressed into the wiring priority queue, the wiring mode is set to disconnection and rewiring, and the three-dimensional wiring algorithm is called to rewire the abnormal timing paths. During the wiring process, the new wiring will fully consider the wiring distribution and space occupancy of other timing paths to avoid resource conflicts or design rule violations. The three-dimensional wiring algorithm can flexibly allocate wiring paths in space and hierarchy, improving the success rate and quality of wiring. In addition, since only the abnormal timing paths are locally optimized, the efficiency of wiring correction can be significantly improved, reducing the complexity and risk of global wiring.

[0134] In general, the above steps 1341 to 1342 ensure that abnormal timing paths can obtain efficient and reliable rewiring support without affecting other normal paths through the "snapshot-clear-restore-partial rewiring" method, thereby improving the maintainability and design quality of digital circuits in ECO scenarios.

[0135] In the present application, the wiring change of the digital circuit after the logic unit change may also be performed according to the following step 135:

[0136] Step 135 , performing global wiring changes on the digital circuit after the logic unit is changed.

[0137] In this application, all timing paths and routing resources for the entire digital circuit can be comprehensively replanned and optimized. This involves reallocating global routing resources, adjusting the routing of all timing paths, resolving potential congestion, timing, or design rule conflicts, and comprehensively considering multi-layer (3D) routing layouts. Ultimately, a global routing algorithm is used to ensure routing quality, timing performance, and full compliance with design rules for the entire digital circuit. This allows for adapting to large-scale ECOs or simultaneous changes to multiple logic cells, significantly improving overall circuit routing optimization and design reliability.

[0138] In this application, after making local wiring changes to the digital circuit after a logic unit change, or after making global wiring changes to the digital circuit after a logic unit change, a 3D DRC (Design Rule Check) engine can be called to perform a three-dimensional design rule check on the wiring results of the changed area or the entire digital circuit. The 3D DRC engine can comprehensively analyze the spatial relationship between all wiring layers, automatically detect wiring spacing, line width, intersections, inter-layer vias (vias), and possible short circuits, open circuits, and other issues, to ensure that the wiring results meet process design specifications and electrical safety requirements in three-dimensional space. Through the 3D DRC engine's rapid inspection, physical violations that may be introduced after wiring changes can be discovered and located in a timely manner, thereby providing strong guarantees for subsequent wiring corrections and design convergence, and improving the correctness and reliability of wiring design.

[0139] Continue to refer to Figure 1 In step 140, if the digital circuit after the wiring change is checked based on the design rule checking engine and there is no wiring violation, then the process returns to the step of performing static timing analysis based on the actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit until there is no abnormal timing path in the digital circuit.

[0140] In this application, if the design rule check engine confirms that there is no wiring violation in the digital circuit after the wiring change, the execution returns to the following steps: Figure 1 Step 110, shown, re-executes static timing analysis based on the actual parasitic resistance and capacitance parameters (RC parameters) of each timing path in the digital circuit. At this point, all timing paths can be analyzed one by one using the latest parasitic parameters after the routing changes to check for any timing anomalies (such as setup or hold violations). If the analysis results show that abnormal timing paths still exist, routing optimization and adjustments are continued, and the above inspection and analysis process is repeated. These steps are repeated until all timing paths meet design requirements and no abnormal timing paths exist, thus ensuring the timing performance and design correctness of the final digital circuit.

[0141] Based on the technical solution proposed in this application, the efficiency of correcting digital circuit engineering can be significantly improved. Specifically, first, after the wiring is completed, static timing analysis is performed based on the resistance and capacitance parasitic parameters of the actual circuit, which can obtain more real and accurate global timing information, avoiding the timing analysis deviation caused by inaccurate parameters before wiring in the traditional ECO method, thereby improving the accuracy of timing violation detection. Secondly, by changing the logic unit of the abnormal logic unit contained in the abnormal timing path, and combining incremental wiring and other means, only the local wiring is quickly changed without the need to re-do the global layout and wiring, which can greatly shorten the correction cycle of the digital circuit engineering and improve the iterative efficiency of the digital circuit. In addition, the present application verifies the digital circuit after the wiring change in real time through the design rule checking engine, ensuring that the wiring violation can be discovered and eliminated in time after each local correction, which can ensure the reliability and design quality of the digital circuit correction process. Iterative analysis and correction are repeated until all timing paths are free of abnormalities, which can further ensure that the timing performance of the final digital circuit meets the design requirements.

[0142] At the same time, this application fully utilizes the global state information and 3D routing grid EVA values ​​after routing is completed to perform local incremental routing, improving the accuracy and efficiency of the routing algorithm and reducing the global impact caused by local modifications. This shows that this application not only improves the accuracy and speed of corrections, but also optimizes the usability and applicability of EDA tools, providing a more efficient and reliable ECO correction method for chip back-end design, greatly improving the overall correction efficiency and design quality of digital circuit engineering.

[0143] The following describes an embodiment of the device of the present application, which can be used to implement the digital circuit engineering correction method in the above embodiment of the present application. For details not disclosed in the embodiment of the device of the present application, please refer to the embodiment of the digital circuit engineering correction method in the above embodiment of the present application.

[0144] See also Figure 4 , shows a block diagram of a digital circuit engineering correction device in an embodiment of the present application.

[0145] like Figure 4 As shown, a digital circuit engineering correction device 400 according to an embodiment of the present application includes: an analyzing unit 401 , a screening unit 402 , a changing unit 403 and a checking unit 404 .

[0146] Among them, the analysis unit 401 is used to perform static timing analysis based on the actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit after the digital circuit wiring is completed, so as to obtain global timing information of each timing path; the screening unit 402 is used to screen out abnormal timing paths containing abnormal logic units from the digital circuit based on the global timing information of each timing path; the change unit 403 is used to perform logic unit changes on the abnormal timing paths containing abnormal logic units, and to perform wiring changes on the digital circuit after the logic unit changes; the inspection unit 404 is used to return to the step of performing static timing analysis based on the actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit if no wiring violation exists in the digital circuit after the wiring change based on the design rule checking engine, until no abnormal timing path exists in the digital circuit.

[0147] In some embodiments of the present application, based on the aforementioned scheme, the analysis unit 401 is configured to: based on the actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit, call the static timing analysis engine to calculate the timing parameter values ​​of each logic unit in each timing path in at least one dimension as the global timing information of each timing path.

[0148] In some embodiments of the present application, based on the aforementioned scheme, the screening unit 402 is configured to: obtain a preset timing parameter threshold; if the timing parameter value of any logic unit in the digital circuit satisfies a preset size relationship with the timing parameter threshold, then determine the any logic unit as an abnormal logic unit, and determine the timing path to which the abnormal logic unit belongs as an abnormal timing path.

[0149] In some embodiments of the present application, based on the aforementioned scheme, the change unit 403 is configured to: obtain a pre-constructed exception list and an alternative list, wherein the exception list is used to record the abnormal timing paths screened out from the digital circuit and the abnormal logic units in the abnormal timing paths, and the alternative list is used to record configurable logic units of different unit types, wherein the unit types include functional units and filler units; select the target abnormal timing path to be changed and the target abnormal logic unit in the target abnormal timing path from the exception list, determine the target change type of the logic unit, and select the logic unit to be placed from the alternative list; wherein the change type of the logic unit includes at least adding a logic unit, replacing a logic unit, and deleting a logic unit; based on the logic unit to be placed and the target abnormal logic unit, perform a logic unit change on the target abnormal timing path according to the target change type.

[0150] In some embodiments of the present application, based on the aforementioned solution, if the target change type is to add a logical unit, the logical unit to be placed is a first functional unit, and the change unit 403 is configured to: place the first functional unit in a target site area on the target abnormal timing path close to the target abnormal logical unit, where a site is a basic location unit on the timing path.

[0151] In some embodiments of the present application, based on the aforementioned scheme, the change unit 403 is configured to: determine the logical units within a preset radius centered on the target abnormal logical unit on the target abnormal timing path to obtain a logical unit list; traverse the sizes of the filling units in the logical unit list in sequence according to the set traversal order; when the size of any filling unit traversed is greater than or equal to the size of the first functional unit, or when the sum of the sizes of any group of consecutively adjacent filling units traversed is greater than or equal to the size of the first functional unit, determine the site area occupied by any one filling unit or the site area occupied by any group of consecutively adjacent filling units as the target site area; delete the filling units in the target site area, and place the first functional unit in the target site area.

[0152] In some embodiments of the present application, based on the aforementioned scheme, the change unit 403 is configured as follows: if the size of the target site area is larger than the size of the first functional unit, then based on the size difference between the size of the target site area and the size of the first functional unit, one or more filling units are searched from the alternative list according to the set search logic; the first functional unit is combined with the one or more filling units to obtain a combined unit, and the size of the target site area is equal to the size of the combined unit; and the combined unit is placed in the target site area.

[0153] In some embodiments of the present application, based on the aforementioned scheme, the change unit 403 is further configured as: if the first functional unit is a buffer unit, then calculating a radius threshold based on a signal integrity analysis engine; determining the preset radius, and the preset radius is greater than or equal to the radius threshold.

[0154] In some embodiments of the present application, based on the aforementioned solution, if the target change type is replacing a logical unit, the logical unit to be placed is a second functional unit that is adapted to the size of the target abnormal logical unit, and the changing unit 403 is configured to: delete the target abnormal logical unit and place the second functional unit in the site area occupied by the target abnormal logical unit.

[0155] In some embodiments of the present application, based on the aforementioned solution, if the target change type is deleting a logical unit, the logical unit to be placed is a filler unit or a combination of filler units that matches the size of the target abnormal logical unit. The changing unit 403 is configured to delete the target abnormal logical unit and place the filler unit or the combination of filler units that matches the size of the target abnormal logical unit in the site area occupied by the target abnormal logical unit.

[0156] In some embodiments of the present application, based on the aforementioned solution, the changing unit 403 is configured to: perform a local wiring change on the digital circuit after the logic unit is changed; or perform a global wiring change on the digital circuit after the logic unit is changed.

[0157] In some embodiments of the present application, based on the aforementioned scheme, the change unit 403 is configured to: take a memory snapshot of the wiring data of other timing paths except the abnormal timing path, and clear the wiring data of the abnormal timing path; obtain the wiring data of the other timing paths in the memory, and based on the wiring data of the other timing paths, call a three-dimensional wiring algorithm to rewire the abnormal timing path.

[0158] Based on the same inventive concept, an embodiment of the present application provides a computer program product, which includes computer instructions stored in a computer-readable storage medium and suitable for being read and executed by a processor, so that a computer device with the processor executes to implement the operations performed by the digital circuit engineering correction method as described above.

[0159] Based on the same inventive concept, an embodiment of the present application provides a computer-readable storage medium, which stores at least one computer program instruction, and the at least one computer program instruction is loaded and executed by a processor to implement the operations performed by the digital circuit engineering correction method described above.

[0160] Based on the same inventive concept, the present application also provides an electronic device, referring to Figure 5 , shows a schematic structural diagram of an electronic device in an embodiment of the present application, wherein the electronic device includes one or more memories 504, one or more processors 502, and at least one computer program (computer program instruction) stored in the memory 504 and executable on the processor 502. When the processor 502 executes the computer program, the digital circuit engineering correction method described above is implemented.

[0161] Among them, Figure 5In the embodiment of the present invention, a bus architecture (represented by bus 500) is shown. Bus 500 may include any number of interconnected buses and bridges. Bus 500 links various circuits, including one or more processors represented by processor 502 and memory represented by memory 504. Bus 500 may also link various other circuits, such as peripherals, voltage regulators, and power management circuits. These are well known in the art and are therefore not described further herein. Bus interface 505 provides an interface between bus 500 and receiver 501 and transmitter 503. Receiver 501 and transmitter 503 may be the same component, namely a transceiver, which provides a means for communicating with various other devices over a transmission medium. Processor 502 is responsible for managing bus 500 and general processing, while memory 504 may be used to store data used by processor 502 when performing operations.

[0162] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope and spirit of this application. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Furthermore, each functional unit may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit.

[0163] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only exemplary. For example, the division of the units can be a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0164] The units described as separate components may or may not be physically separate, and the components of the control device may or may not be physical units, that is, they may be located in one place or distributed across multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0165] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store computer program instructions, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0166] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A digital circuit engineering correction method, characterized in that: The method comprises: After completing the routing of the digital circuit, static timing analysis is performed based on actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit to obtain global timing information of each timing path, where the global timing information includes timing parameter values ​​of each logic unit in each timing path in at least one dimension; Obtaining a preset timing parameter threshold; if a timing parameter value of any logic unit in the digital circuit satisfies a preset magnitude relationship with the timing parameter threshold, determining the any logic unit as an abnormal logic unit, and determining the timing path to which the abnormal logic unit belongs as an abnormal timing path; Obtaining a pre-built exception list and an alternative list, wherein the exception list is used to record abnormal timing paths screened out from the digital circuit and abnormal logic units in the abnormal timing paths, and the alternative list is used to record configurable logic units of different unit types, wherein the unit types include functional units and filler units; Selecting a target abnormal timing path to be changed and a target abnormal logical unit in the target abnormal timing path from the abnormal list, determining a target change type of the logical unit, and selecting a logical unit to be placed from the candidate list; wherein the change type of the logical unit includes at least adding a logical unit, replacing a logical unit, and deleting a logical unit; Based on the logic unit to be placed and the target abnormal logic unit, according to the target change type, performing a logic unit change on the target abnormal timing path, and performing a wiring change on the digital circuit after the logic unit change; If the digital circuit after the wiring change is checked based on the design rule checking engine and no wiring violation exists, returning to the step of performing static timing analysis based on actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit until no abnormal timing path exists in the digital circuit; If the target change type is adding a logic unit, the logic unit to be placed is a first functional unit, and the logic unit change of the target abnormal timing path includes: Determine, on the target abnormal timing path, logical units within a preset radius centered on the target abnormal logical unit to obtain a logical unit list; traverse the sizes of the filling units in the logical unit list in sequence according to a set traversal order; when the size of any traversed filling unit is greater than or equal to the size of the first functional unit, or when the sum of the sizes of any group of sequentially adjacent filling units is greater than or equal to the size of the first functional unit, determine the site area occupied by the any one filling unit or the site area occupied by the any group of sequentially adjacent filling units as the target site area, where a site is a basic location unit on the timing path; Delete the filling unit of the target site area and place the first functional unit in the target site area; if the size of the target site area is larger than the size of the first functional unit, based on the size difference between the size of the target site area and the size of the first functional unit, search for one or more filling units from the alternative list according to the set search logic; combine the first functional unit with the one or more filling units to obtain a combined unit, and the size of the target site area is equal to the size of the combined unit; place the combined unit in the target site area.

2. The method according to claim 1, characterized in that The performing of static timing analysis based on actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit to obtain global timing information of each timing path includes: Based on the actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit, a static timing analysis engine is called to calculate the timing parameter values ​​of each logic unit in each timing path in at least one dimension as the global timing information of each timing path.

3. The method according to claim 1, characterized in that The method further comprises: If the first functional unit is a buffer unit, calculating a radius threshold based on a signal integrity analysis engine; The preset radius is determined, where the preset radius is greater than or equal to the radius threshold.

4. The method according to claim 1, wherein If the target change type is to replace a logic unit, the logic unit to be placed is a second functional unit that is adapted to the size of the target abnormal logic unit, and the logic unit change of the target abnormal timing path includes: The target abnormal logical unit is deleted, and the second functional unit is placed in the site area occupied by the target abnormal logical unit.

5. The method according to claim 1, wherein If the target change type is to delete a logical unit, the logical unit to be placed is a filler unit or a combination of filler units that is adapted to the size of the target abnormal logical unit, and the logical unit change of the target abnormal timing path includes: The target abnormal logical unit is deleted, and a filling unit or a combination of filling units that are adapted to the size of the target abnormal logical unit is placed in the site area occupied by the target abnormal logical unit.

6. The method according to claim 1, characterized in that The step of changing the wiring of the digital circuit after the logic unit is changed includes: Performing a local wiring change on the digital circuit after the logic unit change; or, A global wiring change is performed on the digital circuit after the logic unit change.

7. The method according to claim 6, characterized in that The locally changing the wiring of the digital circuit after the logic unit is changed includes: Taking a memory snapshot of the wiring data of other timing paths except the abnormal timing path, and clearing the wiring data of the abnormal timing path; The wiring data of the other timing paths in the memory are obtained, and based on the wiring data of the other timing paths, a three-dimensional wiring algorithm is called to rewire the abnormal timing path.

8. A digital circuit engineering correction device, characterized in that: The device comprises: an analysis unit configured to, after completing the routing of the digital circuit, perform static timing analysis based on actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit to obtain global timing information of each timing path, wherein the global timing information includes timing parameter values ​​of each logic unit in each timing path in at least one dimension; a screening unit configured to obtain a preset timing parameter threshold; if a timing parameter value of any logic unit in the digital circuit satisfies a preset magnitude relationship with the timing parameter threshold, determining the any logic unit as an abnormal logic unit, and determining the timing path to which the abnormal logic unit belongs as an abnormal timing path; A change unit is configured to obtain a pre-built exception list and an alternative list, wherein the exception list is configured to record abnormal timing paths and abnormal logic units in the abnormal timing paths screened out from the digital circuit, and the alternative list is configured to record configurable logic units of different unit types, wherein the unit types include functional units and filler units; select a target abnormal timing path to be changed and a target abnormal logic unit in the target abnormal timing path from the exception list, determine a target change type for the logic unit, and select a logic unit to be placed from the alternative list; wherein the change type for the logic unit includes at least adding a logic unit, replacing a logic unit, and deleting a logic unit; based on the logic unit to be placed and the target abnormal logic unit, perform a logic unit change on the target abnormal timing path according to the target change type, and perform a wiring change on the digital circuit after the logic unit change; a checking unit configured to return to the step of performing static timing analysis based on actual circuit resistance and capacitance parasitic parameters of each timing path in the digital circuit, if no wiring violation exists in the digital circuit after the wiring change is checked based on a design rule checking engine, until no abnormal timing path exists in the digital circuit; If the target change type is adding a logical unit, the logical unit to be placed is a first functional unit, and the logical unit change of the target abnormal timing path includes: Determine, on the target abnormal timing path, logical units within a preset radius centered on the target abnormal logical unit to obtain a logical unit list; traverse the sizes of the filling units in the logical unit list in sequence according to a set traversal order; when the size of any traversed filling unit is greater than or equal to the size of the first functional unit, or when the sum of the sizes of any group of sequentially adjacent filling units is greater than or equal to the size of the first functional unit, determine the site area occupied by the any one filling unit or the site area occupied by the any group of sequentially adjacent filling units as the target site area, where a site is a basic location unit on the timing path; Delete the filling unit of the target site area and place the first functional unit in the target site area; if the size of the target site area is larger than the size of the first functional unit, based on the size difference between the size of the target site area and the size of the first functional unit, search for one or more filling units from the alternative list according to the set search logic; combine the first functional unit with the one or more filling units to obtain a combined unit, and the size of the target site area is equal to the size of the combined unit; place the combined unit in the target site area.

9. A computer program product, characterized in that The computer program product includes computer instructions, which are stored in a computer-readable storage medium and are suitable for being read and executed by a processor, so as to enable a computer device having the processor to perform the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores at least one program code, and the at least one program code is loaded and executed by a processor to implement the operations performed by the method according to any one of claims 1 to 7.

11. An electronic device, characterized in that: The electronic device includes one or more processors and one or more memories, wherein at least one program code is stored in the one or more memories, and the at least one program code is loaded and executed by the one or more processors to implement the method according to any one of claims 1 to 7.

Images