Clock amplifier circuit and memory device including same

Abstract

A memory device includes: a memory cell array; an input / output circuit receiving data to be stored in the memory cell array based on a write clock signal received from an external device during a write operation; and a clock amplifier circuit that supplies the internal clock signal to the input / output circuit by amplifying the write clock signal, and includes a folded cascode amplifier that amplifies the write clock signal. The folded cascode amplifier amplifies a write clock signal according to a gain between an input unit and an output unit, and includes a gain adjustment unit connected to the output unit and increasing the gain between the input unit and the output unit based on the write clock signal.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0013355, filed with the Korean Intellectual Property Office on January 29, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure described herein relate to a semiconductor memory device, and more particularly, to a clock amplifier circuit and a memory device including the clock amplifier circuit. Background Art

[0004] Semiconductor memories can be mainly classified into volatile memories or non - volatile memories. Volatile memories (e.g., DRAM or SRAM) have fast read and write speeds, but the data stored in volatile memories disappears when the power is turned off. In contrast, non - volatile memories can retain data even when the power is turned off. Thus, non - volatile memories can be used to store content that must be preserved regardless of whether power is supplied.

[0005] A representative example of a volatile memory device is DRAM. A memory cell of a volatile memory device may include a single N - type transistor serving as a switch and a single capacitor for storing charge DATA. Binary information “1” or “0” may correspond to the presence or absence of charge in the capacitor stored in the memory cell, e.g., whether the terminal voltage of the cell capacitor is high or low. The memory cell may be connected to a word line and a bit line. The bit line may be connected to a sense amplifier. The sense amplifier may sense the data stored in the memory cell through the bit line based on the voltage applied to the word line.

[0006] A volatile memory device may receive data from a memory controller or send data to a memory controller through an input / output circuit. A volatile memory device may receive a write clock signal from the memory controller during a write operation. The input / output circuit of the volatile memory device may receive data based on the write clock signal during a write operation. However, the write clock signal attenuates during transmission and needs to be amplified inside the volatile memory device. Summary of the Invention

[0007] Example embodiments of the present disclosure provide a clock amplifier circuit and a memory device including the clock amplifier circuit, the clock amplifier circuit adjusting a gain based on a write clock signal when amplifying the write clock signal received from a memory controller during a write operation.

[0008] According to an embodiment, a memory device includes: a memory cell array; an input / output circuit that receives data to be stored in the memory cell array based on a write clock signal received from an external device during a write operation; and a clock amplifier circuit that provides an internal clock signal to the input / output circuit by amplifying the write clock signal, and includes a folded cascode amplifier that amplifies the write clock signal. The folded cascode amplifier amplifies the write clock signal according to a gain between an input unit and an output unit, and includes a gain adjustment unit that is connected to the output unit and increases the gain between the input unit and the output unit based on the write clock signal.

[0009] According to an embodiment, a folded cascode amplifier circuit includes: a differential input unit that receives a first differential input signal and a second differential input signal that are complementary to each other, and outputs a first differential current signal in which the first differential input signal is inverted and a second differential current signal in which the second differential input signal is inverted based on a first current source; a differential output unit that outputs a first differential amplified signal in response to the first differential current signal and outputs a second differential amplified signal in response to the second differential current signal; and a gain adjustment unit that determines a gain between the first differential input signal and the first differential amplified signal based on the second differential current signal and determines a gain between the second differential input signal and the second differential amplified signal based on the first differential current signal.

[0010] According to an embodiment, a folded cascode amplifier circuit includes: a first differential amplification unit that receives a first differential input signal and outputs a first differential amplified signal that is inverted and amplified from the first differential input signal; a second differential amplification unit that receives a second differential input signal complementary to the first differential input signal and outputs a second differential amplified signal that is inverted and amplified from the second differential input signal; a first DC gain adjustment unit that increases the DC gain of the first differential amplification unit based on the second differential input signal; a second DC gain adjustment unit that increases the DC gain of the second differential amplification unit based on the first differential input signal; a first AC gain adjustment unit that increases the AC gain of the first differential amplification unit based on the first differential input signal; and a second AC gain adjustment unit that increases the AC gain of the second differential amplification unit based on the second differential input signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects and features of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0012] Figure 1 is a block diagram showing a memory system according to an exemplary embodiment.

[0013] Figure 2 is showingFigure 1 Block diagram of a memory device.

[0014] Figure 3 is to show Figure 2 Block diagram of an exemplary embodiment of a clock amplifier circuit.

[0015] Figure 4 is to show Figure 3 Circuit diagram of an exemplary embodiment of a folded cascode amplifier.

[0016] Figure 5 is to show Figure 4 Diagram of an exemplary embodiment of the amplification operation of a folded cascode amplifier.

[0017] Figure 6 is to show Figure 3 Circuit diagram of another example of a folded cascode amplifier.

[0018] Figure 7 is to show Figure 6 Diagram of an exemplary embodiment of the amplification operation of a folded cascode amplifier.

[0019] Figure 8 is to show Figure 6 Diagram of an exemplary embodiment of a first main resistor and a first sub-resistor.

[0020] Figure 9 is to show Figure 3 Circuit diagram of another example of a folded cascode amplifier.

[0021] Figure 10 is to show Figure 9 Diagram of an exemplary embodiment of the amplification operation of a folded cascode amplifier.

[0022] Figure 11 is to show Figure 3 Circuit diagram of another example of a folded cascode amplifier. Detailed Description

[0023] Hereinafter, exemplary embodiments of the present disclosure will be described in detail and clearly to the extent that a person of ordinary skill in the art can easily implement the inventive concept.

[0024] Hereinafter, DRAM will be used as an example to illustrate the features and functions of the present disclosure. However, a person of ordinary skill in the art can easily understand other features and performances based on the information disclosed herein. The present disclosure can be implemented by other embodiments or applied to other embodiments. In addition, without departing from the scope, spirit, and other purposes of the present disclosure, the detailed description can be modified or changed according to viewpoints and applications.

[0025] Figure 1 is a block diagram showing a memory system according to an exemplary embodiment. Refer to Figure 1 , the memory system 1000 may include a memory controller 1100 and a memory device 1200.

[0026] According to an exemplary embodiment, the memory controller 1100 may perform access operations of writing data to the memory device 1200 or reading data stored in the memory device 1200. For example, the memory controller 1100 may generate a command CMD and an address ADDR for writing data to the memory device 1200 or reading data stored in the memory device 1200. The memory controller 1100 may include a control circuit for controlling the memory device 1200, at least one of a system-on-chip (SoC) such as an application processor (AP), a central processing unit (CPU), a digital signal processor (DSP), and a graphics processing unit (GPU).

[0027] According to an exemplary embodiment, the memory controller 1100 may provide various signals for controlling the overall operation of the memory device 1200. For example, the memory controller 1100 may control memory access operations of the memory device 1200, such as read operations and write operations. The memory controller 1100 may provide a command CMD and an address ADDR to the memory device 1200 to write data DATA to the memory device 1200 or read data DATA from the memory device 1200.

[0028] According to an exemplary embodiment, the memory controller 1100 may generate various types of commands CMD for controlling the memory device 1200. For example, the memory controller 1100 may generate a bank request corresponding to a bank operation of changing the state of a bank among memory banks to read or write data DATA.

[0029] As an example, the bank request may include an activation request for changing the state of a bank among banks to an active state. The memory device 1200 may activate a row included in the bank, such as a word line, in response to the activation request. The bank request may include a precharge request for changing the bank from the active state to a standby state after completion of reading or writing data DATA.

[0030] In addition, the memory controller 1100 may generate an input / output (I / O) request (e.g., a column address strobe (CAS) request) for the memory device 1200 to perform a read operation or a write operation on the data DATA. As an example, the I / O request may include a read request for reading the data DATA from an activated bank. The I / O request may include a write request for writing the data DATA to an activated bank.

[0031] In addition, the memory controller 1100 may generate a refresh command for controlling a refresh operation for a bank. However, the various types of commands CMD described herein are merely exemplary, and there may be other types of commands CMD.

[0032] According to an exemplary embodiment, the memory device 1200 may output the data DATA requested to be read by the memory controller 1100 to the memory controller 1100, or may store the data DATA requested to be written by the memory controller 1100 in the memory cells of the memory device 1200. The memory device 1200 may input and output the data DATA based on the command CMD and the address ADDR. The memory device 1200 may include a bank.

[0033] The memory device 1200 may be a volatile memory device such as a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate (DDR) DRAM, a DDR SDRAM, a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), and a static random access memory (SRAM), etc. Alternatively, the memory device 1200 may be implemented as a non-volatile memory device such as a resistive RAM (RRAM), a phase change memory (PRAM), a magnetoresistive memory (MRAM), a ferroelectric memory (FRAM), a spin transfer torque RAM (STT-RAM), etc. In this specification, the advantages of the present disclosure have been described with respect to DRAM, but the exemplary embodiments are not limited thereto.

[0034] According to an exemplary embodiment, a bank may include a memory cell array divided in units of banks, a row decoder, a column decoder, a sense amplifier, a write driver, etc. The bank may store the data DATA requested to be written to the memory device 1200 through the write driver, and may read the data DATA requested to be read using the sense amplifier. The bank may also include a component for a refresh operation for storing and maintaining data in the cell array, or a selection circuit based on an address.

[0035] According to an example embodiment, the memory device 1200 may include a clock amplifier circuit 100. For example, during a write operation, the memory device 1200 may receive a write clock signal WCK from the memory controller 1100. The clock amplifier circuit 100 may amplify the write clock signal WCK and output an internal write clock signal. The input / output circuit of the memory device 1200 may perform a write operation on the data DATA received from the memory controller 1100 based on the internal write clock signal.

[0036] Figure 2 is a block diagram of the Figure 1 memory device shown. Referring to Figure 2 , the memory device 1200 may include a memory cell array 1210, an address buffer 1220, a row decoder 1221, a column decoder 1222, a bit line sense amplifier 1230, a command decoder 1240, a control logic 1250, and an input / output circuit 1260. In addition, the memory device 1200 may include a clock amplifier circuit 100.

[0037] According to an example embodiment, the memory cell array 1210 may include a plurality of memory cells arranged in a matrix of rows and columns. For example, the memory cell array 1210 may include a plurality of word lines WL and a plurality of bit lines BL connected to the memory cells. The plurality of word lines WL may be connected to the rows of the memory cells, and the plurality of bit lines BL may be connected to the columns of the memory cells.

[0038] According to an example embodiment, the address buffer 1220 may receive an address ADDR from Figure 1 the memory controller 1100. For example, the address ADDR may include a row address RA for addressing the rows of the memory cell array 1210 and a column address CA for addressing the columns of the memory cell array 1210. The address buffer 1220 may send the row address RA to the row decoder 1221 and may send the column address CA to the column decoder 1222.

[0039] According to an example embodiment, the row decoder 1221 may select one word line WL from the plurality of word lines WL connected to the memory cell array 1210. The row decoder 1221 may decode the row address RA received from the address buffer 1220 to select a single word line corresponding to the row address RA and may activate the selected word line.

[0040] According to an example embodiment, the column decoder 1222 may select a predetermined bit line from the plurality of bit lines BL of the memory cell array 1210. The column decoder 1222 may decode the column address CA received from the address buffer 1220 to select a predetermined bit line BL corresponding to the column address CA.

[0041] According to an example embodiment, the bit line sense amplifier 1230 may be connected to the bit lines BL of the memory cell array 1210. For example, the bit line sense amplifier 1230 may sense a voltage change of a selected bit line among a plurality of bit lines BL, and may amplify and output the voltage change.

[0042] According to an example embodiment, the command decoder 1240 may decode the write enable signal / WE, row address strobe signal / RAS, column address strobe signal / CAS, and chip select signal / CS received from the memory controller 1100, such that control signals corresponding to the command CMD are generated in the control logic 1250. The command CMD may include an activation request, a read request, a write request, or a precharge request.

[0043] According to an example embodiment, the control logic 1250 may control the overall operation of the bit line sense amplifier 1230 through control signals corresponding to the command CMD. In addition, the control logic 1250 may control the overall operation of the memory device 1200.

[0044] According to an example embodiment, the input / output circuit 1260 may output data DATA to the memory controller 1100 through a data pad based on the voltage sensed and amplified by the bit line sense amplifier 1230. For example, the input / output circuit 1260 may include an input buffer or an output buffer. The input buffer or the output buffer may be connected to the data pad. The input / output circuit 1260 may perform a serialization operation or a deserialization operation on the data DATA.

[0045] According to an example embodiment, the clock amplifier circuit 100 may amplify the write clock signal WCK and output an internal write clock signal IWCK. For example, during a write operation, the memory device 1200 may receive the write clock signal WCK from the memory controller 1100. The clock amplifier circuit 100 may amplify the write clock signal WCK, which attenuates during transmission from the memory controller 1100. In addition, the clock amplifier circuit 100 may divide the write clock signal WCK to generate the internal write clock signal IWCK. The input / output circuit 1260 may transfer the data DATA received from the memory controller 1100 to the bit line sense amplifier 1230 based on the internal write clock signal IWCK.

[0046] Figure 3 is a block diagram showing Figure 2 an example embodiment of the clock amplifier circuit. Refer to Figure 2 and Figure 3 The clock amplifier circuit 100 may amplify the received from Figure 1receives the write clock signal WCK received by the memory controller 1100 and outputs an internal write clock signal IWCK. The clock amplifier circuit 100 may include a folded cascode amplifier 110, a current mode logic 120, and / or a current mode logic (CML) divider 130.

[0047] According to an example embodiment, the folded cascode amplifier 110 may amplify the write clock signal WCK and output a first amplified clock signal ACK1. The write clock signal WCK may attenuate when being sent from the memory controller 1100 to the memory device 1200. The folded cascode amplifier 110 may primarily amplify the write clock signal WCK.

[0048] According to an example embodiment, the current mode logic 120 may amplify the first amplified clock signal ACK1 and output a second amplified clock signal ACK2. The current mode logic 120 may secondly amplify the first amplified clock signal ACK1 to a size required in the memory device 1200. In addition, the current mode logic 120 may process the first amplified clock signal ACK1 such that the high level and the low level of the first amplified clock signal ACK1 are clearly distinguished.

[0049] According to an example embodiment, the CML divider 130 may change the frequency of the second amplified clock signal ACK2 to output the internal write clock signal IWCK. During a write operation, the CML divider 130 may divide the second amplified clock signal ACK2 to correspond to the frequency used in the input / output circuit 1260.

[0050] Figure 4 is a circuit diagram showing Figure 3 an example embodiment of the folded cascode amplifier. Referring to Figure 4 , the folded cascode amplifier 110 may include an input unit 111 and an output unit 112. The folded cascode amplifier 110 may amplify a differential input signal (e.g., the write clock signal WCK and the complementary write clock signal WCKB) based on a specified gain between the input unit 111 and the output unit 112 to output a differential output signal (e.g., the first amplified clock signal ACK1 and the first complementary amplified clock signal ACKB1). The input unit 111 and the output unit 112 may include a mirror structure that amplifies a pair of differential signals.

[0051] According to an exemplary embodiment, the input unit 111 may include a first P-type transistor PM1 and a second P-type transistor PM2. For example, the sources of the first P-type transistor PM1 and the second P-type transistor PM2 may be connected to a current source Ib. The gate of the first P-type transistor PM1 may be connected to an input terminal IN. The drain of the first P-type transistor PM1 may be connected to a first node N1. The gate of the second P-type transistor PM2 may be connected to a complementary input terminal INB. The drain of the second P-type transistor PM2 may be connected to a second node N2.

[0052] According to an exemplary embodiment, the output unit 112 may include a first N-type transistor NM1 and a second N-type transistor NM2. For example, the gates of the first N-type transistor NM1 and the second N-type transistor NM2 may be connected to a terminal of a first bias voltage Vb1. The drain of the first N-type transistor NM1 may be connected to a complementary output terminal OUTB. The source of the first N-type transistor NM1 may be connected to the first node N1. The drain of the second N-type transistor NM2 may be connected to an output terminal OUT. The source of the second N-type transistor NM2 may be connected to the second node N2.

[0053] In addition, the output unit 112 may include a first main resistor Rm1 and a second main resistor Rm2. For example, the first main resistor Rm1 may be connected between a terminal of a power supply voltage VDD and the complementary output terminal OUTB. The second main resistor Rm2 may be connected between the terminal of the power supply voltage VDD and the output terminal OUT.

[0054] According to an exemplary embodiment, a third N-type transistor NM3 may operate as a current source for the first N-type transistor NM1. For example, the gate of the third N-type transistor NM3 may be connected to a terminal of a second bias voltage Vb2. The drain of the third N-type transistor NM3 may be connected to the first node N1. The source of the third N-type transistor NM3 may be connected to a ground terminal.

[0055] According to an exemplary embodiment, a fourth N-type transistor NM4 may operate as a current source for the second N-type transistor NM2. For example, the gate of the fourth N-type transistor NM4 may be connected to the terminal of the second bias voltage Vb2. The drain of the fourth N-type transistor NM4 may be connected to the second node N2. The source of the fourth N-type transistor NM4 may be connected to the ground terminal.

[0056] Figure 5 is a diagram Figure 4 illustrating an exemplary embodiment of the amplification operation of a folded cascode amplifier. Refer to Figure 4 and Figure 5, the folded cascode amplifier 110 may perform an amplification operation based on a specified gain between the input unit 111 and the output unit 112. As an example, the differential input signal may be a write clock signal WCK and a complementary write clock signal WCKB. The differential output signal may be a first amplified clock signal ACK1 and a first complementary amplified clock signal ACKB1. Thus, the input unit 111 may also be referred to as a differential input unit, and the output unit 112 may also be referred to as a differential output unit.

[0057] According to an example embodiment, in the first node N1, a first current I1 may be determined by a third N-type transistor NM3. A second current I2 may be determined by a first P-type transistor PM1. A third current I3 may be determined by a difference between the first current I1 and the second current I2.

[0058] According to an example embodiment, in the second node N2, a fourth current I4 may be determined by a fourth N-type transistor NM4. A fifth current I5 may be determined by a second P-type transistor PM2. A sixth current I6 may be determined by a difference between the fourth current I4 and the fifth current I5.

[0059] According to an example embodiment, the write clock signal WCK may be input to the input terminal IN. The complementary write clock signal WCKB may be input to the complementary input terminal INB. For example, the write clock signal WCK and the complementary write clock signal WCKB may have a first voltage amplitude V1. In Figure 5 , the write clock signal WCK switches from a high level to a low level, while the complementary write clock signal WCKB switches from a low level to a high level.

[0060] According to an example embodiment, when the write clock signal WCK that switches from a high level to a low level is input, the first P-type transistor PM1 may be gradually turned on, and the second current I2 may have a waveform complementary to the waveform of the write clock signal WCK. Thus, in response to an increase in the second current I2, the third current I3 may have a decreasing waveform. Since the third current I3 flowing through the first main resistor Rm1 decreases, the complementary output terminal OUTB may output a first complementary amplified clock signal ACKB1 that switches from a low level to a high level.

[0061] According to an example embodiment, the first complementary amplified clock signal ACKB1 may have a second voltage amplitude V2 greater than the first voltage amplitude V1. The second voltage amplitude V2 may be determined by a gain between the first P-type transistor PM1 and the first N-type transistor NM1. In addition, since the first N-type transistor NM1 is turned on by a fixed first bias voltage Vb1, the second voltage amplitude V2 may be determined by a fixed gain.

[0062] According to an exemplary embodiment, when a complementary write clock signal WCKB that switches from a low level to a high level is input, the second P-type transistor PM2 can be gradually turned off, and the fifth current I5 can have a waveform complementary to the waveform of the complementary write clock signal WCKB. Accordingly, in response to the decrease in the fifth current I5, the sixth current I6 can have an increasing waveform. Since the sixth current I6 flowing through the second main resistor Rm2 increases, the output terminal OUT can output a first amplified clock signal ACK1 that switches from a high level to a low level.

[0063] According to an exemplary embodiment, the first amplified clock signal ACK1 can have a second voltage amplitude V2 greater than the first voltage amplitude V1. The second voltage amplitude V2 can be determined by the gain between the second P-type transistor PM2 and the second N-type transistor NM2. In addition, since the second N-type transistor NM2 is turned on by a fixed first bias voltage Vb1, the second voltage amplitude V2 can be determined by a fixed gain.

[0064] However, Figure 4 and Figure 5 the folded cascode amplifier 110 of may have a fixed gain between the input unit 111 and the output unit 112, and when the magnitude of the input signal (e.g., the write clock signal WCK and the complementary write clock WCKB) decreases, the magnitude of the output signal (e.g., the first amplified clock signal ACK1 and the first complementary amplified clock signal ACKB1) can also decrease at the same rate. Accordingly, the second amplified clock signal ACK2 output by the current mode logic 120 may also decrease, and an error may occur in the CML frequency divider 130 of Figure 3

[0065] Figure 6 is a circuit diagram showing another example of the folded cascode amplifier of Figure 3 Figure 6 Referring to, the folded cascode amplifier 110 can include an input unit 111 and an output unit 112. The folded cascode amplifier 110 can further include a gain adjustment unit 113. The gain adjustment unit 113 can include a first gain adjustment unit 113a and a second gain adjustment unit 113b.

[0066] According to an exemplary embodiment, the folded cascode amplifier 110 can amplify an input signal (e.g., the write clock signal WCK and the complementary write clock signal WCKB) based on the gain between the input unit 111 and the output unit 112 to output an output signal (e.g., the first amplified clock signal ACK1 and the first complementary amplified clock signal ACKB1). The gain between the input unit 111 and the output unit 112 can be changed based on the amplitude of the input signal.

[0067] According to an exemplary embodiment, the input unit 111 may include a first P-type transistor PM1 and a second P-type transistor PM2. For example, the sources of the first P-type transistor PM1 and the second P-type transistor PM2 may be connected to a current source Ib. The gate of the first P-type transistor PM1 may be connected to an input terminal IN. The drain of the first P-type transistor PM1 may be connected to a first node N1. The gate of the second P-type transistor PM2 may be connected to a complementary input terminal INB. The drain of the second P-type transistor PM2 may be connected to a second node N2.

[0068] According to an exemplary embodiment, the output unit 112 may include a first N-type transistor NM1. For example, the drain of the first N-type transistor NM1 may be connected to a complementary output terminal OUTB. The source of the first N-type transistor NM1 may be connected to the first node N1. The gate of the first N-type transistor NM1 may be connected to a third node N3.

[0069] In addition, the output unit 112 may include a second N-type transistor NM2. For example, the drain of the second N-type transistor NM2 may be connected to an output terminal OUT. The source of the second N-type transistor NM2 may be connected to the second node N2. The gate of the second N-type transistor NM2 may be connected to a fourth node N4.

[0070] In addition, the output unit 112 may include a first main resistor Rm1 and a second main resistor Rm2. For example, the first main resistor Rm1 may be connected between a terminal of a power supply voltage VDD and the complementary output terminal OUTB. The second main resistor Rm2 may be connected between the terminal of the power supply voltage VDD and the output terminal OUT. The first P-type transistor PM1, the first N-type transistor NM1, and the first main resistor Rm1 may be collectively referred to as a first differential amplification unit herein. The second P-type transistor PM2, the second N-type transistor NM2, and the second main resistor Rm2 may be collectively referred to as a second differential amplification unit herein.

[0071] According to an exemplary embodiment, the first gain adjustment unit 113a may include a fifth N-type transistor NM5 and a first sub-resistor Rs1. For example, the gate and the drain of the fifth N-type transistor NM5 may be connected to the third node N3. The source of the fifth N-type transistor NM5 may be connected to the second node N2. The first sub-resistor Rs1 may be connected between the terminal of the power supply voltage VDD and the third node N3.

[0072] According to an exemplary embodiment, the second gain adjustment unit 113b may include a sixth N-type transistor NM6 and a second sub-resistor Rs2. For example, the gate and drain of the sixth N-type transistor NM6 may be connected to the fourth node N4. The source of the sixth N-type transistor NM6 may be connected to the first node N1. The second sub-resistor Rs2 may be connected between the terminal of the power supply voltage VDD and the fourth node N4. The first gain adjustment unit 113a may also be referred to as the first DC gain adjustment unit herein. The second gain adjustment unit 113b may also be referred to as the second DC gain adjustment unit herein.

[0073] According to an exemplary embodiment, the third N-type transistor NM3 may operate as a current source for the first N-type transistor NM1. For example, the gate of the third N-type transistor NM3 may be connected to the terminal of the second bias voltage Vb2. The drain of the third N-type transistor NM3 may be connected to the first node N1. The source of the third N-type transistor NM3 may be connected to the ground terminal.

[0074] According to an exemplary embodiment, the fourth N-type transistor NM4 may operate as a current source for the second N-type transistor NM2. For example, the gate of the fourth N-type transistor NM4 may be connected to the terminal of the second bias voltage Vb2. The drain of the fourth N-type transistor NM4 may be connected to the second node N2. The source of the fourth N-type transistor NM4 may be connected to the ground terminal.

[0075] Figure 7 is a diagram Figure 6 showing an exemplary embodiment of the amplification operation of a folded cascode amplifier. Referring to Figure 6 and Figure 7 , the folded cascode amplifier 110 may perform an amplification operation based on the gain between the input unit 111 and the output unit 112. The gain between the input unit 111 and the output unit 112 may be changed based on the amplitude of the input signal. As an example, the differential input signal may be a write clock signal WCK and a complementary write clock signal WCKB. The differential output signal may be a first amplified clock signal ACK1 and a first complementary amplified clock signal ACKB1.

[0076] According to an exemplary embodiment, in the first node N1, the first current I1 may be determined by the third N-type transistor NM3. The second current I2 may be determined by the first P-type transistor PM1. The third current I3 and the eighth current I8 may be determined by the difference between the first current I1 and the second current I2.

[0077] According to an exemplary embodiment, in the second node N2, the fourth current I4 may be determined by the fourth N-type transistor NM4. The fifth current I5 may be determined by the second P-type transistor PM2. The sixth current I6 and the seventh current I7 may be determined by the difference between the fourth current I4 and the fifth current I5.

[0078] According to an exemplary embodiment, the write clock signal WCK may be input to the input terminal IN. The complementary write clock signal WCKB may be input to the complementary input terminal INB. For example, the write clock signal WCK and the complementary write clock signal WCKB may have a first voltage amplitude V1. In Figure 7 this case, the write clock signal WCK may switch from a high level to a low level, while the complementary write clock signal WCKB may switch from a low level to a high level.

[0079] According to an exemplary embodiment, when the write clock signal WCK that switches from a high level to a low level is input, the first P-type transistor PM1 may gradually turn on, and the second current I2 may have a waveform complementary to the waveform of the write clock signal WCK. Therefore, in response to the increase in the second current I2, the third current I3 and the eighth current I8 may have a decreasing waveform. Since the third current I3 flowing through the first main resistor Rm1 decreases, the complementary output terminal OUTB may output the first complementary amplified clock signal ACKB1 that switches from a low level to a high level.

[0080] According to an exemplary embodiment, the first gain adjustment unit 113a may increase the gain of the amplifier including the first P-type transistor PM1 and the first N-type transistor NM1 based on the signal of the complementary input terminal INB. For example, when the write clock signal WCK switches from a high level to a low level, the complementary write clock signal WCKB may switch from a low level to a high level, and the fifth current I5 flowing through the second P-type transistor PM2 may decrease. When the fifth current I5 decreases, the seventh current I7 flowing through the fifth N-type transistor NM5 and / or the first sub-resistor Rs1 may increase, and the voltage level of the third node N3 may decrease. Therefore, the voltage difference between the gate and the source of the first N-type transistor NM1 may decrease, and the third current I3 flowing through the first N-type transistor NM1 and / or the first main resistor Rm1 may further decrease.

[0081] Therefore, the first complementary amplified clock signal ACKB1 may have a third voltage amplitude V3 greater than Figure 5 the second voltage amplitude V2. The gate voltage of the first N-type transistor NM1 may change in response to the complementary write clock signal WCKB, and the gain of the amplifier including the first P-type transistor PM1 and the first N-type transistor NM1 may increase from Figure 5 the gain shown.

[0082] According to an exemplary embodiment, when a complementary write clock signal WCKB that switches from a low level to a high level is input, the second P-type transistor PM2 may be gradually turned off, and the fifth current I5 may have a waveform complementary to the waveform of the complementary write clock signal WCKB. Accordingly, in response to the decrease in the fifth current I5, the sixth current I6 and the seventh current I7 may have an increasing waveform. Since the sixth current I6 flowing through the second main resistor Rm2 increases, the output terminal OUT may output a first amplified clock signal ACK1 that switches from a high level to a low level.

[0083] According to an exemplary embodiment, the second gain adjustment unit 113b may increase the gain of an amplifier including the second P-type transistor PM2 and the second N-type transistor NM2 based on a signal from the input terminal IN. For example, when the complementary write clock signal WCKB switches from a low level to a high level, the write clock signal WCK may switch from a high level to a low level, and the second current I2 flowing through the first P-type transistor PM1 may increase. When the second current I2 increases, the eighth current I8 flowing through the sixth N-type transistor NM6 and the second sub-resistor Rs2 may decrease, and the voltage level of the fourth node N4 may increase. At this time, the voltage difference between the gate and the source of the second N-type transistor NM2 may increase, and the sixth current I6 flowing through the second N-type transistor NM2 and the second main resistor Rm2 may further increase.

[0084] Accordingly, the first amplified clock signal ACK1 may have a third voltage amplitude V3 that is greater than Figure 5 the second voltage amplitude V2. The gate voltage of the second N-type transistor NM2 may change in response to the write clock signal WCK, and the gain of the amplifier including the second P-type transistor PM2 and the second N-type transistor NM2 may increase from Figure 5 the gain shown.

[0085] According to an exemplary embodiment, the gain of the folded cascode amplifier 110 may be determined based on the ratio of the main resistor and the sub-resistor. For example, the gain of the amplifier including the first P-type transistor PM1 and the first N-type transistor NM1 may be determined according to the ratio of the resistance of the first main resistor Rm1 and the resistance of the first sub-resistor Rs1. The gain of the amplifier including the second P-type transistor PM2 and the second N-type transistor NM2 may be determined according to the ratio of the resistance of the second main resistor Rm2 and the resistance of the second sub-resistor Rs2.

[0086] Figure 8 is a diagram showing Figure 6 an exemplary embodiment of the first main resistor and the first sub-resistor. Refer to Figure 8, the first sub-resistor Rs1 may include a plurality of sub-resistors Rs11 to Rs1n. Each of the plurality of sub-resistors Rs11 to Rs1n may be connected to a terminal of the power supply voltage VDD through each of a plurality of resistive switches SW1 to SWn. The plurality of sub-resistors Rs11 to Rs1n may be connected in parallel between the terminal of the power supply voltage VDD and the third node N3.

[0087] According to an exemplary embodiment, the folded cascode amplifier 110 may change the gain. For example, the folded cascode amplifier 110 may change the magnitude of the first sub-resistor Rs1 through a plurality of resistive switches SW1 to SWn. When the magnitude of the first sub-resistor Rs1 changes, the ratio between the resistance of the first main resistor Rm1 and the resistance of the first sub-resistor Rs1 may change, and the gain of the amplifier including the first P-type transistor PM1 and the first N-type transistor NM1 may change.

[0088] Although Figure 8 the first sub-resistor Rs1 is shown as an example, Figure 6 the second sub-resistor Rs2 may also include a plurality of sub-resistors. Each of the plurality of sub-resistors included in the second sub-resistor Rs2 may be connected to a terminal of the power supply voltage VDD through a plurality of resistive switches. The plurality of sub-resistors included in the second sub-resistor Rs2 may be connected in parallel between the terminal of the power supply voltage VDD and the fourth node N4.

[0089] Figure 9 is a circuit diagram showing Figure 3 another example of the folded cascode amplifier. Figure 10 is a diagram showing Figure 9 an exemplary embodiment of the amplification operation of the folded cascode amplifier. Referring to Figure 9 and Figure 10 , the first gain adjustment unit 113a may include a first peak resistor Rpk1. The second gain adjustment unit 113b may include a second peak resistor Rpk2.

[0090] According to an exemplary embodiment, the folded cascode amplifier 110 may include the same or similar configuration and features as the Figure 6 folded cascode amplifier 110. Therefore, a description of the configuration and features that are the same as or similar to those of the Figure 6 folded cascode amplifier 110 will be omitted.

[0091] According to an exemplary embodiment, the first peak resistor Rpk1 may be connected between the gate of the fifth N-type transistor NM5 and the third node N3. The voltage of the third node N3 may change as the seventh current I7 increases or decreases. However, parasitic capacitors may exist in the third node N3. Due to the parasitic capacitors, the voltage of the third node N3 may change more slowly compared to the change in the seventh current I7.

[0092] According to an exemplary embodiment, the first peak resistor Rpk1 may cause a difference between the voltage of the gate of the fifth N-type transistor NM5 and the voltage of the third node N3 within a specified time. Thus, the parasitic capacitors may be charged by the seventh current I7 within the specified time. After the specified time has elapsed, the voltage of the third node N3 may change rapidly.

[0093] According to an exemplary embodiment, the second peak resistor Rpk2 may be connected between the gate of the sixth N-type transistor NM6 and the fourth node N4. The voltage of the fourth node N4 may change as the eighth current I8 increases or decreases. However, parasitic capacitors may exist in the fourth node N4. Due to the parasitic capacitors, the voltage of the fourth node N4 may change more slowly compared to the change in the eighth current I8.

[0094] According to an exemplary embodiment, the second peak resistor Rpk2 may cause a difference between the voltage of the gate of the sixth N-type transistor NM6 and the voltage of the fourth node N4 within a specified time. Thus, the parasitic capacitors may be charged by the eighth current I8 within the specified time. After the specified time has elapsed, the voltage of the fourth node N4 may change rapidly.

[0095] Figure 11 is a circuit diagram showing Figure 3 another example of a folded cascode amplifier. Referring Figure 11 , the folded cascode amplifier 110 may include a first AC gain controller 114a and a second AC gain controller 114b. Herein, the first AC gain controller 114a may also be referred to as the first AC gain adjustment unit, and the second AC gain controller 114b may also be referred to as the second AC gain adjustment unit.

[0096] According to an exemplary embodiment, the folded cascode amplifier 110 may include the same or similar configurations and features as the Figure 9 folded cascode amplifier 110. Thus, the description of the configurations and features that are the same as or similar to those of the Figure 9 folded cascode amplifier 110 will be omitted.

[0097] According to an exemplary embodiment, the first AC gain controller 114a may be connected between the drain and the gate of the third N-type transistor NM3. For example, the first AC gain controller 114a may include a first capacitor C1, a third sub-resistor Rs3, and / or a seventh N-type transistor NM7. The first AC gain controller 114a may increase the AC gain of an amplifier including a first P-type transistor PM1 and a first N-type transistor NM1.

[0098] According to an exemplary embodiment, the first capacitor C1 may be connected between the input terminal IN and the fifth node N5. The third sub-resistor Rs3 may be connected between the gate of the third N-type transistor NM3 and the fifth node N5. The drain of the seventh N-type transistor NM7 may be connected to the first node N1. The gate of the seventh N-type transistor NM7 may be connected to the fifth node N5. The source of the seventh N-type transistor NM7 may be connected to the ground terminal.

[0099] According to an exemplary embodiment, the second AC gain controller 114b may be connected between the drain and the gate of the fourth N-type transistor NM4. For example, the second AC gain controller 114b may include a second capacitor C2, a fourth sub-resistor Rs4, and / or an eighth N-type transistor NM8. The second AC gain controller 114b may increase the AC gain of an amplifier including a second P-type transistor PM2 and a second N-type transistor NM2.

[0100] According to an exemplary embodiment, the second capacitor C2 may be connected between the complementary input terminal INB and the sixth node N6. The fourth sub-resistor Rs4 may be connected between the gate of the fourth N-type transistor NM4 and the sixth node N6. The drain of the eighth N-type transistor NM8 may be connected to the second node N2. The gate of the eighth N-type transistor NM8 may be connected to the sixth node N6. The source of the eighth N-type transistor NM8 may be connected to the ground terminal.

[0101] According to the present disclosure, the gain of the clock amplifier circuit may be adjusted based on a write clock signal received from a memory controller.

[0102] Although the present disclosure has been described with reference to embodiments of the present disclosure, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made to the present disclosure without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A memory device, comprising: A memory cell array; An input / output circuit configured to receive data to be stored in the memory cell array based on a write clock signal received from an external device during a write operation; And A clock amplifier circuit configured to provide an internal clock signal to the input / output circuit by amplifying the write clock signal, and including a folded cascode amplifier that amplifies the write clock signal, Wherein the folded cascode amplifier is configured to amplify the write clock signal according to a gain between an input unit and an output unit, and includes a gain adjustment unit that is connected to the output unit and increases the gain between the input unit and the output unit based on the write clock signal.

2. The memory device according to claim 1, wherein, The clock amplifier circuit includes: The folded cascode amplifier configured to amplify the write clock signal and output a first amplified clock signal; A current mode logic (CML) configured to amplify the first amplified clock signal and output a second amplified clock signal; and A CML frequency divider configured to divide the second amplified clock signal to output the internal clock signal.

3. The memory device according to claim 1, wherein, The input unit includes: A first P-type transistor configured to include a gate to which the write clock signal is applied, a source connected to a first current source, and a drain connected to a first node; and A second P-type transistor configured to include a gate to which a complementary write clock signal is applied, a source connected to the first current source, and a drain connected to a second node.

4. The memory device according to claim 3, wherein, The output unit includes: A first N-type transistor configured to include a gate connected to a third node, a drain connected to a first main resistor, and a source connected to the first node; and A second N-type transistor configured to include a gate connected to a fourth node, a drain connected to a second main resistor, and a source connected to the second node, Wherein the drain of the first N-type transistor is configured to output a complementary amplified clock signal that is inverted and amplified from the write clock signal, and Wherein the drain of the second N-type transistor is configured to output an amplified clock signal that is inverted and amplified from the complementary write clock signal.

5. The memory device according to claim 4, wherein, The gain adjustment unit includes a first gain adjustment unit and a second gain adjustment unit, Wherein the first gain adjustment unit includes: A third N-type transistor configured to include a source connected to the second node and a drain and a gate connected to the third node; and A first sub-resistor connected between a power supply voltage terminal and the third node, and Wherein the second gain adjustment unit includes: A fourth N-type transistor configured to include a source connected to the first node and a drain and a gate connected to the fourth node; and A second sub-resistor connected between the power supply voltage terminal and the fourth node.

6. The memory device according to claim 4, wherein, The first main resistor is connected between the power supply voltage terminal and the drain of the first N-type transistor, and Wherein the second main resistor is connected between the power supply voltage terminal and the drain of the second N-type transistor.

7. The memory device according to claim 4, wherein, The first node is connected to a second current source, and wherein, the second node is connected to a third current source.

8. A folded cascode amplifier circuit, comprising: A differential input unit configured to receive a first differential input signal and a second differential input signal that are complementary to each other, and output a first differential current signal in which the first differential input signal is inverted and a second differential current signal in which the second differential input signal is inverted based on a first current source; A differential output unit configured to output a first differential amplified signal in response to the first differential current signal and output a second differential amplified signal in response to the second differential current signal; And A gain adjustment unit configured to determine a gain between the first differential input signal and the first differential amplified signal based on the second differential current signal, and determine a gain between the second differential input signal and the second differential amplified signal based on the first differential current signal.

9. The folded cascode amplifier circuit according to claim 8, wherein, The differential input unit includes: A first P-type transistor configured to include a source connected to the first current source, a gate to which the first differential input signal is applied, and a drain connected to the second current source; and A second P-type transistor configured to include a source connected to the first current source, a gate to which the second differential input signal is applied, and a drain connected to the third current source.

10. The folded cascode amplifier circuit according to claim 8, wherein, The differential output unit includes: A first N-type transistor configured to include a drain from which the first differential amplified signal is output, a source connected to the second current source, and a gate whose voltage varies based on the second differential input signal; A second N-type transistor configured to include a drain from which the second differential amplified signal is output, a source connected to the third current source, and a gate whose voltage varies based on the first differential input signal; A first main resistor connected between a power supply voltage terminal and the drain of the first N-type transistor; and A second main resistor connected between the power supply voltage terminal and the drain of the second N-type transistor.

11. The folded cascode amplifier circuit according to claim 10, wherein, The gain adjustment unit includes: A third N-type transistor configured to include a drain and a gate connected to the gate of the first N-type transistor and a source connected to the third current source; A fourth N-type transistor configured to include a drain and a gate connected to the gate of the second N-type transistor and a source connected to the second current source; A first sub-resistor connected between the power supply voltage terminal and the drain of the third N-type transistor; and A second sub-resistor connected between the power supply voltage terminal and the drain of the fourth N-type transistor.

12. The folded cascode amplifier circuit according to claim 11, wherein, The gain between the first differential input signal and the first differential amplified signal is configured to be proportional to the ratio between the resistance of the first main resistor and the resistance of the first sub-resistor.

13. The folded cascode amplifier circuit according to claim 11, wherein, The gain between the second differential input signal and the second differential amplified signal is configured to be proportional to the ratio between the resistance of the second main resistor and the resistance of the second sub-resistor.

14. The folded cascode amplifier circuit according to claim 11, wherein, The first sub-resistor is configured to include a plurality of first gain adjustment resistors, Each of the plurality of first gain adjustment resistors is configured to be connected in parallel between the power supply voltage terminal and the drain of the third N-type transistor through each of the plurality of first switches, and wherein the gain between the first differential input signal and the first differential amplified signal is configured to be determined based on whether the plurality of first switches are turned on.

15. The folded cascode amplifier circuit according to claim 11, wherein, The gain adjustment unit includes: a first peak resistor connected between the gate and the drain of the third N-type transistor; and a second peak resistor connected between the gate and the drain of the fourth N-type transistor.

16. A folded cascode amplifier circuit, comprising: a first differential amplification unit configured to receive a first differential input signal and output a first differential amplified signal that is inverted and amplified from the first differential input signal; a second differential amplification unit configured to receive a second differential input signal complementary to the first differential input signal, and output a second differential amplified signal that is inverted and amplified from the second differential input signal; a first DC gain adjustment unit configured to increase the DC gain of the first differential amplification unit based on the second differential input signal; a second DC gain adjustment unit configured to increase the DC gain of the second differential amplification unit based on the first differential input signal; a first AC gain adjustment unit configured to increase the AC gain of the first differential amplification unit based on the first differential input signal; and a second AC gain adjustment unit configured to increase the AC gain of the second differential amplification unit based on the second differential input signal.

17. The folded cascode amplifier circuit according to claim 16, wherein, The first differential amplification unit includes: a first P-type transistor configured to include a source connected to a first current source, a gate to which the first differential input signal is applied, and a drain connected to a first node; a first N-type transistor configured to include a drain that outputs the first differential amplified signal, a source connected to the first node, and a gate whose voltage varies based on the second differential input signal; and a first main resistor connected between the power supply voltage terminal and the drain of the first N-type transistor, wherein the second differential amplification unit includes: a second P-type transistor configured to include a source connected to the first current source, a gate to which the second differential input signal is applied, and a drain connected to a second node; a second N-type transistor configured to include a drain that outputs the second differential amplified signal, a source connected to the second node, and a gate whose voltage varies based on the first differential input signal; and a second main resistor connected between the power supply voltage terminal and the drain of the second N-type transistor.

18. The folded cascode amplifier circuit according to claim 17, wherein, The first DC gain adjustment unit includes: a third N-type transistor configured to include a drain and a gate connected to the gate of the first N-type transistor and a source connected to the second node; and a first sub-resistor connected between the power supply voltage terminal and the drain of the third N-type transistor, wherein the second DC gain adjustment unit includes: A fourth N-type transistor configured to include a drain and a gate connected to the gate of the second N-type transistor and a source connected to the first node; and A second sub-resistor connected between the power supply voltage terminal and the drain of the fourth N-type transistor.

19. The folded cascode amplifier circuit according to claim 18, further comprising: A fifth N-type transistor configured to include a drain connected to the first node, a gate to which a bias voltage is applied, and a source connected to the ground terminal; And A sixth N-type transistor configured to include a drain connected to the second node, a gate to which the bias voltage is applied, and a source connected to the ground terminal, wherein the first AC gain adjustment unit includes: A third sub-resistor connected between the gate of the fifth N-type transistor and the fifth node; A first capacitor connected between a first input terminal receiving the first differential input signal and the fifth node; and A seventh N-type transistor configured to include a drain connected to the first node, a gate connected to the fifth node, and a source connected to the ground terminal, wherein the second AC gain adjustment unit includes: A fourth sub-resistor connected between the gate of the sixth N-type transistor and the sixth node; A second capacitor connected between a second input terminal receiving the second differential input signal and the sixth node; and An eighth N-type transistor configured to include a drain connected to the second node, a gate connected to the sixth node, and a source connected to the ground terminal.

20. The folded cascode amplifier circuit according to claim 18, wherein, The first DC gain adjustment unit includes a first peak resistor connected between the gate and the drain of the third N-type transistor wherein the second DC gain adjustment unit includes a second peak resistor connected between the gate and the drain of the fourth N-type transistor.

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