Copper interconnection structure and forming method thereof

Abstract

The invention discloses a copper interconnection structure and a forming method thereof. The forming method comprises the following steps: providing a substrate; forming a dielectric layer on the substrate, wherein a conductive opening is formed in the dielectric layer; forming an initial barrier layer on the side wall and the bottom of the conductive opening; forming an initial copper conductive layer on the initial barrier layer; performing planarization processing to form a barrier layer and a copper conductive layer; performing deionized water cleaning treatment on the surfaces of the dielectric layer, the barrier layer and the copper conductive layer; carrying out annealing treatment; and forming a covering layer on the dielectric layer. Through deionized water cleaning treatment, a corrosive solution enriched after planarization treatment can be removed, so that corrosion damage to the surface of the copper conducting layer is reduced, the flatness of the surface of the copper conducting layer is improved, the coverage of the covering layer is improved, migration of copper ions in the copper conducting layer is reduced, and therefore the dielectric breakdown resistance of copper interconnection is enhanced. The annealing treatment can reduce water vapor remaining in the dielectric layer after deionized water cleaning treatment, and the dielectric breakdown resistance of copper interconnection is further enhanced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a copper interconnect structure and a method for forming the same. Background Art

[0002] With the development of semiconductor technology, the integration density of very large scale integrated circuit chips has reached a scale of hundreds of millions or even billions of devices, and multi-layer metal interconnect technologies with two or more layers are widely used. Traditional metal interconnects are made of aluminum metal. However, as the device feature size in integrated circuit chips continues to decrease, the circuit density in metal interconnect lines continues to increase, and the required response time continues to decrease. Traditional aluminum interconnects can no longer meet the requirements, and copper interconnects gradually replace aluminum interconnects. Compared with aluminum, copper has lower resistivity and higher resistance to electromigration, which can reduce the resistance capacitance (RC) delay of interconnect lines, improve electromigration, and enhance device stability.

[0003] However, there are still many problems in the formation process of metal layer interconnects in the prior art. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a copper interconnect structure and a method for forming the same to enhance the dielectric breakdown resistance of copper interconnects.

[0005] To solve the above problems, the present invention provides a method for forming a copper interconnect structure, including: providing a substrate; forming a dielectric layer on the substrate; forming a conductive opening in the dielectric layer; forming an initial barrier layer on the sidewall and bottom surface of the conductive opening; forming an initial copper conductive layer on the initial barrier layer, and the initial copper conductive layer fills the conductive opening; performing a planarization process on the initial barrier layer and the initial copper conductive layer until the top surface of the dielectric layer is exposed, forming a barrier layer and a copper conductive layer; after the planarization process, performing a deionized water cleaning process on the surfaces of the dielectric layer, the barrier layer, and the copper conductive layer; performing an annealing process after the deionized water cleaning process; after the annealing process, forming a capping layer on the dielectric layer, and the capping layer covers the surfaces of the barrier layer and the copper conductive layer.

[0006] Optionally, the planarization process includes: a chemical mechanical polishing process.

[0007] Optionally, the time of the deionized water cleaning process is 10 s to 30 s.

[0008] Optionally, the parameters of the annealing process include: the annealing temperature is 180°C to 250°C; the annealing time is 120 s to 180 s.

[0009] Optionally, the conductive opening is a conductive via or a conductive trench.

[0010] Optionally, the conductive opening includes: a conductive through-hole and a conductive trench located on the conductive through-hole, and the conductive trench exposes the conductive through-hole.

[0011] Optionally, after forming the dielectric layer, the method further includes: performing ultraviolet irradiation treatment on the dielectric layer.

[0012] Optionally, the material of the barrier layer includes: one or more of titanium, tantalum, titanium nitride, and tantalum nitride.

[0013] Optionally, the material of the dielectric layer includes: an ultra-low dielectric constant material.

[0014] Optionally, the material of the capping layer includes: silicon carbonitride.

[0015] Correspondingly, the technical solution of the present invention further provides a copper interconnect structure, which is formed by using the formation method of the copper interconnect structure described in any one of the above technical solutions. The copper interconnect structure includes: a substrate; a dielectric layer located on the substrate, and the dielectric layer has a conductive opening therein; a barrier layer located on the sidewall and bottom surface of the conductive opening; a copper conductive layer located on the barrier layer, and the copper conductive layer fills the conductive opening; a capping layer located on the dielectric layer, and the capping layer covers the surface of the barrier layer and the exposed copper conductive layer.

[0016] Optionally, the conductive opening is a conductive through-hole or a conductive trench.

[0017] Optionally, the conductive opening includes: a conductive through-hole and a conductive trench located on the conductive through-hole, and the conductive trench exposes the conductive through-hole.

[0018] Optionally, the material of the barrier layer includes: one or more of titanium, tantalum, titanium nitride, and tantalum nitride.

[0019] Optionally, the material of the dielectric layer includes: an ultra-low dielectric constant material.

[0020] Optionally, the material of the capping layer includes: silicon carbonitride

[0021] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0022] In the method for forming the copper interconnect structure of the technical solution of the present invention, after the planarization treatment of the initial barrier layer and the initial copper conductive layer, the surfaces of the dielectric layer, the barrier layer, and the copper conductive layer are subjected to deionized water cleaning treatment. Through the deionized water cleaning treatment, the corrosive solution enriched on the surfaces of the dielectric layer, the barrier layer, and the copper conductive layer after the planarization treatment can be removed, thereby reducing the corrosion damage to the surface of the copper conductive layer, improving the flatness of the surface of the copper conductive layer, improving the coverage of the covering layer, reducing the migration of copper ions in the copper conductive layer, and thus enhancing the anti-dielectric breakdown performance of the copper interconnect. In addition, an annealing treatment is added after the deionized water cleaning treatment. The annealing treatment can reduce the water vapor remaining in the dielectric layer after the deionized water cleaning treatment, and further enhance the anti-dielectric breakdown performance of the copper interconnect.

[0023] Further, after forming the dielectric layer, it further includes: performing ultraviolet irradiation treatment on the dielectric layer. Through the ultraviolet irradiation treatment, the material properties of the dielectric layer can be optimized, thereby improving the electrical performance and reliability of the copper interconnect structure.

[0024] In the copper interconnect structure of the technical solution of the present invention, after the planarization treatment of the initial barrier layer and the initial copper conductive layer, the surfaces of the dielectric layer, the barrier layer, and the copper conductive layer are subjected to deionized water cleaning treatment. Through the deionized water cleaning treatment, the corrosive solution enriched on the surfaces of the dielectric layer, the barrier layer, and the copper conductive layer after the planarization treatment can be removed, thereby reducing the corrosion damage to the surface of the copper conductive layer, improving the flatness of the surface of the copper conductive layer, improving the coverage of the covering layer, reducing the migration of copper ions in the copper conductive layer, and thus enhancing the anti-dielectric breakdown performance of the copper interconnect. In addition, an annealing treatment is added after the deionized water cleaning treatment. The annealing treatment can reduce the water vapor remaining in the dielectric layer after the deionized water cleaning treatment, and further enhance the anti-dielectric breakdown performance of the copper interconnect. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1 to 2 are schematic structural diagrams of each step of a method for forming a copper interconnect structure;

[0026] Figures 3 to 10 are schematic structural diagrams of each step of the method for forming the copper interconnect structure according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0027] As described in the background art, there are still many problems in the formation process of metal layer interconnection in the prior art. The following will be specifically described with reference to the drawings.

[0028] Figures 1 to 2It is a schematic diagram of the structures of each step in a method for forming a copper interconnect structure.

[0029] Please refer to Figure 1 , a method for forming a copper interconnect structure, comprising: providing a substrate 100; forming a dielectric layer 101 on the substrate 100; forming a conductive opening (not labeled) in the dielectric layer 101; forming an initial barrier layer 102 on the sidewalls and bottom surface of the conductive opening; forming an initial copper conductive layer 103 on the initial barrier layer 102, and the initial copper conductive layer 103 fills the conductive opening.

[0030] Please refer to Figure 2 , performing a planarization process on the initial barrier layer 102 and the initial copper conductive layer 103 until the top surface of the dielectric layer 101 is exposed, to form a barrier layer 104 and a copper conductive layer 105; after the planarization process, forming a capping layer 106 on the dielectric layer 101, and the capping layer 106 covers the surfaces of the barrier layer 104 and the copper conductive layer 105.

[0031] With the high-performance requirements for resistance-capacitance (RC) delay at the 45nm and higher technology nodes, the reduction of the interconnect line pitch and the application of ultra-low dielectric constant materials make time-dependent dielectric breakdown (TDDB) also very important.

[0032] The planarization process for the initial barrier layer 102 and the initial copper conductive layer 103 uses a chemical mechanical polishing process. After the planarization process, the chemical polishing solution will be enriched at the contact position of the formed barrier layer 104 and the copper conductive layer 105, and thus it is easy to cause intergranular corrosion of the copper conductive layer 105 near the barrier layer 104 to form voids (as shown at position A in Figure 2 ), which affects the surface flatness of the copper conductive layer 105, and further leads to poor coverage of the deposited capping layer 106. Since it is very difficult for the capping layer 106 to fill the formed void positions, the void positions will become weak points where copper ions migrate in the copper conductive layer 105 and thus the reliable performance of dielectric breakdown is poor.

[0033] On this basis, the present invention provides a copper interconnect structure and a method for forming the same. After the planarization treatment of the initial barrier layer and the initial copper conductive layer, the surfaces of the dielectric layer, the barrier layer, and the copper conductive layer are subjected to deionized water cleaning treatment. Through the deionized water cleaning treatment, the corrosive solution enriched on the surfaces of the dielectric layer, the barrier layer, and the copper conductive layer after the planarization treatment can be removed, thereby reducing the corrosion damage to the surface of the copper conductive layer, improving the flatness of the surface of the copper conductive layer, improving the coverage of the capping layer, reducing the migration of copper ions in the copper conductive layer, and thus enhancing the dielectric breakdown resistance of the copper interconnect. Additionally, an annealing treatment is further provided after the deionized water cleaning treatment. The annealing treatment can reduce the water vapor remaining in the dielectric layer after the deionized water cleaning treatment, and further enhance the dielectric breakdown resistance of the copper interconnect.

[0034] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically describes the embodiments of the present invention in detail with reference to the accompanying drawings.

[0035] Figures 3 to 10 It is a schematic structural diagram of each step of the method for forming a copper interconnect structure in an embodiment of the present invention.

[0036] Please refer to Figure 3 , and a substrate 200 is provided.

[0037] In this embodiment, the substrate 200 includes: a substrate, a device layer located on the substrate, and one or more electrical interconnect layers (not shown) formed on the device layer. The device layer has several device structures, and the electrical interconnect layers are electrically connected to the device structures in the device layer.

[0038] In other embodiments, the substrate may only include a substrate and a device layer located on the substrate.

[0039] In this embodiment, the material of the substrate is silicon.

[0040] In other embodiments, the material of the substrate may also include silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI), etc. Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0041] In this embodiment, the device structure includes one or more of a transistor, a capacitor, a resistor, and an inductor.

[0042] Please refer to Figure 4 , and a dielectric layer 201 is formed on the substrate 200.

[0043] In this embodiment, the material of the dielectric layer 201 is an ultra-low dielectric constant material (Ultra-Low k, ULK). The advantages of using an ultra-low dielectric constant material are as follows: reducing signal delay. In an integrated circuit, when a signal propagates in an interconnect structure, it is affected by the dielectric constant of the dielectric layer 201. The ultra-low dielectric constant material can significantly reduce the propagation delay of the signal between interconnect lines. Since the signal propagation speed is inversely proportional to the square root of the dielectric constant of the dielectric layer 201, the lower the dielectric constant, the faster the signal propagation speed, thus effectively reducing the time delay of signal transmission inside the chip, which is crucial for high-speed and high-frequency integrated circuit applications and can improve the overall working speed and performance of the chip; reducing signal crosstalk. With the continuous increase in the integration density of integrated circuits, the spacing between interconnect lines is getting smaller and smaller, and the signal crosstalk problem is becoming increasingly serious. The ultra-low dielectric constant material can effectively reduce the capacitive coupling between interconnect lines, thereby reducing signal crosstalk. A lower dielectric constant means that the electric field interaction between lines is weakened, and the signal is less interfered by the signals of adjacent lines during transmission, ensuring the integrity and accuracy of the signal. This advantage is particularly obvious in the chip design of high-density and high-speed signal transmission, which helps to improve the reliability and performance of the chip; reducing dynamic power consumption. In a copper interconnect structure, the switching of signals causes dynamic power consumption. Due to its lower dielectric constant, the ultra-low dielectric constant material can reduce the capacitance between interconnect lines, thereby reducing the amount of charge storage and release during signal switching. This reduces the energy required during signal transmission, thereby reducing the dynamic power consumption of the chip. This is of great significance for power-sensitive application scenarios such as mobile devices, which can extend the battery life of the device. At the same time, it also helps to reduce the heat generation of the chip during operation and improve the stability and reliability of the chip; reducing leakage power consumption. The ultra-low dielectric constant material usually has good insulation performance and can reduce leakage to a certain extent. Under high-voltage and high-frequency working conditions, leakage power consumption is an important part of the chip power consumption. By using the ultra-low dielectric constant material, the leakage current can be effectively reduced, thereby reducing the leakage power consumption, further optimizing the power consumption performance of the chip, and improving the energy efficiency ratio of the chip; reducing interconnect size. Since the ultra-low dielectric constant material can effectively reduce signal delay and crosstalk, a smaller interconnect line spacing and thinner interconnect line width can be used when designing the interconnect structure. This makes it possible to further miniaturize the chip, and more transistors and interconnect lines can be integrated on the same chip area, thereby improving the integration density of the chip; optimizing the wiring space. After using the ultra-low dielectric constant material, due to the improvement of signal transmission performance, the redundant space required for wiring can be reduced to a certain extent. For example, when designing the wiring, the isolation distance between lines can be appropriately reduced, thereby releasing more wiring space and making the wiring more flexible and efficient.This helps to improve the design flexibility of the chip, better meet the requirements of complex circuit design, and also helps to reduce the manufacturing cost of the chip; good thermal stability, ultra-low dielectric constant materials usually have good thermal stability, and the heat generated during the operation of the chip has little impact on its performance. This means that in a high-temperature environment, electrical properties such as the dielectric constant of the material can remain relatively stable, thus ensuring that the signal transmission performance of the interconnect structure is not significantly affected by temperature changes; high mechanical temperature resistance, ultra-low dielectric constant materials have good mechanical properties and can withstand certain mechanical stresses and strains during the chip manufacturing and packaging processes, and are not easily deformed or damaged. This helps to improve the mechanical stability of the interconnect structure, reduce signal transmission failures caused by mechanical factors, and thus enhance the overall reliability of the chip.

[0044] In this embodiment, the dielectric layer 201 is formed by chemical vapor deposition.

[0045] Please continue to refer to Figure 4 , after forming the dielectric layer 201, ultraviolet irradiation treatment is performed on the dielectric layer 201.

[0046] In this embodiment, the purpose of subjecting the dielectric layer 201 to the ultraviolet irradiation treatment is to form a porous structure inside the dielectric layer 201, which can optimize the material properties of the dielectric layer 201 and thus improve the electrical performance and reliability of the copper interconnect structure. Specifically, it includes: when the dielectric layer 201 is made of an ultra-low dielectric constant material, it usually contains organic pore formers during deposition. These pore formers are expelled from the film under ultraviolet irradiation, and at the same time, cross-linking reactions occur inside the film to form a porous structure. The formation of the porous structure helps to reduce the dielectric constant, thereby reducing the parasitic capacitance between the interconnect lines and improving the performance of the integrated circuit; ultraviolet irradiation can promote the rearrangement and cross-linking of chemical bonds in the film, making the structure of the film more stable. For example, large-angle Si-O-Si bonds will transform into more stable small-angle or "network" structures under ultraviolet irradiation, and at the same time, the degree of cross-linking will increase, thereby enhancing the hardness and elastic modulus of the film; improving the adhesion of the film, ultraviolet irradiation can improve the adhesion of the ultra-low dielectric constant material film to the upper and lower layer materials, which is very important for the subsequent copper interconnect process. Good adhesion can prevent the film from peeling or being damaged during subsequent processes (such as copper electroplating and chemical mechanical polishing); optimizing the dielectric properties of the film. During the ultraviolet irradiation process, although the film will shrink to a certain extent, by optimizing process parameters (such as irradiation time and temperature), it is possible to reduce the dielectric constant while minimizing the negative impact of shrinkage on performance. For example, performing the ultraviolet curing process in multiple steps can, to a certain extent, avoid severe shrinkage of the film during curing, thereby reducing the k value; repairing film defects, ultraviolet irradiation can repair certain defects in the film. For example, through mechanisms such as photodecomposition and chain migration, the structure of the film becomes more complete, which helps to improve the reliability and stability of the film and reduce possible electrical performance problems in subsequent processes.

[0047] In this embodiment, the irradiation time of the ultraviolet irradiation treatment is 200 s to 300 s.

[0048] Please refer to Figure 5 , and a conductive opening 202 is formed in the dielectric layer 201.

[0049] In this embodiment, the method for forming the conductive opening 202 includes: forming a patterned layer (not shown) on the dielectric layer 201, and the patterned layer exposes a part of the top surface of the dielectric layer 201; etching the dielectric layer 201 using the patterned layer as a mask to form the conductive opening 202 in the dielectric layer 201.

[0050] In this embodiment, the conductive opening 202 includes: a conductive through-hole and a conductive trench located on the conductive through-hole, and the conductive trench exposes the conductive through-hole. That is, the subsequent copper interconnect structure is formed using the dual damascene process.

[0051] In other embodiments, the conductive opening, conductive via or conductive trench, i.e., the subsequent copper interconnect structure, is formed by a single damascene process.

[0052] Please refer to Figure 6 , and an initial barrier layer 203 is formed on the sidewall and bottom surface of the conductive opening 202 and on the surface of the dielectric layer 201.

[0053] In this embodiment, the initial barrier layer 203 is formed by an atomic layer deposition process.

[0054] In this embodiment, the material of the initial barrier layer 203 includes one or more of titanium, tantalum, titanium nitride, and tantalum nitride.

[0055] Please refer to Figure 7 , and an initial copper conductive layer 204 is formed on the initial barrier layer 203, and the initial copper conductive layer 204 fills the conductive opening 202.

[0056] In this embodiment, the initial copper conductive layer 204 is formed by an electroplating process.

[0057] In other embodiments, the initial copper conductive layer may also be formed by a chemical vapor deposition process.

[0058] Please refer to Figure 8 , and the initial barrier layer 203 and the initial copper conductive layer 204 are planarized until the top surface of the dielectric layer 201 is exposed, forming the barrier layer 205 and the copper conductive layer 206.

[0059] In this embodiment, the planarization process uses a chemical mechanical polishing process.

[0060] It should be noted that in this embodiment, the formed barrier layer 205 surrounds the copper conductive layer 206 to prevent the diffusion of copper ions in the copper conductive layer 206 and thus cause metal contamination.

[0061] Please refer to Figure 9 , and after the planarization process, the surfaces of the dielectric layer 201, the barrier layer 205, and the copper conductive layer 206 are subjected to deionized water cleaning treatment.

[0062] In this embodiment, the deionized water cleaning treatment is used to remove the corrosive solution enriched on the surfaces of the dielectric layer 201, the barrier layer 205, and the copper conductive layer 206 after the planarization process.

[0063] In this embodiment, the time of the deionized water cleaning treatment is 10 s to 30 s.

[0064] Please continue to refer to Figure 9 , an annealing process is performed after the deionized water cleaning process.

[0065] In this embodiment, the annealing process is used to reduce the water vapor remaining in the dielectric layer 201 after the deionized water cleaning process.

[0066] In this embodiment, the parameters of the annealing process include: the annealing temperature is 180°C to 250°C; the annealing time is 120 s to 180 s.

[0067] Please refer to Figure 10 , after the annealing process, a covering layer 207 is formed on the dielectric layer 201, and the covering layer 207 covers the surfaces of the barrier layer 205 and the copper conductive layer 206.

[0068] After the planarization process is performed on the initial barrier layer 203 and the initial copper conductive layer 204, the surfaces of the dielectric layer 201, the barrier layer 205, and the copper conductive layer 206 are subjected to a deionized water cleaning process. Through the deionized water cleaning process, the corrosive solution enriched on the surfaces of the dielectric layer 201, the barrier layer 205, and the copper conductive layer 206 after the planarization process can be removed, thereby reducing the corrosion damage to the surface of the copper conductive layer 206, improving the flatness of the surface of the copper conductive layer 206, improving the coverage of the covering layer 207, thereby reducing the migration of copper ions in the copper conductive layer 206, and thus enhancing the anti-dielectric breakdown performance of the copper interconnection. Additionally, an annealing process is added after the deionized water cleaning process, and the annealing process can reduce the water vapor remaining in the dielectric layer 201 after the deionized water cleaning process, further enhancing the anti-dielectric breakdown performance of the copper interconnection.

[0069] In this embodiment, the material of the covering layer 207 is silicon carbide nitride (Nitride Doped SiiconCarbide, NDC).

[0070] In this embodiment, the covering layer 207 is formed by a chemical vapor deposition process.

[0071] It should be noted that in this embodiment, although the dielectric layer 201 forming the porous structure can reduce the dielectric constant by introducing air with a lower dielectric constant, the porous structure also results in very weak mechanical properties of the film layer of the dielectric layer 201. Therefore, forming the capping layer 207 can provide adhesion and mechanical support for the dielectric layer 201. In addition, the formed capping layer 207 also has the following important functions: blocking copper diffusion, the capping layer 207 can effectively prevent the diffusion of copper ions between the copper interconnect structures in different process layers. The diffusion of copper ions may cause short circuits or leakage between the interconnect lines, thus affecting the performance and reliability of the circuit; increasing the breakdown voltage, the capping layer 207 can increase the breakdown voltage between the metal layer and the dielectric layer 201, thereby enhancing the electrical performance and reliability of the integrated circuit; improving adhesion, the capping layer 207 can improve the adhesion between copper and the dielectric material, reduce defects and stress at the interface, and thus improve the overall stability of the interconnect structure; etching selectivity, the capping layer 207 has good etching selectivity, which enables more precise control of the etching process during semiconductor manufacturing and avoids damage to other layers; protecting the copper layer, the capping layer 207 can prevent the copper layer from being oxidized when exposed to air, thereby reducing the formation of copper oxide and avoiding the diffusion of oxides into the dielectric layer 201 to cause damage.

[0072] Correspondingly, an embodiment of the present invention also provides a copper interconnect structure, which is formed by using the formation method of the copper interconnect structure described in any one of the above embodiments. Please continue to refer to Figure 10 , the copper interconnect structure includes: a substrate 200; a dielectric layer 201 located on the substrate 200, and the dielectric layer 201 has a conductive opening 202 therein; a barrier layer 205 located on the sidewall and bottom surface of the conductive opening 202; a copper conductive layer 206 located on the barrier layer 205, and the copper conductive layer 206 fills the conductive opening 202; a capping layer 207 located on the dielectric layer 201, and the capping layer 207 covers the exposed surfaces of the barrier layer 205 and the copper conductive layer 206.

[0073] After performing the planarization process on the initial barrier layer 203 and the initial copper conductive layer 204, the surfaces of the dielectric layer 201, the barrier layer 205, and the copper conductive layer 206 are cleaned with deionized water. Through this deionized water cleaning process, the corrosive solution enriched on the surfaces of the dielectric layer 201, the barrier layer 205, and the copper conductive layer 206 after the planarization process can be removed, thereby reducing the corrosion damage to the surface of the copper conductive layer 206, improving the flatness of the surface of the copper conductive layer 206, improving the coverage of the cover layer 207, thereby reducing the migration of copper ions in the copper conductive layer 206, and thus enhancing the anti-dielectric breakdown performance of the copper interconnect. Additionally, an annealing process is added after the deionized water cleaning process. The annealing process can reduce the water vapor remaining in the dielectric layer 201 after the deionized water cleaning process, further enhancing the anti-dielectric breakdown performance of the copper interconnect.

[0074] In this embodiment, the substrate 200 includes: a substrate, and a device layer located on the substrate, and a plurality of device structures are provided in the device layer.

[0075] In this embodiment, the material of the substrate is silicon.

[0076] In other embodiments, the material of the substrate may further include silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI), etc. Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0077] In this embodiment, the device structure includes one or more of a transistor, a capacitor, a resistor, and an inductor.

[0078] In this embodiment, the material of the dielectric layer 201 is an ultra-low dielectric constant material (Ultra-Low k, ULK). The advantages of using an ultra-low dielectric constant material are as follows: reducing signal delay. In an integrated circuit, when a signal propagates in an interconnect structure, it is affected by the dielectric constant of the dielectric layer 201. The ultra-low dielectric constant material can significantly reduce the propagation delay of the signal between interconnect lines. Since the signal propagation speed is inversely proportional to the square root of the dielectric constant of the dielectric layer 201, the lower the dielectric constant, the faster the signal propagation speed, thus effectively reducing the time delay of signal transmission inside the chip, which is crucial for high-speed and high-frequency integrated circuit applications and can improve the overall working speed and performance of the chip; reducing signal crosstalk. As the integration density of integrated circuits continues to increase, the spacing between interconnect lines becomes smaller and smaller, and the signal crosstalk problem becomes increasingly serious. The ultra-low dielectric constant material can effectively reduce the capacitive coupling between interconnect lines, thereby reducing signal crosstalk. A lower dielectric constant means that the electric field interaction between lines weakens, and the signal is less interfered by the signals of adjacent lines during transmission, ensuring the integrity and accuracy of the signal. This advantage is particularly obvious in the chip design of high-density and high-speed signal transmission, which helps to improve the reliability and performance of the chip; reducing dynamic power consumption. In a copper interconnect structure, the switching of signals causes dynamic power consumption. Due to its lower dielectric constant, the ultra-low dielectric constant material can reduce the capacitance between interconnect lines, thereby reducing the amount of charge storage and release during signal switching. This reduces the energy required during signal transmission, thereby reducing the dynamic power consumption of the chip. This is of great significance for power-sensitive application scenarios such as mobile devices, which can extend the battery life of the device. At the same time, it also helps to reduce the heat generation of the chip during operation and improve the stability and reliability of the chip; reducing leakage power consumption. The ultra-low dielectric constant material usually has good insulation performance and can reduce leakage to a certain extent. Under high-voltage and high-frequency operating conditions, leakage power consumption is an important part of the chip's power consumption. By using the ultra-low dielectric constant material, the leakage current can be effectively reduced, thereby reducing the leakage power consumption, further optimizing the power consumption performance of the chip, and improving the energy efficiency ratio of the chip; reducing interconnect size. Since the ultra-low dielectric constant material can effectively reduce signal delay and crosstalk, a smaller interconnect line spacing and thinner interconnect line width can be used when designing the interconnect structure. This makes it possible to further miniaturize the chip, and more transistors and interconnect lines can be integrated on the same chip area, thereby increasing the integration density of the chip; optimizing the wiring space. After using the ultra-low dielectric constant material, due to the improvement of signal transmission performance, the redundant space required for wiring can be reduced to a certain extent. For example, when designing the wiring, the isolation distance between lines can be appropriately reduced, thereby releasing more wiring space and making the wiring more flexible and efficient.This helps improve the design flexibility of the chip, better meet the requirements of complex circuit design, and also helps reduce the manufacturing cost of the chip; good thermal stability, ultra-low dielectric constant materials usually have good thermal stability, and the heat generated during the operation of the chip has little impact on their performance. This means that in a high-temperature environment, electrical properties such as the dielectric constant of the material can remain relatively stable, thus ensuring that the signal transmission performance of the interconnect structure is not significantly affected by temperature changes; high mechanical temperature resistance, ultra-low dielectric constant materials have good mechanical properties and can withstand certain mechanical stresses and strains during chip manufacturing and packaging, and are not easily deformed or damaged. This helps improve the mechanical stability of the interconnect structure, reduce signal transmission failures caused by mechanical factors, and thus enhance the overall reliability of the chip.

[0079] In this embodiment, the conductive opening 202 includes: a conductive through-hole and a conductive trench located on the conductive through-hole, and the conductive trench exposes the conductive through-hole. That is, the subsequent copper interconnect structure is formed by a dual damascene process.

[0080] In other embodiments, the conductive opening is a conductive through-hole or a conductive trench, that is, the subsequent copper interconnect structure is formed by a single damascene process.

[0081] In this embodiment, the barrier layer 205 surrounds the copper conductive layer 206 to prevent the copper ions in the copper conductive layer 206 from diffusing and causing metal contamination.

[0082] In this embodiment, the material of the barrier layer 205 includes one or more of titanium, tantalum, titanium nitride, and tantalum nitride.

[0083] In this embodiment, the material of the capping layer 207 is silicon carbonitride. The capping layer 207 has the following important functions: preventing copper diffusion, the capping layer 207 can effectively prevent the diffusion of copper ions between the copper interconnect structures in different process layers. Copper ion diffusion may cause short circuits or leakage between interconnect lines, thus affecting the performance and reliability of the circuit; increasing the breakdown voltage, the capping layer 207 can increase the breakdown voltage between the metal layer and the dielectric layer 201, thus enhancing the electrical performance and reliability of the integrated circuit; improving adhesion, the capping layer 207 can improve the adhesion between copper and the dielectric material, reduce defects and stresses at the interface, and thus improve the overall stability of the interconnect structure; etching selectivity, the capping layer 207 has good etching selectivity, which enables more precise control of the etching process during semiconductor manufacturing and avoids damage to other layers; protecting the copper layer, the capping layer 207 can prevent the copper layer from being oxidized when exposed to air, thus reducing the formation of copper oxide and avoiding the diffusion of oxides into the dielectric layer 201 to cause damage.

[0084] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a copper interconnect structure, characterized in that Comprising: Providing a substrate; Forming a dielectric layer on the substrate; Forming a conductive opening in the dielectric layer; Forming an initial barrier layer on the sidewalls and bottom surface of the conductive opening; Forming an initial copper conductive layer on the initial barrier layer, the initial copper conductive layer filling the conductive opening; Performing a planarization process on the initial barrier layer and the initial copper conductive layer until the top surface of the dielectric layer is exposed, forming a barrier layer and a copper conductive layer; After the planarization process, performing a deionized water cleaning process on the surfaces of the dielectric layer, the barrier layer, and the copper conductive layer; Performing an annealing process after the deionized water cleaning process; After the annealing process, forming a capping layer on the dielectric layer, the capping layer covering the surfaces of the barrier layer and the copper conductive layer.

2. The method for forming a copper interconnect structure according to claim 1, wherein, The planarization process includes: a chemical mechanical polishing process.

3. The method for forming a copper interconnect structure according to claim 1, characterized in that, The time of the deionized water cleaning process is 10s to 30s.

4. The method for forming a copper interconnect structure according to claim 1, wherein, The parameters of the annealing process include: the annealing temperature is 180°C to 250°C; the annealing time is 120s to 180s.

5. The method for forming a copper interconnect structure according to claim 1, wherein The conductive opening is a conductive via or a conductive trench.

6. The method for forming a copper interconnect structure according to claim 1, wherein, The conductive opening includes: a conductive via and a conductive trench located on the conductive via, the conductive trench exposing the conductive via.

7. The method for forming a copper interconnect structure according to claim 1, characterized in that, After forming the dielectric layer, further including: performing an ultraviolet irradiation process on the dielectric layer.

8. The method for forming a copper interconnect structure according to claim 1, characterized in that, The material of the barrier layer includes: one or more of titanium, tantalum, titanium nitride, and tantalum nitride.

9. The method for forming a copper interconnect structure according to claim 1, wherein, The material of the dielectric layer includes: an ultra-low dielectric constant material.

10. The method for forming a copper interconnect structure according to claim 1, characterized in that, The material of the capping layer includes: silicon carbonitride.

11. A copper interconnect structure, characterized in that, The copper interconnect structure is formed by using the method for forming the copper interconnect structure according to any one of claims 1 to 10, and the copper interconnect structure includes: A substrate; A dielectric layer located on the substrate, the dielectric layer having a conductive opening therein; A barrier layer located on the sidewalls and bottom surface of the conductive opening; A copper conductive layer located on the barrier layer, the copper conductive layer filling the conductive opening; A capping layer located on the dielectric layer, the capping layer covering the exposed surfaces of the barrier layer and the copper conductive layer.

12. The copper interconnect structure according to claim 11, wherein, The conductive opening is a conductive via or a conductive trench.

13. The copper interconnect structure according to claim 11, wherein The conductive opening includes: a conductive via and a conductive trench located on the conductive via, the conductive trench exposing the conductive via.

14. The copper interconnect structure according to claim 11, characterized in that, The material of the barrier layer includes: one or more of titanium, tantalum, titanium nitride, and tantalum nitride.

15. The copper interconnect structure according to claim 11, wherein The material of the dielectric layer includes: an ultra-low dielectric constant material.

16. The copper interconnect structure according to claim 11, wherein The material of the capping layer includes: silicon carbonitride.

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