Method for improving copper interconnection defect in semiconductor device and improving electromigration performance
By optimizing etching process parameters and using reducing gases to repair the copper surface, the problems of copper surface damage and oxidation were solved, thereby improving the electromigration performance and reliability of semiconductor devices.
Patent Information
- Application Number
- CN202511064461.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-30
- Publication Date
- 2025-11-14
AI Technical Summary
In the integrated etching process of semiconductor devices, the copper surface is easily damaged and oxidized by by-products and plasma, resulting in interface defects such as copper loss and smile cracks, which affect electromigration performance and reliability.
By reducing ion bombardment energy and oxygen flow rate, and combining this with the use of reducing gas to repair the copper surface after dielectric layer etching, damage is mitigated and copper oxide is reversed, thus constructing a stable copper interconnect interface.
It significantly improves the interface quality of copper interconnects, enhances electromigration performance and long-term device reliability, and provides a wider process window and greater flexibility.
Smart Images
Figure CN120955040A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving copper interconnect defects and enhancing electromigration performance in semiconductor devices. Background Technology
[0002] As semiconductor technology nodes continue to evolve, the integration density of integrated circuits is increasing, and feature sizes are shrinking. Copper, due to its excellent conductivity and resistance to electromigration, has become the primary material for metal interconnects in advanced technology nodes. In the manufacturing process of copper interconnect structures, the damascus process is typically employed, with integrated etching being a key step in forming vias and / or trenches.
[0003] In some integrated circuit designs, such as those employing a dielectric-cap-less structure, the integrated etching process requires directly exposing the underlying copper layer in the later stages of etching the low-dielectric-constant dielectric material. However, this process faces significant challenges. During etching, high-energy ion bombardment and chemical reactions in the plasma are unavoidable. When the copper surface is exposed, byproducts such as fluorocarbon polymers generated during etching deposit on the copper surface. These byproducts, along with residual oxygen and moisture in the reaction chamber, react chemically with the exposed copper, leading to oxidation or modification of the copper surface and the formation of unstable compounds such as copper oxide or copper hydroxide.
[0004] In subsequent wet cleaning steps, these modified or oxidized copper layers are highly susceptible to excessive dissolution by the cleaning solution. This process leads to so-called copper missing defects and the formation of smile-shaped cracks at the interface. These physical defects severely compromise the interface integrity between the copper interconnects and the dielectric layer, resulting in decreased interfacial adhesion. Consequently, this significantly reduces the electromigration performance and reliability of the device, impacting chip yield and long-term stability.
[0005] Therefore, there is an urgent need for a new process method in the existing technology to effectively reduce damage to the copper interconnect surface in the integrated etching process, suppress the formation of defects such as copper missing parts, and thus improve and enhance the electromigration performance of the device. Summary of the Invention
[0006] The technical problem this invention aims to solve is that in existing semiconductor integrated etching processes, especially when etching structures that directly expose the underlying copper layer, the exposed copper surface is easily damaged, modified, or oxidized by byproducts and plasma during the etching process. This leads to interface defects such as copper missing and smile cracks in subsequent wet cleaning steps, which severely affect the electromigration (EM) performance and reliability of the device.
[0007] To achieve the above and other related objectives, the present invention provides a method for improving copper interconnect defects and enhancing electromigration performance in semiconductor devices. The method is applied in an integrated etching process for forming copper interconnect structures on a semiconductor substrate, and includes at least:
[0008] Step 1: Perform a dielectric layer etching step to etch the dielectric layer above the copper layer to expose the copper layer. In the dielectric layer etching step, damage to the surface of the copper layer is mitigated by reducing the ion bombardment energy applied to the semiconductor substrate and reducing the introduction of oxygen-containing etching gas.
[0009] Step 2: After the dielectric layer etching step, a first post-etching process is performed to remove the polymer byproducts generated in the dielectric layer etching step.
[0010] Step 3: After the first post-etching process, a second post-etching process is performed, in which a reducing gas is introduced into the exposed copper layer surface to repair the copper layer surface that may have been damaged in the dielectric layer etching process.
[0011] Preferably, in step one, reducing the ion bombardment energy applied to the semiconductor substrate includes reducing the low-frequency power applied to the semiconductor substrate.
[0012] Preferably, the low-frequency power ranges from 0 to 200W.
[0013] Preferably, in step one, reducing the introduction of oxygen-containing etching gas includes controlling the flow rate of oxygen.
[0014] Preferably, the oxygen flow rate is in the range of 0-20 sccm.
[0015] Preferably, in step one, the dielectric layer etching step further includes introducing a fluorine-containing gas.
[0016] Preferably, the fluorine-containing gas is carbon tetrafluoride, and the flow rate of the carbon tetrafluoride is in the range of 0-20 sccm.
[0017] Preferably, in step three, the reducing gas is hydrogen.
[0018] Preferably, in step three, nitrogen gas is also introduced along with the hydrogen gas.
[0019] Preferably, the flow rate of the hydrogen gas is in the range of 0-100 sccm, and the flow rate of the nitrogen gas is in the range of 0-400 sccm.
[0020] As described above, the method of the present invention for improving copper interconnect defects and enhancing electromigration performance in semiconductor devices has the following characteristics:
[0021] Beneficial effects:
[0022] This invention employs a dual strategy combining damage mitigation and active repair. By optimizing process parameters at the etching source to protect the copper layer and introducing reducing gases to chemically repair any oxides that may have formed, it effectively suppresses the generation of critical interface defects such as copper gaps and smile cracks, significantly improving the interface quality of copper interconnects. Ultimately, this high-quality interface greatly enhances the device's resistance to electromigration and long-term operational reliability, while providing a wider process window and greater flexibility for the development of advanced node processes. Attached Figure Description
[0023] Figure 1 The diagram shown is a schematic representation of the process flow of the present invention.
[0024] Figure 2 The diagram shown is a schematic diagram of a dielectric layer structure according to an embodiment of the present invention;
[0025] Figure 3 The image shown is a schematic diagram of wafer defect scanning obtained using an integrated etching process based on existing technology.
[0026] Figure 4 The image shown is a schematic diagram of a wafer defect scan according to the present invention.
[0027] Figure 5 The diagram shown is a comparison of electromigration between the present invention and the prior art. Detailed Implementation
[0028] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0029] Please see Figure 1 An embodiment of the present invention provides a method for improving copper interconnect defects and enhancing electromigration performance in semiconductor devices. The method is applied in an integrated etching process used to form copper interconnect structures on a semiconductor substrate. The method includes:
[0030] Step 1: Perform a dielectric layer etching step to etch the dielectric layer above a copper layer 101, thereby exposing the copper layer 101. In this dielectric layer etching step, damage to the surface of the copper layer 101 is mitigated by reducing the ion bombardment energy applied to the semiconductor substrate and minimizing the introduction of oxygen-containing etching gases. This step is designed to control physical and chemical damage to the copper surface at its source. By actively reducing ion bombardment, the direct physical impact of high-energy particles on the copper lattice structure can be effectively reduced, maintaining the flatness and integrity of the copper surface. Simultaneously, by controlling the introduction of oxygen, the tendency for oxidation reactions (such as Cu + O₂ → CuOx) on the copper surface can be significantly suppressed, thereby reducing the amount of easily soluble copper oxide byproducts generated in subsequent processes. This lays a good foundation for interface repair in subsequent steps and is a crucial first step in ensuring the final interface quality.
[0031] In some embodiments, please refer to Figure 2 The dielectric layer may include a dielectric-free cap layer (NDC) 103, an ultra-low dielectric constant (ULK) layer 104, and a titanium nitride (TiN) hard mask layer 105 stacked from bottom to top.
[0032] In some embodiments, step one, reducing the ion bombardment energy applied to the semiconductor substrate, includes reducing the low-frequency power applied to the semiconductor substrate. Low-frequency power primarily controls the bombardment energy of ions in the plasma. By reducing the low-frequency power, the physical bombardment intensity of ions on the exposed copper surface can be directly weakened, thereby protecting the copper surface from physical damage.
[0033] In some embodiments, the low-frequency power ranges from 0 to 200 W. Adjusting within this power range allows for maintaining a sufficient etching rate while keeping physical damage to the copper layer 101 to an extremely low level, achieving an optimized balance between etching requirements and copper surface protection.
[0034] In some embodiments, step one, reducing the introduction of oxygen-containing etching gas, includes controlling the oxygen flow rate. Oxygen is one of the main sources of oxidation on copper surfaces, and precise control of its flow rate can effectively reduce the active oxygen species in contact with copper in the etching environment, thereby directly inhibiting the formation of copper oxide.
[0035] In some embodiments, the oxygen flow rate ranges from 0 to 20 sccm. Controlling the oxygen flow rate within this lower range has been shown to effectively reduce the generation of oxygen-containing byproducts (e.g., TiOxFy / COxFy) and significantly alleviate the degree of chemical modification on the copper surface.
[0036] In some embodiments, step one, the dielectric layer etching step further includes introducing a fluorine-containing gas. The fluorine-containing gas serves as the primary etching gas, effectively removing the dielectric layer material.
[0037] In some embodiments, the fluorinated gas is carbon tetrafluoride, and the flow rate of carbon tetrafluoride ranges from 0 to 20 sccm. Appropriate introduction of carbon tetrafluoride helps to adjust the etch selectivity and profile control, while also working synergistically with other process parameters to achieve low-damage etching of the copper surface.
[0038] Step 2: Following the dielectric layer etching step, a first post-etching process is performed to remove the polymer byproducts 102 generated during the dielectric layer etching step. This is a routine cleaning step designed to remove most of the carbon-containing fluoropolymer residue deposited on the wafer surface, preparing for subsequent fine repair steps.
[0039] Step 3: Following the first post-etching step, a second post-etching step is performed, introducing a reducing gas into the exposed copper layer 101 surface to repair any damage that may have occurred during the dielectric layer etching step. This repair step is one of the core innovations of this invention. Unlike traditional processes that only perform cleaning, this step utilizes the chemical properties of a strong reducing gas to actively reduce the small amount of copper oxide (CuO or CuOx) inevitably generated during the dielectric layer etching process to chemically stable pure metallic copper (e.g., CuO + H2 → Cu + H2O). This chemical repair process significantly enhances the copper surface's chemical resistance to subsequent wet cleaning solutions, fundamentally preventing the formation of "copper loss" and "smile-shaped cracks" defects caused by copper oxide dissolution. Ultimately, by constructing a clean, complete, and chemically stable copper interconnect interface, a significant improvement in electromigration performance is achieved, greatly enhancing the long-term reliability of the device.
[0040] The process method of this invention effectively reduces the number of defects, provides a new solution for the process development of advanced technology nodes, and, while ensuring the process window, also provides greater inclusiveness for diversified and specialized product designs, which helps to shorten the R&D cycle of new processes.
[0041] In some embodiments, in step three, the reducing gas is hydrogen. Hydrogen is a powerful and clean reducing gas that can react efficiently with copper oxides to produce metallic copper and water. The reaction products are easy to remove and do not introduce new pollution.
[0042] In some embodiments, nitrogen gas is also introduced along with hydrogen gas in step three. Nitrogen gas can be used as a dilution gas or carrier gas, and its mixing with hydrogen gas helps to stabilize plasma discharge, making the repair reaction more uniform and controllable across the entire wafer surface, thereby improving the stability and uniformity of the process.
[0043] In some embodiments, the flow rate of hydrogen is in the range of 0-100 sccm, and the flow rate of nitrogen is in the range of 0-400 sccm. Experimental verification shows that controlling the flow rates of hydrogen and nitrogen within these ranges efficiently repairs the copper surface while avoiding potential negative impacts on other structures of the device. Furthermore, the processing time in this step can be reasonably adjusted to ensure that the oxides on the copper surface are fully reduced, achieving the best repair effect.
[0044] The beneficial effects of the present invention can be more clearly illustrated through comparison.
[0045] Please see Figure 3 In contrast, a traditional integrated etching process was used, where no reduction in ion bombardment and oxygen flow was specifically implemented during the dielectric layer etching step, and the post-etching process only included a conventional polymer removal step. As shown in the upper part of the comparison image, the wafer map after processing reveals a large number of defect sites, especially concentrated in the wafer edge region, which is more susceptible to stronger plasma bombardment. The corresponding magnified structural image shows that multiple via structures exhibit severe copper loss defects, forming black hole-like failure points, which seriously impairs interface integrity and electrical performance.
[0046] Please see Figure 4 The method provided in this invention, which reduces damage by lowering low-frequency power and oxygen flow rate during the dielectric layer etching step and adds a second repair step using reducing gas in the post-etching process, significantly improved the experimental results. As shown in the lower half of the comparison image, the wafer defect scan after treatment shows that the overall number of defects was significantly reduced, the wafer edges maintained high cleanliness, and the defect distribution was sparse. The corresponding magnified structural image further confirms that the via morphology is uniform and complete, no obvious copper loss was observed, and the integrity of the copper interconnect structure was effectively guaranteed.
[0047] This result intuitively demonstrates that the present invention, through a strategy combining "reducing etching damage" and "active chemical repair," successfully suppresses the formation of copper missing defects, laying a solid foundation for improving electromigration performance and final product yield.
[0048] Ultimately, this improvement in interface defects directly translates into enhanced device reliability, a fact strongly validated by electromigration (EM) testing.
[0049] Please see Figure 5As shown in the electromigration comparison chart, the chart compares the T0.01 lifetime (in years) of devices fabricated using existing technologies and the method described in this application across multiple test batches. T0.01 lifetime is a key indicator for evaluating a device's resistance to electromigration and long-term reliability. The chart clearly shows that in all test groups, the devices using the method described in this application have a T0.01 lifetime several times longer than those fabricated using existing technologies, consistently and significantly exceeding the design specifications. This result strongly demonstrates that the clean and complete copper interconnect interface constructed using the method of this invention effectively suppresses the formation and movement of atomic vacancies during electron migration, thereby greatly enhancing the electromigration resistance of copper interconnects and ensuring high reliability of the devices under long-term use.
[0050] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0051] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for improving copper interconnect defects and enhancing electromigration performance in semiconductor devices, characterized in that, The method is applied in an integrated etching process for forming copper interconnect structures on a semiconductor substrate, and includes at least: Step 1: Perform a dielectric layer etching step to etch the dielectric layer above the copper layer to expose the copper layer. In the dielectric layer etching step, damage to the surface of the copper layer is mitigated by reducing the ion bombardment energy applied to the semiconductor substrate and reducing the introduction of oxygen-containing etching gas. Step 2: After the dielectric layer etching step, a first post-etching process is performed to remove the polymer byproducts generated in the dielectric layer etching step. Step 3: After the first post-etching process, a second post-etching process is performed, in which a reducing gas is introduced into the exposed copper layer surface to repair the copper layer surface that may have been damaged in the dielectric layer etching process.
2. The method for improving copper interconnect defects and enhancing electromigration performance in semiconductor devices according to claim 1, characterized in that: In step one, reducing the ion bombardment energy applied to the semiconductor substrate includes reducing the low-frequency power applied to the semiconductor substrate.
3. The method for improving copper interconnect defects and enhancing electromigration performance in semiconductor devices according to claim 2, characterized in that: The low-frequency power range is 0-200W.
4. The method for improving copper interconnect defects and enhancing electromigration performance in semiconductor devices according to claim 1, characterized in that: In step one, reducing the introduction of oxygen-containing etching gas includes controlling the oxygen flow rate.
5. The method for improving copper interconnect defects and enhancing electromigration performance in semiconductor devices according to claim 4, characterized in that: The oxygen flow rate ranges from 0 to 20 sccm.
6. The method for improving copper interconnect defects and enhancing electromigration performance in semiconductor devices according to claim 1, characterized in that: In step one, the dielectric layer etching step further includes introducing a fluorine-containing gas.
7. The method for improving copper interconnect defects and enhancing electromigration performance in semiconductor devices according to claim 6, characterized in that: The fluorine-containing gas is carbon tetrafluoride, and the flow rate of the carbon tetrafluoride is in the range of 0-20 sccm.
8. The method for improving copper interconnect defects and enhancing electromigration performance in semiconductor devices according to claim 1, characterized in that: In step three, the reducing gas is hydrogen.
9. The method for improving copper interconnect defects and enhancing electromigration performance in semiconductor devices according to claim 8, characterized in that: In step three, nitrogen gas is also introduced along with the hydrogen gas.
10. The method for improving copper interconnect defects and enhancing electromigration performance in semiconductor devices according to claim 1, characterized in that: The flow rate of the hydrogen gas is in the range of 0-100 sccm, and the flow rate of the nitrogen gas is in the range of 0-400 sccm.