Damascus film layer structure and preparation method thereof

Abstract

The invention discloses a Damascus film layer structure and a preparation method thereof, and belongs to the technical field of semiconductor manufacturing. The method adopts a PECVD (Plasma Enhanced Chemical Vapor Deposition) process, and Si3N4 is deposited on a copper substrate at 350 DEG C to serve as SiO2 is deposited on the stop layer at the temperature of 180 DEG C to serve as a graphical layer; siOxNy is deposited at the temperature of 400 DEG C to serve as a dielectric anti-reflection layer. By regulating and controlling the deposition temperature difference between different layers, the SiO2 layer formed at a low temperature has relatively low density and shows a higher etching rate during etching, so that the selection ratio of photoresist to oxides is remarkably improved. The structure effectively inhibits excessive etching, realizes accurate etching termination and high-quality pattern transfer, and is suitable for high-performance copper interconnection process requirements.

Description

Technical Field

[0001] This invention belongs to the field of advanced packaging technology, and in particular to a damascus film structure and its preparation method. Background Technology

[0002] With the rapid development of VLSI and advanced packaging technologies, interconnect linewidths are continuously shrinking, and device integration density is significantly improving. Traditional aluminum interconnects, due to their high resistivity and electromigration issues, have been gradually replaced by copper interconnect (Cu Damascene) technology. The Damascene process, as the core technology for forming copper interconnects, involves etching trenches or vias in a dielectric layer, followed by the deposition of a barrier layer and a seed layer, and then copper electroplating for filling. Planarization is achieved through chemical mechanical polishing (CMP), resulting in a high-density, high-reliability metal interconnect structure. This technology is widely used in advanced process nodes (such as 7nm, 5nm, 3nm, and more advanced processes) and is a crucial step in ensuring chip performance and reliability.

[0003] In the Damascus process, film deposition parameters, especially deposition temperature, have a significant impact on the performance of interconnect structures. Deposition temperature not only determines the microstructure, density, and chemical composition of the film but also directly affects the interfacial bonding strength and stress state with the underlying dielectric or metal layer. Taking common SiO2 dielectric layers, Ta / TaN barrier layers, and Cu seed layers as examples, temperature variations can lead to significant differences in film crystallinity, atomic diffusion behavior, and interfacial reaction mechanisms. While excessively high deposition temperatures can improve film density and crystallinity, they may cause interfacial reactions, thermal stress accumulation, and decreased adhesion; conversely, excessively low temperatures can result in a porous film structure, increased porosity, a higher dielectric constant, and metal diffusion failure. Therefore, how to rationally control the deposition temperature to optimize film structure and interfacial properties is one of the key issues in current advanced interconnect technology research.

[0004] Taking chemical vapor deposition (CVD) and plasma-enhanced chemical vapor deposition (PECVD) as examples, the formation mechanism and structural characteristics of the thin films differ significantly when the deposition temperature is between 180℃ and 400℃. At low temperatures (around 180℃), the precursor dissociates insufficiently, leaving residual organic matter and hydrogen bonds in the film, resulting in low dielectric density, poor mechanical strength, and insufficient heat resistance. At high temperatures (around 400℃), the precursor decomposes more thoroughly, forming a stable Si-O-Si bond structure in the film, significantly increasing density and hardness, reducing dielectric constant, and exhibiting better thermal stability. However, high-temperature deposition may also induce reactions between the underlying material (such as TaN, Cu) and the dielectric layer, leading to stress concentration and even interfacial delamination, thus affecting the overall reliability of the damascus structure. From the perspective of interfacial physicochemistry, deposition temperature affects atomic migration rate, bonding energy, and interfacial reaction kinetics; the interfacial bonding strength and chemical bond type of the films formed at different temperatures show significant differences. At low temperatures, the thin film may contain numerous unsaturated bonds and organic residues, leading to poor interfacial adhesion and making it prone to delamination or detachment during thermal cycling. While high-temperature deposition helps improve interfacial bonding, it may also generate unstable intermediate layers (such as tantalum oxide and carbides) due to excessive reactions, affecting electrical properties and structural stability. Therefore, in advanced damascus processes, balancing the dual effects of temperature on structural compactness and interfacial reactions is crucial for achieving high-performance interconnect structures.

[0005] Currently, most traditional damascus film deposition processes employ fixed-temperature CVD or PVD process parameters, making it difficult to simultaneously ensure film density, stress control, and interface stability. This results in reliability fluctuations and defect generation under different process environments. Particularly in advanced packaging and 3D integration applications, the thermal expansion coefficients of different interlayer materials differ significantly. Improper temperature control can easily lead to interfacial microcracks and stress accumulation, severely impacting device lifespan.

[0006] In summary, existing technologies lack methods for optimizing the structure of damascus films under different deposition temperature conditions. How to control the microstructure, stress state, and interfacial chemical reactions of the film by adjusting the temperature, thereby achieving a highly dense, low-stress, and strongly bonded multilayer interconnect structure, has become a pressing technical problem to be solved in the industry. Summary of the Invention

[0007] The purpose of this invention is to provide a damascus film structure and its preparation method, thereby solving the problem of poor selectivity of photoresist for damascus oxide in the prior art.

[0008] To achieve the above objectives, the present invention employs the following technical solution: A method for preparing a damascus film structure includes: Using PECVD deposition process, silane and ammonia gas are introduced at a deposition temperature of 350℃ to deposit a Si3N4 film as a stop layer on the surface of a copper substrate. By introducing silane, N2O and nitrogen gas, a SiO2 layer is deposited on the surface of the stop layer as a damascus patterning layer at a deposition temperature of 180°C. A layer of SiO2 was deposited on the surface of the Damascus patterned layer at a deposition temperature of 400℃. x N y The membrane is used as a dielectric antireflective layer to obtain a damascus membrane structure.

[0009] Furthermore, the deposition power of the stop layer is 1024~1536W, the cavity pressure is 2.5~4T, and the target-substrate distance is 15~23mm.

[0010] Furthermore, during the stop layer deposition process, the silane flow rate was 1140~1708 sccm, the ammonia flow rate was 422~633 sccm, and the single step time was 6~10 s.

[0011] Furthermore, the deposition power of the damascus patterned layer is 160~240W, the cavity pressure is 1~2T, and the target-substrate distance is 8~12mm.

[0012] Furthermore, during the deposition of the damascus patterned layer, the silane flow rate was 64–96 sccm, the N2O flow rate was 6400–9600 sccm, the nitrogen flow rate was 3600–5400 sccm, and the single-step time was 224–337 s.

[0013] Furthermore, the deposition power of the dielectric antireflective layer is 96~144W, the cavity pressure is 1.68~2.52T, and the target-substrate distance is 16~24mm.

[0014] Furthermore, during the deposition of the dielectric antireflective layer, the silane flow rate is 110~165 sccm, the N2O flow rate is 130~195 sccm, the nitrogen flow rate is 6400~9600 sccm, and the single-step time is 102~154 s.

[0015] A damascus film structure prepared by the aforementioned method.

[0016] Furthermore, the Si-N bond energy of the Si3N4 film is 470 kJ / mol.

[0017] Furthermore, the resistivity of the SiO2 layer is 10. 14 ~10 16 Its dielectric constant is 3.9.

[0018] Compared with the prior art, the present invention has the following beneficial effects: This invention provides a method for fabricating a damascus patterned layer structure. Using a PECVD deposition process, at a deposition temperature of 350°C, silane and ammonia are introduced to deposit a Si3N4 film as a stop layer on the surface of a copper substrate. This precisely prevents the etchant from eroding the underlying copper substrate, completely solving the problem of copper interconnect damage caused by excessive etching in existing processes and ensuring the structural stability of semiconductor devices. Next, silane, N2O, and nitrogen are introduced, and at a deposition temperature of 180°C, a SiO2 layer is deposited on the surface of the stop layer as a damascus patterning layer. This layer has a relatively low density and a controllable etching rate. Finally, at a deposition temperature of 400°C, another SiO2 layer is deposited on the surface of the damascus patterning layer. x N y The film serves as a dielectric anti-reflection layer, resulting in a damascus patterned film structure. Besides its anti-reflection function, the dielectric anti-reflection layer also acts as a secondary etching barrier layer. On one hand, it isolates the photoresist from direct reaction with plasma, preventing photoresist decomposition products from contaminating the film layer; on the other hand, it prevents excessive erosion of the underlying SiO2 layer by gases such as O2 and CF4, maintaining the sidewall morphology of the trenches / vias and further improving the etching precision of the film structure. This invention, by adjusting the temperature range, sequentially deposits a Si3N4 stop layer, a SiO2 damascus patterning layer, and a SiO2 layer at different temperatures. x N y The dielectric antireflective layer utilizes the significant difference in film density between the low-temperature deposited SiO2 layer and the upper and lower layers deposited at high temperatures to alter the selectivity of the photoresist for oxides during etching. Combined with the control of specific process parameters for each layer, it enhances the ability to control the etching endpoint, achieving synergistic optimization of the structure and performance of the barrier layer, dielectric layer, and metal layer. This solves the over-etching problem caused by low selectivity in existing technologies, improves patterning accuracy and process stability, and has significant application value and promising prospects for industrial promotion. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the etching effect of the present invention.

[0021] Figure 2 This is a diagram showing the etching effect of the damascus film structure in Embodiment 1 of the present invention.

[0022] Figure 3 This is an image showing the etching effect of the damascus film structure in Embodiment 2 of the present invention.

[0023] Figure 4 This is an image showing the etching effect of the damascus film structure in Embodiment 3 of the present invention. Detailed Implementation

[0024] To enable those skilled in the art to understand the features and effects of the present invention, the terms and expressions used in the specification and claims are explained and defined in general below. Unless otherwise specified, all technical and scientific terms used herein have the ordinary meaning understood by those skilled in the art regarding the present invention, and in case of conflict, the definitions in this specification shall prevail.

[0025] The theories or mechanisms described and disclosed herein, whether right or wrong, should not in any way limit the scope of the invention, that is, the contents of the invention can be implemented without being limited by any particular theory or mechanism.

[0026] In this document, all features defined by numerical ranges or percentage ranges, such as numerical values, quantities, contents, and concentrations, are for the sake of brevity and convenience only. Accordingly, descriptions of numerical ranges or percentage ranges should be considered as covering and specifically disclosing all possible sub-ranges and individual numerical values ​​(including integers and fractions) within those ranges.

[0027] In this article, unless otherwise specified, “contains,” “includes,” “containing,” “has,” or similar terms cover the meanings of “composed of” and “mainly composed of,” for example, “A contains a” covers the meanings of “A contains a and others” and “A contains only a.”

[0028] For the sake of brevity, not all possible combinations of the technical features in each implementation scheme or embodiment are described herein. Therefore, as long as there is no contradiction in the combination of these technical features, the technical features in each implementation scheme or embodiment can be combined arbitrarily, and all possible combinations should be considered within the scope of this specification.

[0029] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0030] The following examples use instruments and equipment conventional in the art. Experimental methods in the following examples, unless otherwise specified, are generally performed under conventional conditions or as recommended by the manufacturer. All raw materials used in the following examples are conventional commercially available products with specifications conventional in the art. In this specification and the following examples, unless otherwise specified, "%" refers to weight percentage, "parts" refers to parts by weight, and "ratio" refers to weight proportion.

[0031] The present invention will now be described in further detail with reference to the accompanying drawings: This invention provides a method for preparing a damascus film structure. Using a PECVD deposition process, by adjusting the deposition temperature of different oxide layers and combining this with dynamic parameter adjustments, a three-layer dielectric structure with gradient density and functional differentiation is constructed. This achieves the modification of the photoresist selectivity for the oxide layer and simultaneously optimizes the photolithographic pattern fidelity. Specifically, the method includes the following steps: S1: Stop layer deposition A PECVD deposition process was employed, with silane and ammonia gas introduced at a deposition temperature of 350℃ to deposit a Si3N4 layer as a stop layer on the copper substrate. This layer was used to stop the etching process on the Si3N4 layer, protecting the copper beneath from over-etching. Silane (SiH4) and ammonia (NH3) are silicon nitride precursors, which dissociate into free radicals in the plasma. These radicals then undergo surface adsorption and recombination to form a Si-N covalent network. The deposition temperature of 350℃ is sufficient to promote the full formation of Si-N bonds and the formation of highly crystalline Si3N4, while simultaneously preventing significant diffusion or oxidation of the copper substrate. The resulting Si3N4 exhibits a highly stable chemical structure, with Si-N bond energies reaching as high as 470 kJ / mol, significantly higher than Si-O bonds (approximately 370 kJ / mol), and exhibits extremely low reactivity in fluorine-containing plasma. Below 300℃, the H content of the Si3N4 film is high, the network structure is incomplete, and the etching resistance decreases. Above 450℃, it may induce a Cu-Si interface reaction to form a brittle Cu3Si phase, which impairs interconnect reliability. Etching gases commonly used in the Damascus etching process include fluorine-containing gases such as CF4, CHF3, C4F8, and C4F6 (used for SiO2 etching) as well as O2 and Ar auxiliary gases. These gases have a high etching rate for SiO2 but hardly react with Si3N4. Therefore, Si3N4 has a high selectivity for SiO2. When etching the SiO2 dielectric layer, the etching rate drops sharply after the plasma reaches the Si3N4 layer, thus stopping the etching.

[0032] Preferably, during the deposition of the Si3N4 layer, the power is 1024~1536W, the chamber pressure is 2.5~4T, the target-substrate distance is 15~23mm, the silane flow rate is 1140~1708sccm, the ammonia flow rate is 422~633sccm, and the single-step time is 6~10s.

[0033] S2: Patterned layer deposition By introducing silane, N2O, and nitrogen gas at a deposition temperature of 180°C, a SiO2 layer is deposited on the surface of the Si3N4 layer as a damascus patterning layer. This layer is used to transfer the pattern from the photoresist onto the SiO2 layer and is the main functional layer for realizing damascus copper interconnects. Silane (SiH4), N2O, and nitrogen (N2) constitute the ternary reaction system for SiO2 deposition. N2O, as an oxygen source, is milder than O2, reducing plasma damage to the underlying Si3N4 layer. Furthermore, its dissociation products help passivate Si and reduce the defect state density of the film. Nitrogen gas mainly acts as a carrier gas and plasma dilution in this step, regulating the electron temperature and active particle concentration, and suppressing particle generation caused by excessive dissociation of SiH4. Its high flow rate (3600~5400 sccm) combined with low power (160~240 W) ensures that the deposition process is in a weak plasma coupling state, avoiding high-energy ion bombardment that could lead to film densification. At a deposition temperature of 180℃, the low temperature condition inhibited the full rearrangement and dehydration of the SiO2 network, resulting in a metastable and loose structure in the obtained SiO2 film. This allowed the SiO2 layer to exhibit a higher etching rate in subsequent plasma etching, thereby increasing the size of the dense layers above and below (Si3N4 and SiO2). x N y The difference in etching rates directly improves the photoresist / SiO2 etching selectivity. The resulting SiO2 layer is a high-resistivity, high-quality insulator, typically with a resistivity in the range of 10⁻⁶. 14 ~10 16 Meanwhile, its dielectric constant k≈3.9 is sufficient to maintain low parasitic capacitance under high frequency signal transmission, thereby reducing signal delay, increasing circuit operating speed and reducing power consumption.

[0034] Preferably, during the deposition of the SiO2 layer, the power is 160~240W, the chamber pressure is 1~2T, the target-substrate distance is 8~12mm, the silane flow rate is 64~96sccm, the N2O flow rate is 6400~9600sccm, the nitrogen flow rate is 3600~5400sccm, and the single-step time is 224~337s.

[0035] S3: Deposition of dielectric antireflective layer At a deposition temperature of 400℃, another layer of SiO2 is deposited on the surface of the SiO2 layer. x N yAs a DARC (Dielectric Anti-Reflective Coating), its function is to suppress reflection interference during photolithography, improve pattern resolution and etching consistency. Simultaneously, the DARC layer also acts as an etching barrier layer, preventing direct reaction between the photoresist and plasma, suppressing excessive etching of the underlying dielectric by gases such as O2 and CF4, and maintaining the sidewall morphology of trenches or vias. A deposition temperature of 400℃ ensures the SiO2... x N y The layer possesses a high-density and strong Si-ON bond network, and its etching rate for CF4 / O2 is only 1 / 4 to 1 / 6 that of low-temperature SiO2. It can act as an etching barrier layer to prevent photoresist carbonization debris from eroding the underlying SiO2 layer, and also provide precisely matched optical impedance in the photolithography exposure band. In addition to its optical function, the DARC dielectric antireflective layer also plays a chemical buffering role in the etching process. The Si-N bonds enriched on its surface can preferentially adsorb fluorine radicals, reduce the flux of active fluorine atoms reaching the SiO2 layer, slow down the advance rate of the etching front, and provide a wider time window for endpoint detection.

[0036] Preferably, SiO2 is deposited. x N y During the layering process, the power is 96~144W, the chamber pressure is 1.68~2.52T, the target-substrate distance is 16~24mm, the silane flow rate is 110~165sccm, the N2O flow rate is 130~195sccm, the nitrogen flow rate is 6400~9600sccm, and the single step time is 102~154s.

[0037] The present invention also provides a damascus membrane structure prepared by the above preparation method, which is a three-layer medium structure with gradient density and functional differentiation.

[0038] This invention achieves a change in the photoresist selectivity for oxide layers during etching by using different deposition temperatures for different oxide layers (350℃ for Si3N4 layer, 180℃ for SiO2 layer, and 400℃ for DARC layer), combined with dynamic adjustments to parameters such as power, deposition time, gas flow rate, and target-substrate distance. The core of this invention lies in the fact that the film density of the SiO2 layer at a deposition temperature of 180℃ differs significantly from that of the DARC layer at 400℃ and the Si3N4 layer at 350℃. This results in significant differences in etching rates among the different film layers. By further altering process parameters such as power, deposition time, and gas flow rate during deposition, the etching rates of each film layer are further influenced, thereby achieving the goal of changing the etching selectivity. Under the conditions of the interaction of the above process parameters, this invention solves the problem of low etching selectivity and easy over-etching in the existing damascus etching process, which affects the patterning of the oxide layer. It provides a stable and reliable oxide layer deposition scheme with high etching selectivity for damascus trench and via etching, and the effect after etching is as follows: Figure 1 As shown.

[0039] The technical solution of the present invention will be further described in detail below through specific embodiments: Example 1: S1. PECVD deposition process is adopted with a deposition power of 1024W, a chamber pressure of 2.5T, a target-substrate distance of 15mm, and a deposition temperature of 350℃. Silane is introduced at a flow rate of 1140sccm and ammonia is introduced at a flow rate of 422sccm. The single step time is 6s. A Si3N4 layer is deposited on the copper substrate as a stop layer, and the introduction of silane and ammonia is stopped.

[0040] S2. Adjust the PECVD deposition process to a deposition power of 160W, a chamber pressure of 1T, a target-substrate distance of 8mm, and a deposition temperature of 180℃. Silane is introduced at a flow rate of 64sccm, N2O at a flow rate of 6400sccm, and ammonia at a flow rate of 3600sccm. The single-step time is 224s. A SiO2 layer is deposited on the surface of the Si3N4 layer as a damascus patterning layer.

[0041] S3. Adjust the PECVD deposition process: deposition power to 96W, chamber pressure to 1.68T, target-substrate distance to 16mm. At a deposition temperature of 400℃, continue to introduce silane at a flow rate of 110sccm, N2O at a flow rate of 130sccm, and ammonia at a flow rate of 6400sccm. The single-step time is 102s. Deposit a layer of SiO2 on the surface of the SiO2 layer. x N y As a dielectric antireflective layer for DARC.

[0042] like Figure 2 The image shown is an etching effect diagram after using the film deposition process parameters of Example 1 of the present invention and performing damascus hole patterning. Figure 2 The etching results show that SiO2 deposited at 180℃ exhibited a good etching rate after etching, and even after the Si3N4 layer was etched through, there was still photoresist remaining, proving the feasibility of the technical solution of the present invention.

[0043] Example 2: S1. PECVD deposition process is adopted with a deposition power of 1536W, a chamber pressure of 4T, a target-substrate distance of 23mm, and a deposition temperature of 350℃. Silane is introduced at a flow rate of 1708sccm and ammonia is introduced at a flow rate of 633sccm. The single step time is 10s. A Si3N4 layer is deposited on the copper substrate as a stop layer, and the introduction of silane and ammonia is stopped.

[0044] S2. Adjust the PECVD deposition process to a deposition power of 240W, a chamber pressure of 2T, a target-substrate distance of 12mm, and a deposition temperature of 180℃. Silane is introduced at a flow rate of 96sccm, N2O at a flow rate of 9600sccm, and ammonia at a flow rate of 5400sccm. The single-step time is 337s. A SiO2 layer is deposited on the surface of the Si3N4 layer as a damascus patterning layer.

[0045] S3. Adjust the PECVD deposition process: deposition power to 144W, chamber pressure to 2.52T, target-substrate distance to 24mm. At a deposition temperature of 400℃, continue to introduce silane at a flow rate of 165sccm, N2O at a flow rate of 195sccm, and ammonia at a flow rate of 9600sccm. The single-step time is 154s, depositing a layer of SiO2 on the surface of the SiO2 layer. x N y As a dielectric antireflective layer for DARC.

[0046] like Figure 3 The image shown is an etching effect diagram after using the film deposition process parameters of Example 2 of the present invention and performing damascene hole patterning. Figure 3 The etching results show that by adjusting the process parameters other than temperature during SiO2 layer deposition, the angles on both sides of the etched damascus groove can be controlled, resulting in a more perpendicular etching angle, increased damascus line density, and optimized process. Subsequent adjustments to the etching process parameters can significantly improve the flexibility of the damascus process, demonstrating the advantages and potential of this invention in damascus etching.

[0047] Example 3: S1. PECVD deposition process is adopted with a deposition power of 1236W, a chamber pressure of 3T, a target-substrate distance of 20mm, and a deposition temperature of 350℃. Silane is introduced at a flow rate of 1508sccm and ammonia is introduced at a flow rate of 532sccm. The single step time is 8s. A Si3N4 layer is deposited on the copper substrate as a stop layer, and the introduction of silane and ammonia is stopped.

[0048] S2. Adjust the PECVD deposition process to a deposition power of 200W, a chamber pressure of 1.5T, a target-substrate distance of 10mm, and a deposition temperature of 180℃. Silane is introduced at a flow rate of 90sccm, N2O at a flow rate of 8000sccm, and ammonia at a flow rate of 4500sccm. The single-step time is 300s. A SiO2 layer is deposited on the surface of the Si3N4 layer as a damascus patterning layer.

[0049] S3. Adjust the PECVD deposition process: deposition power to 130W, chamber pressure to 2T, target-substrate distance to 20mm. At a deposition temperature of 400℃, continue to introduce silane at a flow rate of 150sccm, N2O at a flow rate of 160sccm, and ammonia at a flow rate of 6000sccm. The single-step time is 150s. Deposit a layer of SiO2 on the surface of the SiO2 layer. x N y As a dielectric antireflective layer for DARC.

[0050] like Figure 4 The image shown is an etching effect diagram after using the film deposition process parameters of Example 3 of the present invention and performing damascene hole patterning. From... Figure 4 The results show that by adjusting the process parameters during deposition, the deposition process of the present invention can also be used for the etching process of damascus holes. When the Si3N4 layer is etched through, there is still photoresist remaining, indicating that the deposition process of the present invention can be used for both the etching of damascus trenches and the etching of damascus holes, demonstrating that the deposition process has good versatility.

[0051] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for preparing a damascus film structure, characterized in that, include: Using PECVD deposition process, silane and ammonia gas are introduced at a deposition temperature of 350℃ to deposit a Si3N4 film as a stop layer on the surface of a copper substrate. By introducing silane, N2O and nitrogen gas, a SiO2 layer is deposited on the surface of the stop layer as a damascus patterning layer at a deposition temperature of 180°C. A layer of SiO2 was deposited on the surface of the Damascus patterned layer at a deposition temperature of 400℃. x N y The membrane is used as a dielectric antireflective layer to obtain a damascus membrane structure.

2. The method for preparing a damascus film structure according to claim 1, characterized in that, The deposition power of the stop layer is 1024~1536W, the cavity pressure is 2.5~4T, and the target-substrate distance is 15~23mm.

3. The method for preparing a damascus film structure according to claim 1, characterized in that, During the stop layer deposition process, the silane flow rate was 1140~1708 sccm, the ammonia flow rate was 422~633 sccm, and the single step time was 6~10 s.

4. The method for preparing a damascus film structure according to claim 1, characterized in that, The deposition power of the Damascus patterned layer is 160~240W, the cavity pressure is 1~2T, and the target-substrate distance is 8~12mm.

5. The method for preparing a damascus film structure according to claim 1, characterized in that, During the deposition of the Damascus patterned layer, the silane flow rate was 64~96 sccm, the N2O flow rate was 6400~9600 sccm, the nitrogen flow rate was 3600~5400 sccm, and the single step time was 224~337 s.

6. The method for preparing a damascus film structure according to claim 1, characterized in that, The deposition power of the dielectric antireflective layer is 96~144W, the cavity pressure is 1.68~2.52T, and the target-substrate distance is 16~24mm.

7. The method for preparing a damascus film structure according to claim 1, characterized in that, During the deposition of the dielectric antireflective layer, the silane flow rate is 110~165 sccm, the N2O flow rate is 130~195 sccm, the nitrogen flow rate is 6400~9600 sccm, and the single-step time is 102~154 s.

8. A damascus film structure prepared by the preparation method according to any one of claims 1 to 7.

9. A damascus membrane structure according to claim 8, characterized in that, The Si-N bond energy of the Si3N4 film is 470 kJ / mol.

10. A damascus membrane structure according to claim 8, characterized in that, The resistivity of the SiO2 layer is 10. 14 ~10 16 Its dielectric constant is 3.9.

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