Capacitor structure embedded in copper interconnect and method of forming the same

Abstract

A capacitor structure embedded in copper interconnection and a forming method thereof, a substrate, the substrate comprising a substrate and a device layer, the device layer having an Nth copper metal interconnection layer; a first insulating layer and a first top electrode on the Nth copper metal interconnection layer; an N+1th dielectric structure on the device layer and having a first height dimension and covering the first insulating layer and the first top electrode; a second bottom electrode, a second insulating layer and a second top electrode on the N+1th dielectric structure, the second bottom electrode on a surface of the Nth copper metal interconnection layer; an N+2th dielectric structure on the N+1th dielectric structure and having a second height dimension and covering the second bottom electrode, the second insulating layer and the second top electrode, the second height dimension being greater than the first height dimension. According to the height dimensions of the N+1th dielectric structure and the N+2th dielectric structure, the number of layers of the capacitor structure can be flexibly designed, that is, the integration of the capacitor structure can be improved, and meanwhile, the electrical contact of the capacitor structure can also be considered.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a capacitor structure embedded in copper interconnects and a method for forming the same. Background Technology

[0002] With the rapid increase in the integration of various functional circuits and the need for miniaturization of functional modules and components, integrated passive technology has become a solution to replace discrete passive components in order to achieve device miniaturization. In various typical circuits, 80% of the components are passive devices, which occupy nearly 50% of the area on the printed circuit board. As the most common and most widely distributed component on the substrate, capacitor integration technology has become a key technology in integrated passive technology.

[0003] Capacitors are commonly used as passive electronic components in integrated circuits such as radio frequency ICs and monolithic microwave ICs. Common capacitors include metal-oxide-semiconductor (MOS) capacitors, PN junction capacitors, and metal-insulator-metal (MIM) capacitors. MIM capacitors offer superior electrical characteristics compared to MOS and PN junction capacitors in certain applications. This is because MOS and PN junction capacitors, due to their inherent structure, are prone to hole formation at the electrodes during operation, leading to reduced frequency characteristics. MIM capacitors, on the other hand, provide better frequency and temperature-dependent characteristics. Furthermore, in semiconductor manufacturing, MIM capacitors can be formed using interlayer metal and copper interconnect processes, reducing the difficulty and complexity of integration with CMOS front-end processes.

[0004] However, there are still many problems with the MIM capacitors formed in the existing technology. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a capacitor structure embedded in copper interconnects and a method for forming the same, which can effectively improve the integration of the capacitor structure in a semiconductor structure of a certain thickness.

[0006] To address the aforementioned problems, the present invention provides a capacitor structure embedded in copper interconnects, comprising: a substrate, the substrate including a base and a device layer located on the base, the device layer having an Nth copper interconnect layer, and the device layer exposing the top surface of the Nth copper interconnect layer, wherein N is an integer greater than or equal to 1; a first insulating layer located on the Nth copper interconnect layer, the first insulating layer covering a portion of the top surface of the Nth copper interconnect layer and a first top electrode located on the first insulating layer; and a capacitor structure embedded in copper interconnects, the Nth copper interconnect layer being a first insulating layer, the Nth copper interconnect layer being a second insulating layer, the Nth copper interconnect layer being a third insulating layer, the Nth copper interconnect layer being a third insulating layer, the Nth copper interconnect layer being a second ... A metal plug and a second metal plug located on the Nth copper interconnect layer, the top surfaces of the first and second metal plugs being flush; an (N+1)th copper interconnect layer located on the first and second metal plugs; an (N+1)th dielectric structure located on the device layer, the (N+1)th dielectric structure having a first height dimension along the normal direction of the substrate, and the (N+1)th dielectric structure covering the first insulating layer, the first top electrode, the first metal plug, the second metal plug, and the (N+1)th copper interconnect layer, and the... The N+1th dielectric layer exposes the top surface of the N+1th copper interconnect layer; a second bottom electrode, a second insulating layer, and a second top electrode are located on the N+1th dielectric layer, the second bottom electrode is located on the N+1th copper interconnect layer, the second insulating layer is located on the second bottom electrode, and the second top electrode is located on the second insulating layer; a third metal plug is located on the second top electrode, and a fourth metal plug is located on the second bottom electrode, the top surfaces of the third metal plug and the fourth metal plug being flush; the third metal plug is located on the N+1th dielectric layer. The N+2nd copper interconnect layer is located on the third metal plug and the fourth metal plug; the N+2nd dielectric structure is located on the N+1th dielectric structure, the N+2nd dielectric structure has a second height dimension along the normal direction of the substrate, the second height dimension is greater than the first height dimension, and the N+2nd dielectric structure covers the second bottom electrode, the second insulating layer, the second top electrode, the third metal plug, the fourth metal plug and the N+2nd copper interconnect layer, and the N+2nd dielectric structure exposes the top surface of the N+2nd copper interconnect layer.

[0007] Optionally, the first height dimension ranges from 20 nanometers to 120 nanometers; the second height dimension ranges from 120 nanometers to 2500 nanometers.

[0008] Optionally, the first top electrode, the second bottom electrode, and the second top electrode are made of the same material; the materials of the first top electrode, the second bottom electrode, and the second top electrode include titanium nitride or tantalum nitride.

[0009] Optionally, the device layer further includes a device structure and an electrical interconnect structure; the device structure includes a capacitor structure; the electrical interconnect structure includes a metal plug, the metal plug being electrically connected to the capacitor structure, and the Nth copper metal interconnect layer being electrically connected to the metal plug.

[0010] Optionally, the N+1th dielectric structure includes: an N+1th etch stop layer and an N+1th dielectric layer located on the N+1th etch stop layer.

[0011] Optionally, the N+2nd dielectric structure includes: an N+2nd etch stop layer and an N+2nd dielectric layer located on the N+2nd etch stop layer.

[0012] Accordingly, the present invention also provides a method for forming a capacitor structure embedded in copper interconnects, comprising: providing a substrate, the substrate including a base and a device layer located on the base, the device layer having an Nth copper interconnect layer, and the device layer exposing the top surface of the Nth copper interconnect layer, wherein N is an integer greater than or equal to 1; forming a first insulating layer on the Nth copper interconnect layer, the first insulating layer covering a portion of the top surface of the Nth copper interconnect layer, and forming a first top electrode on the first insulating layer; and forming an (N+1)th dielectric structure on the device layer. The (N+1)th dielectric layer has a first height dimension along the normal direction of the substrate, and the (N+1)th dielectric layer covers the first insulating layer and the first top electrode; a first metal plug and a second metal plug are formed within the (N+1)th dielectric layer, the first metal plug being located on the first top electrode, and the second metal plug being located on the Nth copper interconnect layer, with the top surfaces of the first metal plug and the second metal plug flush; an (N+1)th copper interconnect layer is formed within the (N+1)th dielectric layer, and the (N+1)th copper interconnect layer is located on the first metal plug and the second metal plug respectively. On the plug, the (N+1)th dielectric layer exposes the top surface of the (N+1)th copper interconnect layer; a second bottom electrode, a second insulating layer, and a second top electrode are formed on the (N+1)th dielectric layer, the second bottom electrode being located on the (N+1)th copper interconnect layer, the second insulating layer being located on the second bottom electrode, and the second top electrode being located on the second insulating layer; an (N+2)th dielectric layer is formed on the (N+1)th dielectric layer, the (N+2)th dielectric layer having a second height dimension along the normal direction of the substrate, the second height dimension being greater than the first height dimension, and the (N+2)th layer... The dielectric structure covers the second bottom electrode, the second insulating layer, and the second top electrode; a third metal plug and a fourth metal plug are formed within the N+2th dielectric structure, the third metal plug being located on the second top electrode and the fourth metal plug being located on the second bottom electrode, with the top surfaces of the third and fourth metal plugs flush; an N+2th copper interconnect layer is formed within the N+2th dielectric structure, the N+2th copper interconnect layer being located on the third and fourth metal plugs respectively, and the top surface of the N+2th copper interconnect layer is exposed by the N+2th dielectric structure.

[0013] Optionally, the first height dimension ranges from 20 nanometers to 120 nanometers; the second height dimension ranges from 120 nanometers to 2500 nanometers.

[0014] Optionally, the first top electrode, the second bottom electrode, and the second top electrode are made of the same material; the materials of the first top electrode, the second bottom electrode, and the second top electrode include titanium nitride or tantalum nitride.

[0015] Optionally, the device layer further includes a device structure and an electrical interconnect structure; the device structure includes a capacitor structure; the electrical interconnect structure includes a metal plug, the metal plug being electrically connected to the capacitor structure, and the Nth copper metal interconnect layer being electrically connected to the metal plug.

[0016] Optionally, the N+1th dielectric structure includes: an N+1th etch stop layer and an N+1th dielectric layer located on the N+1th etch stop layer.

[0017] Optionally, the N+2nd dielectric structure includes: an N+2nd etch stop layer and an N+2nd dielectric layer located on the N+2nd etch stop layer.

[0018] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0019] In the structure of the technical solution of this invention, the N+1th dielectric layer of the first height dimension has a first insulating layer and a first top electrode. Since only the first insulating layer and the first top electrode can be formed in the N+1th dielectric layer of the first height dimension, the Nth copper metal interconnect layer is used as an electrode plate, and a capacitor structure is formed by the Nth copper metal interconnect layer, the first insulating layer, and the first top electrode. In the direction perpendicular to the substrate surface, the integration of the capacitor structure can be improved, and the photomask for fabricating an electrode plate can be saved.

[0020] Furthermore, the N+2th dielectric layer in the second height dimension contains a second bottom electrode, a second insulating layer on the second bottom electrode, and a second top electrode on the second insulating layer. Since the second bottom electrode, the second insulating layer, and the second top electrode can be formed simultaneously within the N+2th dielectric layer in the second height dimension, it is not necessary to use the N+1th copper interconnect layer as an electrode plate. Moreover, the surface flatness of the second bottom electrode and the second top electrode is higher than that of the N+1th copper interconnect layer, resulting in better electrical contact between the subsequently formed third and fourth metal plugs and the second top and second bottom electrodes, greater flexibility in area design, and better uniformity, thereby improving the performance of the final capacitor structure embedded in the copper interconnect.

[0021] Based on the height dimensions of the N+1th and N+2th dielectric layers, the number of layers in the capacitor structure can be flexibly designed, which can both improve the integration of the capacitor structure and take into account the electrical contact of the capacitor structure.

[0022] In the method for forming the technical solution of this invention, a first insulating layer and a first top electrode are formed within the (N+1)th dielectric layer of the first height dimension. Since only the first insulating layer and the first top electrode can be formed within the (N+1)th dielectric layer of the first height dimension, the Nth copper metal interconnect layer is used as an electrode plate, thereby forming a capacitor structure from the Nth copper metal interconnect layer, the first insulating layer, and the first top electrode. In the direction perpendicular to the substrate surface, the integration density of the capacitor structure can be improved, and a photomask for fabricating an electrode plate can be saved.

[0023] Furthermore, a second bottom electrode, a second insulating layer on the second bottom electrode, and a second top electrode on the second insulating layer are formed within the N+2 layer dielectric structure of the second height dimension. Since the second bottom electrode, the second insulating layer, and the second top electrode can be formed simultaneously within the N+2 layer dielectric structure of the second height dimension, it is not necessary to use the N+1 layer copper interconnect as an electrode plate. Moreover, the surface flatness of the second bottom electrode and the second top electrode is higher than that of the N+1 layer copper interconnect, resulting in better electrical contact between the subsequently formed third and fourth metal plugs and the second top and second bottom electrodes, greater flexibility in area design, and better uniformity, thereby improving the performance of the final capacitor structure embedded in the copper interconnect.

[0024] Based on the height dimensions of the N+1th and N+2th dielectric layers, the number of layers in the capacitor structure can be flexibly designed, which can both improve the integration of the capacitor structure and take into account the electrical contact of the capacitor structure. Attached Figure Description

[0025] Figure 1 and Figure 2 This is a schematic diagram of a capacitor structure embedded in copper interconnects;

[0026] Figures 3 to 12 This is a schematic diagram of the steps in an embodiment of the method for forming a capacitor structure embedded in a copper interconnect according to the present invention. Detailed Implementation

[0027] As described in the background section, existing MIM capacitors still have many problems. These will be explained in detail below with reference to the accompanying drawings.

[0028] Please refer to Figure 1The system includes a substrate 100; a first capacitor structure located on the substrate 100, the first capacitor structure including a first electrode plate 101, a first insulating layer 102 located on the first electrode plate 101, and a second electrode plate 103 located on the first insulating layer 102.

[0029] Please refer to Figure 2 A first electrical interconnect structure and a second electrical interconnect structure are located on the first capacitor structure, wherein the first electrical interconnect structure is connected to the first electrode plate 101 and the second electrical interconnect structure is connected to the second electrode plate 103; and a second capacitor structure (not shown) is located on the surface of the first electrical interconnect structure.

[0030] In this embodiment, in order to increase the capacitance value in the capacitor structure, the capacitance value is increased by connecting multiple capacitor structures in parallel.

[0031] In this embodiment, to allow for greater flexibility in electrical interconnection between the first and second capacitor structures, both structures employ a complete three-layer structure. However, the first electrical interconnection structure includes a first metal plug 104 and a first Nth copper interconnect layer 105 located on the first metal plug 104; the second electrical interconnection structure includes a second metal plug 106 and a second Nth copper interconnect layer 107 located on the second metal plug 106. The first Nth copper interconnect layer 105 and the second Nth copper interconnect layer 107 occupy space due to their thickness. With the rapid increase in the integration density of various functional circuits and the need for miniaturization of functional modules and components, reducing the total thickness of vertical integration is a key attribute in the development of advanced semiconductor device technologies (e.g., below 7 nanometers). Therefore, using the electrical interconnection structure of this embodiment to connect multiple capacitor structures reduces the integration density of the capacitor structures.

[0032] Based on this, the present invention provides a capacitor structure embedded in copper interconnect and a method for forming the same. The number of layers of the capacitor structure can be flexibly designed according to the height dimensions of the N+1th and N+2th dielectric layers, which can both improve the integration of the capacitor structure and take into account the electrical contact of the capacitor structure.

[0033] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] Figures 3 to 12 This is a schematic diagram of the formation process of a capacitor structure embedded in a copper interconnect according to an embodiment of the present invention.

[0035] Please refer to Figure 3 and Figure 4 , Figure 3 This is a 3D diagram of a capacitor structure embedded in copper interconnects. Figure 4 yes Figure 3 A schematic cross-sectional view along line AA shows a substrate, which includes a base 200 and a device layer 201 on the base 200. The device layer 201 has an Nth copper interconnect layer 202, and the device layer 201 exposes the top surface of the Nth copper interconnect layer 202, where N is an integer greater than or equal to 1.

[0036] In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0037] In this embodiment, the device layer 201 also includes a device structure 203 and an electrical interconnection structure 204.

[0038] In this embodiment, the device structure 203 includes a capacitor structure; the electrical interconnect structure 204 includes a metal plug, the metal plug is electrically connected to the capacitor structure, and the Nth copper metal interconnect layer 202 is electrically connected to the metal plug.

[0039] In this embodiment, the device layer 201 is made of silicon oxide; in other embodiments, the device layer may also be made of low-K dielectric material (referring to dielectric material with a relative permittivity of less than 3.9) or ultra-low-K dielectric material (referring to dielectric material with a relative permittivity of less than 2.5).

[0040] It should be noted that since the semiconductor device structure is formed by stacking multiple layers of film sequentially, in this embodiment, the device layer can be regarded as the Nth dielectric layer. The Nth dielectric layer can be the first dielectric layer or any dielectric layer with a length greater than 1 in the copper interconnect.

[0041] Please refer to Figure 5 , Figure 5 and Figure 4 With the view direction consistent, a first insulating layer 205 is formed on the Nth copper metal interconnect layer 202. The first insulating layer 205 covers part of the top surface of the Nth copper metal interconnect layer 202, and a first top electrode 206 is formed on the first insulating layer 205.

[0042] In this embodiment, the method for forming the first insulating layer 205 and the first top electrode 206 includes: forming a first insulating material layer (not shown) on the Nth copper metal interconnect layer 202; forming a first top electrode material layer (not shown) on the first insulating material layer; forming a first patterned layer (not shown) on the first top electrode material layer, wherein the first patterned layer exposes a portion of the top surface of the first top electrode material layer; etching the first insulating material layer and the first top electrode material layer using the first patterned layer as a mask until the top surface of the device layer 201 is exposed, thereby forming the first insulating layer 205 and the first top electrode 206.

[0043] In this embodiment, the first top electrode 206 is made of titanium nitride; in other embodiments, the first top electrode may also be made of tantalum nitride, tantalum or aluminum.

[0044] In this embodiment, the first insulating layer 205 is made of zirconium oxide; in other embodiments, the first insulating layer may also be made of aluminum oxide, hafnium oxide, silicon oxide, or silicon oxide.

[0045] In this embodiment, a capacitor structure is formed by the Nth copper metal interconnect layer 202, the first insulating layer 205 and the first top electrode 206.

[0046] Please refer to Figure 6 An N+1th dielectric structure 207 is formed on the device layer 201. The N+1th dielectric structure 207 has a first height dimension d1 along the normal direction of the substrate, and the N+1th dielectric structure d1 covers the first insulating layer 205 and the first top electrode 206.

[0047] It should be noted that the first height dimension d1 of the N+1th dielectric structure 207 is determined by the height dimension of other device structures (such as transistor structures). Since only the first insulating layer 205 and the first top electrode 206 can be formed within the N+1th dielectric structure 207 with the first height dimension d1, the Nth copper metal interconnect layer 202 is used as an electrode plate, thereby forming a capacitor structure from the Nth copper metal interconnect layer 202, the first insulating layer 205, and the first top electrode 206. In the direction perpendicular to the substrate surface, the integration density of the capacitor structure can be improved, and the photomask for fabricating an electrode plate can be saved.

[0048] In this embodiment, the first height dimension d1 ranges from 20 nanometers to 120 nanometers.

[0049] In this embodiment, the N+1th dielectric structure 207 includes: an N+1th etch stop layer and an N+1th dielectric layer (not shown) located on the N+1th etch stop layer; wherein the material of the N+1th dielectric layer is silicon oxide; in other embodiments, the material of the N+1th dielectric layer may also be a low-K dielectric material (referring to a dielectric material with a relative permittivity lower than 3.9) or an ultra-low-K dielectric material (referring to a dielectric material with a relative permittivity lower than 2.5).

[0050] Please refer to Figure 7 A first metal plug 208 and a second metal plug 210 are formed in the N+1th dielectric structure 207. The first metal plug 208 is located on the first top electrode 206, and the second metal plug 210 is located on the Nth copper metal interconnect layer 202. The top surfaces of the first metal plug 208 and the second metal plug 210 are flush.

[0051] In this embodiment, the first metal plug 208 and the second metal plug 210 are made of copper.

[0052] Please refer to Figure 8 An N+1 copper metal interconnect layer 209 is formed within the N+1th dielectric structure 207. The N+1th copper metal interconnect layer 209 is located on the first metal plug 208 and the second metal plug 210, respectively, and the top surface of the N+1th copper metal interconnect layer 209 is exposed in the N+1th dielectric structure 207.

[0053] Please refer to Figure 9 A second bottom electrode 211, a second insulating layer 212, and a second top electrode 213 are formed on the N+1th dielectric structure 209. The second bottom electrode 211 is located on the N+1th copper metal interconnect layer 209, the second insulating layer 212 is located on the second bottom electrode 211, and the second top electrode 213 is located on the second insulating layer 212.

[0054] In this embodiment, the method for forming a second bottom electrode 211, a second insulating layer 212, and a second top electrode 213 on the N+1th dielectric structure 207 includes: forming a second bottom electrode material layer (not shown) on the N+1th dielectric structure 207; forming a second insulating material layer on the second bottom electrode material layer; forming a second top electrode material layer (not shown) on the second insulating material layer; forming a second patterned layer (not shown) on the second top electrode material layer, wherein the second patterned layer exposes a portion of the top surface of the second top electrode material layer; etching the second top electrode material layer, the second insulating material layer, and the second bottom electrode material layer using the second patterned layer as a mask until the top surface of the N+1th dielectric structure 207 is exposed, thereby forming the second top electrode 213, the second insulating layer 212, and the second bottom electrode 211.

[0055] In this embodiment, the second bottom electrode 211 and the second top electrode 213 are made of the same material, and the material of the second bottom electrode 211 and the second top electrode 213 is titanium nitride; in other embodiments, the material of the second bottom electrode and the second top electrode may also be tantalum nitride, tantalum or aluminum.

[0056] In this embodiment, the material of the second insulating layer 212 is zirconium oxide; in other embodiments, the material of the first insulating layer may also be aluminum oxide, hafnium oxide, silicon oxide or silicon oxide.

[0057] In this embodiment, a capacitor structure is formed by the second bottom electrode 211, the second insulating layer 212, and the second top electrode 213.

[0058] Please refer to Figure 10 An N+2 dielectric structure 214 is formed on the N+1 dielectric structure 207. The N+2 dielectric structure 214 has a second height dimension d2 along the normal direction of the substrate. The second height dimension d2 is greater than the first height dimension d1. The N+2 dielectric structure 214 covers the second bottom electrode 211, the second insulating layer 212, and the second top electrode 213.

[0059] It should be noted that the second height dimension d2 of the N+2nd dielectric layer 214 is also determined by the height of other device structures. Since the second bottom electrode 211, the second insulating layer 212, and the second top electrode 213 can be simultaneously formed within the N+2nd dielectric layer 214 with the second height dimension d2, it is not necessary to use the N+1th copper interconnect layer 209 as an electrode plate. Furthermore, since the N+1th copper interconnect layer 209 is made of copper, its material properties cause a depression on the top surface. The second bottom electrode 211 and the second top electrode 213 are made of titanium nitride, whose surface flatness is higher than that of the N+1th copper interconnect layer 209. This results in better electrical contact for the subsequently formed third and fourth metal plugs, thereby improving the performance of the final capacitor structure embedded in the copper interconnect.

[0060] In this embodiment, the second height dimension d2 ranges from 120 nanometers to 2500 nanometers.

[0061] In this embodiment, the number of layers of the capacitor structure is flexibly designed based on the height dimensions of the N+1th dielectric structure 207 and the N+2th dielectric structure 214, which can satisfy the improvement of the integration of the capacitor structure while also taking into account the electrical contact of the capacitor structure.

[0062] In this embodiment, the N+2nd dielectric structure 214 includes: an N+2nd etch stop layer and an N+2nd dielectric layer (not shown) located on the N+2nd etch stop layer, wherein the material of the N+2nd dielectric layer is silicon oxide; in other embodiments, the material of the N+2nd dielectric layer may also be a low-K dielectric material (referring to a dielectric material with a relative permittivity lower than 3.9) or an ultra-low-K dielectric material (referring to a dielectric material with a relative permittivity lower than 2.5).

[0063] Please refer to Figure 11 After forming the N+2nd layer dielectric structure 214, a third metal plug 215 and a fourth metal plug 216 are formed within the N+2nd layer dielectric structure 214. The third metal plug 215 is located on the second top electrode 213, and the fourth metal plug 216 is located on the second bottom electrode 211. The top surfaces of the third metal plug 215 and the fourth metal plug 216 are flush.

[0064] In this embodiment, the third metal plug 215 and the fourth metal plug 216 are made of copper.

[0065] Please refer to Figure 12 An N+2 copper metal interconnect layer 217 is formed within the N+2 layer dielectric structure 214. The N+2 layer copper metal interconnect layer 217 is located on the third metal plug 215 and the fourth metal plug 216, respectively, and the top surface of the N+2 layer copper metal interconnect layer 217 is exposed in the N+2 layer dielectric structure 214.

[0066] Accordingly, embodiments of the present invention also provide a capacitor structure embedded in a copper interconnect; please refer to [further details to follow]. Figure 12The device includes: a substrate, the substrate comprising a base 200 and a device layer 201 on the base 200, the device layer 201 having an Nth copper interconnect layer 202 therein, and the device layer 201 exposing the top surface of the Nth copper interconnect layer 202, where N is an integer greater than or equal to 1; a first insulating layer 205 on the Nth copper interconnect layer 202, the first insulating layer 205 covering a portion of the top surface of the Nth copper interconnect layer 202, and a first top electrode 206 on the first insulating layer 205; a first metal plug 208 on the first top electrode 206, and a first metal plug 208 on the Nth copper interconnect layer 202. A second metal plug 210, the top surfaces of the first metal plug 208 and the second metal plug 210 are flush; an N+1th copper interconnect layer 209 is located on the first metal plug 208 and the second metal plug 210; an N+1th dielectric structure 207 is located on the device layer 201, the N+1th dielectric structure 207 has a first height dimension d1 along the normal direction of the substrate, and the N+1th dielectric structure 207 covers the first insulating layer 205, the first top electrode 206, the first metal plug 208, the second metal plug 210 and the N+1th copper interconnect layer 209, and the N+1th dielectric structure 207 exposes the first... The top surface of the N+1 layer copper interconnect layer 209; the second bottom electrode 211, the second insulating layer 212, and the second top electrode 213 located on the N+1 layer dielectric structure 207, wherein the second bottom electrode 211 is located on the N+1 layer copper interconnect layer 209, the second insulating layer 212 is located on the second bottom electrode 211, and the second top electrode 213 is located on the second insulating layer 212; a third metal plug 215 located on the second top electrode 213, and a fourth metal plug 216 located on the second bottom electrode 211, wherein the top surfaces of the third metal plug 215 and the fourth metal plug 216 are flush; the top surfaces of the third metal plug 215 and the fourth metal plug 216 are flush; The N+2nd copper interconnect layer 217 is located on the fourth metal plug 216; the N+2nd dielectric structure 214 is located on the N+1th dielectric structure 207, the N+2nd dielectric structure 214 has a second height dimension d2 along the normal direction of the substrate, the second height dimension d2 is greater than the first height dimension d1, and the N+2nd dielectric structure 214 covers the second bottom electrode 211, the second insulating layer 212, the second top electrode 213, the third metal plug 215, the fourth metal plug 216 and the N+2nd copper interconnect layer 217, and the N+2nd dielectric structure 214 exposes the top surface of the N+2nd copper interconnect layer 217.

[0067] In this embodiment, the (N+1)th dielectric layer 207 with a first height dimension d1 includes a first insulating layer 205 and a first top electrode 206. Since only the first insulating layer 205 and the first top electrode 206 can be formed within the (N+1)th dielectric layer 207 with the first height dimension d1, the Nth copper interconnect layer 202 is used as an electrode plate, thereby forming a capacitor structure from the Nth copper interconnect layer 202, the first insulating layer 205, and the first top electrode 206. In the direction perpendicular to the substrate surface, the integration density of the capacitor structure can be improved, and a photomask for fabricating an electrode plate can be saved.

[0068] Furthermore, the N+2nd dielectric layer 214 of the second height dimension d2 includes a second bottom electrode 211, a second insulating layer 212 on the second bottom electrode 211, and a second top electrode 213 on the second insulating layer 212. Since the second bottom electrode 211, the second insulating layer 212, and the second top electrode 213 can be formed simultaneously within the N+2nd dielectric layer 214 of the second height dimension d2, it is not necessary to use the N+1th copper interconnect layer 209 as an electrode plate. Moreover, the surface flatness of the second bottom electrode 211 and the second top electrode 213 is higher than that of the N+1th copper interconnect layer 209, resulting in better electrical contact between the subsequently formed third metal plug 215 and fourth metal plug 216 and the second top electrode 213 and the second bottom electrode 211, thereby improving the performance of the final capacitor structure embedded in the copper interconnect.

[0069] Based on the height dimensions of the N+1th dielectric structure 207 and the N+2th dielectric structure 214, the number of layers in the capacitor structure can be flexibly designed, which can both improve the integration of the capacitor structure and take into account the electrical contact of the capacitor structure.

[0070] In this embodiment, the first height dimension d1 ranges from 20 nanometers to 120 nanometers; the second height dimension d2 ranges from 120 nanometers to 2500 nanometers.

[0071] In this embodiment, the first top electrode 206, the second bottom electrode 211, and the second top electrode 213 are made of the same material; the materials of the first top electrode 206, the second bottom electrode 211, and the second top electrode 213 include: titanium nitride or tantalum nitride.

[0072] In this embodiment, the device layer 201 also includes a device structure 203 and an electrical interconnection structure 204; the device structure 203 includes a capacitor structure; the electrical interconnection structure 204 includes a metal plug, the metal plug is electrically connected to the capacitor structure, and the Nth copper metal interconnection layer 202 is electrically connected to the metal plug.

[0073] In this embodiment, the N+1th dielectric structure 207 includes: an N+1th etch stop layer and an N+1th dielectric layer (not shown) located on the N+1th etch stop layer.

[0074] In this embodiment, the N+2nd dielectric structure 214 includes: an N+2nd etch stop layer and an N+2nd dielectric layer (not shown) located on the N+2nd etch stop layer.

[0075] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A capacitor structure embedded in a copper interconnect, characterized in that, include: A substrate, the substrate including a base and a device layer located on the base, the device layer having an Nth copper interconnect layer, and the device layer exposing the top surface of the Nth copper interconnect layer, where N is an integer greater than or equal to 1; A first insulating layer is located on the Nth copper metal interconnect layer, the first insulating layer covering a portion of the top surface of the Nth copper metal interconnect layer and a first top electrode located on the first insulating layer; The first metal plug located on the first top electrode and the second metal plug located on the Nth copper metal interconnect layer have their top surfaces flush. The (N+1)th copper interconnect layer located on the first metal plug and the second metal plug; The N+1th dielectric structure is located on the device layer, the N+1th dielectric structure has a first height dimension along the normal direction of the substrate, the N+1th dielectric structure covers the first insulating layer, the first top electrode, the first metal plug, the second metal plug and the N+1th copper metal interconnect layer, and the N+1th dielectric structure exposes the top surface of the N+1th copper metal interconnect layer; The second bottom electrode, the second insulating layer, and the second top electrode are located on the N+1th dielectric structure. The second bottom electrode is located on the N+1th copper metal interconnect layer, the second insulating layer is located on the second bottom electrode, and the second top electrode is located on the second insulating layer. A third metal plug located on the second top electrode and a fourth metal plug located on the second bottom electrode, the top surfaces of the third metal plug and the fourth metal plug being flush; The N+2th copper interconnect layer located on the third and fourth metal plugs; The (N+2)th dielectric layer is located on the (N+1)th dielectric layer, and the (N+2)th dielectric layer has a second height dimension along the normal direction of the substrate, the second height dimension being greater than the first height dimension. The N+2nd dielectric structure covers the second bottom electrode, the second insulating layer, the second top electrode, the third metal plug, the fourth metal plug, and the N+2nd copper interconnect layer, and the N+2nd dielectric structure exposes the top surface of the N+2nd copper interconnect layer.

2. The capacitor structure embedded in copper interconnects as described in claim 1, characterized in that, The first height dimension ranges from 20 nanometers to 120 nanometers; the second height dimension ranges from 120 nanometers to 2500 nanometers.

3. The capacitor structure embedded in copper interconnects as described in claim 1, characterized in that, The first top electrode, the second bottom electrode, and the second top electrode are made of the same material; the materials of the first top electrode, the second bottom electrode, and the second top electrode include: titanium nitride or tantalum nitride.

4. The capacitor structure embedded in copper interconnects as described in claim 1, characterized in that, The device layer also includes a device structure and an electrical interconnection structure; the device structure includes a capacitor structure; the electrical interconnection structure includes a metal plug, the metal plug being electrically connected to the capacitor structure, and the Nth copper metal interconnection layer being electrically connected to the metal plug.

5. The capacitor structure embedded in copper interconnect as described in claim 1, characterized in that, The N+1th dielectric structure includes: an N+1th etch stop layer and an N+1th dielectric layer located on the N+1th etch stop layer.

6. The capacitor structure embedded in a copper interconnect as described in claim 1, characterized in that, The N+2nd dielectric structure includes: an N+2nd etch stop layer and an N+2nd dielectric layer located on the N+2nd etch stop layer.

7. A method for forming a capacitor structure embedded in a copper interconnect, characterized in that, include: A substrate is provided, the substrate including a base and a device layer located on the base, the device layer having an Nth copper interconnect layer therein, and the device layer exposing the top surface of the Nth copper interconnect layer, where N is an integer greater than or equal to 1; A first insulating layer is formed on the Nth copper metal interconnect layer, the first insulating layer covering a portion of the top surface of the Nth copper metal interconnect layer, and a first top electrode is formed on the first insulating layer; An N+1th dielectric structure is formed on the device layer, the N+1th dielectric structure having a first height dimension along the normal direction of the substrate, and the N+1th dielectric structure covering the first insulating layer and the first top electrode; A first metal plug and a second metal plug are formed within the N+1th dielectric structure. The first metal plug is located on the first top electrode, and the second metal plug is located on the Nth copper interconnect layer. The top surfaces of the first metal plug and the second metal plug are flush. An N+1 copper interconnect layer is formed within the N+1th dielectric structure. The N+1th copper interconnect layer is located on the first metal plug and the second metal plug, respectively, and the N+1th dielectric structure exposes the top surface of the N+1th copper interconnect layer. A second bottom electrode, a second insulating layer, and a second top electrode are formed on the N+1th dielectric structure. The second bottom electrode is located on the N+1th copper metal interconnect layer, the second insulating layer is located on the second bottom electrode, and the second top electrode is located on the second insulating layer. An N+2 dielectric structure is formed on the N+1 dielectric structure. The N+2 dielectric structure has a second height dimension along the normal direction of the substrate. The second height dimension is greater than the first height dimension. The N+2 dielectric structure covers the second bottom electrode, the second insulating layer, and the second top electrode. A third metal plug and a fourth metal plug are formed within the N+2th dielectric structure. The third metal plug is located on the second top electrode, and the fourth metal plug is located on the second bottom electrode. The top surfaces of the third metal plug and the fourth metal plug are flush. An N+2 copper interconnect layer is formed within the N+2 dielectric structure. The N+2 copper interconnect layer is located on the third metal plug and the fourth metal plug, respectively, and the N+2 dielectric structure exposes the top surface of the N+2 copper interconnect layer.

8. The method for forming a capacitor structure embedded in a copper interconnect as described in claim 7, characterized in that, The first height dimension ranges from 20 nanometers to 120 nanometers; the second height dimension ranges from 120 nanometers to 2500 nanometers.

9. The method for forming a capacitor structure embedded in a copper interconnect as described in claim 7, characterized in that, The first top electrode, the second bottom electrode, and the second top electrode are made of the same material; the materials of the first top electrode, the second bottom electrode, and the second top electrode include: titanium nitride or tantalum nitride.

10. The method for forming a capacitor structure embedded in a copper interconnect as described in claim 7, characterized in that, The device layer also includes a device structure and an electrical interconnection structure; the device structure includes a capacitor structure; the electrical interconnection structure includes a metal plug, the metal plug being electrically connected to the capacitor structure, and the Nth copper metal interconnection layer being electrically connected to the metal plug.

11. The method for forming a capacitor structure embedded in a copper interconnect as described in claim 7, characterized in that, The N+1th dielectric structure includes: an N+1th etch stop layer and an N+1th dielectric layer located on the N+1th etch stop layer.

12. The method for forming a capacitor structure embedded in a copper interconnect as described in claim 7, characterized in that, The N+2nd dielectric structure includes: an N+2nd etch stop layer and an N+2nd dielectric layer located on the N+2nd etch stop layer.

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