Wafer level packaging method and packaging structure of filter chip

Abstract

The invention discloses a wafer-level packaging method and packaging structure for filter chips, and the packaging method comprises the steps: providing a substrate wafer, the front surface of the substrate wafer is provided with a plurality of to-be-packaged filter chips, and each filter chip comprises an effective function region and a plurality of I / O pins located at the periphery of the effective function region; forming an enclosing wall surrounding the effective function area around the filter chip, and forming a first opening for exposing the I / O pin in the enclosing wall; a top cover layer is manufactured, the size of the top cover layer is matched with the size of the substrate wafer, and a net-shaped reinforcing structure is arranged in the top cover layer; one side surface of the top cover layer is bonded with the top surface of the enclosing wall, a cavity is defined by the top cover layer and the enclosing wall, and the effective function area is located in the cavity. The strength of the cavity top cover structure of the filter chip is improved, and the problem of cavity collapse is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and more particularly, to a wafer-level packaging method and packaging structure for a filter chip. Background Art

[0002] In recent years, with the increasing demand for miniaturization of radio frequency modules, the packaging of filters has developed rapidly. A mainstream process is the wafer-level packaging (WLP) of filters. After directly forming a wall on the filter substrate by lithography of an organic material, a photosensitive organic material (such as a dry film) is attached to the wall and a cavity roof is formed by a lithography process. Then, the pins are led out through laser or etching and electroplating processes, and then welded to the packaging substrate or PCB through the pins to finally obtain a radio frequency module. However, the traditional organic material for lithography to make the cavity roof has high material cost, complex process, and insufficient structural strength of the cavity roof, and it is easy to have the problem of cavity collapse during the packaging process, thus unable to ensure the quality of the packaging process and affecting the chip performance. Summary of the Invention

[0003] The object of the present invention is to provide a wafer-level packaging method and packaging structure for a filter chip, so as to improve the strength of the cavity roof structure and avoid the problem of cavity collapse.

[0004] To achieve the above object, in a first aspect, the present invention provides a wafer-level packaging method for a filter chip, including:

[0005] Providing a substrate wafer, the front surface of the substrate wafer has a plurality of filter chips to be packaged, and the filter chip includes an effective functional area and a plurality of I / O pins located around the effective functional area;

[0006] Forming a wall surrounding the effective functional area around the filter chip, and forming a first opening exposing the I / O pins in the wall;

[0007] Fabricating a top cover layer, the size of the top cover layer matches the size of the substrate wafer, and the inside of the top cover layer has a mesh reinforcement structure;

[0008] Gluing one side surface of the top cover layer to the top surface of the wall, the top cover layer and the wall enclose a cavity, and the effective functional area is located in the cavity.

[0009] Optionally, the fabricating the top cover layer includes:

[0010] Providing a top cover layer material, the components of the top cover layer material include resin and glass fiber cloth;

[0011] Press and cure the top cover layer material into a hard film with a set thickness as the top cover layer, and the fiberglass cloth forms the network reinforcement structure inside the top cover layer.

[0012] Optionally, before bonding one side surface of the top cover layer to the top surface of the enclosure, it further includes:

[0013] Pre - fabricate a second opening corresponding to the first opening on the top cover layer;

[0014] When bonding one side surface of the top cover layer to the top surface of the enclosure, align the second opening with the first opening to expose the I / O pins.

[0015] Optionally, after bonding one side surface of the top cover layer to the top surface of the enclosure, it further includes:

[0016] Form I / O terminals electrically connected to the I / O pins in the first opening and the second opening;

[0017] Form a third opening on the top cover layer, and the third opening exposes the scribe lanes between multiple filter chips on the substrate wafer;

[0018] Cut the substrate wafer along the scribe lanes to divide the multiple filter chips into individual packaged chips.

[0019] Optionally, after bonding one side surface of the top cover layer to the top surface of the enclosure, it further includes:

[0020] Form a second opening and a third opening on the top cover layer, the second opening exposes the I / O pins, and the third opening exposes the scribe lanes between multiple filter chips on the substrate wafer;

[0021] Form I / O terminals electrically connected to the I / O pins in the first opening and the second opening;

[0022] Cut the substrate wafer along the scribe lanes to divide the multiple filter chips into individual packaged chips.

[0023] Optionally, after bonding one side surface of the top cover layer to the top surface of the enclosure, it further includes:

[0024] Form a third opening on the top cover layer, and the third opening exposes the scribe lanes between multiple filter chips on the substrate wafer;

[0025] Form a sealing layer on the front surface of the substrate wafer, and the sealing layer covers the side walls of the top cover layer and the enclosure and fills the third opening;

[0026] Form a second opening exposing the I / O pins on the sealing layer and the top cover layer;

[0027] Form I / O terminals electrically connected to the I / O pins in the first opening and the second opening;

[0028] Cut the substrate wafer along the scribe lane to divide the multiple filter chips into individual packaged chips.

[0029] Optionally, bonding one side surface of the top cover layer to the top surface of the enclosure includes:

[0030] Coat an adhesive layer on one side surface of the top cover layer or the top surface of the enclosure, and bond the top cover layer and the enclosure together through the adhesive layer.

[0031] In a second aspect, the present invention provides a wafer-level packaging structure for a filter chip, including:

[0032] A substrate wafer, the front surface of the substrate wafer having multiple filter chips, the filter chips including an effective functional area and a plurality of I / O pins located around the effective functional area;

[0033] An enclosure surrounding the effective functional area is provided around the filter chip, a top cover layer is provided on the enclosure, one side surface of the top cover layer is bonded to the top surface of the enclosure, the top cover layer and the enclosure enclose a cavity, and the effective functional area is located in the cavity;

[0034] The material of the top cover layer includes resin and fiberglass cloth, and the fiberglass cloth constitutes the mesh reinforcing structure. Optionally, the material of the top cover layer includes resin and fiberglass cloth.

[0035] Optionally, it further includes I / O terminals, the I / O terminals penetrate the top cover layer and the enclosure and are electrically connected to the I / O pins;

[0036] And / or,

[0037] It further includes a sealing layer, the sealing layer covering the side walls of the top cover layer and the enclosure.

[0038] The beneficial effects of the present invention are as follows:

[0039] The present invention manufactures a top cover layer with a mesh reinforcement structure inside, and then bonds the top cover layer to the enclosure to form a cavity. Since the top cover layer has a mesh reinforcement structure inside, the structural strength of the top cover layer is higher, which can greatly improve the compressive resistance of the cavity top cover, thereby effectively avoiding the problem of cavity collapse during the encapsulation process, and further ensuring the encapsulation quality and product performance of the filter chip. At the same time, the cavity top cover with a mesh reinforcement structure inside adopted by the present invention has a higher structural strength compared with the traditional cavity top cover made of photosensitive organic materials, and the process steps are simpler, which can effectively reduce the process cost.

[0040] The system of the present invention has other characteristics and advantages, which will be obvious from the accompanying drawings incorporated herein and the subsequent detailed description, or will be described in detail in the accompanying drawings incorporated herein and the subsequent detailed description. These accompanying drawings and detailed description are jointly used to explain the specific principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] By describing the exemplary embodiments of the present invention in more detail in conjunction with the accompanying drawings, the above and other objects, features, and advantages of the present invention will become more obvious. In the exemplary embodiments of the present invention, the same reference numerals generally represent the same components.

[0042] Figures 1 - 9 It is a device structure diagram corresponding to each step of a wafer-level packaging method for a filter chip according to Embodiment 1 of the present invention.

[0043] Figure 10 It is a schematic structural diagram of the top cover layer.

[0044] Figure 11 It is a physical slice diagram of the top cover layer.

[0045] Figures 12 - 16 It is a device structure diagram corresponding to each step of a wafer-level packaging method for a filter chip according to Embodiment 2 of the present invention.

[0046] Figures 17 - 21 It is a device structure diagram corresponding to each step of a wafer-level packaging method for a filter chip according to Embodiment 3 of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0047] The present invention will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present invention more thorough and complete, and to fully convey the scope of the present invention to those skilled in the art.

[0048] Embodiment 1

[0049] This embodiment provides a wafer-level packaging method for a filter chip, comprising the following steps:

[0050] S1: Provide a substrate wafer 1, the front surface of the substrate wafer 1 having a plurality of filter chips to be packaged, the filter chips comprising an effective functional area and a plurality of I / O pins 3 located around the effective functional area;

[0051] As Figure 1 shown, in this embodiment, the filter chips to be packaged are surface acoustic wave (SAW) filter chips, the substrate wafer 1 is a piezoelectric substrate, an interdigital transducer 2 (IDT) is provided in the effective functional area, a plurality of I / O pins 3 are located at the chip edge, and the I / O pins 3 are electrically connected to the interdigital transducer and are bonding pads exposed on the surface of the piezoelectric substrate.

[0052] In other embodiments, the filter chips to be packaged may also be bulk acoustic wave filter chips, such as BAW filter chips, FBAR filter chips. Correspondingly, a piezoelectric stack structure (including a stacked upper electrode, piezoelectric layer, and lower electrode) of bulk acoustic wave resonator units is provided in the effective functional area, and the substrate wafer 1 may have corresponding working cavities or Bragg reflectors. This embodiment takes the SAW filter chip as an example to illustrate the packaging method of the present invention.

[0053] S2: Form a fence 4 surrounding the effective functional area around the filter chips, and form a first opening 5 exposing the I / O pins 3 in the fence 4;

[0054] As Figure 2 and Figure 3 shown ( Figure 2 is a cross-sectional view, Figure 3 is a top view), in this step, a support layer may be formed on the front surface of the substrate wafer 1, the support layer covering the effective functional area and the I / O pins 3 of the filter chips, and then the support layer is patterned to expose the effective functional area and form a first opening 5 exposing the I / O pins 3. In this embodiment, the material of the support layer is preferably a dry film. A layer of dry film is coated or attached to the front surface of the substrate wafer 1 to form a support layer, the thickness of the support layer being greater than the electrode thickness of the interdigital transducer 2 in the effective functional area, and then the dry film is patterned (exposed and developed) to expose the effective functional area and the I / O pins 3, and at the same time expose the scribe lanes between the filter chips, thereby forming a fence 4 surrounding the effective functional area.

[0055] S3: Fabricate a top cover layer, the size of the top cover layer matching the size of the substrate wafer, and the interior of the top cover layer having a mesh reinforcement structure;

[0056] This step specifically includes: providing a top cover layer material, the components of the top cover layer material including resin and fiberglass cloth; laminating and curing the top cover layer material into a rigid film with a set thickness as the top cover layer 6, and the fiberglass cloth forms the reticular reinforcement structure inside the top cover layer 6, and its structure is as Figure 10 shown.

[0057] In this embodiment, to reduce material and process costs, the top cover layer material is preferably a PP material, and the components of the PP material include fiberglass cloth, resin, hardener, accelerant, solvent, and filler. The PP material is laminated and cured to form a rigid film with a set thickness (hereinafter referred to as the PP board), and the PP board has horizontally and vertically interwoven fiberglass (fiberglass cloth) inside. The PP board is used as the top cover layer 6, and the size of the top cover layer 6 matches the size of the substrate wafer 1. In other embodiments, other suitable adhesives and other insulating fiber materials other than resin can also be selected to make the top cover layer 6 of the present invention.

[0058] In the specific implementation process, a single layer or multiple layers of PP (PREPREG, semi-cured sheet) materials can be laminated and cured to form a rigid PP board with a thickness of 15 - 20 um, and the PP board is used as the material for subsequently making the top cover layer 6. The PP material is mainly composed of resin and fiberglass cloth, and its structure is as Figure 10 shown, and the physical section is as Figure 11 shown. The horizontally and vertically interwoven fiberglass structure in the fiberglass cloth can greatly improve the structural strength and compressive capacity of the top cover layer 6, thereby avoiding the problem of cavity top cover collapse during the process.

[0059] In this embodiment, a PP board having substantially the same size as the substrate wafer 1 is used as the top cover layer 6, and a second opening 7 corresponding to the first opening 5 on the enclosure wall 4 is prefabricated on the top cover layer 6. The second opening 7 can be prefabricated on the PP board by means of laser ablation.

[0060] S4: Bond one side surface of the top cover layer 6 to the top surface of the enclosure wall 4, and the top cover layer 6 and the enclosure wall 4 enclose a cavity, and the effective functional area is located inside the cavity.

[0061] As Figure 4 and Figure 5 shown ( Figure 4 is a cross-sectional view, Figure 5 is a top view), in this step, an adhesive layer 8 is coated on one side surface of the top cover layer 6 or the top surface of the enclosure wall 4, and the top cover layer 6 and the enclosure wall 4 are bonded together through the adhesive layer 8, so that the effective functional area of the filter chip is located inside the cavity enclosed by the top cover layer 6 and the enclosure wall 4. When bonding one side surface of the top cover layer 6 to the top surface of the enclosure wall 4, the second opening 7 is aligned with the first opening 5 to expose the I / O pins 3.

[0062] In this embodiment, after bonding one side surface of the top cover layer 6 to the top surface of the enclosure 4, the following steps are further included:

[0063] S5: Form I / O terminals 9 electrically connected to the I / O pins 3 in the first opening 5 and the second opening 7;

[0064] As Figure 6 shown, this step can be achieved by forming a seed layer in the first opening 5 and the second opening 7, then forming copper pillars electrically connected to the I / O pins 3 in the first opening 5 and the second opening 7 through an electroplating process, and then forming solder balls on the top of the copper pillars through a reflow soldering process, thereby fabricating the I / O terminals 9 for electrical lead-out.

[0065] S6: Form a third opening 10 in the top cover layer 6, and the third opening 10 exposes the saw streets between multiple filter chips on the substrate wafer 1;

[0066] As Figure 7 shown, this step can be achieved by forming the third opening 10 exposing the saw streets on the top cover layer 6 by means of laser ablation.

[0067] S7: Cut the substrate wafer 1 along the saw streets to divide the multiple filter chips into individual packaged chips.

[0068] As Figures 8 - 9 shown, after the saw streets are exposed, the substrate wafer 1 is scribed along the saw streets, thereby dividing the multiple filter chips on the wafer into individual packaged chips.

[0069] Embodiment 2

[0070] This embodiment provides another wafer-level packaging method for filter chips. The difference between this embodiment and Embodiment 1 is that in this embodiment, the second opening 7 is not prefabricated on the top cover layer 6, but the second opening 7 is fabricated after bonding the top cover layer 6 to the enclosure 4. The specific steps are as follows:

[0071] S01: Provide a substrate wafer 1, the front surface of the substrate wafer 1 has multiple filter chips to be packaged, and the filter chips include an effective functional area and multiple I / O pins 3 located around the effective functional area;

[0072] S02: Form an enclosure 4 surrounding the effective functional area around the filter chips, and form a first opening 5 exposing the I / O pins 3 in the enclosure 4;

[0073] For the specific implementation manners of the above steps S01 - S02, please refer to steps S1 - S2 of Embodiment 1 and Figures 1 - 3 , and details are not described herein.

[0074] S03: Fabricate the top cover layer, the size of the top cover layer matching that of the substrate wafer, and the interior of the top cover layer having a mesh reinforcement structure;

[0075] Similar to Example 1, press and cure the PP material to form a PP board, the interior of the PP board having horizontally and vertically interwoven glass fibers, and use the PP board as the top cover layer 6, the size of the top cover layer 6 matching that of the substrate wafer 1;

[0076] Different from Example 1, in this step, the complete PP board is used as the top cover layer 6, and no second opening 7 is prefabricated on the PP board.

[0077] S04: Bond one side surface of the top cover layer 6 to the top surface of the enclosure 4, the top cover layer 6 and the enclosure 4 enclosing a cavity, and the effective functional area being located within the cavity.

[0078] As Figure 12 and Figure 13 shown ( Figure 12 is a cross-sectional view, Figure 13 is a top view), in this step, bond one side surface of the top cover layer 6 to the top surface of the enclosure 4 through the adhesive layer 8.

[0079] S05: Form a second opening 7 and a third opening 10 on the top cover layer 6, the second opening 7 exposing the I / O pins 3, and the third opening 10 exposing the cutting channels between multiple filter chips on the substrate wafer 1;

[0080] As Figure 14 and Figure 15 shown ( Figure 14 is a cross-sectional view, Figure 15 is a top view), in this step, use the laser ablation method to simultaneously form the second opening 7 exposing the I / O pins 3 and the third opening 10 exposing the cutting channels on the top cover layer 6.

[0081] S06: Form I / O terminals 9 electrically connected to the I / O pins 3 in the first opening 5 and the second opening 7;

[0082] As Figure 16 shown, in this step, form the I / O terminals 9 in the first opening 5 and the second opening 7 through electroplating and reflow soldering processes.

[0083] S07: Cut the substrate wafer 1 along the cutting channels to divide the multiple filter chips into individual packaged chips.

[0084] This step can refer to Figures 8 - 9 , and since the cutting channels have been exposed by the third opening 10, the substrate wafer 1 can be directly sliced along the cutting channels to form multiple individual packaged chips.

[0085] Example 3

[0086] This embodiment provides another wafer-level packaging method for filter chips. The difference between this embodiment and the above-mentioned Embodiment 2 is that a sealing layer 11 is added on the top cover layer 6 to prevent moisture from invading and damaging the device due to the gap between the top cover layer 6 and the enclosure 4. The method of this embodiment includes the following steps:

[0087] S001: Provide a substrate wafer 1, the front surface of the substrate wafer 1 has a plurality of filter chips to be packaged, and the filter chips include an effective functional area and a plurality of I / O pins 3 located around the effective functional area;

[0088] S002: Form an enclosure 4 surrounding the effective functional area around the filter chip, and form a first opening 5 exposing the I / O pins 3 in the enclosure 4;

[0089] S003: Fabricate a top cover layer, the size of the top cover layer matches the size of the substrate wafer, and the inside of the top cover layer has a mesh reinforcement structure;

[0090] S004: Bond one side surface of the top cover layer 6 to the top surface of the enclosure 4, and the top cover layer 6 and the enclosure 4 enclose a cavity, and the effective functional area is located in the cavity.

[0091] The above steps are the same as steps S01 - S04 of Embodiment 2 and will not be elaborated here. Based on Figure 12 the device structure, the following subsequent steps are carried out.

[0092] S005: Form a third opening 10 on the top cover layer 6, and the third opening 10 exposes the saw streets between the plurality of filter chips on the substrate wafer 1;

[0093] As Figure 17 shown, in this step, a third opening 10 exposing the saw streets is formed on the top cover layer 6 by means of laser ablation.

[0094] S006: Form a sealing layer 11 on the front surface of the substrate wafer 1, the sealing layer 11 covers the top cover layer 6 and the side walls of the enclosure 4, and fills the third opening 10;

[0095] As Figure 18 shown, in this step, a sealing layer 11 is formed on the top cover layer 6, and the material of the sealing layer 11 is preferably photosensitive resin.

[0096] S007: Form a second opening 7 exposing the I / O pins 3 on the sealing layer 11 and the top cover layer 6;

[0097] AsFigure 19 As shown in the figure, in this step, the top cover layer 6 and the sealing layer 11 above the first opening 5 are removed to form a second opening 7 exposing the I / O pins 3. The top cover layer 6 and the sealing layer 11 can be ablated simultaneously by laser to form the second opening 7. It is also possible to first pattern and remove the sealing layer 11 (photosensitive resin) above the first opening 5 through a photolithography process, and then remove the sealing layer 11 above the first opening 5 by laser ablation, thereby forming the second opening 7.

[0098] S008: Form I / O terminals 9 electrically connected to the I / O pins 3 in the first opening 5 and the second opening 7;

[0099] As Figure 20 shown in the figure, in this step, the I / O terminals 9 are formed in the first opening 5 and the second opening 7 through electroplating and reflow soldering processes.

[0100] S009: Cut the substrate wafer 1 along the scribe lanes to divide the multiple filter chips into individual packaged chips.

[0101] As Figure 21 shown in the figure, in this step, the substrate wafer 1 is cut along the scribe lanes to form a filter chip packaging structure with a sealing layer 11.

[0102] Embodiment 4

[0103] As Figure 6 or Figure 16 shown in the figure, this embodiment provides a wafer-level packaging structure for a filter chip, including:

[0104] A substrate wafer 1, the front surface of the substrate wafer 1 has multiple filter chips, and the filter chips include an effective functional area and a plurality of I / O pins 3 located around the effective functional area;

[0105] A fence 4 surrounding the effective functional area is provided around the filter chip. A top cover layer 6 is provided on the fence 4. One side surface of the top cover layer 6 is adhered to the top surface of the fence 4. The top cover layer 6 and the fence 4 enclose a cavity, and the effective functional area is located in the cavity;

[0106] The interior of the top cover layer 6 has a mesh reinforcement structure. The material of the top cover layer 6 includes resin and fiberglass cloth, and the fiberglass cloth constitutes the mesh reinforcement structure. In this embodiment, the material of the top cover layer 6 is preferably a PP material. The PP material is pressed and cured into a hard film (PP board) with a set thickness to form the top cover layer 6, and the internal mesh fiberglass cloth serves as a reinforcement structure to improve the overall strength of the top cover layer.

[0107] In this embodiment, the encapsulation structure further includes an I / O terminal 9, and the I / O terminal 9 penetrates through the top cover layer 6 and the enclosure 4 and is electrically connected to the I / O pin 3.

[0108] In other embodiments, as Figure 20 shown, the encapsulation structure further includes a sealing layer 11, and the sealing layer 11 covers the side walls of the top cover layer 6 and the enclosure 4.

[0109] The embodiments of the present invention have been described above. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A wafer-level packaging method for a filter chip, characterized in that, Comprising: Providing a substrate wafer, on the front surface of which there are multiple filter chips to be encapsulated, the filter chips including an effective functional area and a plurality of I / O pins located around the effective functional area; Forming a wall around the filter chip to enclose the effective functional area, and forming a first opening in the wall to expose the I / O pins; Fabricating a top cover layer, the size of the top cover layer matching the size of the substrate wafer, and the interior of the top cover layer having a mesh reinforcement structure; Bonding one side surface of the top cover layer to the top surface of the wall, the top cover layer and the wall enclosing a cavity, and the effective functional area being located within the cavity.

2. The wafer-level packaging method of the filter chip according to claim 1, wherein The fabricating the top cover layer includes: Providing a top cover layer material, the components of the top cover layer material including resin and fiberglass cloth; Pressing and curing the top cover layer material into a hard film with a set thickness as the top cover layer, and the fiberglass cloth forming the mesh reinforcement structure within the top cover layer.

3. The wafer-level packaging method of the filter chip according to claim 1, wherein Before bonding one side surface of the top cover layer to the top surface of the wall, it further includes: Pre-forming a second opening corresponding to the first opening on the top cover layer; When bonding one side surface of the top cover layer to the top surface of the wall, aligning the second opening with the first opening to expose the I / O pins.

4. The wafer-level packaging method of the filter chip according to claim 3, characterized in that, After bonding one side surface of the top cover layer to the top surface of the wall, it further includes: Forming I / O terminals electrically connected to the I / O pins within the first opening and the second opening; Forming a third opening on the top cover layer, the third opening exposing the saw streets between multiple filter chips on the substrate wafer; Cutting the substrate wafer along the saw streets to divide the multiple filter chips into individual packaged chips.

5. The wafer-level packaging method of the filter chip according to claim 1, characterized in that After bonding one side surface of the top cover layer to the top surface of the wall, it further includes: Forming a second opening and a third opening on the top cover layer, the second opening exposing the I / O pins, and the third opening exposing the saw streets between multiple filter chips on the substrate wafer; Forming I / O terminals electrically connected to the I / O pins within the first opening and the second opening; Cutting the substrate wafer along the saw streets to divide the multiple filter chips into individual packaged chips.

6. The wafer-level packaging method of the filter chip according to claim 1, characterized in that After bonding one side surface of the top cover layer to the top surface of the wall, it further includes: Forming a third opening on the top cover layer, the third opening exposing the saw streets between multiple filter chips on the substrate wafer; Forming a sealing layer on the front surface of the substrate wafer, the sealing layer covering the side walls of the top cover layer and the wall, and filling the third opening; Forming a second opening exposing the I / O pins on the sealing layer and the top cover layer; Forming I / O terminals electrically connected to the I / O pins within the first opening and the second opening; Cutting the substrate wafer along the saw streets to divide the multiple filter chips into individual packaged chips.

7. The wafer-level packaging method of the filter chip according to claim 1, characterized in that Bonding one side surface of the top cover layer to the top surface of the wall includes: Apply an adhesive layer on one side surface of the top cover layer or on the top surface of the enclosure wall, and bond the top cover layer and the enclosure wall together through the adhesive layer.

8. A wafer-level packaging structure of a filter chip, characterized in that, Comprising: A substrate wafer, on the front surface of which there are a plurality of filter chips, and the filter chips include an effective functional area and a plurality of I / O pins located around the effective functional area; Around the filter chips, there is an enclosure wall surrounding the effective functional area, and on the enclosure wall there is a top cover layer. One side surface of the top cover layer is bonded to the top surface of the enclosure wall. The top cover layer and the enclosure wall enclose a cavity, and the effective functional area is located within the cavity; The interior of the top cover layer has a mesh reinforcement structure.

9. The wafer-level packaging structure of the filter chip according to claim 8, characterized in that, The material of the top cover layer includes resin and fiberglass cloth, and the fiberglass cloth constitutes the mesh reinforcement structure.

10. The wafer-level packaging structure of the filter chip according to claim 8, characterized in that, It further includes I / O terminals, and the I / O terminals penetrate through the top cover layer and the enclosure wall and are electrically connected to the I / O pins; And / or, It further includes a sealing layer, and the sealing layer covers the top cover layer and the side walls of the enclosure wall.

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