Active eye opening detection correction device and correction method

Abstract

The invention relates to an active eye opening detection correction device and a correction method, which receive a reference clock signal and an eye opening detection clock signal, control whether the reference clock signal is sampled from the eye opening detection clock signal or not by adopting a correction selection signal, and then output an indication signal. The phase indication decision circuit receives the indication signal and executes a correction program according to the indication signal so as to output a phase offset signal, so that the eye opening detection clock signal can be corrected according to the phase offset signal so as to be in phase with a reference clock signal synchronously after correction. By adopting the active eye opening detection correction device and correction method disclosed by the invention, the phase synchronization of the eye opening detection clock signal and the reference clock signal thereof can be effectively realized, and meanwhile, the problems of phase delay or mismatch and the like in the prior art are solved.

Description

Technical Field

[0001] The present invention relates to a calibration technique for an eye opening detection clock signal, and particularly to an active calibration device and a calibration method for an eye opening detection clock signal. By adopting a calibration program, the calibrated eye opening detection clock signal can be in phase with its reference clock signal synchronously. Background Art

[0002] In a binary data transmission system, an eye diagram is a commonly used signal measurement method. For example, two common noises affecting a data transmission system include, for example, amplitude noise and timing jitter. By using the measurement of an eye diagram, better analysis can be provided for these noises, especially timing jitter, and the extinction ratio can also be measured. Traditional eye diagram measurement usually requires the use of a digital oscilloscope, so a large amount of data needs to be collected, which is very time-consuming. Therefore, it is not suitable for real-time processing. In view of this, an improved method using digital signal processing (DSP) can be used to improve the traditional eye diagram measurement method.

[0003] In view of the fact that an eye diagram is a very effective measurement that can provide an effective visual inspection for inter-symbol interference (ISI), clock error, and noise margin in a signal transmission system. At the same time, a large amount of information can be directly provided by generating an eye diagram. Therefore, an eye open monitor (EOM), hereinafter referred to as eye opening detection, is used to check whether the signal quality is good, which is actually a common detection module in today's high-speed data transmission system. By adopting eye opening detection, the input signal quality of the signal at the input end of a clock and data recovery (CDR) system can be monitored in real time. For example, please refer to Figure 1 which is a circuit architecture diagram showing the application of eye opening detection in a de-serializer circuit in the prior art, as shown in Figure 1As shown, the input signal RXIN sequentially passes through a continuous time linear equalizer (CTLE) 10, several D-type flip-flops 20, 22, 24, 26, and the sampling clock signals CLK_0, CLK_90, CLK_180, CLK_270, and a demultiplexer (DMX) 30 for data transmission in the system. For the transmitted data signal among them, in order to evaluate its yield, it is usually necessary to detect the eye diagram of the data signal to determine whether the performance of the data transmission system is good. Generally speaking, the eye diagram measurement of the prior art mainly uses multiple different clock signals, for example: CLK_0, CLK_90, CLK_180, CLK_270 to sample and scan the data, so as to extract the eye diagram quality of the input data. By using an eye opening detection circuit (EOM) 40 with an adjustable threshold VTH and a sampling clock as a data sampler, the signal quality of the input signal RXIN in the CDR data transmission system can be detected. Among them, as Figure 1 shown, these sampling clock signals can usually be provided by using a phase interpolator (PI). Further, please refer to Figure 2 shown, which discloses the waveform schematic diagrams of the respective clock signals in the prior art Figure 1 . Among them, these sampling clock signals CLK_0, CLK_90, CLK_180, CLK_270 each have different phases (0 degrees, 90 degrees, 180 degrees, 270 degrees). The eye opening detection clock signal CLK_EOM@0 has the same phase (0 degrees) as the sampling clock signal CLK_0, so it is denoted by "CLK_EOM@0". It should be noted that, in order to achieve the purpose of reducing power, the eye opening detection clock signal CLK_EOM@0 usually forms a phase delay 221 with other sampling clock signals, and such a phase delay 221 is usually caused by the phase interpolator. Therefore, problems of asynchronous transmission of data often occur in the existing deserialization circuits. In addition, the phase mismatch problem between the eye opening detection signal and other sampling clock signals, as shown by the variable 223 in the figure, also has various variations due to the PVT (process, voltage, and temperature) problems in the circuit process. In view of the above, it is obvious that for the existing eye opening detection clock signal CLK_EOM, due to the problems of phase delay and unstable variations, it cannot meet the requirement of signal in-phase in the data transmission system, resulting in problems such as transmission data errors and asynchronization in the system.

[0004] In view of this, in order to ensure the synchronization between the open - eye detection clock signal CLK_EOM and its reference clock signal, several methods have been disclosed in the prior art, but the effectiveness is still not significant. Therefore, how to further provide more effective improvement and alternative methods has become one of the research focuses that need to be urgently developed in recent years. Thus, in view of the above, it can be clearly seen that professionals in this field urgently need to develop an open - eye detection circuit that is both novel and creative and can improve the prior art, so as to solve the problems existing in the above - mentioned prior art, make the eye - diagram measurement signal and the clock signal in the transmission system synchronized, and avoid errors in the transmitted data. Summary of the Invention

[0005] To solve the above - mentioned various deficiencies, an object of the present invention is to provide an optimized active open - eye detection and correction device and its correction method.

[0006] By adopting the active open - eye detection and correction device disclosed in the present invention, it can achieve the inventive effect of making the open - eye detection clock signal CLK_EOM in instant in - phase with its reference clock signal (such as but not limited to CLK_0, CLK_90, CLK_180, CLK_270). The present invention can eliminate the problem of phase mismatch between sampling clock signals in the prior art and avoid errors in the transmitted data. Therefore, when applied to a clock - data recovery (CDR) data transmission system, it can effectively measure and evaluate its input signal accurately.

[0007] What the present invention discloses is an active open - eye detection and correction device and its active correction method. In one embodiment, the present invention takes the deserialization circuit applied in a CDR data transmission system as an illustrative example for the following description. However, the present invention is not limited to this application. According to the active open - eye detection and correction device and correction method disclosed in the present invention, it can also be optionally applied to other types of data transmission systems. Once the technical solution disclosed herein is known, optional substitution and modification examples will be optional for those skilled in the art, but still should belong to the scope of the present invention.

[0008] According to the illustrative example of the present invention, the active open - eye detection and correction device disclosed in the present invention includes: a phase - control circuit, a phase - indication determination circuit, and a phase - correction circuit. The phase - control circuit is adapted to receive a reference clock signal and an open - eye detection clock signal, and a correction selection signal is provided to the phase - control circuit to control whether to sample the open - eye detection clock signal with the reference clock signal or sample the reference clock signal with the open - eye detection clock signal. Then, the phase - control circuit outputs an indication signal.

[0009] The described phase indication determination circuit is electrically coupled to the phase control circuit and receives the indication signal, such that the phase indication determination circuit can execute a calibration procedure according to the indication signal, thereby outputting a phase offset signal.

[0010] The described phase calibration circuit is electrically coupled to the phase indication determination circuit and receives the phase offset signal, such that the phase calibration circuit calibrates the eye opening detection clock signal according to the phase offset signal. Therefore, the calibrated eye opening detection clock signal can be in phase with its reference clock signal synchronously and have the same phase.

[0011] Specifically, according to an embodiment of the present invention, when the calibration selection signal is at a low voltage level, the eye opening detection clock signal samples the reference clock signal, and when the indication signal remains at the low voltage level, a phase control signal increases sequentially. When the indication signal transitions and stably maintains at the high voltage level, at this time, the phase control signal correspondingly has a first phase. The present invention records this first phase.

[0012] After that, the indication signal is reset to the low voltage level, and the calibration selection signal is switched to the high voltage level, and then the reference clock signal samples the eye opening detection clock signal. In this case, when the indication signal remains at the low voltage level, the phase control signal decreases sequentially. When the indication signal transitions and stably maintains at the high voltage level, at this time, the phase control signal correspondingly has a second phase. The present invention records this second phase.

[0013] Based on this, the average value of the first phase and the second phase is calculated as a final phase, and the final phase is output as the phase offset signal. Therefore, the phase calibration circuit can receive the phase offset signal and calibrate the eye opening detection clock signal according to the average value of the first phase and the second phase, such that the calibrated eye opening detection clock signal can be in phase with the reference clock signal synchronously.

[0014] On the other hand, the present invention also provides an active eye opening detection calibration method, including the following steps:

[0015] (a) Providing a calibration selection signal to control whether to sample an eye opening detection clock signal with a reference clock signal and output an indication signal;

[0016] (b) Executing a calibration procedure according to the indication signal to output a phase offset signal; and

[0017] (c) Calibrating the eye opening detection clock signal according to the phase offset signal, such that the calibrated eye opening detection clock signal is in phase with the reference clock signal synchronously.

[0018] According to an embodiment of the present invention, the reference clock signal optionally has an initial sampling clock phase of 0 degrees, 90 degrees, 180 degrees, or 270 degrees. Moreover, the reference clock signal and the eye opening detection clock signal can be received by a data selection circuit, and the data selection circuit is triggered and enabled by a calibration selection signal. Preferably, the data selection circuit can be composed of at least one multiplexer triggered and enabled by the calibration selection signal.

[0019] Meanwhile, a buffer circuit can be further electrically coupled to the data selection circuit, such that a data input terminal and a clock input terminal of the buffer circuit can be selectively switched between the reference clock signal and the eye opening detection clock signal under the control of the calibration selection signal, so that the reference clock signal samples the eye opening detection clock signal, or the eye opening detection clock signal samples the reference clock signal. According to an embodiment of the present invention, the buffer circuit can be composed of, for example, a D flip-flop. The D flip-flop generates and outputs the indication signal (such as a flag signal) for reception by the phase indication decision circuit, so that the calibration procedure can be further executed based on the indication signal.

[0020] Therefore, by adopting the technical solution disclosed in the present invention, the phase synchronization between the eye opening detection clock signal and its reference clock signal can be effectively achieved.

[0021] The active eye opening detection calibration device and the active eye opening detection calibration method disclosed in the present invention are described by taking their application to a CDR transmission system as an example, but the present invention is not limited to this application. Those skilled in the art can optionally design applicable implementation forms according to their needs. When the present invention is applied to other optional data transmission systems, the phase synchronization of the clock signal can also be achieved, and the problem of phase mismatch can be avoided. Thus, it can be assured that the present invention has successfully solved the long-existing deficiencies in this technical field, and thus has a high industrial competitiveness and can be widely applied in this technical field.

[0022] Generally speaking, the active eye-opening detection and correction device and correction method disclosed according to the present invention can preferably be applied to existing known data transmission system architectures. Once the disclosure content of this application is known, other alternative and modified exemplary examples will be obvious to those skilled in the art. However, the present invention is not limited to the disclosed embodiments, and the patent scope claimed by the present invention requires and covers other alternative examples and modified examples equivalent thereto. At the same time, it should be understood that the foregoing technical abstract and the following detailed description are both exemplary and are intended to provide further explanations for the claimed invention. Hereinafter, in order to enable those skilled in the art to have a further understanding and recognition of the structural features and achieved effects of the present invention, preferred embodiment figures and detailed descriptions will be provided as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 FIG. is a circuit architecture diagram of a deserialization circuit of the prior art, in which an eye-opening detection circuit is applied.

[0024] Figure 2 FIG. discloses the prior art Figure 1 The waveform diagrams of each clock signal in FIG. include: CLK_0, CLK_90, CLK_180, CLK_270, and CLK_EOM@0.

[0025] Figure 3 FIG. is a circuit schematic diagram of an active eye-opening detection and correction device disclosed in an embodiment of the present invention.

[0026] Figure 4 FIG. is a schematic diagram of the step flow of an active eye-opening detection and correction method disclosed in an embodiment of the present invention.

[0027] Figure 5 FIG. is a schematic diagram of sampling a reference clock signal with an eye-opening detection clock signal when a correction selection signal is at a low voltage level in an embodiment of the present invention.

[0028] Figure 6 FIG. is a schematic diagram of sampling an eye-opening detection clock signal with a reference clock signal when a correction selection signal is at a high voltage level in another embodiment of the present invention.

[0029] Figure 7A FIG. is a state diagram of an active eye-opening detection and correction device disclosed in an embodiment of the present invention executing a correction program to extract a first phase.

[0030] Figure 7B FIG. is a state diagram of an active eye-opening detection and correction device disclosed in an embodiment of the present invention executing a correction program to extract a second phase and calculate a final phase.

[0031] Figure 8According to the present invention Figure 7A and Figure 7B A schematic diagram showing exemplary correction selection signals, indication signals, and phase control signals.

[0032]

Symbol Explanation

[0033] 10: Continuous-time linear equalizer

[0034] 20: D-type flip-flop

[0035] 22: D-type flip-flop

[0036] 24: D-type flip-flop

[0037] 26: D-type flip-flop

[0038] 30: Demultiplexer

[0039] 40: Eye opening detection circuit

[0040] 221: Phase delay

[0041] 223: Variable

[0042] 900: Deserialization circuit

[0043] 1000: Active eye opening detection and correction device

[0044] 302: Phase control circuit

[0045] 304: Phase indication determination circuit

[0046] 306: Phase correction circuit

[0047] 313: Data selection circuit

[0048] 315: Temporary storage circuit

[0049] S402, S404, S406: Steps

[0050] S71, S73, S75, S77, S79, S81, S83, S85, S87, S89: States

[0051] S91, S93, S95, S97, S99, S101, S103, S105, S107, S109: States

[0052] MUX1, MUX2: Multiplexers

[0053] DFF: D-type flip-flop

[0054] CLK_0: Reference clock signal

[0055] CLK_EOM: Eye opening detection clock signal

[0056] EOM_CAL_SEL: Calibration selection signal

[0057] EOM_CAL_OUT: Indication signal

[0058] PI_CTRL: Phase control signal

[0059] Phase offset signal Detailed implementation manners

[0060] Embodiments of the present invention will be further explained below in conjunction with the relevant drawings. As much as possible, in the drawings and the specification, the same reference numerals represent the same or similar components. In the drawings, for the sake of simplicity and convenience of marking, the shapes and thicknesses may be exaggerated. It can be understood that the components not specifically shown in the drawings or described in the specification are in the forms known to those skilled in the art. Those skilled in the art can make various changes and modifications according to the content of the present invention.

[0061] Unless otherwise specified, some conditional clauses or words, such as "can", "could", "might", or "may", usually attempt to express that the embodiments of the present application have features, elements, or steps that, however, can also be interpreted as possibly not required. In other embodiments, these features, elements, or steps may not be required.

[0062] The description of "an embodiment" or "one embodiment" hereinafter refers to a specific element, structure, or feature associated with at least one embodiment. Therefore, the multiple descriptions of "an embodiment" or "one embodiment" that appear many times hereinafter are not directed to the same embodiment. Furthermore, the specific components, structures, and features in one or more embodiments can be combined in a suitable manner.

[0063] In the specification and the claims, certain terms are used to refer to specific elements. However, those skilled in the art should understand that the same element may be referred to by different names. The specification and the claims do not use the difference in names as a way to distinguish elements, but use the difference in the functions of the elements as the basis for distinction. The term "comprising" mentioned in the specification and the claims is an open-ended term and should be interpreted as "comprising but not limited to". In addition, "coupled" herein includes any direct and indirect connection means. Therefore, if it is described in the text that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection, wireless transmission, optical transmission, or other signal connection means, or can be indirectly electrically or signal-connected to the second element through other elements or connection means.

[0064] The present disclosure is particularly described by the following examples, which are for illustrative purposes only. For those skilled in the art, various modifications and refinements can be made without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the scope defined in the appended claims. Throughout the specification and claims, unless the context clearly dictates otherwise, the meanings of "a" and "the" include such recitations as "one or at least one" of the element or component. In addition, as used in the present disclosure, unless it is clearly visible from a specific context that multiple elements are excluded, the singular article also includes recitations of multiple elements or components. Moreover, when applied in the description herein and in all the following claims, unless the context clearly dictates otherwise, the meaning of "therein" can include "therein" and "thereon". The terms used throughout the specification and claims, unless otherwise noted, generally have their ordinary meanings in the art, in the context of the present disclosure, and in the specific context. Certain terms used to describe the present disclosure will be discussed below or elsewhere in this specification to provide additional guidance to practitioners in the description of the present disclosure. The use of examples anywhere in the specification, including the use of examples of any of the terms discussed herein, is for illustrative purposes only and does not limit the scope and meaning of the present disclosure or any of the exemplified terms. Similarly, the present disclosure is not limited to the various embodiments presented in this specification.

[0065] In the following paragraphs, the present invention will provide an active eye-opening detection and correction device and an active eye-opening detection and correction method. According to the correction device and its correction method disclosed by the present invention, the problem of phase mismatch between clock signals in the prior art can be eliminated, and at the same time, the invention effect of synchronizing the eye-opening detection clock signal with its reference clock signal can be achieved. The correction device and its correction method disclosed by the present invention are illustratively described by taking an application to a deserialization circuit as an example. However, the correction device and correction method provided in the following description of the present invention can also be applied to other similar circuit architectures. The present invention is not limited by the following embodiments.

[0066] First, please refer to Figure 3 shown, which is a schematic diagram of an active eye-opening detection and correction device according to an embodiment of the present invention. As shown in the figure, the active eye-opening detection and correction device 1000 can be applied to a deserialization circuit 900, so that its eye-opening detection clock signal CLK_EOM can have the same phase as the reference clock signal CLK_0 / 90 / 180 / 270 in real-time synchronization. Figure 4 For the Figure 3 schematic diagram of the flow steps of the active eye-opening detection and correction method according to the embodiment architecture of the present invention. To fully understand the technical solution disclosed by the present invention, the following technical description of the present invention is also referred toFigures 3 to 4 as shown

[0067] The active eye opening detection and correction device 1000 is applied to the deserialization circuit 900. And the active eye opening detection and correction device 1000 includes: a phase control circuit 302, a phase indication determination circuit 304, and a phase correction circuit 306. According to an embodiment of the present invention, the phase control circuit 302 is adapted to receive an eye opening detection clock signal CLK_EOM and a reference clock signal related to the eye opening detection clock signal CLK_EOM. Hereinafter, the present invention takes the reference clock signal having a 0-degree phase as an illustrative example for description, and in the following paragraphs, the reference clock signal is represented by "CLK_0". However, it is worth noting that the present invention is not limited to the reference clock signal CLK_0 having a 0-degree phase. In other specific embodiments of the present invention, the reference clock signal may alternatively be a clock signal having an initial sampling clock phase of 90 degrees, 180 degrees, or 270 degrees. Generally speaking, those skilled in the art can appropriately modify or vary without departing from the spirit of the present invention. That is to say, the present invention is not limited by certain limited configurations and / or circuit layouts disclosed in the embodiments of the present invention, so that these modified or varied embodiments should still fall within the scope of the present invention, and the scope of the present invention covers these modified or varied examples.

[0068] The present invention provides a correction selection signal EOM_CAL_SEL, so that the phase control circuit 302 receives the correction selection signal EOM_CAL_SEL and determines and controls whether to sample the eye opening detection clock signal CLK_EOM with the reference clock signal (CLK_0 in this embodiment) according to the correction selection signal EOM_CAL_SEL. That is to say, according to the technical solution taught by the present invention, the reference clock signal CLK_0 and the eye opening detection clock signal CLK_EOM can alternately sample each other. Under the control of the correction selection signal EOM_CAL_SEL, it is determined whether to sample the eye opening detection clock signal CLK_EOM with the reference clock signal CLK_0, or to sample the reference clock signal CLK_0 with the eye opening detection clock signal CLK_EOM. Please refer to Figure 4Step S402 shown therein discloses a technical solution of providing a calibration selection signal EOM_CAL_SEL to control sampling the eye opening detection clock signal CLK_EOM with the reference clock signal CLK_0 or sampling the reference clock signal CLK_0 with the eye opening detection clock signal CLK_EOM. Thereafter, the phase control circuit 302 can generate and output an indication signal EOM_CAL_OUT, and use this indication signal EOM_CAL_OUT as a flag signal of its result. This indication signal EOM_CAL_OUT is then transmitted to the phase indication decision circuit 304 and received by the phase indication decision circuit 304.

[0069] The phase indication decision circuit 304 is electrically coupled to the aforementioned phase control circuit 302 and receives the indication signal EOM_CAL_OUT, as Figure 4 shown in step S404 therein. Therefore, the phase indication decision circuit 304 can execute a calibration program according to the received indication signal EOM_CAL_OUT, so as to calculate and output a phase offset signal

[0070] Subsequently, the phase correction circuit 306 electrically coupled to the phase indication decision circuit 304 receives this phase offset signal and corrects the eye opening detection clock signal CLK_EOM according to this phase offset signal Therefore, as Figure 4 shown in step S406 therein, when the eye opening detection clock signal CLK_EOM is corrected according to this phase offset signal after correction, the present invention can successfully control so that the corrected eye opening detection clock signal CLK_EOM can be synchronously in phase (in-phase) with its reference clock signal CLK_0.

[0071] Specifically, please refer to Figure 3The component 302 shown in [figure reference] is, according to an exemplary embodiment of the present invention, the phase control circuit 302 disclosed by the present invention may be composed of a data selection circuit 313 and a latch circuit 315, for example. The data selection circuit 313 may include first and second multiplexers MUX1 and MUX2, for example, and these multiplexers MUX1 and MUX2 are triggered and enabled by a calibration selection signal EOM_CAL_SEL. The latch circuit 315 is electrically coupled to the first and second multiplexers MUX1 and MUX2. In this embodiment, a D flip-flop (DFF) is used as the circuit configuration of the latch circuit 315. By adopting such a circuit layout, when the data selection circuit 313 receives a reference clock signal CLK_0 and an eye-opening detection clock signal CLK_EOM and is triggered and enabled by the calibration selection signal EOM_CAL_SEL, the data input terminal and the clock input terminal of the D flip-flop can be selectively switched between the reference clock signal CLK_0 and the eye-opening detection clock signal CLK_EOM under the control of the calibration selection signal EOM_CAL_SEL, that is, the eye-opening detection clock signal CLK_EOM can be sampled by the reference clock signal CLK_0 optionally, or the reference clock signal CLK_0 can be sampled by the eye-opening detection clock signal CLK_EOM. After that, an indication signal EOM_CAL_OUT is generated and output by the D flip-flop, and the indication signal EOM_CAL_OUT is transmitted to the phase indication determination circuit 304 and received by the phase indication determination circuit 304.

[0072] Please refer to Figure 5 and Figure 6 shown, which discloses how the present invention controls the alternating sampling between the eye-opening detection clock signal CLK_EOM and the reference clock signal CLK_0 through the calibration selection signal EOM_CAL_SEL. First, please refer to Figure 5 shown. When the calibration selection signal EOM_CAL_SEL is at a low voltage level (EOM_CAL_SEL = 0), in this case, the data input terminal of the D flip-flop receives the reference clock signal CLK_0, and the clock input terminal of the D flip-flop receives the eye-opening detection clock signal CLK_EOM, so that the eye-opening detection clock signal CLK_EOM samples the reference clock signal CLK_0. After that, when the indication signal EOM_CAL_OUT transitions from a low voltage level to a high voltage level and stably maintains at the high voltage level (EOM_CAL_OUT transitions from logic 0 to logic 1 and stably maintains at logic 1), at this time, the eye-opening detection clock signal CLK_EOM lags behind the reference clock signal CLK_0 by a setup time T of the D flip-flop. In this case, the present invention records a first phase SETUP behind the reference clock signal CLK_0. In this case, the present invention records a first phase

[0073] After that, the present invention resets the correction selection signal EOM_CAL_SEL to a high voltage level, as Figure 6 shown. At this time, when the correction selection signal EOM_CAL_SEL is at a high voltage level (EOM_CAL_SEL = 1), in this case, the data input terminal of the D flip-flop turns to receive the eye opening detection clock signal CLK_EOM, and the clock input terminal of the D flip-flop receives the reference clock signal CLK_0, so that the reference clock signal CLK_0 samples the eye opening detection clock signal CLK_EOM. After that, when the indication signal EOM_CAL_OUT transitions from a low voltage level to a high voltage level and stably maintains at this high voltage level (EOM_CAL_OUT transitions from logic 0 to logic 1 and stably maintains at logic 1), at this time, the eye opening detection clock signal CLK_EOM is ahead of the reference clock signal CLK_0 by the set time T of this D flip-flop. In this case, the present invention records a second phase SETUP ahead of the reference clock signal CLK_0. In this case, the present invention records a second phase

[0074] Therefore, after successfully obtaining the above-mentioned first phase and the second phase After that, the present invention can calculate the average value of the first phase and the second phase and use the average value of the first phase and the second phase as a final phase as shown in the following formula (1), and output the calculated final phase as the phase offset signal

[0075]

[0076] In view of this, as shown in step S406 of the accompanying drawings of the present invention Figure 4 After receiving the phase offset signal the phase correction circuit 306 can correct the eye opening detection clock signal CLK_EOM according to the average value of the first phase and the second phase so that the corrected eye opening detection clock signal can be in phase with the reference clock signal CLK_0 synchronously.

[0077] Furthermore, please refer to Figure 7A and Figure 7B shown, which discloses the state machine diagram of the correction program executed by the active eye opening detection correction device of the present invention. Figure 8 Based on Figure 7A andFigure 7B An illustrative example of a state diagram. First, as shown in state S71, the present invention is first enabled via the instruction "EOM_CAL_EN". Then, in state S73, the calibration selection signal EOM_CAL_SEL is set to a low voltage level (logic 0) to sample the reference clock signal CLK_0 by the eye opening detection clock signal CLK_EOM. At this time, the phase control signal PI_CTRL starts from 0, as shown in state S75: PI_CTRL = 0, and then sequentially increments from 0. Subsequently, in state S77, the present invention checks the indication signal EOM_CAL_OUT, and then in state S79, it determines whether the indication signal EOM_CAL_OUT is at a low voltage level (logic 0).

[0078] According to an embodiment of the present invention, if the indication signal EOM_CAL_OUT is logic 0, the phase control signal PI_CTRL sequentially increments, as shown in state S81: PI_CTRL++. Please refer to it together with Figure 8 As shown, when EOM_CAL_SEL = 0 and the indication signal EOM_CAL_OUT is also logic 0, the phase control signal PI_CTRL sequentially increments from 0, such as: 0, 1, 2... 20, so as to advance the phase of the eye opening detection clock signal CLK_EOM forward.

[0079] Otherwise, if the indication signal EOM_CAL_OUT is not logic 0, then state S83 is executed, the indication signal EOM_CAL_OUT is checked again, and in state S85, it is determined whether the indication signal EOM_CAL_OUT is at a high voltage level (logic 1). If the indication signal EOM_CAL_OUT is logic 1, then in state S87, the first phase is recorded According to an embodiment of the present invention, the phase control signal PI_CTRL corresponding to the time point when the indication signal EOM_CAL_OUT changes from logic 0 to logic 1 and remains stable at logic 1 will be recorded as the first phase Otherwise, the present invention executes state S89 to continuously increase the phase control signal PI_CTRL (PI_CTRL++) until it is checked in state S85 that the indication signal EOM_CAL_OUT changes from logic 0 to logic 1 and remains stable at logic 1, so as to record the first phase Please refer to it together with Figure 8 As shown, it can be seen that when the indication signal EOM_CAL_OUT changes from logic 0 to logic 1 and remains stable at logic 1, PI_CTRL = 21, that is to say, the present invention can successfully record the first phase at state S87

[0080] After completing the recording of the first phase After that, please refer to Figure 7B the state diagram. As shown in state S91, the present invention resets the indication signal EOM_CAL_OUT to a low voltage level (logic 0), and at the same time switches the calibration selection signal EOM_CAL_SEL to a high voltage level (logic 1), so that "EOM_CAL_OUT = 0, EOM_CAL_SEL = 1". At this time, the reference clock signal CLK_0 is used to sample the eye opening detection clock signal CLK_EOM. Please also refer to Figure 8 As shown, during the period when the phase control signal PI_CTRL maintains the indication signal EOM_CAL_OUT at the low voltage level, it starts from the aforementioned first phase and starts to decrease sequentially (21, 20, 19, 18...). As shown in state S93: "PI_CTRL--", so that the phase of the eye opening detection clock signal CLK_EOM moves backward. After that, the indication signal EOM_CAL_OUT is checked in state S95, and then it is judged in state S97 whether the indication signal EOM_CAL_OUT is at a high voltage level (logic 1).

[0081] According to an embodiment of the present invention, if the indication signal EOM_CAL_OUT is not at a high voltage level (not logic 1), then state S99 is executed, and the phase control signal PI_CTRL continues to decrease.

[0082] On the contrary, if the indication signal EOM_CAL_OUT is at a high voltage level (logic 1), then state S101 is executed. The present invention checks the indication signal EOM_CAL_OUT again, and then judges in state S103 whether the indication signal EOM_CAL_OUT is stably maintained at the high voltage level (steady-state logic 1). If so, the second phase is recorded in state S105 According to an embodiment of the present invention, the phase control signal PI_CTRL corresponding to the time point when the indication signal EOM_CAL_OUT changes from the logic 0 state to the logic 1 state and maintains the stable logic 1 will be recorded as the second phase Please also refer to Figure 8 As shown, it can be seen that when the indication signal EOM_CAL_OUT changes from the logic 0 state to the logic 1 state and maintains the stable logic 1, PI_CTRL = 15. That is to say, the present invention can successfully record the second phase at state S105 Otherwise, the present invention executes state S107 to continuously decrease the phase control signal PI_CTRL (PI_CTRL--) until the indication signal EOM_CAL_OUT is checked in state S101 and the indication signal EOM_CAL_OUT is checked to change from logic 0 to logic 1 and remain stable at logic 1 in state S103, so that the second phase can be recorded at state S105.

[0083] In view of the above process, after successfully recording the first phase and the second phase the present invention can then calculate the average value of the first phase and the second phase and use the average value of the first phase and the second phase as a final phase As shown in state S109, output the calculated final phase as Figure 3 the phase offset signal shown in

[0084] S109:

[0085] For example, in the embodiment shown in Figure 8 then And this is the phase control signal PI_CTRL that can make the eye opening detection clock signal CLK_EOM have a phase precisely synchronized with the reference clock signal CLK_0. In view of this, the present invention can then correct the eye opening detection clock signal CLK_EOM based on such a phase offset signal so that the corrected eye opening detection clock signal CLK_EOM can be in phase with its reference clock signal synchronously. By adopting the technical solution disclosed by the present invention, the phase of the corrected eye opening detection clock signal can be precisely consistent with the phase of its reference clock signal. It is obvious that the active eye opening detection correction device and its correction method disclosed by the present invention can effectively achieve the clock phase synchronization effect.

[0086] Furthermore, according to the technical solution disclosed by the present invention, before enabling the EOM detection circuit each time, the calibration process disclosed in Figure 7A and Figure 7B can be first executed to effectively avoid the problem of phase mismatch caused by power supply and temperature changes in the system. The active eye opening detection correction device and its active correction method disclosed by the present invention are beneficial to clock phase synchronization. At the same time, based on the present invention, only a simple circuit such as a data selection circuit and a D-type flip-flop needs to be configured, so the circuit complexity can also be effectively controlled to be relatively low.

[0087] In summary, it is obvious that the active eye-opening detection and correction device and the active eye-opening detection and correction method disclosed in the present invention can be applied to the deserialization circuit as shown above. However, the present invention is not limited thereto. Other compatible, optional, and implementable circuit configurations are also preferably feasible. Therefore, the scope of the claims of the present invention naturally also covers similar circuit configurations.

[0088] Generally speaking, for those skilled in the art, they can make equivalent modifications or changes based on the present invention without departing from the technical core of the present invention, according to different circuit specifications and / or norms. That is to say, the scope of protection claimed by the present invention is not limited to the above. Moreover, various modifications or variations and / or implementation manners of the circuit based on the present invention should still fall within the scope of the claims of the present invention.

[0089] It can be seen from the above-mentioned various embodiments that the present invention provides an effective active eye-opening detection and correction device and its correction method. By adopting the technical solution disclosed in the present invention, the optimization effect of the phase synchronization between the eye-opening detection clock signal and its reference sampling clock signal can be achieved. Compared with the prior art, it can obviously and effectively solve many deficiencies existing in the prior art, and present a more efficient optimization invention effect, and can be widely used in related industries, and successfully overcome many long-existing defects of the prior art. Therefore, it is obvious that the technical solution claimed by the applicant in this case indeed has excellent industrial applicability and competitiveness. At the same time, the technical features, method means, and achieved effects disclosed in the present invention are significantly different from the current solutions, and are not easily completed by those skilled in the art, and should have patent requirements.

[0090] The above-described embodiments are only for illustrating the technical idea and features of the present invention, and the purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. It cannot be used to limit the patent scope of the present invention. That is, all equivalent changes or modifications made according to the spirit disclosed in the present invention should still be covered by the scope of protection claimed by the claims of the present invention.

Claims

1. An active eye-opening detection and correction device, comprising: A phase control circuit that receives a reference clock signal and an eye-opening detection clock signal. A correction selection signal is provided to the phase control circuit to control whether to sample the eye-opening detection clock signal with the reference clock signal. The phase control circuit outputs an indication signal. A phase indication determination circuit electrically coupled to the phase control circuit and receiving the indication signal. The phase indication determination circuit performs a correction procedure based on the indication signal to output a phase offset signal. A phase correction circuit electrically coupled to the phase indication determination circuit and receiving the phase offset signal. The phase correction circuit corrects the eye-opening detection clock signal based on the phase offset signal so that the corrected eye-opening detection clock signal is in phase with the reference clock signal synchronously.

2. The active eye-opening detection and correction device according to claim 1, wherein, The phase control circuit includes: A data selection circuit that receives the reference clock signal and the eye-opening detection clock signal. The correction selection signal is used to trigger the data selection circuit. A register circuit electrically coupled to the data selection circuit. The data input terminal and the clock input terminal of the register circuit can be selectively switched between the reference clock signal and the eye-opening detection clock signal under the control of the correction selection signal. The register circuit outputs the indication signal.

3. The active eye detection and correction device according to claim 2, wherein The data selection circuit includes at least one multiplexer triggered and enabled by the correction selection signal.

4. The active eye opening detection and correction device according to claim 2, wherein, The register circuit is a D flip-flop (DFF).

5. The active eye opening detection and correction device according to claim 2, wherein, When the correction selection signal is at a low voltage level, the data input terminal of the register circuit receives the reference clock signal, and the clock input terminal of the register circuit receives the eye-opening detection clock signal, so that the eye-opening detection clock signal samples the reference clock signal.

6. The active eye-opening detection and correction device according to claim 2, wherein, When the correction selection signal is at a high voltage level, the data input terminal of the register circuit receives the eye-opening detection clock signal, and the clock input terminal of the register circuit receives the reference clock signal, so that the reference clock signal samples the eye-opening detection clock signal.

7. The active eye opening detection and correction device according to claim 1, wherein, When the eye-opening detection clock signal samples the reference clock signal and the indication signal remains at a low voltage level, the phase control signal increases sequentially. When the indication signal changes state and stably maintains at a high voltage level, the first phase corresponding to the phase control signal is recorded.

8. The active eye opening detection and correction device as described in claim 7, after which the indication signal is reset to the low voltage level, and the correction selection signal is switched to sample the eye opening detection clock signal by the reference clock signal, wherein When the indication signal remains at the low voltage level, the phase control signal decreases sequentially. When the indication signal changes state and stably maintains at the high voltage level, the second phase corresponding to the phase control signal is recorded.

9. The active eye opening detection and correction device according to claim 8, wherein, The average value of the first phase and the second phase is calculated as the final phase, and the final phase is output as the phase offset signal.

10. The active eye-opening detection and correction device according to claim 4, wherein, When the correction selection signal is at a low voltage level and the indication signal changes state from a low voltage level and stably maintains at a high voltage level, the eye-opening detection clock signal lags behind the reference clock signal by the setup time of the D flip-flop, thereby recording the first phase.

11. The active eye opening detection and correction device according to claim 10, wherein, When the calibration selection signal is at a high voltage level and the indication signal transitions from a low voltage level and is stably maintained at a high voltage level, the eye opening detection clock signal leads the reference clock signal by the setup time of the D flip-flop, thereby recording the second phase.

12. The active eye opening detection and correction device according to claim 11, wherein, The average value of the first phase and the second phase is calculated as the final phase, and the final phase is output as the phase offset signal, such that the phase correction circuit corrects the eye opening detection clock signal according to the average value of the first phase and the second phase, so that the corrected eye opening detection clock signal is in phase with the reference clock signal synchronously.

13. The active eye opening detection and correction device according to claim 1, wherein, The reference clock signal optionally has an initial sampling clock phase of 0 degrees, 90 degrees, 180 degrees, or 270 degrees.

14. An active eye opening detection correction method, comprising: Providing a calibration selection signal to control whether to sample the eye opening detection clock signal with a reference clock signal and output an indication signal; Performing a correction procedure according to the indication signal, thereby outputting a phase offset signal; And Correcting the eye opening detection clock signal according to the phase offset signal, such that the corrected eye opening detection clock signal is in phase with the reference clock signal synchronously.

15. The active eye opening detection and correction method according to claim 14, wherein, When the calibration selection signal is at a low voltage level, the eye opening detection clock signal samples the reference clock signal.

16. The active eye opening detection and correction method according to claim 14, wherein, When the calibration selection signal is at a high voltage level, the reference clock signal samples the eye opening detection clock signal.

17. The active eye opening detection and correction method according to claim 15, wherein, When the eye opening detection clock signal samples the reference clock signal and the indication signal is maintained at a low voltage level, the phase control signal increases sequentially, and when the indication signal transitions and is stably maintained at a high voltage level, the first phase corresponding to the phase control signal is recorded.

18. The active eye opening detection and correction method according to claim 17, after that, the indication signal is reset to the low voltage level, and the correction selection signal is switched to the high voltage level, and the eye opening detection clock signal is sampled by the reference clock signal instead, wherein, When the indication signal is maintained at the low voltage level, the phase control signal decreases sequentially, and when the indication signal transitions and is stably maintained at the high voltage level, the second phase corresponding to the phase control signal is recorded.

19. The active eye opening detection and correction method according to claim 18, wherein, The average value of the first phase and the second phase is calculated as the final phase, and the final phase is output as the phase offset signal.

20. The active eye opening detection and correction method according to claim 14, wherein, The reference clock signal optionally has an initial sampling clock phase of 0 degrees, 90 degrees, 180 degrees, or 270 degrees.

21. The active eye opening detection and correction method according to claim 14, wherein, The reference clock signal and the eye opening detection clock signal are received by a data selection circuit, and the calibration selection signal is used to trigger the data selection circuit.

22. The active eye opening detection and correction method according to claim 21, wherein, The data selection circuit is further electrically coupled to a register circuit. The data input terminal and the clock input terminal of the register circuit can be selectively switched between the reference clock signal and the eye opening detection clock signal under the control of the calibration selection signal, and the register circuit outputs the indication signal.

23. The active eye-opening detection and correction method according to claim 21, wherein, The data selection circuit includes at least one multiplexer triggered and enabled by the calibration selection signal.

24. The active eye opening detection and correction method according to claim 22, wherein, The register circuit is a D flip-flop (DFF).

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