Eight-phase output phase interpolator

Abstract

The invention discloses an eight-phase output phase interpolator, which belongs to the technical field of analog integrated circuit design and comprises a frequency divider, an input buffer, a CMOS-to-CML (Complementary Metal Oxide Semiconductor-to-Complementary Metal Oxide Semiconductor) circuit, a digital decoder, a first phase interpolation core, a second phase interpolation core, an amplitude limiter, a phase fusion device and a CML-to-CMOS circuit. According to the invention, a phase interpolation structure is adopted, and four-phase orthogonal CML signals are respectively interpolated by two phase interpolation cores of an odd path and an even path. The difference between the two paths of output signals is 45 degrees, and the phase deviation introduced in the linear interpolation structure has the characteristic of opposite directions between the two paths. Two paths of output signals are fused through the phase fusion device, nonlinear errors in a single-path structure are effectively counteracted, the linearity of overall interpolation output is improved, the INL of an interpolator is remarkably reduced, and the phase resolution and precision of a multi-phase clock system are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuit design, and particularly relates to an eight-phase output phase interpolator. Background Art

[0002] With the development of high-speed communication systems, higher requirements are put forward for clock generation and recovery modules with high precision, high speed, and low power consumption. In applications such as clock data recovery, multi-phase clock generation, and high-speed data sampling, as a key circuit module for realizing high-resolution phase control, the performance of the phase interpolator directly affects the time resolution, jitter characteristics, and power consumption index of the system. Traditional phase interpolators mostly adopt weighted current interpolation structures or voltage interpolation structures, and control signal paths through different logic control codes to achieve interpolation between adjacent multi-phase clocks.

[0003] However, traditional eight-phase output phase interpolators usually adopt the way of linear interpolation, with large integral nonlinearity (INL) and poor interpolation effect. For traditional eight-phase output phase interpolators to adapt to interpolation paths in different quadrants, interpolation units are often enabled as needed in a switchable form. This control method makes most interpolation units idle when working in non-current quadrants and not participate in effective interpolation, resulting in waste of chip area and current resources and reducing the utilization efficiency of the overall structure. Moreover, traditional eight-phase output phase interpolators usually achieve phase control in different quadrants through an external quadrant selector. This part of the circuit requires additional layout of a multi-way switch network and control logic, which not only significantly increases the structural complexity and clock path length of the system, but also easily introduces phase jitter and boundary switching errors, affecting the stability and interpolation accuracy of the system. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides an eight-phase output phase interpolator. The technical problems to be solved by the present invention are realized through the following technical solutions: The present invention provides an eight-phase output phase interpolator, including: a frequency divider, an input buffer, a CMOS-to-CML circuit, a digital decoder, a first phase interpolation core, a second phase interpolation core, a limiter, a phase fuser, and a CML-to-CMOS circuit; wherein, the frequency divider is used for dividing the dual-phase input signal and outputting a four-phase input signal; the input buffer is used for isolating the frequency divider and the CMOS-to-CML circuit, and shaping and matching the four-phase input signal output by the frequency divider, and outputting the matched four-phase input signal; The CMOS-to-CML circuit is used to convert the matched four-phase input signal into a four-phase orthogonal CML signal; The digital decoder is used to decode the externally input CODE code and output an odd-path logic control code and an even-path logic control code; The first phase interpolation core is used to perform phase interpolation on the four-phase orthogonal CML signal under the control of the odd-path logic control code and output an odd-path four-phase orthogonal interpolation signal; The second phase interpolation core is used to perform phase interpolation on the four-phase orthogonal CML signal under the control of the even-path logic control code and output an even-path four-phase orthogonal interpolation signal; The limiter is used to perform amplitude limiting processing on the odd-path four-phase orthogonal interpolation signal and the even-path four-phase orthogonal interpolation signal and output an eight-phase interpolation signal; The phase fuser is used to perform phase fusion on the eight-phase interpolation signal and output an eight-phase fusion signal; The CML-to-CMOS circuit is used to convert the eight-phase fusion signal into a clock signal of CMOS level and output it.

[0005] Advantages of the present invention: 1. The present invention adopts a phase interpolation structure. Two phase interpolation cores, an odd path and an even path, respectively perform interpolation on the four-phase orthogonal CML signal. The two output signals have a 45° difference, and the phase deviation introduced in the linear interpolation structure shows the characteristic of opposite directions between the two paths. By fusing the two output signals through a phase fuser, the non-linear error in the single-path structure is effectively cancelled, the linearity of the overall interpolation output is improved, the INL of the interpolator is significantly reduced, and the phase resolution and accuracy of the multi-phase clock system are improved; 2. Each interpolation unit proposed by the present invention selects different quadrant output paths according to the logic control code switch, realizing the internalization of the quadrant inversion function without the need to use an additional quadrant switching circuit, thereby reducing the structural complexity of the system and the clock path length and reducing the area; 3. Each interpolation unit proposed by the present invention is always in a working state. Compared with an eight-phase output phase interpolator composed of four phase interpolators, only half of the interpolation units are required, saving the layout area, making the circuit module more compact, improving the integrability of the interpolator in high-speed chips, and being applicable to large-scale integrated communication systems and SoC platforms; 4. The input load of the phase interpolation core proposed by the present invention is the same under any externally input CODE code, and the input signal does not change with the change of the number of interpolation units, ensuring the stability of the working state. Description of the drawings

[0006] Figure 1Schematic diagram of the principle of an eight-phase output phase interpolator provided by an embodiment of the present invention; Figure 2 Schematic diagram of the structure of the phase interpolation core in an eight-phase output phase interpolator provided by an embodiment of the present invention; Figure 3 Schematic diagram of the structure of the interpolation unit in the phase interpolation core provided by an embodiment of the present invention; Figure 4 Output schematic diagram of the first phase interpolation core and the second phase interpolation core provided by an embodiment of the present invention; Figure 5 Schematic diagram of the principle of the first fusion situation during phase fusion provided by an embodiment of the present invention; Figure 6 Schematic diagram of the principle of the second fusion situation during phase fusion provided by an embodiment of the present invention; Figure 7 Simulation diagram of the output signal INL of the phase interpolation core and the output signal INL of the phase fuser provided by an embodiment of the present invention; Figure 8 Simulation result diagram of the eight-phase clock signal finally output by an eight-phase output phase interpolator provided by an embodiment of the present invention. Detailed implementation manners

[0007] The following further describes the present invention in detail with reference to specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0008] An embodiment of the present invention provides an eight-phase output phase interpolator, as Figure 1 shown, which may include: A frequency divider, an input buffer, a CMOS-to-CML circuit, a digital decoder, a first phase interpolation core, a second phase interpolation core, a limiter, a phase fuser, and a CML-to-CMOS circuit; wherein, The frequency divider is used to divide the dual-phase input signal and output a four-phase input signal; The input buffer is used to isolate the frequency divider and the CMOS-to-CML circuit, and shape and match the four-phase input signal output by the frequency divider, and output the matched four-phase input signal; The CMOS-to-CML circuit is used to convert the matched four-phase input signal into a four-phase quadrature CML signal; The digital decoder is used to decode the externally input CODE code and output an odd-channel logic control code and an even-channel logic control code; The first phase interpolation core is used to perform phase interpolation on the four-phase quadrature CML signal under the control of the odd-channel logic control code and output an odd-channel four-phase quadrature interpolation signal; A second-phase interpolation core, which is used to perform phase interpolation on a four-phase quadrature CML signal under the control of an even-path logic control code, and output an even-path four-phase quadrature interpolation signal; A limiter, which is used to perform amplitude limiting processing on an odd-path four-phase quadrature interpolation signal and an even-path four-phase quadrature interpolation signal, and output an eight-phase interpolation signal; A phase fuser, which is used to perform phase fusion on the eight-phase interpolation signal, and output an eight-phase fusion signal; A CML-to-CMOS circuit, which is used to convert the eight-phase fusion signal into a clock signal with CMOS level and output it.

[0009] The eight-phase output phase interpolator proposed in the embodiment of the present invention adopts a phase interpolation structure. Two phase interpolation cores, namely an odd path and an even path, respectively perform interpolation on the four-phase quadrature CML signal. The two output signals have a 45° difference. The phase deviation introduced in the linear interpolation structure shows the characteristic of opposite directions between the two paths. By fusing the two output signals through a phase fuser, the non-linear error in the single-path structure is effectively cancelled, the linearity of the overall interpolation output is improved, the INL of the interpolator is significantly reduced, and the phase resolution and accuracy of the multi-phase clock system are improved.

[0010] For ease of understanding, each module of the eight-phase output phase interpolator proposed in the embodiment of the present invention will be introduced separately below.

[0011] A frequency divider divides the dual-phase input signal, and outputs a four-phase input signal.

[0012] The frequency divider divides the high-frequency dual-phase input signals: CLK P 、CLK N to the four-phase input signals: CLK IP 、CLK IN 、CLK QP 、CLK QN .

[0013] An input buffer isolates the frequency divider and the CMOS-to-CML circuit, shapes and matches the four-phase input signal output by the frequency divider, and enhances the driving ability for the subsequent CMOS-to-CML circuit.

[0014] The CMOS-to-CML circuit converts the clock signal with CMOS level into a current-mode logic (CML) differential signal, and outputs four-phase quadrature CML signals: CLK I,P 、CLK I,N 、CLK Q,P and CLK Q,N , to meet the input requirements of the phase interpolator.

[0015] The digital decoder decodes the N - Bit CODE code input externally, generates the odd - path logic control code and the even - path logic control code, and controls the first - phase interpolation core and the second - phase interpolation core respectively.

[0016] The difference between the odd - path logic control code and the even - path logic control code is 2 N-3 , so that the phase difference between the output odd - path quadrature interpolation signal and the even - path quadrature interpolation signal is 45°; where N represents the number of bits of the CODE code.

[0017] The structures of the first - phase interpolation core and the second - phase interpolation core are the same. As Figure 2 shown, both include: the first resistor R NODD , the second resistor R PODD , the third resistor R NEVEN , the fourth resistor R PEVEN , the first interpolation array and the second interpolation array; where The first end of the first resistor R NODD is connected to the power supply voltage, and the second end is connected to the first output end of the first interpolation array, and the second end serves as the first output end of the corresponding phase interpolation core; The first end of the second resistor R PODD is connected to the power supply voltage, and the second end is connected to the second output end of the first interpolation array, and the second end serves as the second output end of the corresponding phase interpolation core; The first end of the third resistor R NEVEN is connected to the power supply voltage, and the second end is connected to the third output end of the second interpolation array, and the second end serves as the third output end of the corresponding phase interpolation core; The first end of the fourth resistor R PEVEN is connected to the power supply voltage, and the second end is connected to the fourth output end of the second interpolation array, and the second end serves as the fourth output end of the corresponding phase interpolation core; The differential input end of the first interpolation array serves as the first signal input end of the corresponding phase interpolation core, the control end serves as the first control - code input end of the corresponding phase interpolation core, the bias end is connected to the bias voltage VB, the first output end is connected to the first output end of the second interpolation array, the second output end is connected to the second output end of the second interpolation array, the third output end is connected to the third output end of the second interpolation array, and the fourth output end is connected to the fourth output end of the second interpolation array; The differential input end of the second interpolation array serves as the second signal input end of the corresponding phase interpolation core, the control end serves as the second control - code input end of the corresponding phase interpolation core, and the bias end is connected to the bias voltage VB.

[0018] The first interpolation array and the second interpolation array have the same structure, and both include a number of parallel interpolation units.

[0019] Both the first interpolation array and the second interpolation array include 2 N-2 parallel interpolation units; where N represents the number of bits of the externally input CODE code.

[0020] Specifically, the 2 N-2 interpolation units in the first interpolation array form the I path, and the 2 N-2 interpolation units in the second interpolation array form the Q path. It can be seen from Figure 2 that the input signals of the first phase interpolation core and the second phase interpolation core are four-phase orthogonal CML signals: CLK I,P 、CLK I,N 、CLK Q,P and CLK Q,N , the logical control signals received by the control ends of the 2 N-2 interpolation units in the I path are LOGIC I , and the logical control signals received by the control ends of the 2 N-2 interpolation units in the Q path are LOGIC Q , thereby controlling the number of interpolation units connected to the first resistor R NODD , the second resistor R PODD , the third resistor R NEVEN and the fourth resistor R PEVEN to achieve current weighted interpolation; a bias voltage VB is connected to the bias terminal to control the current flowing through the MOS transistor corresponding to the bias terminal, and the output four-phase orthogonal interpolation signals are respectively: VOP ODD , VON ODD , VOP EVEN , VON EVEN . It can be understood that for the first phase interpolation core, LOGIC I is the weighting coefficient of the odd path logic control code acting on the I path, and LOGIC Q is the weighting coefficient of the odd path logic control code acting on the Q path; for the second phase interpolation core, LOGIC I is the weighting coefficient of the even path logic control code acting on the I path, and LOGIC Q is the weighting coefficient of the even path logic control code acting on the Q path.

[0021] The interpolation unit, as Figure 3 shown, may include: MOS transistor MN1, MOS transistor MN2, MOS transistor MN3, first single-pole four-throw switch S1 and second single-pole four-throw switch S2; where the gate terminals of MOS transistor MN1 and MOS transistor MN2 serve as the differential input terminals of the corresponding interpolation array; The source terminal of MOS transistor MN1 is connected to the source terminal of MOS transistor MN2, and the drain terminal is connected to the input terminal of the first single-pole four-throw switch S1; The drain terminal of MOS transistor MN2 is connected to the input terminal of the second single-pole four-throw switch S2; The source terminal of MOS transistor MN3 is grounded, the gate terminal serves as the bias terminal of the corresponding interpolation array, and the drain terminal is connected to the source terminal of MOS transistor MN1; The control terminal of the first single-pole four-throw switch S1 serves as the control terminal of the corresponding interpolation array, and the output terminals are respectively connected to the first output terminal ODD_IN, the second output terminal ODD_IP, the third output terminal EVEN_IN, and the fourth output terminal EVEN_IP of the corresponding interpolation array; The control terminal of the second single-pole four-throw switch S2 is connected to the control terminal of the first single-pole four-throw switch S1, and the output terminals are respectively connected to the first output terminal ODD_IN, the second output terminal ODD_IP, the third output terminal EVEN_IN, and the fourth output terminal EVEN_IP of the corresponding interpolation array.

[0022] It can be understood that for the convenience of representation, the logic signal LOGIC input to the control terminal of the first single-pole four-throw switch S1 represents that the logic control signal is LOGIC I or the logic control signal is LOGIC Q , CLK P and CLK N represent differential input signals. For the interpolation units in the first interpolation array, LOGIC refers to the logic control signal being LOGIC I , CLK P refers to CLK I,P , CLK N refers to CLK I,N , for the interpolation units in the second interpolation array, LOGIC refers to the logic control signal being LOGIC Q , CLK P refers to CLK Q,P , CLK N refers to CLK Q,N , which means that the control terminal of the interpolation array is used to receive a binary logic control code to control the connection mode of the interpolation units, so that the current output is connected to different resistance paths, thereby completing interpolation.

[0023] The differential input terminals of the interpolation array are connected to four-phase quadrature CML signals: CLK I,P , CLK I,N , CLK Q,P and CLK Q,N .

[0024] The interpolation unit can achieve inversion in different quadrants under the control of the logic control code. When the output terminal of the first single-pole four-throw switch S1 of an interpolation unit on the I path selects to connect to the first resistor R NODD and the output terminal of the second single-pole four-throw switch S2 selects to connect to the second resistor R PODD this interpolation unit provides a positive I-path unit current for the first resistor R NODD and the second resistor R PODD and has no effect on the third resistor R NEVEN and the fourth resistor R PEVEN When the output terminal of the first single-pole four-throw switch S1 of an interpolation unit on the I path selects to connect to the second resistor R PODD and the output terminal of the second single-pole four-throw switch S2 selects to connect to the first resistor R NODD this interpolation unit provides a reverse I-path unit current for the first resistor R NODD and the second resistor R PODD and has no effect on the third resistor R NEVEN and the fourth resistor R PEVEN When the output terminal of the first single-pole four-throw switch S1 of an interpolation unit on the I path selects to connect to the third resistor R NEVEN and the output terminal of the second single-pole four-throw switch S2 selects to connect to the fourth resistor R PEVEN this interpolation unit provides a positive I-path unit current for the third resistor R NEVEN and the fourth resistor R PEVEN and has no effect on the first resistor R NODD and the second resistor R PODD When the output terminal of the first single-pole four-throw switch S1 of an interpolation unit on the I path selects to connect to the fourth resistor R PEVEN and the output terminal of the second single-pole four-throw switch S2 selects to connect to the third resistor R NEVEN this interpolation unit provides a reverse I-path unit current for the third resistor R NEVEN and the fourth resistor R PEVEN and has no effect on the first resistor R NODD and the second resistor R PODD ; When the output terminal of the first single-pole four-throw switch S1 of an interpolation unit on the Q path selects to connect to the first resistor R NODD and the output terminal of the second single-pole four-throw switch S2 selects to connect to the second resistor R PODD this interpolation unit provides a positive Q-path unit current for the first resistor R NODD and the second resistor R PODD and has no effect on the third resistor R NEVEN and the fourth resistor R PEVENFunction; When the output terminal of the first single-pole four-throw switch S1 of an interpolation unit in the Q path selectively connects to the second resistor R PODD and the output terminal of the second single-pole four-throw switch S2 selectively connects to the first resistor R NODD this interpolation unit provides a reverse Q-path unit current for the first resistor R NODD and the second resistor R PODD and has no effect on the third resistor R NEVEN and the fourth resistor R PEVEN Function; When the output terminal of the first single-pole four-throw switch S1 of an interpolation unit in the Q path selectively connects to the third resistor R NEVEN and the output terminal of the second single-pole four-throw switch S2 selectively connects to the fourth resistor R PEVEN this interpolation unit provides a forward Q-path unit current for the third resistor R NEVEN and the fourth resistor R PEVEN and has no effect on the first resistor R NODD and the second resistor R PODD Function; When the output terminal of the first single-pole four-throw switch S1 of an interpolation unit in the Q path selectively connects to the fourth resistor R PEVEN and the output terminal of the second single-pole four-throw switch S2 selectively connects to the third resistor R NEVEN this interpolation unit provides a reverse Q-path unit current for the third resistor R NEVEN and the fourth resistor R PEVEN and has no effect on the first resistor R NODD and the second resistor R PODD Function; Among them, the Q-path unit current is the current output by an interpolation unit in the Q path, and the I-path unit current is the current output by an interpolation unit in the I path.

[0025] The first single-pole four-throw switch S1 and the second single-pole four-throw switch S2 have the same structure, both of which are composed of four parallel transistors. The opening of the transistors is controlled by controlling the gate voltage of the transistors, thereby realizing the function of the single-pole four-throw switch.

[0026] Schematic diagram of the outputs of the first phase interpolation core and the second phase interpolation core, as Figure 4 shown, VOP ODD (first phase interpolation core), VOP EVEN (first phase interpolation core), VON ODD (first phase interpolation core) and VON EVEN (first phase interpolation core) represent the four-phase orthogonal interpolation signals output by the first phase interpolation core, VOP ODD (second phase interpolation core), VOP EVEN (second phase interpolation core), VON ODD (second phase interpolation core) and VONEVEN (The second - phase interpolation core) represents the four - phase orthogonal interpolation signal output by the second - phase interpolation core. As can be seen from Figure 4 , in VOP ODD and VON ODD are differential signals with opposite phases. VOP EVEN and VON EVEN are differential signals with opposite phases. Therefore, in Figure 4 only the coordinates of one of the signals in the differential signal are given. 2 N-2 parallel interpolation units constitute the I - path, and 2 N-2 parallel interpolation units constitute the Q - path. If at this time, for the Q - path, the output terminals of S1 of 2 N-2 - 15 interpolation units are selected to connect to R NODD , and the output terminals of S2 are selected to connect to R PODD , then these interpolation units provide 2 NODD and the second resistor R PODD with 2 N-2 - 15 positive Q - path unit currents. When the output terminals of S1 of 15 interpolation units in the I - path are selected to connect to R NODD , and the output terminals of S2 are selected to connect to R PODD , then these interpolation units provide 15 positive I - path unit currents for the first resistor R NODD and the second resistor R PODD ; meanwhile, when the output terminals of S1 of the remaining 15 units in the Q - path are selected to connect to R PEVEN , and the output terminals of S2 are selected to connect to R NEVEN , these interpolation units provide 15 negative Q - path unit currents for the third resistor R NEVEN and the fourth resistor R PEVEN . When the output terminals of S1 of the remaining 2 N-2 - 15 units in the I - path are selected to connect to R NEVEN , and the output terminals of S2 are selected to connect to R PEVEN , these interpolation units provide 15 positive I - path unit currents for the third resistor R NEVEN and the fourth resistor R PEVEN . So as shown in Figure 4 , the 2 NODD and the second resistor R PODD with 2 N-2 - 15 positive Q - path unit currents and 15 positive I - path unit currents are superimposed, and after passing through the pull - up resistor, they are converted into differential signals VOP ODD and VON ODD ; the third resistor R NEVEN and the fourth resistor R PEVEN with 15 negative Q - path unit currents and 2 N-2- Superposition of 15 positive I-channel unit currents, which is converted into differential signals VOP EVEN and VON EVEN . It can be obtained from Figure 4 that the phase difference between the phase differential signal VOP and the differential signal VON is 90°, so the phase interpolation core can output four-phase orthogonal interpolation signals of 0°, 90°, 180°, and 270°; among them, the Q-channel unit current is the current output by an interpolation unit in the Q channel, and the I-channel unit current is the current output by an interpolation unit in the I channel.

[0027] It can be understood that the odd-channel logic control codes and even-channel logic control codes input to the first phase interpolation core and the second phase interpolation core are different. The 2 N-2 control codes input to the I channel of the second phase interpolation core and the 2 N-2 control codes input to the I channel of the first phase interpolation core have a phase difference of 2 N-3 ; the 2 N-2 control codes input to the Q channel of the second phase interpolation core and the control codes input to the Q channel of the first phase interpolation core differ by 2 N-3 , so that the first phase interpolation core can output four-phase orthogonal interpolation signals of 0°, 90°, 180°, and 270°, and the second phase interpolation core can output four-phase orthogonal interpolation signals of 45°, 135°, 225°, and 315°.

[0028] The output signal of the eight-phase output phase interpolator proposed by the present invention can be expressed as: ; where and represent the weighting coefficients respectively acting on the I channel or the Q channel, represents the angular frequency, represents the amplitude of the output signal, represents the phase of the output signal.

[0029] In order to make the output signal have a constant swing, the ideal control code should change in a trigonometric function with the decimal digital code corresponding to the externally input N-Bit CODE code : ; ; where N represents the number of bits of the CODE code.

[0030] The linear control method proposed by the embodiment of the present invention for the digital decoder is: The first quadrant: ; The fourth quadrant: ; The third quadrant: ; The fourth quadrant: 。

[0031] Each interpolation unit proposed in the embodiment of the present invention selects different quadrant output paths through switches according to the logic control signal, realizing the internalization of the quadrant inversion function without using an additional quadrant switching circuit, thereby reducing the structural complexity and clock path length of the system and reducing the area; each interpolation unit is always in a working state. Compared with an eight-phase phase interpolator composed of four phase interpolators, only half of the interpolation units are required, saving the layout area, making the circuit module more compact, improving the integrability of the interpolator in high-speed chips, and being applicable to large-scale integrated communication systems and SoC platforms; the input load of each bit interpolation core is the same under any externally input CODE code, and the input signal does not change with the change in the number of interpolation units, ensuring the stability of the working state.

[0032] The limiter performs a limiting process on the odd-path quadrature interpolation signal and the even-path quadrature interpolation signal, and outputs an eight-phase interpolation signal, including: The limiter converts the odd-path quadrature interpolation signal and the even-path quadrature interpolation signal into square-wave signals with the same swing; The square-wave signals with the same swing are converted into CML signals with the same swing through a filter, and the CML signals with the same swing are output as the eight-phase interpolation signal.

[0033] The limiter may include a CMOS-to-CML circuit and a filter circuit. The phase interpolation core is a linear interpolation. The quadrature interpolation signals output by the linear interpolation structure have different swings under different CODE codes. The limiter first converts the input odd-path quadrature interpolation signal and even-path quadrature interpolation signal into square-wave signals with the same swing through the CMOS-to-CML circuit, and then converts the square-wave signals with the same swing into CML signals with the same swing through the filter circuit and outputs them as the eight-phase interpolation signal, providing input signals with consistent swing and slope for the subsequent phase combiner.

[0034] The phase combiner performs phase combination on the eight-phase interpolation signal and outputs an eight-phase combined signal. The schematic diagram of the principle of phase combination provided in the embodiment of the present invention is as Figure 5 and Figure 6 shown. The phase combiner performs phase combination on two CML signals with a phase difference of 45°. Assume the two CML signals are as follows: ; ; For the two CML signals and are superimposed to obtain the superimposed signal : ; wherein, represents the amplitude of the signal , represents the angular frequency, represents the time, represents the signal 's phase, represents the signal 's amplitude, represents the signal 's phase.

[0035] Derivation using trigonometric identities gives: ; wherein, , represents the amplitude of the superimposed signal ; , represents the phase of the superimposed signal .

[0036] Now given specific conditions: The first fusion case: If the CML signals and have the same frequency, the same swing, and , the superimposed is: ; ; It can be obtained from the formula that the phase of the superimposed is in the middle and the amplitude is amplified, as shown in Figure 5 .

[0037] The second fusion case: If the CML signals and have the same frequency, , , and , the superimposed is: ; ; It can be obtained from the formula that the phase of the superimposed is closer to the term with the larger amplitude, and the amplitude is amplified, as shown in Figure 6 .

[0038] As can be seen from the above, the inconsistent amplitudes (swing amplitudes) of the two signals will cause the phase after fusion to deviate from the expected position, thus leading to clock errors. To ensure the accuracy of phase fusion, it is necessary to ensure that the amplitudes of the signals participating in the fusion are strictly the same. Therefore, the limiter is extremely necessary. The limiter performs amplitude limiting processing on the input odd-channel quadrature interpolation signal and even-channel quadrature interpolation signal. The core of phase interpolation is linear interpolation. The quadrature interpolation signals output by the linear interpolation structure have different swing amplitudes under different CODE codes. The limiter first converts the input odd-channel quadrature interpolation signal and even-channel quadrature interpolation signal into square wave signals with the same swing amplitude through a CML-to-CMOS circuit, and then converts the square wave signals with the same swing amplitude into CML signals with the same swing amplitude through a filter, and outputs an eight-phase interpolation signal, providing input signals with the same swing and slope for the subsequent phase fuser. The eight-phase clock signals finally output by the eight-phase output phase interpolator are: CKOUT_0, CKOUT_45, CKOUT_90, CKOUT_135, CKOUT_180, CKOUT_225, CKOUT_270, and CKOUT_315.

[0039] The simulation diagrams of the output signal INL of the phase interpolation core provided by the embodiment of the present invention and the output signal INL of the phase fuser are as Figure 7 shown, Figure 7 where the abscissa represents the decimal digital code PI CODE corresponding to the externally input N-Bit CODE code, and the ordinate represents the integral nonlinearity. Taking the 7Bit phase interpolator in the figure as an example, the dashed curve represents the INL output of the first phase interpolation core; the dotted-dashed curve represents the INL output of the second phase interpolation core; the solid curve represents the final output INL of the phase fuser. The INL output by a single-path phase interpolation core (the first phase interpolation core or the second phase interpolation core) has obvious periodic fluctuations, and large-amplitude nonlinear offsets occur in some sections, indicating that the interpolation accuracy of the traditional linear structure is poor at some phase points; after the phase fuser fuses the interpolation results of the two phase interpolation core, the finally output INL curve is significantly smoother, the overall nonlinear error is significantly reduced, the maximum INL is reduced, showing better linearity; this fusion mechanism effectively suppresses the periodic error accumulation effect of a single path and realizes the output of eight-phase signals with higher accuracy and better consistency.

[0040] The simulation result diagram of the eight-phase clock signals finally output by an eight-phase output phase interpolator provided by the embodiment of the present invention is as Figure 8 shown, Figure 8The abscissa represents the working time of the eight-phase output phase interpolator in nanoseconds (ns), and the ordinate represents the output signal of the eight-phase output phase interpolator in millivolts (mV). Under the condition of CODE = 0, the phase interpolator outputs eight groups of equally spaced clocks with a phase difference of 45° in sequence. The phases of the clock signals are 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°. The periods of all output signals are the same, showing good period stability. There is a fixed phase offset between adjacent clocks, and the time delay corresponds to approximately 1 / 8 of the clock period, indicating that the final interpolation effect is good and the eight-phase clock output is achieved.

[0041] An embodiment of the present invention provides an eight-phase output phase interpolator, which adopts a dual-path phase interpolation structure. Two phase interpolation cores, namely the odd path and the even path, respectively interpolate the four-phase orthogonal CML signals. The two output signals have a phase difference of 45°. The phase deviation introduced in the linear interpolation structure shows the characteristic of opposite directions between the two paths. By fusing the two output signals through a phase combiner, the non-linear error in the single-path structure is effectively cancelled, the linearity of the overall interpolation output is improved, the INL of the interpolator is significantly reduced, and the phase resolution and accuracy of the multi-phase clock system are improved; each interpolation unit selects different quadrant output paths according to the logic control code switch, realizing the internalization of the quadrant inversion function without using an additional quadrant switching circuit, thus reducing the circuit complexity and the area; each interpolation unit is always in the working state. Compared with the eight-phase phase interpolator composed of four phase interpolators, only half of the interpolation units are required, saving the layout area, making the circuit module more compact, improving the integratability of the interpolator in high-speed chips, and being applicable to large-scale integrated communication systems and SoC platforms; the input load of the phase interpolation core is the same under any externally input CODE code, and the input signal does not change with the change of the number of interpolation units, ensuring the stability of the working state.

[0042] It should be noted that in the description of the present invention, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0043] The above are only the preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. An eight-phase output phase interpolator, characterized in that Including: A frequency divider, an input buffer, a CMOS-to-CML circuit, a digital decoder, a first phase interpolation core, a second phase interpolation core, a limiter, a phase fuser, and a CML-to-CMOS circuit; wherein, The frequency divider is used to divide the two-phase input signal and output a four-phase input signal; The input buffer is used to isolate the frequency divider and the CMOS-to-CML circuit, and shape and match the four-phase input signal output by the frequency divider, and output the matched four-phase input signal; The CMOS-to-CML circuit is used to convert the matched four-phase input signal into a four-phase quadrature CML signal; The digital decoder is used to decode the externally input CODE code and output an odd-channel logic control code and an even-channel logic control code; The first phase interpolation core is used to perform phase interpolation on the four-phase quadrature CML signal under the control of the odd-channel logic control code and output an odd-channel four-phase quadrature interpolation signal; The second phase interpolation core is used to perform phase interpolation on the four-phase quadrature CML signal under the control of the even-channel logic control code and output an even-channel four-phase quadrature interpolation signal; The limiter is used to perform limiting processing on the odd-channel four-phase quadrature interpolation signal and the even-channel four-phase quadrature interpolation signal and output an eight-phase interpolation signal; The phase fuser is used to perform phase fusion on the eight-phase interpolation signal and output an eight-phase fusion signal; The CML-to-CMOS circuit is used to convert the eight-phase fusion signal into a clock signal of CMOS level and output it.

2. The octal-phase output phase interpolator according to claim 1, wherein The odd path logic control code and the even path logic control code differ by 2 N-3 ; where N represents the number of bits of the externally input CODE code.

3. The eight-phase output phase interpolator according to claim 1, wherein The first phase interpolation core and the second phase interpolation core have the same structure, both including: a first resistor R NODD , a second resistor R PODD , a third resistor R NEVEN , a fourth resistor R PEVEN , a first interpolation array and a second interpolation array; where The first resistor R NODD has its first end connected to the power supply voltage and its second end connected to the first output end of the first interpolation array, and the second end serves as the first output end of the corresponding phase interpolation core; The second resistor R PODD has its first end connected to the power supply voltage, and its second end is connected to the second output end of the first interpolation array, and the second end serves as the second output end of the corresponding phase interpolation core; The third resistor R NEVEN has its first end connected to the power supply voltage and its second end connected to the third output end of the second interpolation array, and the second end serves as the third output end of the corresponding phase interpolation core; The fourth resistor R PEVEN has its first end connected to the power supply voltage and its second end connected to the fourth output end of the second interpolation array, and the second end serves as the fourth output end of the corresponding phase interpolation core; The differential input end of the first interpolation array serves as the first signal input end of the corresponding phase interpolation core, the control end serves as the first control code input end of the corresponding phase interpolation core, the bias end is connected to the bias voltage VB, the first output end is connected to the first output end of the second interpolation array, the second output end is connected to the second output end of the second interpolation array, the third output end is connected to the third output end of the second interpolation array, and the fourth output end is connected to the fourth output end of the second interpolation array; The differential input end of the second interpolation array serves as the second signal input end of the corresponding phase interpolation core, the control end serves as the second control code input end of the corresponding phase interpolation core, and the bias end is connected to the bias voltage VB.

4. An eight-phase output phase interpolator according to claim 3, characterized in that, The first interpolation array and the second interpolation array have the same structure and both include a plurality of parallel interpolation units.

5. An eight-phase output phase interpolator according to claim 4, wherein Both the first interpolation array and the second interpolation array include 2 N-2 parallel interpolation units; where N represents the number of bits of the externally input CODE code.

6. An eight-phase output phase interpolator according to claim 4, wherein Each of the interpolation units includes: MOS transistor MN1, MOS transistor MN2, MOS transistor MN3, a first single-pole four-throw switch S1, and a second single-pole four-throw switch S2; wherein, The gate terminals of the MOS transistor MN1 and the MOS transistor MN2 serve as the differential input ends of the corresponding interpolation array; The source terminal of the MOS transistor MN1 is connected to the source terminal of the MOS transistor MN2, and the drain terminal is connected to the input terminal of the first single-pole four-throw switch S1; The drain terminal of the MOS transistor MN2 is connected to the input terminal of the second single-pole four-throw switch S2; The source terminal of the MOS transistor MN3 is grounded, the gate terminal serves as the bias end of the corresponding interpolation array, and the drain terminal is connected to the source terminal of the MOS transistor MN1; The control terminal of the first single-pole four-throw switch S1 serves as the control terminal of the corresponding interpolation array, and the output terminals are respectively connected to the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal of the corresponding interpolation array; The control terminal of the second single-pole four-throw switch S2 is connected to the control terminal of the first single-pole four-throw switch S1, and the output terminals are respectively connected to the first output terminal, the second output terminal, the third output terminal, and the fourth output terminal of the corresponding interpolation array.

7. An eight-phase output phase interpolator according to claim 6, characterized in that, The first single-pole four-throw switch S1 and the second single-pole four-throw switch S2 have the same structure and are both composed of four transistors connected in parallel.

8. An eight-phase output phase interpolator according to claim 1, wherein The limiter performs limiting processing on the odd-channel quadrature interpolation signal and the even-channel quadrature interpolation signal, and outputs an eight-phase interpolation signal, including: The limiter converts the odd-channel quadrature interpolation signal and the even-channel quadrature interpolation signal into square-wave signals with the same swing; The square-wave signals with the same swing are converted into CML signals with the same swing through a filter, and the CML signals with the same swing are output as the eight-phase interpolation signal.

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