High-speed multi-rate reconfigurable clock data recovery chip for optical communication

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a radio frequency front-end system chip applied to a 5G millimeter wave and satellite communication phased array. The circuit structure of the phased array transceiver system comprises a radio frequency switch, a phase shifter, a power amplifier and a low noise amplifier, the circuit provided by the invention comprises a transmitting path and a receiving path; when the radio frequency switch opens a transmitting path, the radio frequency front-end system chip plays a role in phase shift amplification of a transmitting signal, an initial signal is input to the phase shifter through the radio frequency switch at the head part of the circuit, and the phase shifter adjusts the signal to a required phase and then inputs the signal to the power amplifier. The power amplifier amplifies the signal to required power and then transmits the signal through the radio frequency switch at the tail of the circuit; when the radio frequency switch opens a receiving path, the radio frequency front-end system chip plays a role in phase shift amplification of a received signal, and low-noise and high-gain amplification of the signal is realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and particularly relates to a Clock and Data Recovery (CDR) circuit. Background Art

[0002] The clock data recovery circuit is one of the key core modules in high-speed communication interfaces. Its function is to accurately extract the clock from the received signal and recover the data to ensure the normal communication of the system. In high-speed communication interfaces, with the continuous increase of data transmission rates, signal integrity faces greater challenges, including problems such as noise, jitter, and crosstalk. This poses higher requirements for the performance of the CDR circuit. The stability and accuracy of the CDR circuit directly determine the transmission quality of the communication interface, so it is of indispensable importance in high-speed transmission scenarios.

[0003] Existing clock data recovery circuits mainly rely on technologies such as Phase Lock Loop (PLL) or Delay Lock Loop (DLL). These circuits are usually designed for a single rate, difficult to adapt to the transmission requirements of multi-rate signals, and their performance is limited at high data rates with low transmission rates. This fixed-parameter design results in deficiencies in flexibility and compatibility. Especially in communication interfaces with multi-standards and high-speed transmission, it is difficult to meet the complex and changing system requirements.

[0004] The present invention proposes an improved clock data recovery circuit. By optimizing the circuit structure and module design, it not only significantly improves the signal transmission rate but also supports the adaptive recovery of multi-rate signals. This circuit has high flexibility and high robustness, can meet the diverse needs of high-speed communication interfaces, and provides a better solution for modern communication systems. Summary of the Invention

[0005] The object of the present invention is to propose a high-speed multi-rate data recovery circuit.

[0006] The high-speed multi-rate clock data recovery circuit proposed by the present invention has a circuit structure including: an input data signal and a signal fed back from a voltage-controlled oscillator and a first frequency divider are input to a phase detector and a current-mode charge pump. The phase detector and the current-mode charge pump sample the input data and output an error pulse signal to a loop filter. The loop filter converts the received current signal into a voltage signal and outputs it to the voltage-controlled oscillator. The voltage-controlled oscillator adjusts the frequency of the output signal according to the input voltage signal, outputs it to the first frequency divider and the second frequency divider, and is fed back to the frequency discriminator and the lock detector through the second frequency divider. An input reference clock signal is input to the frequency discriminator and the lock detector. The frequency discriminator compares the input clock signal and the signal fed back from the second frequency divider and outputs an error signal to the charge pump. The charge pump generates a corresponding current signal to a switch, which is connected to the loop filter through the switch. The control signal of the switch is generated by the output of the lock detector.

[0007] In the present invention, the frequency discriminator, the charge pump, the loop filter, the voltage-controlled oscillator and the second frequency divider form a frequency-locked loop; the phase detector and the current-mode charge pump, the loop filter, the voltage-controlled oscillator and the first frequency divider form a phase-locked loop.

[0008] In the present invention, the phase detector adopts a Bang-Bang phase detector based on a current-mode flip-flop, which contains four current-mode flip-flops. The clock signal samples the input data signal through the current-mode flip-flop. The input data signal is simultaneously connected to the input terminals of the first and third flip-flops, while the clock signal is simultaneously input to the clock terminals of all flip-flops. Among them, the third flip-flop samples the clock signal at the falling edge, and the remaining flip-flops sample the clock signal at the rising edge. The output signal of the first flip-flop is connected to the input terminal of the second flip-flop module, and the second flip-flop outputs a second signal. The output signal of the third flip-flop is connected to the input terminal of the fourth flip-flop, and the fourth flip-flop outputs a fourth signal.

[0009] In the present invention, the current-mode flip-flop contains eight load resistors and fourteen NMOS transistors. Among them, the load separation technology is adopted for the resistors, thereby improving the working speed of the circuit and realizing the input of a higher data rate.

[0010] In the present invention, the current-mode charge pump contains two current-mode exclusive-OR gates, four PMOS transistors MCP1, MCP2, MCP3, MCP4 and two NMOS transistors MCN1, MCN2. The output current of the exclusive-OR gate is directly connected to the current mirror of the charge pump, and the subtraction operation of the output currents of the two exclusive-OR gates is realized in the charge pump, and the current corresponding to the phase difference is injected into the loop filter.

[0011] The clock data recovery circuit designed by the present invention can accept signals with high data rates because it adopts a Bang-Bang phase detector composed of current-mode flip-flops. Since it uses a charge pump based on a current-mode exclusive-OR gate, the bandwidth of the charge pump is increased, thus speeding up the response speed of the loop. Since it uses a dual-phase detection channel composed of a Bang-Bang phase detector based on current-mode flip-flops and a current-mode charge pump, multi-rate support for the input signal is achieved. Brief Description of the Drawings

[0012] Figure 1 It is a schematic structural diagram of the high-speed multi-rate clock data recovery circuit of the present invention.

[0013] Figure 2 It is a schematic structural diagram of the phase detector and the current-mode charge pump.

[0014] Figure 3 It is a schematic structural diagram of the Bang-Bang phase detector.

[0015] Figure 4 It is a schematic circuit diagram of the flip-flop based on the current-mode structure.

[0016] Figure 5 It is a schematic circuit diagram of the current-mode charge pump.

[0017] Figure 6 It is a schematic circuit diagram of the current-mode exclusive-OR gate. Detailed Description of the Preferred Embodiment

[0018] The present invention will be described in more detail below with reference to the accompanying drawings. In the various drawings, like elements are denoted by like reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the figures.

[0019] Many specific details of the present invention are described below, such as the structure, materials, dimensions, processing techniques and technologies of the devices, in order to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention can be implemented without these specific details.

[0020] Figure 1 It shows a schematic structural diagram of the high-speed multi-rate clock data recovery circuit of the present invention.

[0021] As Figure 1 shown, the high-speed multi-rate clock data recovery circuit 100 in the present invention includes: a phase detector and a current-mode charge pump 101, a loop filter 102, a voltage-controlled oscillator 103, a first frequency divider 104, a second frequency divider 105, a frequency discriminator / phase detector 106, a charge pump 107, a lock detector 108, and a switch 109. The input data signal D INand the signal CLK fed back from the voltage-controlled oscillator 103 H and the low-frequency clock signal CLK fed back from the frequency divider 104 L As the inputs of the phase detector and the current-mode charge pump 101, the output signal I of the phase detector and the current-mode charge pump 101 ER2 is coupled to the input of the loop filter 102 and outputs the restored high-rate data D OUTH and the clock CLK OUTH as well as the low-rate data D OUTL and the clock CLK OUTL . The output signal of the loop filter is coupled to the input of the voltage-controlled oscillator 103, and the output signal CLK of the voltage-controlled oscillator 103 H is coupled to the inputs of the phase detector and the current-mode charge pump 101, the frequency divider 104 and the frequency divider 105. The output of the frequency divider 104 is coupled to the input of the phase detector and the current-mode charge pump 101. The output signal F of the frequency divider 105 DIV is coupled to the inputs of the frequency discriminator and phase detector 106 and the lock detector 108, and the reference clock signal F REF is connected to the frequency discriminator and phase detector 106 and the lock detector 108. The output signal V of the frequency discriminator and phase detector ER1 is coupled to the input of the charge pump 107. The output of the charge pump 107 is coupled to the input of the switch 109. The output LD of the lock detector 108 is connected to the control terminal of the switch 109 as a control signal, and the output terminal of the switch 109 is connected to the input of the loop filter 102.

[0022] Figure 2 Shows the structural schematic diagram of the phase detector and the current-mode charge pump of the present invention.

[0023] As Figure 2 shown, the phase detector and the current-mode charge pump 101 in the present invention include: two Bang-Bang phase detectors (BBPD) 201 and 203, and two current-mode charge pumps (CML_CP) 202 and 204. The low-frequency clock signal CLK L and the input data signal D IN are respectively input to the Bang-Bang phase detector 201, and the output signal S of the Bang-Bang phase detector 201 ER1 is connected to the input terminal of the current-mode charge pump 202. The high-frequency clock signal CLK H and the input data signal D IN are respectively input to the Bang-Bang phase detector 203, and the output signal S of the Bang-Bang phase detector 203 ER2 is connected to the input terminal of the current-mode charge pump 204. The output terminal of the current-mode charge pump 202 is connected to the error signal I through the low-level switch L SW ​ER2 is connected, and the output terminal of the current-mode charge pump 204 is connected to the high-level switch H SW and I ER2 is connected.

[0024] Figure 3 is a structural schematic diagram of a Bang-Bang phase detector.

[0025] As Figure 3 shown, the Bang-Bang phase detector 201 in the present invention includes four identical current-mode flip-flops (CML_DFF), namely 301, 302, 303, and 304. The input data signal D IN is simultaneously connected to the input terminals of the CML_DFF modules 301 and 303, and the clock signal CLK is simultaneously input to the clock terminals of all CML_DFF modules. Among them, the CML_DFF module 303 samples the falling edge of the clock signal CLK, and the CML_DFF modules 301, 302, and 304 sample the rising edge of the clock signal CLK. The output signal Q1 of the CML_DFF module 301 is connected to the input terminal of the CML_DFF module 302, and the CML_DFF module 302 outputs the signal Q2. The output signal Q3 of the CML_DFF module 303 is connected to the input terminal of the CML_DFF module 304, and the CML_DFF module 304 outputs the signal Q4.

[0026] Figure 4 is a circuit schematic diagram of the flip-flop CML_DFF based on a current-mode structure.

[0027] As Figure 4As shown in the figure, the flip-flop (CML_DFF) based on the current-mode structure in the present invention includes: eight load resistors R1, R2, R3, R4, R5, R6, R7, R8 and fourteen NMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14. The source of transistor M7 is connected to the ground GND, the gate is connected to the input bias voltage VB, and the drain is connected to the sources of transistors M5 and M6. The gate of transistor M5 is connected to the negative input clock signal CLKN, the drain of transistor M5 is connected to the sources of transistors M1 and M2, the gate of transistor M6 is connected to the positive input clock signal CLKP, and the drain of transistor M6 is connected to the sources of transistors M3 and M4. The input signal DP is connected to the gate of transistor M1, and the input signal DN is connected to the gate of transistor M2. The drain of transistor M1 is connected to the lower port of resistor R3 and the gate of transistor M3, and the drain of transistor M2 is connected to the lower port of resistor R4 and the gate of transistor M4. The upper port of resistor R3 is connected to the lower port of resistor R1 and the drain of transistor M3, the upper port of resistor R4 is connected to the lower port of resistor R2 and the drain of transistor M4, and the upper ports of resistors R1 and R2 are connected to the power supply VDD. The source of transistor M14 is connected to the ground GND, the gate is connected to the input bias voltage VB, and the drain is connected to the sources of transistors M12 and M13. The gate of transistor M12 is connected to the positive input clock signal CLKP, the drain of transistor M13 is connected to the sources of transistors M8 and M9, the gate of transistor M13 is connected to the negative input clock signal CLKN, and the drain of transistor M13 is connected to the sources of transistors M10 and M11. The gate of transistor M8 is connected to the drain of transistor M4, and the gate of transistor M9 is connected to the drain of transistor M3. The drain of transistor M8 is connected to the lower port of resistor R7 and the gate of transistor M10, and the drain of transistor M9 is connected to the lower port of resistor R8 and the gate of transistor M11. The upper port of resistor R7 is connected to the lower port of resistor R5 and the drain of transistor M10, and is output as the output signal QN, the upper port of resistor R8 is connected to the lower port of resistor R6 and the drain of transistor M11, and is output as the output signal QP, and the upper ports of resistors R1 and R2 are connected to the power supply VDD.

[0028] Figure 5 Schematic diagram of the circuit of the current-mode charge pump.

[0029] As Figure 5As shown in the figure, the current-mode charge pump 102 in the present invention includes: two current-mode exclusive-OR gates (CML XOR) 401 and 402, four PMOS transistors MCP1, MCP2, MCP3, MCP4, and two NMOS transistors MCN1, MCN2. Among them, the input signals Q1 and Q4 are connected to the inputs of the current-mode exclusive-OR gate 401. The output of the current-mode exclusive-OR gate 401 is connected to the drain of the transistor (PMOS transistor) MCP1 and is connected to the gates of the transistors (PMOS transistors) MCP1 and MCP2. The input signals Q4 and Q2 are connected to the inputs of the current-mode exclusive-OR gate 402. The output of the current-mode exclusive-OR gate 402 is connected to the drain of the transistor (PMOS transistor) MCP4 and is connected to the gates of the transistors (PMOS transistors) MCP3 and MCP4. The sources of the transistors (PMOS transistors) MCP1, MCP2, MCP3, MCP4 are connected to the power supply VDD. The drain of the transistor (PMOS transistor) MCP2 is connected to the drain of the transistor (NMOS transistor) MCN1 and is connected to the gates of the transistors (NMOS transistors) MCN1 and MCN2. The drain of the transistor (PMOS transistor) MCP3 is connected to the drain of the transistor (NMOS transistor) MCN2 and is output as the output signal CPOUT. The sources of the transistors (NMOS transistors) MCN1 and MCN2 are connected to the ground GND.

[0030] Figure 6 It is a circuit schematic diagram based on a current-mode exclusive-OR gate.

[0031] As Figure 6 shown in the figure, the current-mode exclusive-OR gate 401 in the present invention includes: two load resistors RL1 and RL2, eight NMOS transistors MD1, MD2, MD3, MD4, MV1, MV2, MC1, MC2. The sources of the transistors MC1 and MC2 are connected to the ground GND, and the gates are connected to the input bias voltage VB. The transistors MD1 and MD2 are used as data transistors, the sources are connected to the drain of the transistor MC1, and the sources are connected to the lower port of the load resistor RL1. The transistors MD3 and MD4 are used as data transistors, the sources are connected to the drain of the transistor MC2, and the sources are connected to the lower port of the load resistor RL2. The transistor MV1 is used as an evaluation transistor, the source is connected to the drain of the transistor MC1, and the gate is connected to the lower port of the load resistor RL1. The transistor MV2 is used as an evaluation transistor, the source is connected to the drain of the transistor MC2, and the gate is connected to the lower port of the load resistor RL2. The drain of the transistor MV1 is connected to the drain of the transistor MV2 and is output as the output signal XOR of the current-mode exclusive-OR gate 401. The upper ports of the load resistors RL1 and RL2 are connected to the power supply VDD.

[0032] In this document, the terms "comprising", "including" or any other variation thereof are intended to cover non-exclusive inclusion, such that a series of elements (such as processes, methods, articles or devices) including those elements not only include those elements but also other elements not expressly listed. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements outside the elements so included.

[0033] In the present invention, the embodiments do not describe all the details in detail, nor limit the invention to the specific embodiments described. According to the above description, many changes can be made. These embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modifications. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A high-speed multi-rate clock data recovery circuit, characterized in that The circuit structure includes: an input data signal and a signal fed back from a voltage-controlled oscillator and a first frequency divider are input into a phase detector and a current-mode charge pump. The phase detector and the current-mode charge pump sample the input data and output an error pulse signal to a loop filter. The loop filter converts the received current signal into a voltage signal and outputs it to the voltage-controlled oscillator. The voltage-controlled oscillator adjusts the frequency of the output signal according to the input voltage signal, outputs it to the first frequency divider and the second frequency divider, and is fed back to the frequency discriminator / phase detector and the lock detector through the second frequency divider. An input reference clock signal is input into the frequency discriminator / phase detector and the lock detector. The frequency discriminator / phase detector compares the input clock signal and the signal fed back from the second frequency divider and outputs an error signal to the charge pump. The charge pump generates a corresponding current signal to a switch, which is connected to the loop filter through the switch. The control signal of the switch is generated by the output of the lock detector.

2. The high-speed multi-rate clock data recovery circuit according to claim 1, characterized in that: There are two loops in the circuit. The frequency discriminator / phase detector, the charge pump, the loop filter, the voltage-controlled oscillator, and the second frequency divider form a frequency-locked loop; the phase detector and the current-mode charge pump, the loop filter, the voltage-controlled oscillator, and the first frequency divider form a phase-locked loop.

3. The high-speed multi-rate clock data recovery circuit according to claim 2, characterized in that: There are two paths, a high-speed path and a low-speed path, in the phase-locked loop. Among them, the input data is simultaneously input into two Bang-Bang phase detectors. The high-speed clock and the low-speed clock are respectively connected to the two Bang-Bang phase detectors. The corresponding switch is selected according to the rate of the input data signal to achieve correct clock data recovery and output.

4. The high-speed multi-rate clock data recovery circuit according to claim 3, characterized in that: The Bang-Bang phase detector includes a total of four identical current-mode flip-flops, namely the first, second, third, and fourth. The input data signal is simultaneously connected to the input terminals of the first and third flip-flops, while the clock signal is simultaneously input into the clock terminals of all flip-flops. Among them, the third flip-flop samples the clock signal at the falling edge, and the remaining flip-flops sample the clock signal at the rising edge. The output signal of the first flip-flop is connected to the input terminal of the second flip-flop module, and the second flip-flop outputs a second signal. The output signal of the third flip-flop is connected to the input terminal of the fourth flip-flop, and the fourth flip-flop outputs a fourth signal.

5. The high-speed multi-rate clock data recovery circuit according to claim 4, characterized in that, A current-mode charge pump with fully symmetric input and high bandwidth. The current-mode charge pump includes two current-mode exclusive-OR gates, four PMOS transistors MCP1, MCP2, MCP3, MCP4, and two NMOS transistors MCN1, MCN2. Among them, the output current of the exclusive-OR gate is directly connected to the current mirror of the charge pump, and the subtraction operation of the output currents of the two exclusive-OR gates is realized in the charge pump, and the current corresponding to the phase difference is injected into the loop filter.

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