Signal processing circuit, signal processing method, chip and electronic equipment

Abstract

The invention discloses a signal processing circuit, a signal processing method, a chip and electronic equipment, and belongs to the technical field of integrated circuits. The signal processing circuit comprises a processing circuit and a frequency multiplier. The processing circuit is used for processing the original signal to obtain a first target signal, and the duty ratio of the first target signal and the reference duty ratio meet a first similarity condition; and the frequency multiplier is used for carrying out frequency multiplication operation on the first target signal to obtain a second target signal, and the duty ratio of the second target signal and the reference duty ratio meet a second similar condition. Based on this, not only can the purpose of making the duty ratio of the signal output by the frequency multiplier close to the reference duty ratio be achieved, but also the fluctuation of the signal output by the frequency multiplier can be reduced by making the duty ratio of the signal input into the frequency multiplier close to the reference duty ratio, thereby improving the stability of the signal output by the frequency multiplier.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of integrated circuit technologies, and particularly to a signal processing circuit, a signal processing method, a chip, and an electronic device. Background Art

[0002] A PLL (Phase Locked Loop) circuit generates an output signal with high precision and low jitter based on a reference clock signal. The frequency of the reference clock signal can significantly affect the anti-noise performance of the PLL circuit. To improve the anti-noise performance of the PLL circuit as much as possible, a frequency multiplier is usually used to perform a frequency multiplication operation on the reference clock signal on the original basis.

[0003] Currently, the stability of the signal output after the frequency multiplier performs the frequency multiplication operation still needs to be improved. Summary of the Invention

[0004] Embodiments of the present application provide a signal processing circuit, a signal processing method, a chip, and an electronic device, which can be used for the stability of the signal output by a frequency multiplier. The technical solutions are as follows:

[0005] On the one hand, embodiments of the present application provide a signal processing circuit, which includes a processing circuit and a frequency multiplier;

[0006] The processing circuit is configured to process an original signal to obtain a first target signal, and the duty cycle of the first target signal satisfies a first similarity condition with a reference duty cycle;

[0007] The frequency multiplier is configured to perform a frequency multiplication operation on the first target signal to obtain a second target signal, and the duty cycle of the second target signal satisfies a second similarity condition with the reference duty cycle.

[0008] In a possible implementation manner, the processing circuit includes a first determination sub-circuit, a first delay module, and a NOR gate;

[0009] The first determination sub-circuit is configured to use the inverted signal of the original signal as a first input signal when the duty cycle of the original signal is greater than the reference duty cycle; and use the original signal as the first input signal when the duty cycle of the original signal is not greater than the reference duty cycle;

[0010] The first delay module is configured to delay the phase of the first input signal according to a first degree to obtain a first output signal;

[0011] The NOR gate is configured to perform a NOR operation on the first input signal and the first output signal to obtain the first target signal;

[0012] Wherein, the first degree is used to make the duty cycle of the first target signal satisfy the first similarity condition with the reference duty cycle.

[0013] In a possible implementation, the signal processing circuit further includes a first counter and a first detection circuit;

[0014] The first counter is used to increase the count value based on the clock edge of the first reference signal in response to the first enable signal, so as to obtain a first count value, and the first reference signal is determined based on the original signal;

[0015] The first delay module is further used to delay the phase of the first input signal according to the degree corresponding to the first count value to obtain an intermediate signal;

[0016] The NOR gate is further used to perform a NOR operation on the first input signal and the intermediate signal to obtain a first processed signal;

[0017] The first detection circuit is used to output a first level signal when the phase difference between the first clock edge of the first processed signal and the second clock edge of the second processed signal is not greater than a first phase difference threshold, and the first level signal is used to indicate that the degree corresponding to the first count value is used as the first degree;

[0018] Wherein, the directions of the first clock edge and the second clock edge are opposite; the phase difference between the first clock edge and the second clock edge not being greater than the first phase difference threshold is used to indicate that the duty cycle of the first processed signal satisfies the first similarity condition with the reference duty cycle; the second processed signal is obtained by delaying the phase of the first processed signal by a second degree, and the difference between the second degree and 180 degrees is not greater than a first difference threshold.

[0019] In a possible implementation, the signal processing circuit further includes a first control circuit;

[0020] The first control circuit is used to reset the first count value to a first initial value and adjust the first phase difference threshold to a second phase difference threshold greater than the first phase difference threshold when the first count value reaches a first count threshold and the first detection circuit still does not output the first level signal.

[0021] In a possible implementation, the first control circuit includes a first logic sub-circuit, a second counter, and a second logic sub-circuit;

[0022] The first logic sub-circuit is used to output a second level signal when the first count value reaches the first count threshold and the first detection circuit still does not output the first level signal;

[0023] The second counter is configured to increase a count value based on the second level signal to obtain a second count value; the second phase difference threshold is the phase difference threshold corresponding to the second count value.

[0024] The second logic sub - circuit is configured to reset the first count value to the first initial value based on the second level signal.

[0025] In a possible implementation, the frequency multiplier includes a second delay module and an exclusive - OR gate.

[0026] The second delay module is configured to delay the phase of the first target signal according to a third degree, where the difference between the third degree and 90 degrees is not greater than a second difference threshold, to obtain a third target signal.

[0027] The exclusive - OR gate is configured to perform an exclusive - OR operation on the first target signal and the third target signal to obtain the second target signal.

[0028] In a possible implementation, the signal processing circuit further includes a third counter, a third delay module, a fourth delay module, a fifth delay module, and a second detection circuit.

[0029] The third counter is configured to, in response to a second enable signal, increase a count value based on the clock edge of a second reference signal to obtain a third count value, where the second reference signal is determined based on the original signal.

[0030] The second delay module is further configured to delay the phase of a second input signal according to the degree corresponding to the third count value to obtain a second output signal, where the second input signal is determined based on the original signal.

[0031] The third delay module is configured to delay the phase of the second output signal according to the degree corresponding to the third count value to obtain a third output signal.

[0032] The fourth delay module is configured to delay the phase of the third output signal according to the degree corresponding to the third count value to obtain a fourth output signal.

[0033] The fifth delay module is configured to delay the phase of the fourth output signal according to the degree corresponding to the third count value to obtain a fifth output signal.

[0034] The second detection circuit is configured to output a third level signal when the phase difference between the second input signal and the fifth output signal is not greater than a third phase difference threshold, and the third level signal is used to indicate that the degree corresponding to the third count value is used as the third degree.

[0035] In a possible implementation, the signal processing circuit further includes a second control circuit;

[0036] The second control circuit is configured to reset the third count value to a second initial value and adjust the third phase difference threshold to a fourth phase difference threshold greater than the third phase difference threshold when the third count value reaches a second count threshold and the second detection circuit still has not output the third level signal.

[0037] In a possible implementation, the second control circuit includes a third logic sub - circuit, a fourth counter, and a fourth logic sub - circuit;

[0038] The third logic sub - circuit is configured to output a fourth level signal when the third count value reaches the second count threshold and the second detection circuit still has not output the third level signal;

[0039] The fourth counter is configured to increase the count value based on the fourth level signal to obtain a fourth count value; the fourth phase difference threshold is the phase difference threshold corresponding to the fourth count value;

[0040] The fourth logic sub - circuit is configured to reset the third count value to the second initial value based on the fourth level signal.

[0041] On the other hand, an embodiment of the present application provides a signal processing method, and the method includes:

[0042] Processing an original signal to obtain a first target signal, where the duty cycle of the first target signal satisfies a first similarity condition with a reference duty cycle;

[0043] Performing a frequency doubling operation on the first target signal to obtain a second target signal, where the duty cycle of the second target signal satisfies a second similarity condition with the reference duty cycle.

[0044] In a possible implementation, processing the original signal to obtain a first target signal includes:

[0045] When the duty cycle of the original signal is greater than the reference duty cycle, using the inverted signal of the original signal as the first input signal; when the duty cycle of the original signal is not greater than the reference duty cycle, using the original signal as the first input signal;

[0046] Delaying the phase of the first input signal according to a first degree to obtain a first output signal;

[0047] Performing a NOR operation on the first input signal and the first output signal to obtain the first target signal;

[0048] Wherein, the first degree is used to make the duty cycle of the first target signal satisfy the first similarity condition with the reference duty cycle.

[0049] In a possible implementation manner, before delaying the phase of the first input signal according to the first degree to obtain a first output signal, it further includes:

[0050] In response to a first enable signal, increasing a count value based on a clock edge of a first reference signal to obtain a first count value, where the first reference signal is determined based on the original signal;

[0051] Delaying the phase of the first input signal according to the degree corresponding to the first count value to obtain an intermediate signal;

[0052] Performing a NOR operation on the first input signal and the intermediate signal to obtain a first processed signal;

[0053] When the phase difference between the first clock edge of the first processed signal and the second clock edge of the second processed signal is not greater than a first phase difference threshold, outputting a first level signal, where the first level signal is used to indicate using the degree corresponding to the first count value as the first degree;

[0054] Wherein, the directions of the first clock edge and the second clock edge are opposite; the phase difference between the first clock edge and the second clock edge not being greater than the first phase difference threshold is used to indicate that the duty cycle of the first processed signal satisfies the first similarity condition with the reference duty cycle; the second processed signal is obtained by delaying the phase of the first processed signal by a second degree, and the difference between the second degree and 180 degrees is not greater than a first difference threshold.

[0055] In a possible implementation manner, the method further includes:

[0056] When the first count value reaches a first count threshold and the first level signal has not been output yet, resetting the first count value to a first initial value and adjusting the first phase difference threshold to a second phase difference threshold, where the second phase difference threshold is greater than the first phase difference threshold.

[0057] In a possible implementation manner, when the first count value reaches the first count threshold and the first level signal has not been output yet, resetting the first count value to a first initial value and adjusting the first phase difference threshold to a second phase difference threshold includes:

[0058] When the first count value reaches the first count threshold and the first level signal has not been output yet, outputting a second level signal;

[0059] Increase the count value based on the second level signal to obtain a second count value; the second phase difference threshold is the phase difference threshold corresponding to the second count value;

[0060] Reset the first count value to the first initial value based on the second level signal.

[0061] In a possible implementation, the operation of doubling the frequency of the first target signal to obtain a second target signal includes:

[0062] Delay the phase of the first target signal according to a third degree to obtain a third target signal; the difference between the third degree and 90 degrees is not greater than a second difference threshold;

[0063] Perform an exclusive OR operation on the first target signal and the third target signal to obtain the second target signal.

[0064] In a possible implementation, before delaying the phase of the first target signal according to the third degree to obtain a third target signal, it further includes:

[0065] In response to a second enable signal, increase the count value based on the clock edge of a second reference signal to obtain a third count value, where the second reference signal is determined based on the original signal;

[0066] Delay the phase of a second input signal according to the degree corresponding to the third count value to obtain a second output signal, where the second input signal is determined based on the original signal;

[0067] Delay the phase of the second output signal according to the degree corresponding to the third count value to obtain a third output signal;

[0068] Delay the phase of the third output signal according to the degree corresponding to the third count value to obtain a fourth output signal;

[0069] Delay the phase of the fourth output signal according to the degree corresponding to the third count value to obtain a fifth output signal;

[0070] When the phase difference between the second input signal and the fifth output signal is not greater than a third phase difference threshold, output a third level signal, where the third level signal is used to indicate taking the degree corresponding to the third count value as the third degree.

[0071] In a possible implementation, the method further includes:

[0072] When the third count value reaches the second count threshold and the third level signal has not been output yet, reset the third count value to the second initial value, and adjust the third phase difference threshold to a fourth phase difference threshold, where the fourth phase difference threshold is greater than the third phase difference threshold.

[0073] In a possible implementation, when the third count value reaches the second count threshold and the third level signal has not been output yet, resetting the third count value to the second initial value and adjusting the third phase difference threshold to the fourth phase difference threshold includes:

[0074] When the third count value reaches the second count threshold and the third level signal has not been output yet, output a fourth level signal;

[0075] Increase the count value based on the fourth level signal to obtain a fourth count value; the fourth phase difference threshold is the phase difference threshold corresponding to the fourth count value;

[0076] Based on the fourth level signal, reset the third count value to the second initial value.

[0077] On the other hand, an embodiment of the present application provides a chip, and the chip includes the signal processing circuit described in any one of the above.

[0078] On the other hand, an embodiment of the present application provides an electronic device, and the electronic device includes the above chip.

[0079] The technical solutions provided by the embodiments of the present application at least bring the following beneficial effects:

[0080] For the technical solutions provided by the embodiments of the present application, the duty cycle of the signal (the first target signal) input to the frequency multiplier and the duty cycle of the signal (the second target signal) output by the frequency multiplier are both close to the reference duty cycle. It can not only achieve the goal of making the duty cycle of the signal output by the frequency multiplier close to the reference duty cycle, but also reduce the fluctuation of the signal output by the frequency multiplier by making the duty cycle of the signal input to the frequency multiplier close to the reference duty cycle, thereby improving the stability of the signal output by the frequency multiplier. Description of the Drawings

[0081] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0082] Figure 1 It is a schematic structural diagram of a signal processing circuit provided by an embodiment of the present application;

[0083] Figure 2 It is a schematic structural diagram of another signal processing circuit provided by an embodiment of the present application;

[0084] Figure 3 It is a schematic structural diagram of another signal processing circuit provided by an embodiment of the present application;

[0085] Figure 4 It is a schematic structural diagram of a first detection circuit provided by an embodiment of the present application;

[0086] Figure 5 It is a schematic structural diagram of another signal processing circuit provided by an embodiment of the present application;

[0087] Figure 6 It is a schematic structural diagram of another signal processing circuit provided by an embodiment of the present application;

[0088] Figure 7 It is a schematic structural diagram of a first control circuit provided by an embodiment of the present application;

[0089] Figure 8 It is a schematic structural diagram of another signal processing circuit provided by an embodiment of the present application;

[0090] Figure 9 It is a schematic structural diagram of another signal processing circuit provided by an embodiment of the present application;

[0091] Figure 10 It is a schematic structural diagram of a second detection circuit provided by an embodiment of the present application;

[0092] Figure 11 It is a schematic structural diagram of another signal processing circuit provided by an embodiment of the present application;

[0093] Figure 12 It is a schematic structural diagram of another signal processing circuit provided by an embodiment of the present application;

[0094] Figure 13 It is a schematic structural diagram of another signal processing circuit provided by an embodiment of the present application;

[0095] Figure 14 It is a working flow chart of Stage1 and Stage2 provided by an embodiment of the present application;

[0096] Figure 15 It is a timing diagram of signals A, B, C, D, and E during the processes of Stage1 and Stage2 provided by an embodiment of the present application;

[0097] Figure 16 It is a schematic diagram of the simulation result of the calibration process of a signal processing circuit provided by an embodiment of the present application;

[0098] Figure 17 It is a schematic diagram of the simulation result of the processing result of a signal processing circuit provided by an embodiment of the present application;

[0099] Figure 18 It is a flowchart of a signal processing method provided by an embodiment of the present application;

[0100] Figure 19 It is a schematic structural diagram of a chip provided by an embodiment of the present application;

[0101] Figure 20 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0102] To make the objectives, technical solutions and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

[0103] The PLL (Phase Locked Loop) circuit generates an output signal with high precision and low jitter based on the signal of the reference clock. The frequency of the signal of the reference clock can greatly affect the anti-noise performance of the PLL circuit. To improve the anti-noise performance of the PLL circuit as much as possible, it is usually necessary to use a frequency multiplier to perform frequency multiplication on the signal of the reference clock on the original basis, thereby reducing the in-band phase noise and output spurs of the PLL circuit. The in-band phase noise of the PLL circuit refers to the random fluctuation of the phase of the output signal within the loop bandwidth of the PLL circuit; the output spurs of the PLL circuit refer to the other unwanted discrete frequency components existing in the signal output by the PLL circuit in addition to the desired fundamental frequency component.

[0104] Traditional frequency multipliers use exclusive-OR gate circuits to implement frequency multiplication operations. To ensure the reliability of the frequency multiplication operation, a duty cycle detection and calibration circuit is usually added to the frequency multiplier to form a frequency multiplier duty cycle calibration circuit. Currently, the common frequency multiplier duty cycle calibration circuits are mainly divided into two types: one is the frequency multiplier duty cycle calibration circuit based on the digital calibration method, and the other is the frequency multiplier duty cycle calibration circuit based on the analog calibration method. The digital calibration method uses logic gates to build a logic circuit on the digital side to perform duty cycle detection and calibration, and is usually greatly affected by process temperature and voltage, and generally has poor calibration accuracy; the analog calibration method usually uses operational amplifiers and capacitors and other analog circuits to perform calibration. Although the accuracy is relatively high, the calibration range of the duty cycle is usually relatively small, so it is limited in application.

[0105] The calibration target of the above duty cycle calibration circuit for the frequency multiplier is to make the signal output by the frequency multiplier close to 50%. However, when the duty cycle of the signal input to the frequency multiplier deviates from 50%, the signal output by the above duty cycle calibration circuit for the frequency multiplier will generate periodic fluctuations, thereby deteriorating the in-band phase noise and output spurs of the PLL circuit.

[0106] An embodiment of the present application provides a signal processing circuit, which can improve the stability of the signal output by the frequency multiplier. Refer to Figure 1 , the signal processing circuit includes a processing circuit 10 and a frequency multiplier 20. The processing circuit 10 is connected to the frequency multiplier 20. The processing circuit 10 is configured to process the original signal to obtain a first target signal, and the duty cycle of the first target signal satisfies a first similarity condition with the reference duty cycle. The frequency multiplier 20 is configured to perform a frequency doubling operation on the first target signal to obtain a second target signal, and the duty cycle of the second target signal satisfies a second similarity condition with the reference duty cycle.

[0107] The original signal refers to the original signal that needs to be frequency doubled by the frequency multiplier 20. In the embodiments of the present application, in order to adjust the duty cycle of the signal input to the frequency multiplier 20, the original signal is not directly input to the frequency multiplier 20, but the signal obtained after processing the original signal is input to the frequency multiplier 20. In some embodiments, the original signal refers to the signal of the reference clock corresponding to the PLL circuit.

[0108] Exemplarily, the reference duty cycle can be 50%, or other values close to 50%. The fact that the duty cycle of the first target signal satisfies the first similarity condition with the reference duty cycle means that the duty cycle of the first target signal is the same as or close to the reference duty cycle. The fact that the duty cycle of the second target signal satisfies the second similarity condition with the reference duty cycle means that the duty cycle of the second target signal is the same as or close to the reference duty cycle. The embodiments of the present application do not limit the first similarity condition and the second similarity condition, which can be set according to experience or flexibly adjusted according to the application scenario. Among them, the duty cycle refers to the ratio of the duration of the high level (or effective level) to the duration of the entire cycle in a complete cycle of the signal.

[0109] Exemplarily, the fact that the duty cycle of the signal (the first target signal or the second target signal) is close to the reference duty cycle means that the difference between the duty cycle of the signal and the reference duty cycle is greater than 0 and not greater than the threshold. The difference between the duty cycle of the signal and the reference duty cycle can refer to the absolute difference between the duty cycle of the signal and the reference duty cycle, or the relative difference between the duty cycle of the signal and the reference duty cycle. Among them, the absolute difference between the duty cycle of the signal and the reference duty cycle refers to the absolute value of the difference between the duty cycle of the signal and the reference duty cycle. The relative difference between the duty cycle of the signal and the reference duty cycle refers to the ratio of the absolute difference between the duty cycle of the signal and the reference duty cycle to the reference duty cycle.

[0110] Exemplarily, taking the difference between the duty cycle of the signal and the reference duty cycle as the absolute difference and the threshold as 2%, the duty cycle of the signal being close to the reference duty cycle means that the absolute difference between the duty cycle of the signal and the reference duty cycle is greater than 0 and not greater than 2%. Assuming the reference duty cycle is 50%, then when the duty cycle of the signal is 48%, 49%, 51%, 52%, etc., the duty cycle of the signal is close to the reference duty cycle. Assuming the reference duty cycle is 55%, then when the duty cycle of the signal is 53%, 54%, 56%, 57%, etc., the duty cycle of the signal is close to the reference duty cycle. Assuming the reference duty cycle is 45%, then when the duty cycle of the signal is 43%, 44%, 46%, 47%, etc., the duty cycle of the signal is close to the reference duty cycle.

[0111] Exemplarily, taking the difference between the duty cycle of the signal and the reference duty cycle as the relative difference and the threshold as 2%, the duty cycle of the signal being close to the reference duty cycle means that the relative difference between the duty cycle of the signal and the reference duty cycle is greater than 0 and not greater than 2%. Assuming the reference duty cycle is 50%, then when the duty cycle of the signal is 49%, 49.5%, 50.5%, 51%, etc., the duty cycle of the signal is close to the reference duty cycle. Assuming the reference duty cycle is 55%, then when the duty cycle of the signal is 53.9%, 54.5%, 55.5%, 56.1%, etc., the duty cycle of the signal is close to the reference duty cycle. Assuming the reference duty cycle is 45%, then when the duty cycle of the signal is 44.1%, 44.5%, 45.5%, 45.9%, etc., the duty cycle of the signal is close to the reference duty cycle.

[0112] The threshold corresponding to the first similarity condition (i.e., the threshold used to determine whether the duty cycle of the first target signal is similar to the reference duty cycle) and the threshold corresponding to the second similarity condition (i.e., the threshold used to determine whether the duty cycle of the second target signal is similar to the reference duty cycle) can be the same or different.

[0113] It should be noted that the first similarity condition can be a condition that directly restricts the magnitude of the duty cycle of the first target signal, or a condition that restricts the magnitude of other factors that can reflect or affect the duty cycle of the first target signal. The embodiments of the present application do not limit this, as long as it can ensure that the duty cycle of the first target signal is the same as or close to the reference duty cycle. The second similarity condition can be a condition that directly restricts the magnitude of the duty cycle of the second target signal, or a condition that restricts the magnitude of other factors that can reflect or affect the duty cycle of the second target signal. The embodiments of the present application do not limit this, as long as it can ensure that the duty cycle of the second target signal is the same as or close to the reference duty cycle.

[0114] Based on such a signal processing circuit, the duty cycles of the signal input to the input frequency doubler 20 (i.e., the first target signal) and the signal output by the frequency doubler 20 (i.e., the second target signal) are both close to the reference duty cycle (the same as or similar to the reference duty cycle). This can not only achieve the goal of making the duty cycle of the signal output by the frequency doubler 20 close to the reference duty cycle, but also reduce the fluctuation of the signal output by the frequency doubler 20 by making the duty cycle of the signal input to the frequency doubler 20 close to the reference duty cycle, which is beneficial to improving the stability of the signal output by the frequency doubler 20.

[0115] In a possible implementation manner, referring to Figure 2 , the processing circuit 10 includes a first determination sub-circuit 11, a first delay module 12, and a NOR gate 13. The first determination sub-circuit 11 is configured to use the inverted signal of the original signal as the first input signal when the duty cycle of the original signal is greater than the reference duty cycle; and use the original signal as the first input signal when the duty cycle of the original signal is not greater than the reference duty cycle. The first delay module 12 is configured to delay the phase of the first input signal according to a first degree to obtain a first output signal. The NOR gate 13 is configured to perform a NOR operation on the first input signal and the first output signal to obtain a first target signal. The first degree is used to make the duty cycle of the first target signal satisfy a first similarity condition with the reference duty cycle.

[0116] The first determination circuit 11 is respectively connected to the first delay module 12 and the NOR gate 13, the NOR gate 13 is connected to the first delay module 12, and the NOR gate 13 is also connected to the frequency doubler 20. The cooperation of the first determination sub-circuit 11, the first delay module 12, and the NOR gate 13 to implement the processing of the original signal is beneficial to improving the standardization of processing the original signal.

[0117] In the embodiments of the present application, taking the reference duty cycle as 50% as an example, since only when the duty cycle of the signal is less than 50%, the signal after the phase delay of the signal and the signal after the NOR operation can gradually converge to a duty cycle of 50%. Therefore, the first determination sub-circuit 11 with the function of detecting the duty cycle of the original signal and determining the first input signal according to the matching method of the duty cycle of the original signal is added to the processing circuit 10.

[0118] Among them, the NOR operation is composed of an OR operation and a NOT operation. Performing a NOR operation on two signals can be understood as first performing an OR operation on the two signals and then performing a NOT operation on the result of the OR operation. When both signals are low-level signals, the result of the NOR operation is a high-level signal; when both signals are high-level signals, or one of the two signals is a high-level signal and the other signal is a low-level signal, the result of the NOR operation is a low-level signal.

[0119] The original signal can be input into the first determination sub-circuit 11. After receiving the original signal, the first determination sub-circuit 11 detects the duty cycle of the original signal. When the duty cycle of the original signal is greater than the reference duty cycle (50%), the original signal is first inverted to obtain the inverted signal of the original signal, and then the inverted signal of the original signal is used as the first input signal. When the duty cycle of the original signal is not greater than the reference duty cycle (50%), the original signal is directly used as the first input signal. After determining the first input signal, the first input signal is transmitted to the first delay module 12 and the NOR gate 13.

[0120] Exemplarily, the input of the original signal into the first determination sub-circuit 11 may mean that the original signal is directly input into the first determination sub-circuit 11, or that the original signal is input into the first determination sub-circuit 11 through a transmission gate. The embodiments of the present application do not limit this.

[0121] The structure of the first determination sub-circuit 11 can be set according to experience or flexibly adjusted according to the application scenario, as long as it is ensured that the first determination sub-circuit 11 has the function of detecting the duty cycle of the original signal and determining the first input signal in a manner matching the duty cycle of the original signal.

[0122] In an exemplary embodiment, the first determination sub-circuit 11 includes a duty cycle detection module, an inverter, a first transmission gate, a second transmission gate, a first switch, and a second switch. The inverter is connected to the first transmission gate. The input end of the duty cycle detection module is used to input the original signal, the output end of the duty cycle detection module is connected to the inverter through the first switch, and the output end of the duty cycle detection module is connected to the second transmission gate through the second switch. The first transmission gate is respectively connected to the first delay module 12 and the NOR gate 13, and the second transmission gate is respectively connected to the first delay module 12 and the NOR gate 13.

[0123] The duty cycle detection module detects the duty cycle of the original signal. When the duty cycle of the original signal is greater than the reference duty cycle, the first switch is turned on and the second switch is turned off. The inverter inverts the original signal to obtain the inverted signal of the original signal, and the first transmission gate transmits the inverted signal of the original signal as the first input signal to the first delay module 12 and the NOR gate 13. When the duty cycle of the original signal is not greater than the reference duty cycle, the first switch is turned off and the second switch is turned on. The second transmission gate transmits the original signal as the first input signal to the first delay module 12 and the NOR gate 13.

[0124] The first delay module 12 can be any hardware module with a phase delay function. After receiving the first input signal, the first delay module 12 delays the phase of the first input signal according to the first degree to obtain the first output signal. After obtaining the first output signal, the first delay module 12 transmits the first output signal to the NOR gate 13. The NOR gate 13 performs a NOR operation on the first input signal and the first output signal after receiving the first input signal and the first output signal to obtain the first target signal.

[0125] The first degree is used to indicate the degree by which the phase of the first input signal needs to be delayed so that the duty cycle of the signal after the NOR operation on the first input signal and the first output signal after the phase delay of the first input signal meets the first similarity condition with the reference duty cycle. Therefore, after the first delay module 12 delays the phase of the first input signal according to the first degree and the NOR gate 13 performs a NOR operation on the first input signal and the first output signal output by the first delay module 12, a first target signal with a duty cycle meeting the first similarity condition with the reference duty cycle can be obtained.

[0126] Before the first delay module 12 delays the phase of the first input signal according to the first degree, the first degree needs to be determined first.

[0127] In an exemplary embodiment, referring to Figure 3 , the signal processing circuit further includes a first counter 30 and a first detection circuit 40. The first counter 30 is configured to increase the count value based on the clock edge of the first reference signal in response to the first enable signal to obtain the first count value, and the first reference signal is determined based on the original signal. The first delay module 12 is further configured to delay the phase of the first input signal according to the degree corresponding to the first count value to obtain an intermediate signal. The NOR gate 13 is further configured to perform a NOR operation on the first input signal and the intermediate signal to obtain a first processed signal. The first detection circuit 40 is configured to output a first level signal when the phase difference between the first clock edge of the first processed signal and the second clock edge of the second processed signal is not greater than the first phase difference threshold, and the first level signal is used to indicate that the degree corresponding to the first count value is used as the first degree.

[0128] Wherein, the directions of the first clock edge and the second clock edge are opposite; the phase difference between the first clock edge and the second clock edge not being greater than the first phase difference threshold is used to indicate that the duty cycle of the first processed signal meets the first similarity condition with the reference duty cycle; the second processed signal is obtained by delaying the phase of the first processed signal by a second degree, and the difference between the second degree and 180 degrees is not greater than the first difference threshold.

[0129] The count value of the first counter 30 is used to adjust the degree of delay of the phase of the first input signal by the first delay module 12. The first enable signal is used to put the first counter 30 into the working state, that is, to make the first counter 30 continuously increase the count value based on the clock edge of the first reference signal.

[0130] In some embodiments, the signal processing circuit further includes a third control circuit, which is used to control the working state of the first counter 30, that is, to control the first counter 30 to be in the working state or the non-working state. The third control circuit can be connected to the first counter 30. When the first counter 30 is required to work, the third control circuit can send a first enable signal to the first counter 30, so that the first counter 30 starts to work under the action of the first enable signal. The embodiment of the present application does not limit the form of the first enable signal, as long as it can ensure that the first counter 30 can recognize it.

[0131] The first reference signal is determined based on the original signal. Exemplarily, the first reference signal can be the original signal. Exemplarily, the first reference signal can also be the first input signal determined by the first determination sub-circuit 11 on the basis of the original signal. Exemplarily, the first reference signal can also be other signals determined on the basis of the original signal. The embodiment of the present application does not limit this, as long as it can ensure that the first counter 30 can receive the first reference signal.

[0132] The clock edge of the first reference signal can refer to the rising edge of the first reference signal or the falling edge of the first reference signal. The embodiment of the present application does not limit this. The first counter 30 increasing the count value based on the clock edge of the first reference signal means that every time the first counter 30 detects a clock edge of the first reference signal, it increases the existing count value by 1 to obtain a new count value.

[0133] Different count values of the first counter 30 correspond to different degrees. Exemplarily, the count value and the degree are in a positive correlation relationship, that is, the larger the count value, the larger the degree corresponding to the count value. Based on this, as the count value of the first counter 30 continuously increases, the first delay module 12 continuously increases the degree of delaying the phase of the first input signal. The first input signal refers to the signal output by the first determination sub-circuit 11 according to the input original signal described above.

[0134] Exemplarily, the count value of the first counter 30 is not less than 0 and not greater than the first counting threshold. The degree of delay of the phase of the first input signal by the first delay module 12 is not less than 0 and not greater than 360 degrees. The corresponding relationship between the count value and the degree can be that for each increase of 1 in the count value, the degree increases by 360 / n degrees, where n represents the first counting threshold and n is an integer greater than 0. The first counting threshold can be set according to experience or flexibly adjusted according to the application scenario. The embodiments of the present application do not limit this. For example, the first counting threshold can be 63 or 255, etc.

[0135] In the embodiments of the present application, the current count value of the first counter 30 is referred to as the first count value. The signal obtained after the first delay module 12 delays the phase of the first input signal according to the degree corresponding to the first count value is referred to as the intermediate signal. The signal obtained by the NOR gate 13 performing a NOR operation on the first input signal and the intermediate signal is referred to as the first processed signal.

[0136] In an exemplary embodiment, the first counter 30 is connected to the first delay module 12. The first delay module 12 can independently determine the corresponding degree according to the first count value and delay the phase of the first input signal according to the determined degree. In an exemplary embodiment, the signal processing circuit further includes a fourth control circuit, which is respectively connected to the first counter 30 and the first delay module 12. The fourth control circuit is used to determine the degree corresponding to the first count value and send a control signal to the first delay module 12. The control signal is used to instruct the first delay module 12 to delay the phase of the first input signal according to the degree corresponding to the first count value. Under the control of the control signal, the first delay module 12 delays the phase of the first input signal according to the degree corresponding to the first count value.

[0137] The first detection circuit 40 can receive the first processed signal and the second processed signal. The first processed signal is transmitted from the NOR gate 13 to the first detection circuit 40. The second processed signal is obtained by delaying the phase of the first processed signal by a second degree. The difference between the second degree and 180 degrees is not greater than the first difference threshold. The first difference threshold can be set according to experience or flexibly adjusted according to the application scenario. The embodiments of the present application do not limit this. Exemplarily, the first difference threshold can be 0 or a relatively small value greater than 0. Since the first difference threshold is small, the second degree can be considered to be the same as or similar to 180 degrees.

[0138] The embodiments of the present application do not limit the determination method of the first detection circuit 40 receiving the second processing signal. Exemplarily, the signal processing circuit further includes a target delay module. The first detection circuit 40 and the NOR gate 13 are respectively connected to the target delay module. The target delay module is configured to delay the phase of the first processing signal according to the second degree to obtain the second processing signal and transmit the second processing signal to the first detection circuit 40.

[0139] After receiving the first processing signal and the second processing signal, the first detection circuit 40 detects the phase difference between the first clock edge of the first processing signal and the second clock edge of the second processing signal, and determines whether the phase difference between the first clock edge of the first processing signal and the second clock edge of the second processing signal is greater than the first phase difference threshold.

[0140] The directions of the first clock edge and the second clock edge are opposite. Exemplarily, the first clock edge is a rising edge and the second clock edge is a falling edge; or the first clock edge is a falling edge and the second clock edge is a rising edge. Exemplarily, the phase difference between the first clock edge of the first processing signal and the second clock edge of the second processing signal may refer to the phase difference between any first clock edge of the first processing signal and the corresponding second clock edge of the second processing signal. The corresponding second clock edge of the second processing signal refers to the second clock edge with the smallest phase difference from the any first clock edge among the respective second clock edges of the second processing signal.

[0141] The first phase difference threshold can be set according to experience or flexibly adjusted according to the application scenario. The embodiments of the present application do not limit this. Exemplarily, the first phase difference threshold can be 0 or a relatively small value greater than 0.

[0142] Since the first phase difference threshold is small, when the phase difference between the first clock edge of the first processing signal and the second clock edge of the second processing signal is not greater than the first phase difference threshold, it can be considered that the first clock edge of the first processing signal is aligned or approximately aligned with the second clock edge of the second processing signal. Since the second processing signal is obtained by delaying the phase of the first processing signal by 180 degrees or approximately 180 degrees, when the first clock edge of the first processing signal is aligned or approximately aligned with the second clock edge of the second processing signal, it indicates that the duty cycle of the first processing signal is the same as or similar to the reference duty cycle (50%), that is, it indicates that the duty cycle of the first processing signal and the reference duty cycle satisfy the first similarity condition. Therefore, in the embodiments of the present application, the phase difference between the first clock edge and the second clock edge not being greater than the first phase difference threshold is used as the judgment criterion for the duty cycle of the first processing signal and the reference duty cycle to satisfy the first similarity condition, so as to improve the convenience of judging whether the duty cycle of the first processing signal and the reference duty cycle satisfy the first similarity condition.

[0143] When the phase difference between the first clock edge of the first processing signal and the second clock edge of the second processing signal is not greater than the first phase difference threshold, the first detection circuit 40 outputs a first level signal, which is used to indicate that the degree corresponding to the first count value is used as the first degree. The first level signal can be any kind of level signal. For example, the first level signal can be a high level signal; for another example, the first level signal can also be a low level signal.

[0144] If the degree corresponding to the first count value is used as the first degree, then the first processing signal is the first target signal. Since the duty cycle of the first processing signal satisfies the first similarity condition with the reference duty cycle, the duty cycle of the first target signal also satisfies the first similarity condition with the reference duty cycle. Thus, the first degree for making the duty cycle of the first target signal satisfy the first similarity condition with the reference duty cycle is determined.

[0145] In an exemplary embodiment, when the phase difference between the first clock edge of the first processing signal and the second clock edge of the second processing signal is greater than the first phase difference threshold, the first detection circuit 40 does not output the first level signal. Exemplarily, the first detection circuit 40 may not output any signal, or may output a signal different from the first level signal.

[0146] In an exemplary embodiment, the first detection circuit 40 may transmit the first level signal to the third control circuit. After receiving the first level signal, the third control circuit transmits a stop counting signal to the first counter 30; after receiving the stop counting signal, the first counter 30 stops counting. Since the count value of the first counter 30 no longer changes, the degree of delaying the phase of the first input signal by the first delay module 12 no longer changes, and this unchanged degree is the first degree.

[0147] If the first detection circuit 40 does not output the first level signal and the first count value does not reach the first counting threshold, the first counter 30, the first delay module 12, the NOR gate 13, and the first detection circuit 40 continue to work based on the same principle until the first detection circuit 40 outputs the first level signal or the first count value reaches the first counting threshold. If the first detection circuit 40 outputs the first level signal, the degree corresponding to the count value of the first counter 30 on which the first level signal depends is used as the first degree.

[0148] The structure of the first detection circuit 40 can be set according to experience or flexibly adjusted according to the application scenario, and the embodiments of the present application do not limit this.

[0149] In a possible implementation, the first detection circuit 40 includes a first detection sub-circuit and a first holding sub-circuit. The first detection sub-circuit is configured to output a first level signal when the phase difference between the first clock edge of the first processing signal and the second clock edge of the second processing signal is not greater than the first phase difference threshold. The first holding sub-circuit is configured to hold the first level signal after the first detection sub-circuit outputs the first level signal. The embodiments of the present application do not limit the specific structures of the first detection sub-circuit and the first holding sub-circuit, as long as the corresponding functions can be implemented.

[0150] Taking the first level signal as a high level signal and the first phase difference threshold as 0 as an example, the structure of the first detection circuit 40 can be as [[ID=G]] Figure 4 shown. In Figure 4 , the first detection sub-circuit in the first detection circuit 40 includes four D flip-flops 41, a NAND gate 42, a NAND gate 43, and a NOR gate 44. The four D flip-flops 41 are respectively configured to sample the AXORC signal according to the A signal, the C signal, the A~ signal, and the C~ signal. The A signal represents the first processing signal, the A~ signal represents the inverted signal of the first processing signal, the C signal represents the second processing signal, the C~ signal represents the inverted signal of the second processing signal, and the AXORC signal represents the signal obtained by performing an exclusive OR operation on the first processing signal and the second processing signal. The rule for performing an exclusive OR operation on two signals is that when the two signals are different, the result of the exclusive OR operation is a high level signal; when the two signals are the same, the result of the exclusive OR operation is a low level signal.

[0151] The NAND gate 42 is configured to perform a NAND operation on the signal output by the first D flip-flop 41 and the signal output by the second D flip-flop 41. The NAND gate 43 is configured to perform a NAND operation on the signal output by the third D flip-flop 41 and the signal output by the fourth D flip-flop 41. The NOR gate 44 is configured to perform a NOR operation on the signal output by the NAND gate 42 and the signal output by the NAND gate 43. The NAND operation is composed of an AND operation and a NOT operation. Performing a NAND operation on two signals can be understood as first performing an AND operation on the two signals and then performing a NOT operation on the result of the AND operation. When both signals are high level signals, the result of the NAND operation is a low level signal; when both signals are low level signals, or when one of the two signals is a high level signal and the other signal is a low level signal, the result of the NAND operation is a high level signal.

[0152] If the first clock edge of the first processing signal and the second clock edge of the second processing signal are completely aligned (phase difference is 0), then the signals output by the four D flip-flops 41 are all high-level signals "1", the signal output by the NAND gate 42 is a low-level signal "0", the signal output by the NAND gate 43 is a low-level signal "0", and the signal output by the NOR gate 44 is a high-level signal "1" (i.e., the first-level signal). Since the degree of phase delay of the first delay module 12 is constantly changing, therefore, in order to prevent the detection result from jumping before it is successfully output, Figure 4 shows a first holding sub-circuit triggered by a high-level signal. That is, once the NOR gate 44 outputs a high-level signal "1", the result output by the first holding sub-circuit always remains a high-level signal "1".

[0153] Figure 4 The first holding sub-circuit shown in includes a NOR gate 45, a NOR gate 46, an inverter 47, and a NOR gate 48. The connection relationship between the NOR gate 45, the NOR gate 46, the inverter 47, and the NOR gate 48 is as Figure 4 shown. It should be noted that one input terminal of the NOR gate 45 is connected to the output terminal of the NOR gate 46. That is, the signal output by the output terminal of the NOR gate 46 will be synchronized to one input terminal of the NOR gate 45. The signals input to the NOR gate 46 and the NOR gate 48 include Rst, and Rst is used to indicate whether to trigger a reset operation. When triggering a reset operation, Rst is a high-level signal "1"; when not triggering a reset operation, Rst is a low-level signal "0". In the embodiments of the present application, the case of not triggering a reset operation is taken as an example for description, that is, Rst is a low-level signal "0".

[0154] When the NOR gate 44 outputs a high-level signal "1", the NOR gate 45 outputs a low-level signal "0", the NOR gate 46 outputs a high-level signal "1", the inverter 47 outputs a low-level signal "0", and the NOR gate 48 outputs a high-level signal "1". In addition, the high-level signal "1" output by the NOR gate 46 will be synchronized to one input terminal of the NOR gate 45, so that the NOR gate 45 always outputs a low-level signal "0", and further enables the NOR gate 48 to always output a high-level signal "1", that is, to achieve maintaining a high-level signal "1".

[0155] In an exemplary embodiment, referring to Figure 5 , the signal processing circuit further includes a first control circuit 50. The first control circuit 50 is used to reset the first count value to the first initial value and adjust the first phase difference threshold to a second phase difference threshold greater than the first phase difference threshold when the first count value reaches the first count threshold and the first detection circuit 40 still has not output the first-level signal. The first control circuit 50 is respectively connected to the first counter 30 and the first detection circuit 40.

[0156] The first initial value is the minimum count value of the first counter 30. Exemplarily, the first initial value is 0. The embodiments of the present application do not limit the manner of adjusting the first phase difference threshold to the second phase difference threshold, as long as it is ensured that the second phase difference threshold is greater than the first phase difference threshold. Exemplarily, a fixed value is added to the first phase difference threshold to obtain the second phase difference threshold. Exemplarily, the total number of times that the count value of the first counter 30 reaches the first count threshold and the first detection circuit 40 still does not output the first level signal is statistically counted. The total number is positively correlated with the phase difference threshold, and the phase difference threshold corresponding to the total number is used as the second phase difference threshold.

[0157] After resetting the first count value to the first initial value and determining the second phase difference threshold, the first counter 30, the first delay module 12, the NOR gate 13, and the first detection circuit 40 repeat the process of determining the first degree based on the first initial value and the second phase difference threshold.

[0158] The embodiments of the present application add a function of automatic threshold adjustment. When the first counter 30 finishes traversing (i.e., the first count value reaches the first count threshold) but the first detection circuit 40 still does not output the first level signal, the decision accuracy is automatically reduced (i.e., the phase difference threshold on which the determination of whether to output the first level signal depends is increased), and the process of determining the first degree is repeated. In this way, the influence of signal fluctuations in different temperature process environments on the process of determining the first degree can be overcome.

[0159] In an exemplary embodiment, referring to Figure 6 , the first control circuit 50 includes a first logic sub-circuit 51, a second counter 52, and a second logic sub-circuit 53. The first logic sub-circuit 51 is configured to output a second level signal when the first count value reaches the first count threshold and the first detection circuit 40 still does not output the first level signal. The second counter 52 is configured to increase the count value based on the second level signal to obtain a second count value; the second phase difference threshold is the phase difference threshold corresponding to the second count value. The second logic sub-circuit 53 is configured to reset the first count value to the first initial value based on the second level signal.

[0160] The first logic sub-circuit 51 is respectively connected to the second counter 52 and the second logic sub-circuit 53. When the first count value reaches the first count threshold and the first detection circuit 40 still does not output the first level signal, the first logic sub-circuit 51 outputs a second level signal. The second level signal can be any level signal, such as a high level signal, a low level signal, etc. After the first logic sub-circuit 51 outputs the second level signal, the second counter 52 and the second logic sub-circuit 53 can receive the second level signal.

[0161] After receiving the second-level signal, the second counter 52 increases the count value based on the second-level signal. In other words, every time the second counter 52 receives a second-level signal, the existing count value is incremented by 1. Different count values of the second counter 52 correspond to different phase difference thresholds. Exemplarily, the count value is positively correlated with the phase difference threshold, that is, the larger the count value, the larger the phase difference threshold corresponding to the count value. Based on this, as the count value of the second counter 52 continuously increases, the phase difference threshold on which the first detection circuit 40 depends to determine whether to output the first-level signal also continuously increases. The correspondence between the count value and the phase difference threshold can be set according to experience or flexibly adjusted according to the application scenario, as long as the count value is positively correlated with the phase difference threshold. In the embodiment of the present application, the count value obtained after the second counter 52 increases the count value based on the second-level signal is referred to as the second count value, and the second phase difference threshold refers to the phase difference threshold corresponding to the second count value.

[0162] Exemplarily, the second counter 52 is connected to the first detection circuit 40, and the first detection circuit 40 can determine the second phase difference threshold according to the second count value, and based on the determined second phase difference threshold, determine whether to output the first-level signal.

[0163] After receiving the second-level signal, the second logic sub-circuit 53 resets the first count value to the first initial value. Exemplarily, the second logic sub-circuit 53 is connected to the first counter 30. After receiving the second-level signal, the second logic sub-circuit 53 transmits a reset signal to the first counter 30, and this reset signal is used to instruct the first counter 30 to reset the first count value to the first initial value. The form of the reset signal is not limited in the embodiment of the present application, as long as the first counter 30 can recognize it.

[0164] Exemplarily, when the first count value does not reach the first count threshold or the first detection circuit 40 outputs the first-level signal, the first logic sub-circuit 51 does not output the second-level signal, the second counter 52 keeps the count value unchanged, and the second logic sub-circuit 53 does not reset the count value of the first counter 30.

[0165] Exemplarily, taking the second-level signal as a high-level signal as an example, the structures of the first logic sub-circuit 51, the second counter 52, and the second logic sub-circuit 53 can be as Figure 7As shown. The first logic sub-circuit 51 includes an inverter 511 and a NOR gate 512. The inverter 511 is used to invert the input End_of_range and output End_of_range_b. The NOR gate 512 is used to perform a NOR operation on End_of_range_b and Duty_end_buf and output Re_cycle1. End_of_range is used to indicate whether the count value of the first counter 30 reaches the first counting threshold. When the count value of the first counter 30 reaches the first counting threshold, End_of_range is a high-level signal "1"; when the count value of the first counter 30 does not reach the first counting threshold, End_of_range is a low-level signal "0". End_of_range_b is the inverted signal of End_of_range. When End_of_range is a high-level signal "1", End_of_range_b is a low-level signal "0"; when End_of_range is a low-level signal "0", End_of_range_b is a high-level signal "1". Duty_end_buf is used to indicate whether the first detection circuit 40 outputs a first-level signal. When the first detection circuit 40 outputs a first-level signal, Duty_end_buf is a high-level signal "1"; when the first detection circuit 40 does not output a first-level signal, Duty_end_buf is a low-level signal "0".

[0166] When the first count value reaches the first counting threshold and the first detection circuit 40 still does not output a first-level signal, End_of_range is a high-level signal "1", End_of_range_b is a low-level signal "0", and Duty_end_buf is a low-level signal "0". The Re_cycle1 output after the NOR gate 512 performs a NOR operation on End_of_range_b and Duty_end_buf is a high-level signal "1" (i.e., the second-level signal).

[0167] The second counter 52 is a 3-bit counter implemented by 3 D flip-flops 521. Such a counter can achieve adjustment of 8 levels of phase difference thresholds. The clock signal CK of the first D flip-flop 521 is provided by the first logic sub-circuit 51. The count value of the second counter 52 is determined based on Th_ctrl_st1<0> output by the first D flip-flop 521, Th_ctrl_st1<1> output by the second D flip-flop 521, and Th_ctrl_st1<2> output by the third D flip-flop 521. When the Re_cycle1 output by the NOR gate 512 is a high-level signal "1", the count value of the second counter 52 counter is incremented by 1 to increase the first phase difference threshold by one level.

[0168] The second logic sub - circuit 53 includes an inverter 531 and an AND gate 532. The inverter 531 is used to invert Re_cycle1 output by the inverter 512 and output Re_cycle1_b. The AND gate 532 is used to perform an AND operation on Re_cycle1_b, Rstn, and Stage2_over, and output Rstn_cnt1. Among them, Rstn is used to indicate whether a reset operation is triggered. When the reset operation is not triggered, Rstn is a high - level signal "1"; when the reset operation is triggered, Rstn is a low - level signal "0". Stage2_over is used to indicate whether the process of determining the first degree is completed. When the process of determining the first degree is not completed, Stage2_over is a high - level signal "1"; when the process of determining the first degree is completed, Stage2_over is a low - level signal "0".

[0169] When Re_cycle1 output by the NOR gate 512 is a high - level signal "1", the inverter 531 outputs Re_cycle1_b as a low - level signal "0". During the process of determining the first degree, the reset operation is not triggered, and the process of determining the first degree is not completed, that is, Rstn is a high - level signal "1" and Stage2_over is a high - level signal "1". In this case, the AND gate 532 performs an AND operation on Re_cycle1_b, Rstn, and Stage2_over and outputs Rstn_cnt1 as a low - level signal "0" (that is, the reset signal), and this reset signal is used to make the first counter 30 reset the count value to the first initial value (which can also be called counting clear).

[0170] It should be noted that the above is only described by taking the first phase - difference threshold being less than the first maximum phase - difference threshold as an example. The first maximum phase - difference threshold refers to the maximum phase - difference threshold on which the judgment of whether to output the first level signal depends. The first maximum phase - difference threshold can be set according to experience or flexibly adjusted according to the application scenario. In the case where the first phase - difference threshold is equal to the first maximum phase - difference threshold, when the first count value reaches the first count threshold and the first detection circuit 40 still does not output the first level signal, it indicates that the process of determining the first degree fails, that is, it indicates that the duty cycle of the first target signal cannot satisfy the first similarity condition with the reference duty cycle.

[0171] In a possible implementation, refer to Figure 8 , the frequency multiplier 20 includes a second delay module 21 and an exclusive - OR gate 22. The second delay module 21 is used to delay the phase of the first target signal according to the third degree to obtain a third target signal; the difference between the third degree and 90 degrees is not greater than the second difference threshold. The exclusive - OR gate 22 is used to perform an exclusive - OR operation on the first target signal and the third target signal to obtain a second target signal.

[0172] The second delay module 21 can be any hardware module with a phase delay function. The second delay module 21 is connected to the processing circuit 10. For example, the second delay module 21 is connected to the NOR gate 13 in the processing circuit 10; the XOR gate 22 is connected to the second delay module 21 and the processing circuit 10. For example, the XOR gate 22 is connected to the second delay module 21 and the NOR gate 13 in the processing circuit 10.

[0173] The second difference threshold can be set according to experience or flexibly adjusted according to the application scenario, and the embodiments of the present application do not limit this. Exemplarily, the second difference threshold can be 0 or a relatively small value greater than 0. The second difference threshold can be the same as or different from the first difference threshold. Since the second difference threshold is small, the third degree can be considered to be the same as or similar to 90 degrees.

[0174] The third target signal can be regarded as a signal obtained by delaying the phase of the first target signal by 90 degrees or approximately 90 degrees. When the duty cycle of the first target signal is close to the reference duty cycle (50%), the duty cycle of the signal obtained by performing an XOR operation on the first target signal and the third target signal is also close to the reference duty cycle (50%). Based on this, it can be ensured that the duty cycle of the second target signal is close to the reference duty cycle (50%), that is, it is ensured that the duty cycle of the second target signal and the reference duty cycle satisfy the second similarity condition.

[0175] Exemplarily, the third degree can be set according to experience or determined through continuous adjustment. The embodiments of the present application will be described by taking the third degree as determined through continuous adjustment as an example. That is, before the second delay module 21 delays the phase of the first target signal according to the third degree, the third degree needs to be determined first.

[0176] In a possible implementation manner, refer to Figure 9, the signal processing circuit further includes a third counter 60, a third delay module 70, a fourth delay module 80, a fifth delay module 90, and a second detection circuit 100. The third counter 60 is configured to increase a count value based on a clock edge of a second reference signal in response to a second enable signal, so as to obtain a third count value, where the second reference signal is determined based on the original signal. The second delay module 21 is further configured to delay a phase of a second input signal according to a degree corresponding to the third count value to obtain a second output signal, where the second input signal is determined based on the original signal. The third delay module 70 is configured to delay a phase of the second output signal according to a degree corresponding to the third count value to obtain a third output signal. The fourth delay module 80 is configured to delay a phase of the third output signal according to a degree corresponding to the third count value to obtain a fourth output signal. The fifth delay module 90 is configured to delay a phase of the fourth output signal according to a degree corresponding to the third count value to obtain a fifth output signal. The second detection circuit 100 is configured to output a third level signal when a phase difference between the second input signal and the fifth output signal is not greater than a third phase difference threshold, where the third level signal is used to indicate using the degree corresponding to the third count value as a third degree.

[0177] The second delay module 21, the third delay module 70, the fourth delay module 80, and the fifth delay module 90 are four serially connected delay modules in sequence. The second delay module 21, the third delay module 70, the fourth delay module 80, and the fifth delay module 90 are all configured to delay a phase of an input signal. In addition, the degrees of delaying the phase of the input signal by the second delay module 21, the third delay module 70, the fourth delay module 80, and the fifth delay module 90 are the same.

[0178] The count value of the third counter 60 is used to adjust the degrees of delaying the phase of the input signal by the second delay module 21, the third delay module 70, the fourth delay module 80, and the fifth delay module 90. The second enable signal is used to make the third counter 60 in a working state, that is, to make the third counter 60 continuously increase the count value based on the clock edge of the second reference signal.

[0179] In some embodiments, for the case where the signal processing circuit further includes a third control circuit, the third control circuit is further configured to control the working state of the third counter 60, that is, to control the third counter 60 to be in a working state or a non-working state. The third control circuit may be connected to the third counter 60. When the third counter 60 needs to work, the third control circuit may send a second enable signal to the third counter 60, so that the third counter 60 starts to work under the action of the second enable signal. Embodiments of the present application do not limit the form of the second enable signal, as long as it can ensure that the third counter 60 can recognize it.

[0180] The second reference signal is determined based on the original signal. Exemplarily, the second reference signal may be the original signal. Exemplarily, the second reference signal may also be the first input signal determined by the first determination sub-circuit 11 based on the original signal. Exemplarily, the second reference signal may also be other signals determined based on the original signal. The embodiments of the present application do not limit this, as long as it is ensured that the third counter 60 can receive the second reference signal. The second reference signal may be the same as the first reference signal or different from the first reference signal.

[0181] The clock edge of the second reference signal may refer to the rising edge of the second reference signal or the falling edge of the second reference signal. The embodiments of the present application do not limit this. The third counter 60 increasing the count value based on the clock edge of the second reference signal means that each time the third counter 60 detects a clock edge of the second reference signal, the existing count value is incremented by 1 to obtain a new count value.

[0182] Different count values of the third counter 60 correspond to different degrees. Exemplarily, there is a positive correlation between the count value and the degree, that is, the larger the count value, the larger the degree corresponding to the count value. Based on this, as the count value of the third counter 60 continuously increases, the second delay module 21, the third delay module 70, the fourth delay module 80, and the fifth delay module 90 continuously increase the degree of delaying the phase of the input signal.

[0183] Exemplarily, the count value of the third counter 60 is not less than 0 and not greater than the second counting threshold. The degrees of delaying the phase of the input signal by the second delay module 21, the third delay module 70, the fourth delay module 80, and the fifth delay module 90 are not less than 0 and not greater than 360 degrees. The correspondence between the count value and the degree may be that for each increase of 1 in the count value, the degree increases by 360 / m degrees, where m represents the second counting threshold and m is an integer greater than 0. The second counting threshold may be set according to experience or flexibly adjusted according to the application scenario. The embodiments of the present application do not limit this. For example, the second counting threshold may be 63 or 255, etc. The second counting threshold may be the same as the first counting threshold or different from the first counting threshold.

[0184] In the embodiments of the present application, the current count value of the third counter 60 is referred to as the third count value. The second delay module 21, the third delay module 70, the fourth delay module 80, and the fifth delay module 90 are used to delay the phase of the input signal according to the degree corresponding to the third count value.

[0185] Among them, in the process of determining the third degree, the signal input by the second delay module 21 is the second input signal, and the second input signal is determined based on the original signal. Exemplarily, the second input signal is the original signal. Exemplarily, the second input signal is the first input signal determined by the first determination sub-circuit 11 based on the original signal. Exemplarily, the second input signal may also be a signal obtained by processing the original signal through the first determination sub-circuit 11, the first delay module 12, and the NOR gate 13 before or after determining the first degree. The embodiments of the present application do not limit this.

[0186] The signal input by the third delay module 70 is the signal output by the second delay module 21 (referred to as the second output signal), the signal input by the fourth delay module 80 is the signal output by the third delay module 70 (referred to as the third output signal), and the signal input by the fifth delay module 90 is the signal output by the fourth delay module 80 (referred to as the fourth output signal). In addition, the embodiments of the present application refer to the signal output by the fifth delay module 90 as the fifth output signal.

[0187] In an exemplary embodiment, the third counter 60 is connected to the second delay module 21, the third delay module 70, the fourth delay module 80, and the fifth delay module 90. The second delay module 21, the third delay module 70, the fourth delay module 80, and the fifth delay module 90 can independently determine the corresponding degree according to the third count value, and delay the phase of the input signal according to the determined degree. In an exemplary embodiment, the signal processing circuit further includes a fifth control circuit, and the fifth control circuit is connected to the third counter 60, the second delay module 21, the third delay module 70, the fourth delay module 80, and the fifth delay module 90. The fifth control circuit is used to determine the degree corresponding to the third count value, and send a control signal to the second delay module 21, the third delay module 70, the fourth delay module 80, and the fifth delay module 90. The control signal is used to instruct the second delay module 21, the third delay module 70, the fourth delay module 80, and the fifth delay module 90 to delay the phase of the input signal according to the degree corresponding to the third count value. Under the control of the control signal, the second delay module 21, the third delay module 70, the fourth delay module 80, and the fifth delay module 90 delay the phase of the input signal according to the degree corresponding to the third count value.

[0188] The second detection circuit 100 can receive a second input signal and a fifth output signal. The fifth output signal is transmitted from the fifth delay module 90 to the second detection circuit 100. Exemplarily, for the case where the second input signal is a signal obtained by processing an original signal through the first determination sub-circuit 11, the first delay module 12, and the NOR gate 13 before or after determining the first degree, the second input signal can be transmitted from the NOR gate 13 to the second detection circuit 100.

[0189] After receiving the second input signal and the fifth output signal, the second detection circuit 100 detects the phase difference between the second input signal and the fifth output signal, and determines whether the phase difference between the second input signal and the fifth output signal is greater than a third phase difference threshold. Exemplarily, the second input signal and the fifth output signal may refer to the phase difference between any clock edge of the second input signal and the corresponding clock edge of the fifth output signal. The corresponding clock edge of the fifth output signal refers to the clock edge with the smallest phase difference from the any first clock edge among the candidate clock edges of the fifth output signal, and the candidate clock edge refers to the clock edge of the fifth output signal with the same type as any clock edge, where the type of any clock edge is a rising edge or a falling edge.

[0190] The third phase difference threshold can be set according to experience or flexibly adjusted according to the application scenario, and the embodiments of the present application do not limit this. Exemplarily, the third phase difference threshold can be 0 or a relatively small value greater than 0. The third phase difference threshold can be the same as the first phase difference threshold or the second phase difference threshold, or can be different from both the first phase difference threshold and the second phase difference threshold.

[0191] When the phase difference between the second input signal and the fifth output signal is not greater than the third phase difference threshold, the second detection circuit 100 outputs a third level signal, and this third level signal is used to indicate taking the degree corresponding to the third count value as the third degree. The third level signal can be any kind of level signal. For example, the third level signal can be a high level signal; for another example, the third level signal can also be a low level signal. Since the third phase difference threshold is small, when the phase difference between the second input signal and the fifth output signal is not greater than the third phase difference threshold, it can be considered that the fifth output signal is obtained by continuously delaying the phase of the second input signal by four times of 90 degrees or approximately 90 degrees, that is, it can be considered that the degree corresponding to the third count value is the same as or similar to 90 degrees. Therefore, the second detection circuit 100 outputs the third level signal for indicating taking the degree corresponding to the third count value as the third degree. Thus, the third degree is determined.

[0192] In an exemplary embodiment, when the phase difference between the second input signal and the fifth output signal is greater than the third phase difference threshold, the second detection circuit 100 does not output a third-level signal. Exemplarily, the second detection circuit 100 may not output any signal, or may output a signal different from the third-level signal.

[0193] In an exemplary embodiment, the second detection circuit 100 may transmit a third-level signal to the third control circuit. After receiving the third-level signal, the third control circuit transmits a stop counting signal to the third counter 60; after receiving the stop counting signal, the third counter 60 stops counting. Since the count value of the third counter 60 no longer changes, the degrees of phase delay of the input signals by the second delay module 21, the third delay module 70, the fourth delay module 80, and the fifth delay module 90 also no longer change, and the unchanged degree is the third degree.

[0194] If the second detection circuit 100 does not output a third-level signal and the third count value does not reach the second counting threshold, the third counter 60, the second delay module 21, the third delay module 70, the fourth delay module 80, the fifth delay module 90, and the second detection circuit 100 continue to work based on the same principle until the second detection circuit 100 outputs a third-level signal or the third count value reaches the second counting threshold. If the second detection circuit 100 outputs a third-level signal, the degree corresponding to the count value of the third counter 60 on which the third-level signal depends is used as the third degree.

[0195] In some embodiments, the target delay module mentioned above for delaying the phase of the first processing signal according to the second degree to obtain the second processing signal may include a second delay module 21 and a third delay module 70 for delaying the phase of the input signal according to the third degree. In this case, the second degree is twice the third degree. Based on this, the process of determining the third degree is first performed, and then the process of determining the first degree is performed.

[0196] The structure of the second detection circuit 100 can be set according to experience or flexibly adjusted according to the application scenario, and the embodiments of the present application do not limit this.

[0197] In a possible implementation manner, the second detection circuit 100 includes a second detection sub-circuit and a second holding sub-circuit. The second detection sub-circuit is configured to output a third-level signal when the phase difference between the second input signal and the fifth output signal is not greater than the third phase difference threshold; the second holding sub-circuit is configured to hold the third-level signal after the second detection sub-circuit outputs the third-level signal. The embodiments of the present application do not limit the specific structures of the second detection sub-circuit and the second holding sub-circuit, as long as the corresponding functions can be implemented.

[0198] Taking the third-level signal as the high-level signal and the third phase difference threshold as 0 as an example, the structure of the second detection circuit 100 can be as follows Figure 10 shown in Figure 10 wherein, the second detection sub-circuit in the second detection circuit 100 includes 4 D flip-flops 101, a NAND gate 102, a NAND gate 103, and a NOR gate 104. The 4 D flip-flops 101 are respectively used to sample the A'XNORE signal according to the A' signal, the E signal, the A'~ signal, and the E~ signal. The A' signal represents the second input signal, the A'~ signal represents the inverted signal of the second input signal, the E signal represents the fifth output signal, the E~ signal represents the inverted signal of the fifth output signal, and the A'XNORE signal represents the signal obtained by performing an exclusive-NOR operation on the second input signal and the fifth output signal. The rule for performing an exclusive-NOR operation on two signals is: when the two signals are the same, the result of the exclusive-NOR operation is a high-level signal; when the two signals are different, the result of the exclusive-NOR operation is a low-level signal.

[0199] The NAND gate 102 is used to perform a NAND operation on the signal output by the first D flip-flop 101 and the signal output by the second D flip-flop 101; the NAND gate 103 is used to perform a NAND operation on the signal output by the third D flip-flop 101 and the signal output by the fourth D flip-flop 101; the NOR gate 104 is used to perform a NOR operation on the signal output by the NAND gate 102 and the signal output by the NAND gate 103.

[0200] The second holding sub-circuit includes a NOR gate 105, a NOR gate 106, an inverter 107, and a NOR gate 108. One input terminal of the NOR gate 105 is connected to the output terminal of the NOR gate 106, that is, the signal output by the output terminal of the NOR gate 106 will be synchronized to one input terminal of the NOR gate 105.

[0201] If the second input signal is completely aligned with the fifth output signal (phase difference is 0), then the signals output by the 4 D flip-flops 101 are all high-level signals "1", the signal output by the NAND gate 102 is a low-level signal "0", the signal output by the NAND gate 103 is a low-level signal "0", and the signal output by the NOR gate 104 is a high-level signal "1" (that is, the third-level signal).

[0202] When the output of the NOR gate 104 is a high-level signal "1", the output of the NOR gate 105 is a low-level signal "0", the output of the NOR gate 106 is a high-level signal "1", the output of the inverter 107 is a low-level signal "0", and the output of the NOR gate 108 is a high-level signal "1". In addition, the high-level signal "1" output by the NOR gate 106 is synchronized to an input terminal of the NOR gate 105, so that the NOR gate 105 always outputs a low-level signal "0", and further enables the NOR gate 108 to always output a high-level signal "1", that is, to achieve maintaining the high-level signal "1". That is, once the output of the NOR gate 104 is a high-level signal "1", the result output by the second holding sub-circuit always remains the high-level signal "1".

[0203] In a possible implementation manner, referring to Figure 11 , the signal processing circuit further includes a second control circuit 110. The second control circuit 110 is used to reset the third count value to the second initial value and adjust the third phase difference threshold to the fourth phase difference threshold when the third count value reaches the second count threshold and the second detection circuit 100 still does not output the third level signal, and the fourth phase difference threshold is greater than the third phase difference threshold. The second control circuit 110 is respectively connected to the third counter 60 and the second detection circuit 100.

[0204] The second initial value is the minimum count value of the third counter 60. Exemplarily, the second initial value is 0. The second initial value may be the same as the first initial value or different from the first initial value. The embodiment of the present application does not limit the manner of adjusting the third phase difference threshold to the fourth phase difference threshold, as long as it is ensured that the fourth phase difference threshold is greater than the third phase difference threshold. Exemplarily, a fixed value is added to the third phase difference threshold to obtain the fourth phase difference threshold. Exemplarily, the total number of times when the count value of the third counter 60 reaches the second count threshold and the second detection circuit 100 still does not output the third level signal is statistically calculated. The total number is positively correlated with the phase difference threshold, and the phase difference threshold corresponding to the total number is used as the fourth phase difference threshold.

[0205] After resetting the third count value to the second initial value and determining the fourth phase difference threshold, the third counter 60, the second delay module 21, the third delay module 70, the fourth delay module 80, the fifth delay module 90, and the second detection circuit 100 repeat the process of determining the third degree value based on the second initial value and the fourth phase difference threshold.

[0206] The embodiment of the present application adds a function of automatic threshold adjustment. When the third counter 60 finishes traversing (that is, the third count value reaches the second counting threshold) but the second detection circuit 100 still does not output the third level signal, the decision accuracy is automatically reduced (that is, the phase difference threshold on which the determination of whether to output the third level signal depends is increased), and the process of determining the third degree is repeatedly executed. In this way, the influence of signal fluctuations in different temperature process environments on the process of determining the third degree can be overcome.

[0207] In a possible implementation manner, refer to Figure 12 , the second control circuit 110 includes a third logic sub - circuit 111, a fourth counter 112, and a fourth logic sub - circuit 113. The third logic sub - circuit 111 is configured to output a fourth level signal when the third count value reaches the second counting threshold and the second detection circuit 100 still does not output the third level signal. The fourth counter 112 is configured to increase the count value based on the fourth level signal to obtain a fourth count value; the fourth phase difference threshold is the phase difference threshold corresponding to the fourth count value. The fourth logic sub - circuit 113 is configured to reset the third count value to the second initial value based on the fourth level signal.

[0208] The third logic sub - circuit 111 is respectively connected to the fourth counter 112 and the fourth logic sub - circuit 113. When the third count value reaches the second counting threshold and the second detection circuit 100 still does not output the third level signal, the third logic sub - circuit 111 outputs the fourth level signal. The fourth level signal can be any level signal, such as a high - level signal, a low - level signal, etc. After the third logic sub - circuit 111 outputs the fourth level signal, the fourth counter 112 and the fourth logic sub - circuit 113 can receive the fourth level signal.

[0209] After receiving the fourth level signal, the fourth counter 112 increases the count value based on the fourth level signal. In other words, each time the fourth counter 112 receives the fourth level signal, the existing count value is increased by 1. Different count values of the fourth counter 112 correspond to different phase difference thresholds. Exemplarily, the count value and the phase difference threshold are in a positive correlation relationship, that is, the larger the count value, the larger the phase difference threshold corresponding to the count value. Based on this, as the count value of the fourth counter 112 continuously increases, the phase difference threshold on which the second detection circuit 100 determines whether to output the third level signal also continuously increases. The correspondence between the count value and the phase difference threshold can be set according to experience or flexibly adjusted according to the application scenario, as long as the count value and the phase difference threshold are in a positive correlation relationship. In the embodiment of the present application, the count value obtained after the fourth counter 112 increases the count value based on the fourth level signal is referred to as the fourth count value, and the fourth phase difference threshold refers to the phase difference threshold corresponding to the fourth count value.

[0210] Exemplarily, the fourth counter 112 is connected to the second detection circuit 100. The second detection circuit 100 can determine a fourth phase difference threshold according to the fourth count value, and based on the determined fourth phase difference threshold, determine whether to output a third level signal.

[0211] After receiving the fourth level signal, the fourth logic sub-circuit 113 resets the third count value to a second initial value. Exemplarily, the fourth logic sub-circuit 113 is connected to the third counter 60. After receiving the fourth level signal, the fourth logic sub-circuit 113 transmits a reset signal to the third counter 60, and this reset signal is used to instruct the third counter 60 to reset the third count value to the second initial value. The form of the reset signal is not limited in the embodiments of the present application, as long as the third counter 60 can recognize it.

[0212] Exemplarily, when the third count value does not reach the second count threshold, or when the second detection circuit 100 outputs a third level signal, the third logic sub-circuit 111 does not output a fourth level signal, the fourth counter 112 keeps the count value unchanged, and the fourth logic sub-circuit 113 does not reset the count value of the third counter 60.

[0213] For the specific structures of the third logic sub-circuit 111, the fourth counter 112, and the fourth logic sub-circuit 113, reference can be made to Figure 7 the specific structures of the first logic sub-circuit 51, the second counter 52, and the second logic sub-circuit 53 described therein, which will not be elaborated here.

[0214] It should be noted that the above is only described by taking the third phase difference threshold being less than the second maximum phase difference threshold as an example. The second maximum phase difference threshold refers to the maximum phase difference threshold on which the determination of whether to output a third level signal depends. The second maximum phase difference threshold can be set according to experience or flexibly adjusted according to the application scenario. When the third phase difference threshold is equal to the second maximum phase difference threshold, and when the third count value reaches the second count threshold and the second detection circuit 100 still does not output a third level signal, it indicates that the process of determining the third degree fails, that is, it indicates that the duty cycle of the second target signal cannot satisfy the second similarity condition with the reference duty cycle.

[0215] It should be noted that different components (such as circuits, sub-circuits, modules, counters, logic gates, etc.) in the embodiments of the present application can be independent of each other or integrated in the same hardware, and the embodiments of the present application do not limit this.

[0216] Exemplarily, the structure of the signal processing circuit can be as Figure 13As shown. The signal processing circuit includes a processing circuit 10, a frequency multiplier 20, a first counter 30, a first detection circuit 40, a first control circuit 50, a third counter 60, a third delay module 70, a fourth delay module 80, a fifth delay module 90, a second detection circuit 100, and a second control circuit 110. Among them, the processing circuit 10 includes a first determination sub-circuit 11, a first delay module 12, and a NOR gate 13; the frequency multiplier 20 includes a second delay module 21 and an exclusive-OR gate 22. It should be noted that Figure 13 only a partial structure of the first determination sub-circuit 11 is shown. In addition to Figure 12 the structure shown in, the first determination sub-circuit may further include a duty cycle detection module, a first switch, a second switch, etc. It should be further noted that Figure 13 in the structure shown in, the NOR gate 13 is connected to the second delay module 21, the first detection circuit 40, the second detection circuit 100, and the exclusive-OR gate 22 through a transmission gate, but the embodiments of the present application are not limited thereto. In some embodiments, the NOR gate 13 may also be directly connected to the second delay module 21, the first detection circuit 40, the second detection circuit 100, and the exclusive-OR gate 22.

[0217] In Figure 13 , the signal processing circuit further includes a selection bypass, and the selection bypass includes two transmission gates. One of the transmission gates is used to transmit the original signal (IN) to the first determination sub-circuit 11, and the other transmission gate is used to transmit the original signal (IN) to the exclusive-OR gate 22. This selection bypass can directly transmit the original signal (IN) to the exclusive-OR gate 22 when the processing circuit 10 fails.

[0218] Based on Figure 13 the signal processing process of the shown signal processing circuit can be divided into three stages. The first stage (Stage1) is used to determine the third degree; the second stage (Stage2) is used to determine the first degree; the third stage (Stage3) is used to obtain the first target signal and the second target signal based on the third degree and the first degree. In some embodiments, Stage1 and Stage2 can be referred to as the calibration process, and Stage3 can be referred to as the processing process. Next, the working processes of the three stages will be introduced.

[0219] When initially powered on, the default phase delay degrees of the second delay module 21, the third delay module 70, the fourth delay module 80, and the fifth delay module 90 are relatively small. Therefore, the phase difference between adjacent signals among the A to E signals is relatively small. Among them, the A signal represents the signal output by the NOR gate 13 (and also represents the signal input to the second delay module 21), the B signal represents the signal output by the second delay module 21, the C signal represents the signal output by the third delay module 70, the D signal represents the signal output by the fourth delay module 80, and the E signal represents the signal output by the fifth delay module 90.

[0220] The working processes of Stage1 and Stage2 can be as Figure 14 shown. First, execute Stage1. In Stage1, the third counter 60 continuously increases its count value, so that the degrees of phase delay of the signals input to the second delay module 21, the third delay module 70, the fourth delay module 80, and the fifth delay module 90 continuously increase. At the same time, the second detection circuit 100 discriminates the phase difference between the A signal and the E signal. When the phase difference between the A signal and the E signal is greater than the third phase difference threshold (TH1), it is judged whether the count value (the third count value) of the third counter 60 reaches the second count threshold. If the third count value does not reach the second count threshold, the third counter 60 continues to increase its count value. If the third count value reaches the second count threshold, the second control circuit 110 increases the third phase difference threshold (TH1) to the fourth phase difference threshold (TH1 + 1) and clears the third count value. Then, the process of the third counter 60 continuously increasing the count and the second detection circuit 100 continuously detecting is executed again.

[0221] When the phase difference between the A signal and the E signal is not greater than the third phase difference threshold (TH1), the second detection circuit 100 outputs a third-level signal, and the degree corresponding to the current count value of the third counter 60 is used as the third degree. At this time, the phase difference between adjacent signals among the A to E signals is 90 degrees, or approximately 90 degrees. Thus, Stage1 ends (over1).

[0222] After Stage1 ends, the first determination sub-circuit 11 determines whether the duty cycle of the original signal (IN) is greater than 50%. When the duty cycle of the original signal (IN) is greater than 50%, the original signal (IN) is inverted so that the A signal is determined based on the signal obtained after the inversion process; when the duty cycle of the original signal (IN) is not greater than 50%, no processing is performed on the original signal (IN) so that the A signal is directly determined based on the original signal (IN).

[0223] Afterwards, it enters Stage 2. In Stage 2, the first counter 30 continuously increases the count value, so that the degree of delay of the phase of the input signal by the first delay module 12 continues to increase. At the same time, the first detection circuit 40 judges the phase difference between the different clock edges of the A signal and the C signal. When the phase difference between the different clock edges of the A signal and the C signal is greater than the first phase difference threshold (TH2), it is determined whether the count value (first count value) of the first counter 30 reaches the first count threshold. If the first count value does not reach the first count threshold, the first counter 30 continues to increase the count value. If the first count value reaches the first count threshold, the first control circuit 50 increases the first phase difference threshold (TH2) to the second phase difference threshold (TH2+1) and clears the first count value. Afterwards, the process of the first counter 30 continuously increasing the count and the first detection circuit 40 continuously detecting is executed again.

[0224] When the phase difference between the different clock edges of signal A and signal C is no greater than the first phase difference threshold (TH2), the first detection circuit 40 outputs a first level signal and uses the degree corresponding to the current count value of the first counter 30 as the first degree. At this point, Stage 2 ends (over2).

[0225] When the phase difference between different clock edges of signal A and signal C is not greater than the first phase difference threshold (TH2), the duty cycle of signal A is 50% or close to 50%. Because if the duty cycle of signal A is not 50% or close to 50%, the different clock edges of signal A and signal C cannot be aligned (alignment means that the phase difference is not greater than the first phase difference threshold). Based on this, an XOR operation is finally performed on signal A and signal B with a phase delay of 90 degrees (or approximately 90 degrees), and the duty cycle of the output signal is 50% or close to 50%.

[0226] After Stage 2 ends, the additional circuits are shut down to reduce power consumption. Exemplarily, the additional circuits refer to circuits other than those participating in Stage 3. For example, the additional circuits include a first counter 30, a first detection circuit 40, a first control circuit 50, a third delay module 70, a fourth delay module 80, a fifth delay module 90, a third counter 60, a second detection circuit 100, and a second control circuit 110.

[0227] After turning off the additional circuit, enter Stage3. In Stage3, when the duty cycle of the original signal is greater than the reference duty cycle, the first determination sub-circuit 11 uses the inverted signal of the original signal as the first input signal; when the duty cycle of the original signal is not greater than the reference duty cycle, the original signal is used as the first input signal. The first delay module 12 delays the phase of the first input signal according to the first degree to obtain the first output signal. The NOR gate 13 performs a NOR operation on the first input signal and the first output signal to obtain the first target signal. The second delay module 21 delays the phase of the first target signal according to the third degree to obtain the third target signal. The XOR gate 22 performs an XOR operation on the first target signal and the third target signal to obtain the second target signal.

[0228] Exemplarily, during the processes of Stage1 and Stage2, the timing diagrams of signals A, B, C, D, and E are as Figure 15 shown. According to Figure 15 it can be known that the goal of Stage1 is to align signal A with signal E so that the phase difference between adjacent signals among signals A, B, C, D, and E is 90 degrees. The goal of Stage2 is to align the different clock edges of signal A and signal C on the basis that the phase difference between adjacent signals among signals A, B, C, D, and E is 90 degrees.

[0229] Exemplarily, the simulation results of the calibration process (Stage1 and Stage2) of the signal processing circuit provided by the embodiments of the present application are as Figure 16 shown. According to Figure 16 it can be seen that after determining the third degree, the Stage1 end signal (stage1over) automatically rises, and at the same time Stage2 starts, that is, the Stage2 start signal (en of stage2) automatically rises. The calibration times (counter1) of the phase delay degrees of the final second delay module 21, third delay module 70, fourth delay module 80, and fifth delay module 90 are 311, and the calibration times (counter2) of the phase delay degree of the first delay module 12 are 21.

[0230] The simulation results of the processing results of the signal processing circuit provided by the embodiments of the present application are as Figure 17 shown. Figure 17 In curve 1 is the duty cycle of the signal input to the frequency doubler 20. According to curve 1, it can be seen that through Stage1 and Stage2, the duty cycle of the signal input to the frequency doubler 20 is successfully adjusted from 54% to 50.0689%; Figure 17The curve 2 in [it] is the frequency of the signal output by the frequency doubler 20. From curve 2, it can be seen that the signal output by the frequency doubler 20 is successfully frequency-doubled to twice the frequency of the signal input to the frequency doubler 20, and the frequency stability is good; Figure 17 The curve 3 in [it] is the duty cycle of the signal output by the frequency doubler 20. From curve 3, it can be seen that through Stage1 and Stage2, the duty cycle of the signal output by the frequency doubler 20 is successfully adjusted from 0% to 50%.

[0231] From Figure 16 and Figure 17 it can be seen that the signal processing circuit designed in the embodiment of the present application can not only automatically adjust the duty cycle of the signal input to the frequency doubler 20, but also automatically adjust the duty cycle of the signal output by the frequency doubler 20, and has good application prospects.

[0232] The signal processing circuit provided by the embodiment of the present application can be regarded as a duty cycle adaptive adjustment circuit of a frequency doubler (Doubler), which can automatically calibrate the duty cycles of the input and output signals of the Doubler. The signal processing circuit provided by the embodiment of the present application can combine the characteristics of a wide adjustment range of digital calibration and high calibration accuracy of analog calibration to realize a Doubler duty cycle adaptive adjustment circuit with a large adjustment range and high adjustment accuracy, and can solve the problem that when the duty cycles of the input and output signals of the Doubler in the PLL circuit deviate from 50%, it has a great impact on the in-band phase noise and output spurs of the PLL circuit.

[0233] In the embodiment of the present application, the duty cycle of the signal (the first target signal) input to the frequency doubler and the duty cycle of the signal (the second target signal) output by the frequency doubler are both close to the reference duty cycle, which can not only achieve the goal of making the duty cycle of the signal output by the frequency doubler close to the reference duty cycle, but also reduce the fluctuation of the signal output by the frequency doubler by making the duty cycle of the signal input to the frequency doubler close to the reference duty cycle, thereby improving the stability of the signal output by the frequency doubler.

[0234] The embodiment of the present application also provides a signal processing method, which can be applied to the signal processing circuit introduced in the above embodiment. Refer to Figure 18 and

[0235] the signal processing method includes the following steps 1801 and 1802.

[0236] Step 1801: Process the original signal to obtain a first target signal, and the duty cycle of the first target signal satisfies a first similarity condition with the reference duty cycle.In a possible implementation, processing the original signal to obtain a first target signal includes: when the duty cycle of the original signal is greater than the reference duty cycle, using the inverted signal of the original signal as the first input signal; when the duty cycle of the original signal is not greater than the reference duty cycle, using the original signal as the first input signal; delaying the phase of the first input signal according to a first degree to obtain a first output signal; performing a NOR operation on the first input signal and the first output signal to obtain a first target signal; wherein, the first degree is used to make the duty cycle of the first target signal satisfy a first similarity condition with the reference duty cycle.

[0237] In a possible implementation, before delaying the phase of the first input signal according to the first degree to obtain the first output signal, it further includes: in response to a first enable signal, increasing a count value based on the clock edge of a first reference signal to obtain a first count value, the first reference signal being determined based on the original signal; delaying the phase of the first input signal according to the degree corresponding to the first count value to obtain an intermediate signal; performing a NOR operation on the first input signal and the intermediate signal to obtain a first processed signal; when the phase difference between the first clock edge of the first processed signal and the second clock edge of a second processed signal is not greater than a first phase difference threshold, outputting a first level signal, the first level signal being used to indicate using the degree corresponding to the first count value as the first degree; wherein, the directions of the first clock edge and the second clock edge are opposite; the phase difference between the first clock edge and the second clock edge not being greater than the first phase difference threshold is used to indicate that the duty cycle of the first processed signal satisfies a first similarity condition with the reference duty cycle; the second processed signal is obtained by delaying the phase of the first processed signal by a second degree, and the difference between the second degree and 180 degrees is not greater than a first difference threshold.

[0238] In a possible implementation, the method further includes: when the first count value reaches a first count threshold and the first level signal has not been output yet, resetting the first count value to a first initial value and adjusting the first phase difference threshold to a second phase difference threshold, the second phase difference threshold being greater than the first phase difference threshold.

[0239] In a possible implementation, when the first count value reaches the first count threshold and the first level signal has not been output yet, resetting the first count value to the first initial value and adjusting the first phase difference threshold to the second phase difference threshold includes: when the first count value reaches the first count threshold and the first level signal has not been output yet, outputting a second level signal; increasing the count value based on the second level signal to obtain a second count value; the second phase difference threshold being the phase difference threshold corresponding to the second count value; based on the second level signal, resetting the first count value to the first initial value.

[0240] Step 1802: Perform a frequency doubling operation on the first target signal to obtain a second target signal, and the duty cycle of the second target signal satisfies a second similarity condition with the reference duty cycle.

[0241] In a possible implementation manner, performing a frequency doubling operation on the first target signal to obtain a second target signal includes: delaying the phase of the first target signal according to a third degree to obtain a third target signal; the difference between the third degree and 90 degrees is not greater than a second difference threshold; performing an exclusive OR operation on the first target signal and the third target signal to obtain the second target signal.

[0242] In a possible implementation manner, before delaying the phase of the first target signal according to the third degree to obtain a third target signal, it further includes: in response to a second enable signal, increasing a count value based on the clock edge of a second reference signal to obtain a third count value, where the second reference signal is determined based on the original signal; delaying the phase of the second input signal according to the degree corresponding to the third count value to obtain a second output signal, where the second input signal is determined based on the original signal; delaying the phase of the second output signal according to the degree corresponding to the third count value to obtain a third output signal; delaying the phase of the third output signal according to the degree corresponding to the third count value to obtain a fourth output signal; delaying the phase of the fourth output signal according to the degree corresponding to the third count value to obtain a fifth output signal; when the phase difference between the second input signal and the fifth output signal is not greater than a third phase difference threshold, output a third level signal, and the third level signal is used to indicate that the degree corresponding to the third count value is used as the third degree.

[0243] In a possible implementation manner, the method further includes: when the third count value reaches a second count threshold and the third level signal has not been output yet, resetting the third count value to a second initial value and adjusting the third phase difference threshold to a fourth phase difference threshold, where the fourth phase difference threshold is greater than the third phase difference threshold.

[0244] In a possible implementation manner, when the third count value reaches a second count threshold and the third level signal has not been output yet, resetting the third count value to a second initial value and adjusting the third phase difference threshold to a fourth phase difference threshold includes: when the third count value reaches a second count threshold and the third level signal has not been output yet, outputting a fourth level signal; increasing a count value based on the fourth level signal to obtain a fourth count value; the fourth phase difference threshold is the phase difference threshold corresponding to the fourth count value; based on the fourth level signal, resetting the third count value to the second initial value.

[0245] The description of the embodiments of the above signal processing method has beneficial effects similar to those of the embodiments of the above signal processing circuit. For the technical details not disclosed in the embodiments of the signal processing method, please refer to the description of the embodiments of the signal processing circuit of this application for understanding.

[0246] See Figure 19 In one embodiment, a chip is further provided, which includes the signal processing circuit in any of the above possible implementation manners.

[0247] Exemplarily, a phase-locked loop circuit is integrated in the chip. The phase-locked loop circuit includes the signal processing circuit. The signal processing circuit is connected to a phase detector in the phase-locked loop circuit. The signal processing circuit multiplies the frequency of the signal input to the phase-locked loop circuit, and then inputs the frequency-multiplied signal to the phase detector for subsequent operations. Specifically, the process of the signal processing circuit multiplying the frequency of the signal input to the phase-locked loop circuit includes: a processing circuit in the signal processing circuit processes the signal input to the phase-locked loop circuit to obtain a first target signal, and the duty cycle of the first target signal satisfies a first similarity condition with a reference duty cycle; a frequency multiplier in the signal processing circuit performs a frequency multiplication operation on the first target signal to obtain a second target signal, and the duty cycle of the second target signal satisfies a second similarity condition with the reference duty cycle. The second target signal is the frequency-multiplied signal.

[0248] See Figure 20 In one embodiment, an electronic device is further provided, which includes the above chip.

[0249] Exemplarily, the electronic device may be a smart phone, a tablet computer, a player, a notebook computer, a desktop computer, etc.

[0250] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with the relevant laws, regulations and standards of relevant countries and regions.

[0251] The terms "first", "second", etc. in this application are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of this application described here can be implemented in an order different from those illustrated or described here. The implementation manners described in the above exemplary embodiments do not represent all implementation manners consistent with this application. On the contrary, they are only examples of devices and methods consistent with some aspects of this application.

[0252] It should be understood that the "plurality" mentioned herein refers to two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0253] The above are only exemplary embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application shall be included within the protection scope of the present application.

Claims

1. A signal processing circuit, characterized in that, The signal processing circuit includes a processing circuit and a frequency multiplier; The processing circuit is configured to process an original signal to obtain a first target signal, and a duty cycle of the first target signal satisfies a first similarity condition with a reference duty cycle; The frequency multiplier is configured to perform a frequency multiplication operation on the first target signal to obtain a second target signal, and a duty cycle of the second target signal satisfies a second similarity condition with the reference duty cycle.

2. The circuit according to claim 1, wherein The processing circuit includes a first determination sub-circuit, a first delay module, and a NOR gate; The first determination sub-circuit is configured to use an inverted signal of the original signal as a first input signal when a duty cycle of the original signal is greater than the reference duty cycle; use the original signal as the first input signal when the duty cycle of the original signal is not greater than the reference duty cycle; The first delay module is configured to delay a phase of the first input signal according to a first degree to obtain a first output signal; The NOR gate is configured to perform a NOR operation on the first input signal and the first output signal to obtain the first target signal; wherein, the first degree is used to make the duty cycle of the first target signal satisfy the first similarity condition with the reference duty cycle.

3. The circuit according to claim 2, wherein, The signal processing circuit further includes a first counter and a first detection circuit; The first counter is configured to increase a count value based on a clock edge of a first reference signal in response to a first enable signal to obtain a first count value, and the first reference signal is determined based on the original signal; The first delay module is further configured to delay a phase of the first input signal according to a degree corresponding to the first count value to obtain an intermediate signal; The NOR gate is further configured to perform a NOR operation on the first input signal and the intermediate signal to obtain a first processed signal; The first detection circuit is configured to output a first level signal when a phase difference between a first clock edge of the first processed signal and a second clock edge of a second processed signal is not greater than a first phase difference threshold, and the first level signal is used to indicate using the degree corresponding to the first count value as the first degree; wherein, directions of the first clock edge and the second clock edge are opposite; the phase difference between the first clock edge and the second clock edge not being greater than the first phase difference threshold is used to indicate that a duty cycle of the first processed signal satisfies the first similarity condition with the reference duty cycle; the second processed signal is obtained by delaying a phase of the first processed signal by a second degree, and a difference between the second degree and 180 degrees is not greater than a first difference threshold.

4. The circuit according to claim 3, characterized in that, The signal processing circuit further includes a first control circuit; The first control circuit is configured to reset the first count value to a first initial value and adjust the first phase difference threshold to a second phase difference threshold greater than the first phase difference threshold when the first count value reaches a first count threshold and the first detection circuit still does not output the first level signal.

5. The circuit according to claim 4, wherein The first control circuit includes a first logic sub-circuit, a second counter, and a second logic sub-circuit; The first logic sub - circuit is configured to output a second level signal when the first count value reaches the first count threshold and the first detection circuit still has not output the first level signal; The second counter is configured to increase the count value based on the second level signal to obtain a second count value; The second phase - difference threshold is the phase - difference threshold corresponding to the second count value; The second logic sub - circuit is configured to reset the first count value to the first initial value based on the second level signal.

6. The circuit according to any one of claims 1 to 5, characterized in that, The frequency multiplier includes a second delay module and an exclusive - OR gate; The second delay module is configured to delay the phase of the first target signal according to a third degree, and obtain a third target signal; the difference between the third degree and 90 degrees is not greater than the second difference threshold; The exclusive - OR gate is configured to perform an exclusive - OR operation on the first target signal and the third target signal to obtain the second target signal.

7. The circuit according to claim 6, characterized in that, The signal processing circuit further includes a third counter, a third delay module, a fourth delay module, a fifth delay module, and a second detection circuit; The third counter is configured to, in response to a second enable signal, increase the count value based on the clock edge of a second reference signal to obtain a third count value, and the second reference signal is determined based on the original signal; The second delay module is further configured to delay the phase of a second input signal according to the degree corresponding to the third count value to obtain a second output signal, and the second input signal is determined based on the original signal; The third delay module is configured to delay the phase of the second output signal according to the degree corresponding to the third count value to obtain a third output signal; The fourth delay module is configured to delay the phase of the third output signal according to the degree corresponding to the third count value to obtain a fourth output signal; The fifth delay module is configured to delay the phase of the fourth output signal according to the degree corresponding to the third count value to obtain a fifth output signal; The second detection circuit is configured to output a third level signal when the phase difference between the second input signal and the fifth output signal is not greater than a third phase - difference threshold, and the third level signal is used to indicate using the degree corresponding to the third count value as the third degree.

8. The circuit according to claim 7, wherein The signal processing circuit further includes a second control circuit; The second control circuit is configured to, when the third count value reaches a second count threshold and the second detection circuit still has not output the third level signal, reset the third count value to a second initial value, and adjust the third phase - difference threshold to a fourth phase - difference threshold, and the fourth phase - difference threshold is greater than the third phase - difference threshold.

9. The circuit according to claim 8, characterized in that, The second control circuit includes a third logic sub - circuit, a fourth counter, and a fourth logic sub - circuit; The third logic sub - circuit is configured to output a fourth level signal when the third count value reaches the second count threshold and the second detection circuit still has not output the third level signal; The fourth counter is configured to increase the count value based on the fourth level signal to obtain a fourth count value; The fourth phase difference threshold is the phase difference threshold corresponding to the fourth count value; The fourth logic sub - circuit is configured to reset the third count value to the second initial value based on the fourth level signal.

10. A signal processing method, characterized in that, The method includes: Processing the original signal to obtain a first target signal, where the duty cycle of the first target signal satisfies a first similarity condition with the reference duty cycle; Performing a frequency - doubling operation on the first target signal to obtain a second target signal, where the duty cycle of the second target signal satisfies a second similarity condition with the reference duty cycle.

11. The method according to claim 10, characterized in that, Processing the original signal to obtain a first target signal includes: When the duty cycle of the original signal is greater than the reference duty cycle, using the inverted signal of the original signal as the first input signal; when the duty cycle of the original signal is not greater than the reference duty cycle, using the original signal as the first input signal; Delaying the phase of the first input signal according to a first degree to obtain a first output signal; Performing a NOR operation on the first input signal and the first output signal to obtain the first target signal; Wherein, the first degree is used to make the duty cycle of the first target signal satisfy the first similarity condition with the reference duty cycle.

12. The method according to claim 11, wherein Before delaying the phase of the first input signal according to the first degree to obtain the first output signal, it further includes: In response to a first enable signal, increasing a count value based on the clock edge of a first reference signal to obtain a first count value, where the first reference signal is determined based on the original signal; Delaying the phase of the first input signal according to the degree corresponding to the first count value to obtain an intermediate signal; Performing a NOR operation on the first input signal and the intermediate signal to obtain a first processing signal; When the phase difference between the first clock edge of the first processing signal and the second clock edge of the second processing signal is not greater than a first phase difference threshold, outputting a first level signal, where the first level signal is used to indicate using the degree corresponding to the first count value as the first degree; Wherein, the directions of the first clock edge and the second clock edge are opposite; the phase difference between the first clock edge and the second clock edge not being greater than the first phase difference threshold is used to indicate that the duty cycle of the first processing signal satisfies the first similarity condition with the reference duty cycle; the second processing signal is obtained by delaying the phase of the first processing signal by a second degree, and the difference between the second degree and 180 degrees is not greater than a first difference threshold.

13. The method according to claim 12, wherein The method further includes: When the first count value reaches a first count threshold and the first level signal has not been output yet, resetting the first count value to a first initial value and adjusting the first phase difference threshold to a second phase difference threshold, where the second phase difference threshold is greater than the first phase difference threshold.

14. The method according to claim 13, wherein When the first count value reaches a first count threshold and the first level signal has not been output yet, resetting the first count value to a first initial value and adjusting the first phase difference threshold to a second phase difference threshold includes: In the case where the first count value reaches the first count threshold and the first level signal has not been output yet, output a second level signal; Based on the second level signal, increase the count value to obtain a second count value; the second phase difference threshold is the phase difference threshold corresponding to the second count value; Based on the second level signal, reset the first count value to the first initial value.

15. The method according to any one of claims 10 to 14, characterized in that, The operation of doubling the frequency of the first target signal to obtain a second target signal includes: Delay the phase of the first target signal according to a third degree to obtain a third target signal; the difference between the third degree and 90 degrees is not greater than the second difference threshold; Perform an exclusive OR operation on the first target signal and the third target signal to obtain the second target signal.

16. The method according to claim 15, wherein Before delaying the phase of the first target signal according to the third degree to obtain a third target signal, it further includes: In response to a second enable signal, increase the count value based on the clock edge of a second reference signal to obtain a third count value, and the second reference signal is determined based on the original signal; Delay the phase of a second input signal according to the degree corresponding to the third count value to obtain a second output signal, and the second input signal is determined based on the original signal; Delay the phase of the second output signal according to the degree corresponding to the third count value to obtain a third output signal; Delay the phase of the third output signal according to the degree corresponding to the third count value to obtain a fourth output signal; Delay the phase of the fourth output signal according to the degree corresponding to the third count value to obtain a fifth output signal; In the case where the phase difference between the second input signal and the fifth output signal is not greater than a third phase difference threshold, output a third level signal, and the third level signal is used to indicate that the degree corresponding to the third count value is used as the third degree.

17. The method according to claim 16, wherein The method further includes: In the case where the third count value reaches a second count threshold and the third level signal has not been output yet, reset the third count value to a second initial value and adjust the third phase difference threshold to a fourth phase difference threshold, and the fourth phase difference threshold is greater than the third phase difference threshold.

18. The method according to claim 17, wherein The step of resetting the third count value to the second initial value and adjusting the third phase difference threshold to the fourth phase difference threshold in the case where the third count value reaches the second count threshold and the third level signal has not been output yet includes: In the case where the third count value reaches the second count threshold and the third level signal has not been output yet, output a fourth level signal; Based on the fourth level signal, increase the count value to obtain a fourth count value; the fourth phase difference threshold is the phase difference threshold corresponding to the fourth count value; Based on the fourth level signal, reset the third count value to the second initial value.

19. A chip, characterized in that, The chip includes the signal processing circuit according to any one of claims 1 to 9.

20. An electronic device, characterized in that, The electronic device includes the chip according to claim 19.

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