Virtual link data transmission method, electronic equipment and storage medium

Abstract

The invention provides a virtual link data transmission method, electronic equipment and a storage medium, and the method comprises the steps: determining an array index of a virtual link according to a bandwidth distribution interval of the virtual link; determining a timing trigger interval and a counting initial value corresponding to each virtual link according to the bandwidth allocation interval of each virtual link; determining a link map corresponding to each array index according to the array index of each virtual link; according to the timing trigger interval and the counting initial value corresponding to each virtual link, polling the link atlas corresponding to each array index to obtain to-be-sent data of the virtual links corresponding to the link atlas meeting the data sending rule; and sending the acquired to-be-sent data of any virtual link to the network card corresponding to the virtual link, so as to increase the number of the virtual links from the software level, and enable the maximum support number of the virtual links to be far greater than the number of the virtual links communicated by mainstream hardware when the AFDX system network runs.

Description

Background Art

[0002] A full-motion simulator is an advanced flight training device that helps pilots improve their flying skills by simulating the actual flight environment. The ARINC664 interface board of the full-motion simulator is a bridge connecting the simulator and the computer, mainly responsible for processing the AFDX (Avionics Full-Duplex Switched Ethernet) bus signals from the simulator, and then realizing operations such as data transceiver, recording and analysis of the simulator. The AFDX system network consists of an end system (ES), an AFDX switch, and a virtual link (VL). Its core is a communication mechanism based on virtual links. A virtual link is a conceptual communication object that defines a logically one-way connection from a source end system to one or more destination end systems. During the communication process of the ARINC664 interface card of the full-motion simulator, the number of virtual links is a key parameter of the AFDX network architecture. More virtual links mean that the full-motion simulator has stronger auxiliary and simulation capabilities. Increasing the order of magnitude of virtual links can enable the full-motion simulator to support the interconnection of more terminal devices, accommodate more complex avionics system architectures, improve the flexibility and scalability of communication, optimize bandwidth utilization, and enhance system reliability. It is an inevitable requirement to adapt to the development of modern and future avionics. However, the number of virtual links of the existing ARINC664 interface board of the full-motion simulator cannot meet this quantity requirement. Summary of the Invention

[0003] For the above technical problems, the technical solution adopted by the present invention is as follows: According to one aspect of the present application, a virtual link data transmission method is provided, including the following steps: Step S100: Determine the array index corresponding to each virtual link according to the bandwidth allocation interval of each virtual link; Step S200: Determine the timing trigger interval and the initial count value corresponding to each virtual link according to the bandwidth allocation interval of each virtual link; the initial count value is the initial value of the counter corresponding to the virtual link; Step S300: Determine the link map corresponding to each array index according to the array index corresponding to each virtual link; each node in the link map corresponds to a virtual link; Step S400: Poll the link map corresponding to each array index according to the timing trigger interval and the initial count value corresponding to each virtual link to obtain the data to be sent of several virtual links corresponding to the link map that meets the data sending rule; Step S500: Send the data to be sent of any virtual link obtained to the network card corresponding to the virtual link.

[0004] In an exemplary embodiment of the present application, step S100 includes: Step S110, obtaining the bandwidth allocation interval of each virtual link to obtain a bandwidth allocation interval list A = (A1, A2,..., A i ,..., A j ); where i = 1, 2,..., j; j is the number of virtual links; A i is the bandwidth allocation interval of the i-th virtual link; Step S120, traversing the bandwidth allocation interval list A. If 0 < A i ≤ 1, then determine A i as 1, and determine 1 as the array index corresponding to the i-th virtual link; If 2 n-1 < A i ≤ 2 n , then determine A i as 2 n , and determine 2 n as the array index corresponding to the i-th virtual link; where n is an integer greater than or equal to 1.

[0005] In an exemplary embodiment of the present application, step S200 includes: Step S210, determining MIN(A) as the timing trigger interval B; where MIN() is a preset minimum value determination function; Step S220, determining the initial count value C i corresponding to the i-th virtual link = (A i / B) - 1.

[0006] In an exemplary embodiment of the present application, step S300 includes: Step S310, traversing the array indexes corresponding to several virtual links, and determining the virtual links with the same array index as the same array index group to obtain several array index groups; Step S320, obtaining the link identifiers corresponding to several virtual links in each array index group to obtain a link identifier list set D = (D1, D2,..., D p ,..., D q ); where p = 1, 2,..., q; q is the number of array index groups; D p is the link identifier list corresponding to the p-th array index group; D p = (D p1 , D p2 ,..., D pe ,..., Dpf(p) ); where e = 1, 2, ..., f(p); f(p) is the number of virtual links in the p-th array index group; D pe is the link identifier corresponding to the e-th virtual link in the p-th array index group; Step S330, obtain the priority corresponding to each virtual link in the p-th array index group to obtain the priority list E corresponding to the p-th array index group p =(E p1 , E p2 , ..., E pe , ..., E pf(p) ); where E pe is the priority corresponding to the e-th virtual link in the p-th array index group; Step S340, sort the priority list E corresponding to the p-th array index group in descending order of priority to obtain the sorted priority list F corresponding to the p-th array index group p =(F p , F p1 , ..., F p2 , ..., F pe , ..., F pf(p) ); where F pe is the e-th priority determined after priority sorting of the p-th array index group; Step S350, place the f(p) link identifiers corresponding to F p1 , F p2 , ..., F pe , ..., F pf(p) in the same balanced binary search tree in descending order of node height to obtain the initial link node tree corresponding to the p-th array index group; Step S360, perform height balancing processing on the initial link node tree corresponding to the p-th array index group to obtain the link map corresponding to the p-th array index group.

[0007] In an exemplary embodiment of the present application, step S400 includes: Step S410, obtain the initial count value of the virtual links in each array index group every timing trigger interval B to obtain the initial count value list G = (G1, G2, ..., G p , ..., G q ); where G p is the initial count value of the virtual links in the p-th array index group; Step S420, if G pIf it is equal to 0, then perform an in-order traversal on several nodes in the link graph corresponding to the p-th array index group, and sequentially obtain the data to be sent of several virtual links corresponding to the link graph of the p-th array index group.

[0008] In an exemplary embodiment of the present application, step S420 further includes: Step S421, if G p > 0, then set G p = G p -1, and return to step S410.

[0009] In an exemplary embodiment of the present application, step S420 further includes: Step S422, if each count initial value in the count initial value list G is zero, then return to step S220.

[0010] In an exemplary embodiment of the present application, step S500 includes: Step S510, when obtaining the data to be sent of any virtual link, obtain the network card identifier corresponding to this virtual link; Step S520, send the data to be sent of this virtual link to the network card corresponding to the network card identifier of this virtual link.

[0011] According to one aspect of the present application, there is provided a non-transitory computer-readable storage medium, in which at least one instruction or at least one segment of program is stored, and the at least one instruction or the at least one segment of program is loaded and executed by a processor to implement the foregoing virtual link data transmission method.

[0012] According to one aspect of the present application, there is provided an electronic device, including a processor and the foregoing non-transitory computer-readable storage medium.

[0013] The present invention has at least the following beneficial effects: The virtual link data transmission method of the present invention first determines the array index corresponding to each virtual link according to the bandwidth allocation interval of each virtual link, then determines the timing trigger interval and the counting initial value corresponding to each virtual link according to the bandwidth allocation interval of each virtual link, and determines the link spectrum diagram corresponding to each array index according to the array index corresponding to each virtual link. Poll the link spectrum diagram corresponding to each array index according to the timing trigger interval and the counting initial value corresponding to each virtual link to obtain the data to be sent of several virtual links corresponding to the link spectrum diagram that meets the data sending rule, and send the data to be sent of any virtual link obtained to the network card corresponding to the virtual link, so as to increase the number of virtual links at the software level, so that when the AFDX system network is running, the maximum supported number of virtual links far exceeds the number of virtual links communicated by mainstream hardware, and can perform sorting and searching functions on virtual links according to priority with a time complexity of logn. When the processor frequency is sufficient, its performance is not inferior to that of traditional hardware logic gate units. Brief Description of the Drawings

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0015] Figure 1 It is a flowchart of the virtual link data transmission method provided by the embodiment of the present invention. Detailed Embodiments

[0016] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0017] Existing network boards compliant with the ARINC664 standard generally do not support a large number of virtual links. Due to the strong binding relationship between virtual links and MAC addresses (Media Access Control Addresses), each manufacturer generally adopts an FPGA (Field Programmable Gate Array) solution to implement the scheduling function of virtual links, comparing the priorities of virtual links based on hardware logic for link scheduling. However, the comparison circuit requires a large number of logic gate units, and each virtual link requires separate parameters such as Bandwidth Allocation Gap (BAG) and Jitter (a parameter measuring signal timing error), which will consume a large amount of register storage. With limited resources in the FPGA, the number of virtual links on the actually produced board is usually limited to around 128 to 256. The relatively low number of virtual links is difficult to meet the link mapping requirements of multiple terminal devices during flight simulation by a full-motion simulator, resulting in a high probability that key subsystems are forced to share virtual links. Additionally, the AFDX requires dual redundant channels to ensure link reliability, further reducing the available number of virtual links. Therefore, there are many limitations in virtual links implemented based on traditional FPGA logic and they cannot be applied to the virtual link implementation scheme of the ARINC664 interface board of a modern full-motion simulator.

[0018] Therefore, due to the defects existing in the existing network boards compliant with the ARINC664 standard, a virtual link data transmission method of the present application is proposed, as Figure 1 shown, including the following steps: Step S100: Determine the array index corresponding to each virtual link according to the bandwidth allocation gap of each virtual link; The array index corresponding to a virtual link is expressed as adjusting the bandwidth allocation gap corresponding to the virtual link to a bandwidth allocation gap compliant with the AFDX standard.

[0019] Further, step S100 includes step S110 - step S120: Step S110: Obtain the bandwidth allocation gap of each virtual link to obtain a bandwidth allocation gap list A = (A1, A2,..., A i ,..., A j ); where i = 1, 2,..., j; j is the number of virtual links; A i is the bandwidth allocation gap of the i-th virtual link; Step S120: Traverse the bandwidth allocation gap list A. If 0 < A i ≤ 1, then determine A i as 1 and determine 1 as the array index corresponding to the i-th virtual link; If 2 n-1 <Ai ≤ 2 n , then set A i to be 2 n , and set 2 n to be the array index corresponding to the i-th virtual link; where n is an integer greater than or equal to 1.

[0020] Round up the bandwidth allocation interval of all virtual links to the nearest power of 2. If the value of the bandwidth allocation interval of a virtual link is between two adjacent powers of 2, then determine the bandwidth allocation interval of the virtual link as the larger number of the two powers of 2 (for example, if the bandwidth allocation interval of a virtual link is 1.8 milliseconds, then determine the bandwidth allocation interval of this virtual link as 2, and its corresponding array index is also 2; if the bandwidth allocation interval of a virtual link is 5.7 milliseconds, then determine the bandwidth allocation interval of this virtual link as 8, and its corresponding array index is also 8), so that the bandwidth allocation interval of each virtual link complies with the AFDX standard (1 millisecond, 2 milliseconds, 4 milliseconds, 8 milliseconds,... 128 milliseconds).

[0021] Step S200: Determine the timing trigger interval and the initial count value corresponding to each virtual link according to the bandwidth allocation interval of each virtual link; The initial count value is the initial value of the counter corresponding to the virtual link. The counter is used to subsequently determine whether the virtual link meets the data sending and receiving requirements within the scheduling period.

[0022] Furthermore, step S200 includes steps S210 - S220: Step S210: Determine the timing trigger interval B as MIN(A); where MIN() is a preset minimum value determination function; Step S220: Determine the initial count value C corresponding to the i-th virtual link i =(A i / B) - 1.

[0023] Step S300: Determine the link graph corresponding to each array index according to the array index corresponding to each virtual link; Each node in the link graph corresponds to a virtual link.

[0024] Furthermore, step S300 includes steps S310 - S360: Step S310: Traverse the array indices corresponding to several virtual links, and determine the virtual links with the same array index as the same array index group to obtain several array index groups; Step S320: Obtain the link identifiers corresponding to several virtual links in each array index group, so as to obtain a set of link identifier lists D = (D1, D2,..., D p ,..., D q ); where p = 1, 2,..., q; q is the number of array index groups; D p is the link identifier list corresponding to the p-th array index group; D p =(D p1 , D p2 ,..., D pe ,..., D pf(p) ); where e = 1, 2,..., f(p); f(p) is the number of virtual links in the p-th array index group; D pe is the link identifier corresponding to the e-th virtual link in the p-th array index group; Step S330: Obtain the priority corresponding to each virtual link in the p-th array index group, so as to obtain the priority list E p =(E p1 , E p2 ,..., E pe ,..., E pf(p) ); where E pe is the priority corresponding to the e-th virtual link in the p-th array index group; The priority corresponding to each virtual link is a value reserved by the user. The lower the value, the higher the priority, indicating that the data transmission and reception of this virtual link are more important.

[0025] Step S340: Sort the priority list E p corresponding to the p-th array index group in descending order of priority, so as to obtain the sorted priority list F p =(F p1 , F p2 ,..., F pe ,..., F pf(p) ); where F pe is the e-th priority determined after priority sorting of the p-th array index group; Step S350: Place the f(p) link identifiers corresponding to F p1 , F p2 ,..., F pe ,..., F pf(p) into the same balanced binary search tree in descending order of node height, so as to obtain the initial link node tree corresponding to the p-th array index group; Step S360: Perform height balancing on the initial link node tree corresponding to the p-th array index group to obtain the link map corresponding to the p-th array index group.

[0026] Height balancing is a node processing method for an AVL tree. The height difference (balance factor) between the two subtrees of any node under the tree is at most 1. When the insertion or deletion of any node causes the balance factor to exceed 1, rotation operations are required to restore the balance of the tree. When inserting a new element, start from the root node and recursively place it in the left or right subtree according to the priority relationship until this node is empty. When deleting an element, for a leaf node, it can be directly deleted; for a node with only one child node, the child node can be raised to the deletion position; for a node with two child nodes, find the inorder predecessor / successor node to replace the current node. Whether inserting or deleting, it is necessary to backtrack from the changed position to update the height of each ancestor node and check for balance. Height balancing includes node processing for AVL trees of LL type, RR type, LR type, and RL type. The node rotation operations in the specific processing process are existing operation methods for AVL trees, so they will not be elaborated here.

[0027] By using an AVL tree at the software level, virtual link scheduling based on priority and time slices is achieved, avoiding the limitation of the number of stacked logic gates in hardware resources, and increasing the number of virtual links supported by the AFDX network architecture of the ARINC664 interface board. Compared with the limitation of the number of virtual links brought by logic gates and hardware resources in FPGA, the AVL tree is implemented based on the CPU processor and memory. When running, the maximum supported number of virtual links far exceeds that of mainstream hardware implementation interface boards, and it can perform sorting and searching functions for virtual links according to priority with a time complexity of logn. When the CPU frequency is sufficient, its performance is not inferior to the traditional FPGA implementation method.

[0028] Step S400: Poll the link map corresponding to each array index according to the timing trigger interval and the initial count value corresponding to each virtual link to obtain the data to be sent for several virtual links corresponding to the link map that meets the data sending rules. By setting different CPU affinities for several virtual links in the link maps corresponding to different array indexes, several virtual links are bound to different CPUs, and the bound CPUs provide computing and processing execution operations for the virtual links (for example, if there are 5 virtual links and a 4-core CPU processor, that is, by setting different CPU affinities for each virtual link to bind to these four CPU processors, and the CPU affinity is set by the user himself).

[0029] Furthermore, step S400 includes steps S410 - S422: Step S410: At every timing trigger interval B, obtain the initial count value of the virtual links in each array index group to obtain an initial count value list G = (G1, G2,..., G p ,..., G q ); where G p is the initial count value of the virtual links in the p-th array index group; Step S420: If G p = 0, then perform an in-order traversal of several nodes in the link graph corresponding to the p-th array index group, sequentially obtain the data to be sent of several virtual links corresponding to the link graph of the p-th array index group, and execute Step S500; Step S421: If G p > 0, then set G p = G p - 1, and return to Step S410.

[0030] Step S422: If each initial count value in the initial count value list G is zero, then return to Step S220.

[0031] At every timing trigger interval B, that is, obtain the initial count value of the virtual links in each array index group at the current moment. The initial count values of several virtual links in the same array index group are the same. Then, according to the initial count value corresponding to each array index group, determine whether the virtual links in each array index group meet the requirements of data transmission and reception. That is, when the initial count value corresponding to any array index group is zero, it means that the virtual links in this array index group meet the requirements of data transmission and reception. Then, according to the priorities of several virtual links in this array index group, sequentially obtain the data to be sent of each virtual link in this array index group; if the initial count value corresponding to the array index group is not zero, it means that the virtual links in this array index group do not yet meet the requirements of data transmission and reception, then it is in the data waiting to be sent stage, subtract one from the initial count value corresponding to this array index group, and return to Step S410, continue to wait for the start of the next data scheduling cycle (that is, after the next timing trigger interval B), and sequentially perform polling scheduling on each array index group until the initial count values corresponding to all array index groups are zero. After obtaining the data to be sent of the virtual links in all array index groups, reset the initial count values corresponding to all array index groups (that is, set them to the initial count values determined in Step S220), and continue to perform new data scheduling on the virtual links in each array index group.

[0032] Step S500: Send the obtained data to be sent of any virtual link to the network card corresponding to this virtual link; Further, Step S500 includes Step S510 - Step S520: Step S510: When the data to be sent of any virtual link is obtained, obtain the network card identifier corresponding to this virtual link; Step S520: Send the data to be sent of this virtual link to the network card with the network card identifier corresponding to this virtual link.

[0033] After the data to be sent of any virtual link is obtained, based on the DPDK (Data Plane Development Kit) architecture, send the data to be sent to the network card corresponding to this virtual link. Use the rte_eth_dev_rx_intr_ctl interface of DPDK to start the interrupt mode, directly store the data to be sent into the memory pool rte_mempool accessible by DMA (Direct Memory Access), and use rte_eth_tx_burst to send the data to be sent, bypassing the switching between the user mode and the kernel mode, and realizing the DMA transfer of the memory data to the physical network card.

[0034] The virtual link data transmission method of the present invention is applied to the ARINC664 interface board of the full-motion simulator. First, according to the bandwidth allocation interval of each virtual link, determine the array index corresponding to each virtual link. Then, according to the bandwidth allocation interval of each virtual link, determine the timing trigger interval and the initial count value corresponding to each virtual link. And according to the array index corresponding to each virtual link, determine the link map corresponding to each array index. According to the timing trigger interval and the initial count value corresponding to each virtual link, poll the link map corresponding to each array index to obtain the data to be sent of several virtual links corresponding to the link map that meets the data sending rules, and send the data to be sent of any virtual link obtained to the network card corresponding to this virtual link, so as to increase the number of virtual links at the software level, so that when the AFDX system network runs, the maximum supported number of virtual links far exceeds the number of virtual links communicated by the mainstream hardware, so as to expand the data communication scheduling ability of the virtual link by increasing the number of virtual links, and can perform sorting and searching functions on the virtual links according to the priority with a time complexity of logn, and its performance is not inferior to that of the traditional hardware logic gate unit when the processor frequency is sufficient.

[0035] The embodiment of the present invention also provides a computer program product, which includes program code. When the program product runs on an electronic device, the program code is used to make the electronic device execute the steps in the method according to various exemplary embodiments of the present invention described above in this specification.

[0036] In addition, although the various steps of the methods in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all of the shown steps must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution, etc.

[0037] From the description of the above embodiments, those skilled in the art can easily understand that the exemplary embodiments described herein can be implemented by software, or by a combination of software and necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0038] In an exemplary embodiment of this disclosure, an electronic device capable of implementing the above method is also provided.

[0039] Those skilled in the art can understand that various aspects of the present invention can be implemented as a system, a method, or a program product. Therefore, various aspects of the present invention can be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or an implementation combining hardware and software aspects, which can be collectively referred to herein as "circuitry", "module", or "system".

[0040] An electronic device according to this embodiment of the present invention. The electronic device is merely an example and should not impose any limitation on the functions and usage scope of the embodiments of the present invention.

[0041] The electronic device is presented in the form of a general-purpose computing device. The components of the electronic device may include, but are not limited to: at least one of the above-mentioned processors, at least one of the above-mentioned memories, and a bus connecting different system components (including the memory and the processor).

[0042] Among them, the memory stores program code, and the program code can be executed by the processor, so that the processor executes the steps according to various exemplary embodiments of the present invention described in the above "Exemplary Method" section of this specification.

[0043] The memory may include a readable medium in the form of a volatile memory, such as a random access memory (RAM) and / or a cache memory, and may further include a read-only memory (ROM).

[0044] The storage may also include a program / utility having a set (at least one) of program modules, such program modules including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of these examples or some combination thereof may include an implementation of a network environment.

[0045] The bus may represent one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus structures.

[0046] The electronic device may also communicate with one or more external devices (such as a keyboard, a pointing device, a Bluetooth device, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device, and / or communicate with any device that enables the electronic device to communicate with one or more other computing devices (such as a router, a modem, etc.). Such communication may be through an input / output (I / O) interface. Further, the electronic device may also communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through a network adapter.

[0047] In an exemplary embodiment of the present disclosure, there is also provided a computer-readable storage medium having stored thereon a program product capable of implementing the above-described method of this specification. In some possible implementation manners, various aspects of the present invention may also be implemented in the form of a program product, which includes program code that, when the program product runs on a terminal device, is used to cause the terminal device to execute the steps according to various exemplary embodiments of the present invention described in the above "Exemplary Method" section of this specification.

[0048] The program product may employ any combination of one or more readable media. The readable media may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0049] A computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries readable program code. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing. The readable signal medium may also be any readable medium other than a readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0050] The program code contained on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0051] The program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, C++, etc., and also including conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's device, executed as a stand-alone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user's computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., by using an Internet service provider to connect through the Internet).

[0052] In addition, the above-mentioned drawings are only schematic illustrations of the processes included in the method according to the exemplary embodiments of the present invention, and are not for limiting purposes. It is easy to understand that the processes shown in the above-mentioned drawings do not indicate or limit the chronological order of these processes. Additionally, it is also easy to understand that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0053] It should be noted that although several modules or units of devices for action execution are mentioned in the above detailed description, such a division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more of the above-mentioned modules or units may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above may be further divided and embodied by multiple modules or units.

[0054] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A virtual link data transmission method, characterized in that, The method includes the following steps: Step S100: Determine the array index corresponding to each virtual link according to the bandwidth allocation interval of each virtual link; Step S200: Determine the timing trigger interval and the initial count value corresponding to each virtual link according to the bandwidth allocation interval of each virtual link; the initial count value is the initial value of the counter corresponding to the virtual link; Step S300: Determine the link graph corresponding to each array index according to the array index corresponding to each virtual link; each node in the link graph corresponds to a virtual link; Step S400: Poll the link graph corresponding to each array index according to the timing trigger interval and the initial count value corresponding to each virtual link, so as to obtain the data to be sent of several virtual links corresponding to the link graph that meets the data sending rule; Step S500: Send the data to be sent of any virtual link obtained to the network card corresponding to the virtual link.

2. The method according to claim 1, wherein The step S100 includes: Step S110: Obtain the bandwidth allocation interval for each of the virtual links to obtain a bandwidth allocation interval list A = (A1, A2,..., A i ,..., A j ); where i = 1, 2,..., j; j is the number of the virtual links; A i is the bandwidth allocation interval of the i-th virtual link; Step S120: Traverse the bandwidth allocation interval list A. If 0 < A i ≤ 1, then set A i to 1, and set 1 as the array index corresponding to the i-th virtual link; If 2 n-1 <A i ≤2 n , then A i is determined to be 2 n , and 2 n is determined to be the array index corresponding to the i-th virtual link; where n is an integer greater than or equal to 1.

3. The method according to claim 2, characterized in that The step S200 includes: Step S210: Determine the timing trigger interval B as MIN(A); where MIN() is a preset minimum value determination function; Step S220: Determine the initial count value C corresponding to the i-th virtual link i =(A i / B)-1 4. The method according to claim 3, wherein The step S300 includes: Step S310: Traverse the array indexes corresponding to several virtual links, and determine the virtual links with the same array index as the same array index group, so as to obtain several array index groups; Step S320: Obtain the link identifiers corresponding to several of the virtual links in each of the array index groups to obtain a set of link identifier lists D = (D1, D2,..., D p ,..., D q ); where p = 1, 2,..., q; q is the number of the array index groups; D p is the link identifier list corresponding to the p-th array index group; D p =(D p1 , D p2 ,..., D pe ,..., D pf(p) ); where e = 1, 2,..., f(p); f(p) is the number of virtual links in the p-th array index group; D pe is the link identifier corresponding to the e-th virtual link in the p-th array index group. Step S330: Obtain the priority corresponding to each of the virtual links in the p-th array index group, so as to obtain the priority list E corresponding to the p-th array index group p =(E p1 ,E p2 ,...,E pe ,...,E pf(p) ); where E pe is the priority corresponding to the e-th virtual link in the p-th array index group; Step S340: Sort the priority list E corresponding to the p-th array index group in descending order of priority p to obtain the sorted priority list F corresponding to the p-th array index group p =(F p1 , F p2 ,..., F pe ,..., F pf(p) ); where F pe is the e-th priority determined after priority sorting of the p-th array index group; Step S350: Place F p1 , F p2 ,..., F pe ,..., F pf(p) The corresponding f(p) link identifiers are sequentially placed in the same balanced binary search tree in the order of decreasing node height to obtain the initial link node tree corresponding to the p-th array index group; Step S360: Perform height balancing processing on the initial link node tree corresponding to the p-th array index group to obtain the link graph corresponding to the p-th array index group.

5. The method according to claim 4, characterized in that The step S400 includes: Step S410: At every timing trigger interval B, obtain the initial count value of the virtual links in each of the array index groups to obtain a list of initial count values G = (G1, G2,..., G p ,..., G q ); where G p is the initial count value of the virtual links in the p-th array index group; Step S420. If G p = 0, perform an in-order traversal on several nodes in the link graph corresponding to the p-th array index group, and sequentially obtain the data to be sent of several virtual links corresponding to the link graph of the p-th array index group.

6. The method according to claim 5, characterized in that The step S420 further includes: Step S421: If G p > 0, then set G p = G p - 1, and return to Step S410.

7. The method according to claim 6, characterized in that, The step S420 further includes: Step S422: If each initial count value in the initial count value list G is zero, return to step S220.

8. The method according to claim 7, wherein The step S500 includes: Step S510: When obtaining the data to be sent of any virtual link, obtain the network card identifier corresponding to the virtual link; Step S520: Send the data to be sent of the virtual link to the network card corresponding to the network card identifier of the virtual link.

9. A non-transitory computer-readable storage medium, characterized in that, At least one instruction or at least one program segment is stored in the storage medium, and the at least one instruction or the at least one program segment is loaded and executed by a processor to implement the method according to any one of claims 1-8.

10. An electronic device, characterized in that, It includes a processor and the non-transitory computer-readable storage medium described in claim 9.

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