Switch boards, switches, and power-on methods for switches

Abstract

The present invention discloses a switching board, a switch and a power-on method for the switch, which relate to the field of computer technology, wherein the switching board includes: a first layer board, a second layer board, a switching network chip and at least one group of connectors, wherein the first layer board includes at least one first expansion port; the second layer board includes at least one second expansion port; the first layer board and the second layer board are plug-in connected via at least one group of connectors; the switching network chip is arranged on the first layer board, and the switching network chip is used to configure and manage at least one first expansion port, and / or, configure and manage at least one second expansion port via at least one group of connectors. Thus, through the layered design and the plug-in connection of the connectors, the problem of the limited number of expansion ports in the prior art and the inability to meet the high-capacity memory requirements of large-model reasoning applications is solved, and technical effects such as high-density expansion capability and high signal transmission efficiency are achieved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a switching board, a switch, and a power-on method for the switch. Background Art

[0002] With the explosive growth of artificial intelligence (AI) applications, server memory systems are gradually evolving from a traditional auxiliary role to a critical factor in determining AI system performance. Modern AI models, especially large ones, place extremely high demands on memory systems, including high capacity, high bandwidth, and low latency to better support complex inference computing tasks. Against this backdrop, Compute Express Link (CXL) technology has emerged. Through memory sharing, heterogeneous resource integration, and modular design, CXL is driving the evolution of server architecture from fixed configurations to dynamic composability, becoming a core memory expansion technology for next-generation data centers.

[0003] In related technologies, servers typically expand memory capacity by connecting to an external MXC (Memory Expander Controller) chip via CXL. MXC chips can connect to the host via a PCIe (Peripheral Component Interconnect Express) interface and support a certain number of memory expansion modules. For example, a common existing solution is to expand memory using an MXC in the form of a PCIe standard card. A single MXC chip can support up to four memory modules, thereby expanding memory capacity. However, this expansion method allows for a limited number of expansion ports, which cannot meet the high-capacity memory requirements of large-model inference applications, and this issue needs to be addressed urgently. Summary of the Invention

[0004] The present invention provides a switching board, a switch, and a power-on method for the switch, to at least address the problem that existing technologies mostly rely on fixed load modes and cannot reflect the dynamic frequency / voltage regulation characteristics of the CPU (Central Processing Unit) in real scenarios, thereby achieving the technical effects of high testing efficiency and high accuracy.

[0005] The present invention provides a switching board, comprising: a first layer board, a second layer board, a switching network chip and at least one group of connectors, wherein:

[0006] The first layer plate includes at least one first expansion port;

[0007] The second layer plate includes at least one second expansion port;

[0008] The first layer board and the second layer board are plug-connected via at least one set of the connectors;

[0009] The switching network chip is arranged on the first layer board, and the switching network chip is used to configure and manage at least one of the first expansion ports, and / or configure and manage at least one of the second expansion ports through at least one group of the connectors.

[0010] The present invention also provides a switch, comprising:

[0011] At least one of the above-mentioned switch boards;

[0012] A management board is used to obtain device configuration information of at least one of the switch boards, and send configuration instructions to the switch network chip of at least one of the switch boards according to the device configuration information, so as to complete the memory expansion configuration through the switch network chip of at least one of the switch boards.

[0013] The present invention also provides a method for powering on a switch, which is applied to the above-mentioned switch, wherein the method includes the following steps:

[0014] When receiving a power-on instruction, controlling the fabric manager to power on, and sending a switch board power-on signal to the baseboard management controller via the fabric manager;

[0015] The baseboard management controller sends the switch board power-on signal to the programmable logic module, so as to close the power supply channel of at least one of the switch boards through the programmable logic module, so that at least one of the switch boards performs initialization after being powered on.

[0016] The present invention also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned switch power-on methods when executing the computer program.

[0017] The present invention also provides a non-volatile computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned methods for powering on a switch are implemented.

[0018] The present invention also provides a computer program product, comprising a computer program, which implements the steps of any of the above-mentioned switch power-on methods when executed by a processor.

[0019] Through the present invention, by utilizing the layered design of the switching board and the plug-in connection of the connector, the problem of the limited number of expansion ports in the prior art, which cannot meet the demand for high-capacity memory for large-model reasoning applications, is solved, and technical effects such as high-density expansion capability and high signal transmission efficiency are achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 A topological diagram of a switch board provided in an embodiment of the present invention;

[0022] Figure 2 A schematic diagram of a structure for extending memory through MXC in the related art;

[0023] Figure 3 A schematic diagram of the specifications and dimensions of a switch board provided in an embodiment of the present invention;

[0024] Figure 4 A schematic diagram of the interconnection of two layers of boards in a switch board provided in an embodiment of the present invention;

[0025] Figure 5 A block diagram of a switch board provided in an embodiment of the present invention;

[0026] Figure 6 A block diagram of a switch provided in an embodiment of the present invention;

[0027] Figure 7 A schematic diagram of the switch topology provided in an embodiment of the present invention;

[0028] Figure 8 A schematic diagram of the layout of a switch chassis provided in an embodiment of the present invention;

[0029] Figure 9 A schematic diagram of the power supply topology of a switch system provided in an embodiment of the present invention;

[0030] Figure 10 A flow chart of a switch power-on method provided in an embodiment of the present invention;

[0031] Figure 11 A flow chart of the switch power-on sequence provided by an embodiment of the present invention;

[0032] Figure 12 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0034] It should be noted that, in the description of the present invention, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. The terms "first," "second," etc., in the present invention are used to distinguish similar objects, and are not used to describe a particular order or precedence.

[0035] In order to enable those skilled in the art to better understand the solutions of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0036] An embodiment of the present invention provides a switch board, and the switch board is described in detail in conjunction with the topology structure of the switch board.

[0037] Figure 1 FIG. 4 is a topological diagram of a switch board according to an embodiment of the present invention.

[0038] Before introducing the switch board proposed in the embodiment of the present invention, the relevant technical background is briefly introduced.

[0039] In the related art, the schematic diagram of memory expansion through MXC can be as follows: Figure 2 As shown, it is designed as a PCIe expansion card. This card can be directly inserted into a host's CEM (Card Electro-Mechanical) connector or a riser card (a hardware device used to expand the functionality of a server or computer motherboard) via x16 gold fingers. It supports two MXC chips, each of which can expand into four DIMMs (Dual Inline Memory Modules), significantly increasing memory capacity and performance. Using CXL bus technology, the CPU and MXC chips can be interconnected, enabling memory expansion.

[0040] However, the memory capacity that can be expanded using MXC chips is limited. This is primarily due to the number of PCIe interfaces in the system. The number of PCIe interfaces supported in a system determines the number of interconnected MXC chips, thus limiting the upper limit of memory expansion. With current technology, a single MXC chip can support up to four memory sticks. If a single 256GB stick is used, the maximum memory capacity that can be expanded on an MXC chip is 1024GB. While this is a considerable amount, it falls far short of meeting the massive memory demands of applications that execute inference on large models.

[0041] Based on the above problems, an embodiment of the present invention proposes a switching board, which, through a layered design and plug-in connection of connectors, solves the problem that the existing technology has a limited number of expansion ports and cannot meet the demand for high-capacity memory for large-model reasoning applications, thereby achieving technical effects such as high-density expansion capability and high signal transmission efficiency.

[0042] The switch board proposed in the embodiment of the present invention will be described in detail below.

[0043] For example, Figure 1 As shown, the switch board 10 includes: a first layer board 100, a second layer board 200, a switching fabric chip 300, and at least one set of connectors 400. The first layer board 100 includes at least one first expansion port 101; the second layer board 200 includes at least one second expansion port 201; the first layer board 100 and the second layer board 200 are pluggably connected via at least one set of connectors 400; the switching fabric chip 300 is disposed on the first layer board 100 and is used to configure and manage the at least one first expansion port 101 and / or, via at least one set of connectors 400, the at least one second expansion port 201.

[0044] Specifically, if Figure 1 As shown, in order to achieve a more efficient and modular structural design, the embodiment of the present invention adopts a layered design concept, dividing the switch board 10 (i.e., the switch chip) into a first layer board 100 (i.e., the lower layer board) and a second layer board 200 (i.e., the upper layer board), as shown in FIG. Figure 3 As shown in (a), the size of the second layer board 200 (i.e., the upper layer board) is 417*96mm. Figure 3 As shown in (b), the size of the first layer board 100 (i.e., the lower layer board) is 417*218mm.

[0045] Each layer board supports at least one expansion port. That is, the first layer board 100 includes at least one first expansion port 101, and the second layer board 200 includes at least one second expansion port 201. For example, in this embodiment of the present invention, a single switch board 10 includes a total of 16 expansion ports: the first layer board 100 includes 8 first expansion ports 101, and the second layer board 200 includes 8 second expansion ports 201.

[0046] In terms of external interface design, the switch board 10 also includes at least one set of connectors 400. In this embodiment, the at least one set of connectors 400 selected is a CDFP (Compact Double Face Plug) connector that supports the PCIe Gen5 standard. This connector not only offers fast transmission speeds but also excellent compatibility and scalability. Using a plug-in connection, the at least one set of connectors 400 effectively connects the first and second boards 100 and 200. These interconnections are achieved via MCIO (Micro Coaxial Interconnect Option) cables, enabling signal transmission and resource sharing. This significantly increases connection density and enhances overall system integration. This allows the at least one second expansion port 201 included on the second board 200 to be successfully connected to the first board 100, fully demonstrating the functionality of the switch board.

[0047] In addition, the switch board 10 also includes a switching network chip 300, which is installed on the first layer board 100. This chip can directly configure and manage at least one first expansion port 101 of the first layer board 100. In addition, it can also configure and manage at least one second expansion port 201 of the second layer board 200 through at least one set of connectors 400. Therefore, through the management of the expansion ports by the switching network chip 300, the system can more flexibly configure and adjust the parameters of the expansion ports, thereby improving the system's adaptability.

[0048] As you can understand, this layered design also offers other significant advantages: First, it facilitates assembly and maintenance, as each layer can be accessed independently, making troubleshooting and upgrades more convenient and efficient. Second, this design also facilitates ventilation and heat dissipation throughout the system. Because the first and second layers 100, 200 are connected via at least one set of connectors 400, a certain amount of space is left between them, which facilitates air circulation, effectively reducing the operating temperature of the entire system and improving the stability and service life of the equipment.

[0049] Optionally, in some embodiments, at least one group of connectors 400 uses a high-density connector and / or a mini-edge input and output cable.

[0050] It is understandable that at least one group of connectors 400 in the embodiment of the present invention may all be high-density connectors, or all be mini edge input and output cables, or a combination of high-density connectors and mini edge input and output cables.

[0051] For high-density connectors, such as Figure 4 As shown, at least one set of connectors 400 (such as Figure 4 The high-density connectors (high-density connectors_A1 and_A2, or high-density connectors_B1 and_B2) shown can be hermaphroditic, such as ExaMezz snap-on connectors. These connectors are placed on the front of the first board 100 and on the back of the second board 200, ensuring they mate seamlessly. For example, high-density connector_A1 can be plugged into high-density connector_B1, creating a tight and stable connection. Similarly, high-density connector_A2 can be plugged into high-density connector_B2, ensuring they also securely fit together.

[0052] Mini Edge Input / Output (MCIO) cables are compact cable solutions ideal for space-constrained environments. Using mini edge input / output cables can further optimize space utilization, making the entire system more compact. For MCIO connectors, choose an MCIO with x16 lanes. In practical applications, MCIO_A1 can be connected to MCIO_B2 via a cable to achieve data and signal transmission. At the same time, MCIO_A2 can be connected to MCIO_B1, MCIO_A3 can be connected to MCIO_B4, and MCIO_A4 can be connected to MCIO_B3. This connection method allows for efficient interconnection between multiple MCIO connectors.

[0053] Therefore, by using high-density connectors and / or mini edge input and output cables, the switch board 10 can provide more interfaces in a limited space, meeting the requirements of high-performance computing and large model reasoning for high-capacity memory.

[0054] Optionally, in some embodiments, each group of connectors 400 includes a first connection unit and a second connection unit, wherein the first connection unit of each group of connectors 400 is arranged on the first layer board 100 and is connected to the switching network chip 300; the second connection unit of each group of connectors 400 is arranged on the second layer board 200 and is correspondingly connected to at least one second expansion port 201; the first connection unit and the second connection unit of each group of connectors 400 are arranged in corresponding positions.

[0055] Specifically, each group of connectors 400 includes two parts, namely a first connection unit and a second connection unit. Among them, the first connection unit is arranged on the first layer board 100 and is connected to the switching network chip 300, so that the switching network chip 300 can directly manage at least one first expansion port 101 through the first connection unit, and communicate with at least one second expansion port 201 through the connector 400. The second connection unit is arranged on the second layer board 200 and is connected to at least one second expansion port 201, so that at least one second expansion port 201 can communicate with the first connection unit through the second connection unit, thereby realizing signal transmission between the upper and lower layers. The first connection unit and the second connection unit of each group of connectors 400 are arranged in corresponding positions, which means that they are aligned in space and can be directly plugged in and connected. This design not only simplifies the assembly process, but also ensures the stability and reliability of signal transmission.

[0056] Through the connectors arranged at corresponding positions, the signal transmission path is optimized, and the signal can be transmitted from the switching network chip 300 of the first layer board 100 through the first connection unit to the second connection unit, and then to at least one second expansion port 201, thereby reducing the delay of signal transmission and improving the overall performance of the system.

[0057] Optionally, in some embodiments, the positions of at least one first extension port 101 and at least one second extension port 201 correspond one to one, and the first extension port and the second extension port with corresponding positions are located in the same column.

[0058] That is, in this embodiment of the present invention, the at least one first expansion port 101 on the first layer board 100 corresponds to the at least one second expansion port 201 on the second layer board 200 in a one-to-one positional correspondence, and the corresponding first and second expansion ports are located in the same column. This corresponding positional correspondence facilitates maintenance and replacement, and through this corresponding positional correspondence, signals can be transmitted directly from the first expansion port to the second expansion port, reducing intermediate links in signal transmission and improving signal transmission efficiency.

[0059] This layout design allows the expansion ports of the two-layer boards to be directly plugged in and connected through at least one set of connectors 400 without the need for complex wiring or additional adapters. The signal can be transmitted directly from the first expansion port to the second expansion port, shortening the transmission path while reducing signal delay and interference.

[0060] Optionally, in some embodiments, the above-mentioned switching board 10 further includes: an Ethernet physical layer interface module 500 and a network interface 600, wherein the Ethernet physical layer interface module 500 is used to convert the received first signal into a second signal; the network interface 600 is connected to the Ethernet physical layer interface module 500, and remote system maintenance and remote management are performed through the network interface 600, and / or out-of-band remote maintenance and management are performed.

[0061] Specifically, if Figure 5 As shown, the switch board 10 also includes two key components: an Ethernet physical layer interface (PHY) module 500 and a network interface 600. The Ethernet PHY module 500 is primarily responsible for converting physical layer signals (converting digital signals into analog signals that can be transmitted on physical media, or vice versa). Specifically, the Ethernet PHY module 500 converts a received first signal (such as an SGMII (Serial Gigabit Media Independent Interface) serial network signal) into a second signal that complies with a specific standard (such as an MDI (Medium Dependent Interface) signal) and transmits this second signal to the network interface 600. The network interface 600 is connected to the Ethernet PHY module 500 and connects to an external network through the network interface 600 (such as an RJ45 Ethernet port), enabling remote system maintenance and management. This allows administrators to remotely monitor, configure, and troubleshoot the switch board or the entire system via a network connection without having to physically access the device. In addition, out-of-band remote maintenance and management can be performed through network interface 600. Out-of-band management refers to system management via a dedicated management channel independent of the system's main processor. This approach is particularly important in the event of a system failure or main processor malfunction, as it allows administrators to access and repair the system through a backup channel.

[0062] Thus, through the Ethernet physical layer interface module 500 and the network interface 600, the switch board 10 can support remote system maintenance and management, as well as out-of-band remote maintenance and management. This design allows administrators to manage devices more flexibly and enables rapid repairs in the event of a system failure, regardless of whether the device is operating normally, thereby improving system availability and reliability.

[0063] Optionally, in some embodiments, the above-mentioned switching board 10 further includes: a serial peripheral interface multiplexer 700 and a storage unit 800, wherein the serial peripheral interface multiplexer 700 is used to determine the target communication device based on the control signal sent by the switching network chip 300; the storage unit 800 is used to store the firmware parameters and configuration parameters required for the operation of the switching network chip 300, so as to read the firmware parameters and configuration parameters from the storage unit when the switching network chip 300 performs an initialization operation.

[0064] Specifically, if Figure 5 As shown, the switch board 10 also includes a serial peripheral interface multiplexer 700 and a storage unit 800. In complex systems, multiple peripherals may share the same SPI (Serial Peripheral Interface) bus. The SPI multiplexer 700 selects the correct peripheral (i.e., the target communication device) for communication based on control signals from the switch fabric chip 300. Specifically, when the switch fabric chip 300 needs to communicate with a target communication device, it sends a control signal to the SPI multiplexer 700, which then connects the SPI bus to the selected target communication device, thereby achieving efficient device management and signal transmission. The storage unit 800 (such as a flash memory or other non-volatile storage device) stores the firmware and configuration parameters required for the operation of the switch fabric chip 300. These parameters, including initialization settings, device configuration, and firmware board information, are essential for the normal operation of the switch fabric chip 300. When the switching network chip 300 performs the initialization operation, the control signal SPI_SEL on the switching board 10 defaults to a low signal, so that the switching network chip 300 can communicate with the storage unit 800 through the SPI bus. Through the SPI bus, the switching network chip 300 can read the necessary firmware parameters and configuration parameters in the storage unit 800, thereby ensuring that the switching network chip 300 can complete its own initialization and enter normal working state.

[0065] Thus, through the serial peripheral interface multiplexer 700 and the storage unit 800, the switch network chip 300 can flexibly communicate with multiple peripherals, improving the flexibility and scalability of the system. The storage unit 800 can quickly load necessary firmware parameters and configuration parameters, ensuring that the switch network chip 300 can quickly complete initialization and enter normal operating state, reducing initialization time and improving system startup efficiency.

[0066] Optionally, in some embodiments, the above-mentioned switching board 10 further includes: a clock generator 900 and a clock buffer 1000, wherein the clock generator 900 is used to generate a clock signal that meets preset requirements; the clock buffer 1000 is used to process the clock signal to obtain a signal that meets the timing requirements of the switching network chip 300, so that the switching network chip 300 works based on the signal that meets the timing requirements of the switching network chip 300.

[0067] Specifically, the switching board 10 also includes a clock generator 900 and a clock buffer 1000. The clock generator 900 on the switching board 10 can generate a clock signal with a frequency of 100 MHz (i.e., meeting the preset requirements), which is the reference frequency required for the normal operation of the switching network chip 300. In order to ensure the stability and accuracy of the clock signal, the clock generator 900 usually adopts a high-precision oscillator, such as a crystal oscillator or a temperature-compensated crystal oscillator. These oscillators can maintain a stable frequency output under different environmental conditions and reduce jitter and noise. The clock buffer 1000 can process the clock signal generated by the clock generator 900 to meet the timing requirements of the switching network chip 300. After passing through the clock buffer 1000, the clock signal can be divided into two forms: one is a single-ended 100 MHz clock signal (such as Figure 5 CLK_SYS shown in the figure), the other is 16 groups of differential clock signals (such as Figure 5 These signals are ultimately sent to the switch network chip 300 to ensure proper operation. Clock buffer 1000 processes the clock signals, ensuring they remain stable and accurate during transmission, reducing the effects of jitter and noise.

[0068] It's understandable that the core of this mechanism lies in the role of the clock signal. In digital circuits, the clock signal acts like a "heartbeat," synchronizing the operations of various components. The stability and accuracy of the clock signal directly impacts system performance and reliability. An unstable or inaccurate clock signal can lead to data transmission errors, degraded system performance, or even system crashes. The difference between single-ended and differential signaling lies in the transmission method. Differential signaling improves the system's anti-interference capabilities, making it suitable for long-distance or high-precision transmission and reducing interference during signal transmission.

[0069] Therefore, the coordinated operation of the clock generator 900 and the clock buffer 1000 ensures that the switching network chip 300 can operate based on a stable and accurate clock signal, thereby improving the overall performance and reliability of the system.

[0070] The switch board proposed in accordance with an embodiment of the present invention solves the problem of the limited number of expansion ports in the prior art and the inability to meet the demand for high-capacity memory for large-model reasoning applications through layered design and plug-in connection of connectors, thereby achieving technical effects such as high-density expansion capability and high signal transmission efficiency.

[0071] Through the description of the above implementation methods, those skilled in the art can clearly understand that the system according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0072] An embodiment of the present invention further provides a switch.

[0073] Figure 6 FIG. 1 is a topological diagram of a switch according to an embodiment of the present invention.

[0074] like Figure 6 As shown, the switch 1 includes: at least one switching board 10 and a management board 20, wherein the management board 20 is used to obtain the device configuration information of at least one switching board 10, and send configuration instructions to the switching network chip 300 of at least one switching board 10 according to the device configuration information, so as to complete the memory expansion configuration through the switching network chip 300 of at least one switching board 10.

[0075] Specifically, if Figure 6As shown, switch 1 primarily consists of two switch boards 10 and a management board 20. The management board 20 interconnects the two switch boards 10 via power connectors and MCIO cables, providing power, I2C, UART (Universal Asynchronous Receiver-Transmitter), PCIe, GPIO (General Purpose Input / Output) and other transmission control signals, enabling in-band and out-of-band management of the entire switch. The management board 20 is 424 mm long and 207 mm wide. The management board 20 is the control center of switch 1, responsible for managing and configuring the entire switch system. It provides system management, monitoring, configuration, and power-on and power-off control. It obtains device configuration information from at least one switch board 10 via the I2C (Inter-Integrated Circuit) bus, including the switch board's hardware status, port type, and firmware version. Based on this information, the management board 20 generates configuration commands and sends them to the switching network chip 300 via the PCIe interface. This configuration instruction instructs the switch fabric chip 300 on how to configure memory expansion, thereby achieving flexible allocation and optimized utilization of memory resources. Specifically, after receiving the configuration instruction from the management board 20, the switch fabric chip 300 can dynamically adjust the memory expansion configuration based on the instruction to accommodate different application scenarios and requirements. This dynamic adjustment capability enhances the system's flexibility and adaptability.

[0076] Furthermore, the two switch boards 10 maintain independent layouts. Each switch board 10 is interconnected via MCIO cables and high-density connectors (i.e., at least one set of connectors 400) between the upper and lower layers (i.e., the first and second layers 100 and 200), providing 32 ports of service. Each switch board 10, acting as a node, supports 16 ports, allowing for arbitrary configuration of upstream and downstream connections. Each port has 16 lanes and a speed of up to 32 Gb / s, resulting in a one-way data transmission capacity of 1024 GB / s, providing strong support for data transmission.

[0077] Thus, through the dynamic configuration management and comprehensive system monitoring of the management board 20, the flexibility, reliability and performance of the system are improved.

[0078] Optionally, in some embodiments, the management board 20 includes: a structure manager 21 and a baseboard management controller 22, wherein the structure manager 21 and the baseboard management controller 22 communicate through a first bus; the baseboard management controller 22 is used to control the power-on of at least one switching board 10 according to the power-on information of the structure manager 21.

[0079] Specifically, if Figure 7 As shown, the management board 20 includes a fabric manager (Fabric Manager, referred to as FM) 21 and a baseboard management controller (Baseboard Management Controller, referred to as BMC) 22. The fabric manager 21 and the baseboard management controller 22 can communicate with each other through a first bus (such as Figure 5 The LPC (Low Pin Count Bus) shown transmits power-on information from the fabric manager 21 and controls power-on and power-off signals for the switch boards 10. This enables communication between the fabric manager 21 and the baseboard management controller 22, as well as the baseboard management controller 22's power-on control of at least one switch board 10. As the system's management center, the baseboard management controller 22 is responsible for out-of-band management and control of the entire switch 1. It not only supports real-time monitoring and management of out-of-band information for the entire device, but also monitors the status of the power supply unit (PSU), the status of power virtualization resources, and the overall temperature of the switch 1.

[0080] The BMC 22 also implements fan control and system display functions to ensure optimal system operation. Specifically, the BMC 22 monitors the internal temperature of the switch 1 in real time using built-in temperature sensors. These sensors are located near key components, such as the CPU and the switch fabric chip 300, ensuring accurate temperature measurement of each component. Based on the monitored temperature data, the BMC 22 intelligently adjusts the fan speed. When temperatures are high, the BMC 22 automatically increases the fan speed to improve heat dissipation; when temperatures are low, the BMC 22 reduces the fan speed to reduce noise and energy consumption. The BMC 22 also detects whether fans are functioning properly. If a fan failure is detected, the BMC 22 can issue an alarm and take other measures (such as increasing the speed of other fans) to ensure system heat dissipation. Regarding the system display function, the BMC 22 displays key system status information (such as temperature, fan speed, and power status) on the management interface or physical display, allowing maintenance personnel to intuitively understand the system's operating status. If the BMC 22 detects a fault, it can display detailed fault information on the display screen or indicator lights, helping maintenance personnel quickly locate and resolve the problem. The BMC 22 can also record system operation logs, including temperature changes, fan speed adjustments, fault alarms, and other information, which can be used for subsequent analysis and maintenance.

[0081] The fabric manager 21 plays a crucial role in managing the network structure or architecture of switch 1. It not only collects operational status information about the switch board 10 (including but not limited to device health, performance indicators, and fault information, which are crucial for real-time monitoring and maintaining stable system operation), but also identifies different port types and retrieves firmware information for the switch board 10. Furthermore, the fabric manager 21 configures port routing, which is crucial for network configuration and optimization. By dynamically adjusting port routing based on network traffic and device status, the network can automatically adapt to changes, improving network flexibility and reliability. The fabric manager 21 also manages memory devices on the downstream ports of the switch board 10 via the PCIe interface, including monitoring memory device capacity and speed. Notably, this memory device management functionality applies not only to x86 processors but also to ARM (Advanced RISC Machine) processors. Both processors can serve as the main control chip for the management board 20, running management software and processing data, enhancing system flexibility and adaptability.

[0082] Thus, the management board 20, through the collaborative work of the fabric manager 21 and the baseboard management controller 22, achieves comprehensive monitoring and management of the switch 1. The fabric manager 21 focuses on optimizing the network structure and collecting information to ensure network efficiency and stability; the baseboard management controller 22, on the other hand, focuses on hardware-level management and control, from power management and temperature monitoring to fan control. The two complement each other, jointly supporting the efficient and reliable operation of the switch 1. Furthermore, by controlling the power-on process of the switch board 10 based on the power-on information from the fabric manager 21, the system can achieve more flexible startup and power-on control, improving overall system performance.

[0083] Optionally, in some embodiments, the structure manager 21 includes: at least one management interface and at least one transmission interface, wherein the structure manager 21 obtains the device configuration information of at least one switch board 10 through at least one management interface; the structure manager 21 sends configuration instructions to the switching network chip 300 of at least one switch board 10 through at least one transmission interface.

[0084] That is to say, if Figure 7As shown, the fabric manager 21 includes at least one management interface (such as an I2C bus) and at least one transmission interface (such as a PCIe interface). The I2C bus is a low-speed, low-pin-count serial communication protocol suitable for device status monitoring and configuration information transmission, while the PCIe interface is a high-speed serial communication protocol suitable for high-speed data transmission and device configuration management. The fabric manager 21 can obtain information such as the status, port type, and firmware version of the switch fabric chip 300 (i.e., device configuration information of at least one switch board 10) via the I2C bus (i.e., at least one management interface). It can also send configuration commands to the switch fabric chip 300 of at least one switch board 10 via the PCIe interface (i.e., at least one transmission interface). These configuration commands instruct the switch fabric chip on how to configure memory expansion to ensure efficient use of memory resources by the system.

[0085] Thus, through the management interface and transmission interface of the structure manager 21, flexible acquisition of device configuration information and efficient sending of configuration instructions are achieved, thereby improving the flexibility and performance of the system.

[0086] Optionally, in some embodiments, the management board 20 further includes: an Ethernet control module 23 and an Ethernet switch 24, wherein the Ethernet control module 23 is used to convert the received third signal into a fourth signal; and the Ethernet switch 24 is used to convert the fourth signal into the first signal.

[0087] Specifically, in order to implement the switching of network port functions between the two switch boards 10, an Ethernet switch chip (Eth SW) can be used to uniformly convert different types of network signals into SGMII serial network signals that support long transmission distances. Figure 7As shown, the PCIe interface signal (i.e., the third signal) of the fabric manager 21 can be converted into an MDI signal (i.e., the fourth signal) by the Ethernet control module 23 (e.g., the I210 chip), then connected to the Ethernet switch 24 and converted into an SGMII (i.e., the first signal). The RGMII (Reduced Gigabit Media Independent Interface) signal directly output by the baseboard management controller 22 can be converted into an MDI signal (i.e., the fourth signal) by the Ethernet control module 23 (e.g., the PHY chip), then connected to the Ethernet switch 24 and converted into an SGMII (i.e., the first signal). The PHY chip can be the 88E1512 model, a high-performance PHY chip that supports Gigabit Ethernet transmission and is suitable for a variety of network devices. The Ethernet interaction chip of the Ethernet switch 24 can be the 88E6190 model, a high-performance Ethernet switching chip that supports a variety of network functions, including flow control.

[0088] Thus, through the Ethernet control module 23 and Ethernet switch 24, different types of network signals are uniformly converted into SGMII signals. This unified signal format enables flexible switching of network port functions between the two switch boards 10, adapting to different network configuration requirements. This design supports multiple network topologies, allowing the system to dynamically adjust network configuration according to different application scenarios and requirements, thereby improving system flexibility and adaptability.

[0089] Optionally, in some embodiments, the management board 20 further includes: an expansion module 25, configured to expand any management interface of the structure manager 21 into at least two management interfaces.

[0090] Specifically, the fabric manager 21 serves as the control center for the switch board 10. If the fabric manager 21 only has one set of I2C interfaces, an expansion module 25 (such as an I2C expander) can be used to expand the number of management interfaces (i.e., expand any one management interface of the fabric manager 21 to at least two management interfaces), allowing the fabric manager 21 to connect to more devices. Through the expansion module 25, the fabric manager 21 can be connected to different switch boards 10, enabling real-time monitoring of the status of each switch board 10, including access to information such as port type and firmware version. Furthermore, the expansion module 25 supports not only static connections but also dynamic configuration. This means that the system can dynamically adjust the number of connected devices as needed, thereby improving the system's flexibility and adaptability.

[0091] Therefore, the introduction of the expansion module 25 enhances the scalability and maintainability of the system, so that when a management interface needs to be added, there is no need to replace the original structure manager 21, only the expansion module 25 needs to be added, which greatly saves cost and time.

[0092] Optionally, in some embodiments, the management board 20 further includes: a programmable logic module 26 and a first heat dissipation component 27, wherein the programmable logic module 26 is used to obtain the actual rotational speed of the first heat dissipation component 27 to adjust the PWM signal of the first heat dissipation component 27 according to the actual rotational speed.

[0093] Specifically, if Figure 7 As shown, the programmable logic module 26 is connected to the baseboard management controller 22 via the I2C bus. The baseboard management controller 22 can upgrade the firmware of the programmable logic module 26 via the I2C bus. This firmware upgrade ensures that the programmable logic module 26 can run the latest control logic, support new features, or fix known issues. The baseboard management controller 22 can also transmit power-on and power-off commands to the programmable logic module 26 to control the power status of the switch network chip 300. The baseboard management controller 22 can also send instructions to the programmable logic module 26 to control the clock signal of the switch network chip 300 and switch the SPI link channel, ensuring the normal operation of the switch network chip 300 and supporting efficient system operation. The programmable logic module 26 can also obtain the actual speed of the first heat dissipation component 27 (such as a fan) through the TACH (Tachometer) signal (a signal used to measure motor speed, typically generated by the fan motor) and adjust the duty cycle of the PWM (Pulse Width Modulation) signal based on the actual speed to achieve speed control of the first heat dissipation component 27. The PWM signal is a method of controlling the motor speed by changing the pulse width. By adjusting the duty cycle of the PWM signal, the speed of the first heat dissipation component 27 can be accurately controlled, thereby optimizing the heat dissipation performance of the system.

[0094] Thus, by precisely controlling the rotational speed of the first heat sink assembly 27, the system can dynamically adjust heat dissipation performance based on actual needs, ensuring adequate heat dissipation under high loads while reducing noise and energy consumption under low loads. By optimizing heat dissipation performance, the hardware's operating time at high temperatures can be reduced, extending its service life.

[0095] Optionally, in some embodiments, the above-mentioned switch 1 further includes: a switch chassis body, wherein, when the switch 1 includes two switch boards 10, the two switch boards 10 are arranged in an overlapping manner, and after the overlapping arrangement, they are arranged in sequence on the switch chassis body along the first direction with the management board 20, and the first direction is the direction from the rear of the switch chassis to the front of the switch chassis.

[0096] Specifically, the switch 1 also includes a switch chassis body, which is 2U high (U is the unit of height of rack-mounted servers and chassis, 1U equals 1.75 inches (about 44.45 mm)), and can support front and rear cabinet racks, facilitating daily maintenance. This design allows the switch 1 to be easily installed in a standard cabinet while maintaining good heat dissipation performance. Figure 8 As shown, when switch 1 includes two switch boards 10, they are designed to overlap to effectively utilize space and reduce the overall size of the switch chassis while maintaining high system performance. The two overlapping switch boards 10 and the management board 20 are sequentially installed in the switch chassis, with the rear of the chassis pointing toward the front. This allows for convenient maintenance or component replacement.

[0097] Furthermore, the front window of the switch chassis includes left and right mounting brackets, network ports, and a CDFP (Common Data Form Factor Pluggable) connector. The left and right mounting brackets secure the chassis' structural components, ensuring that the chassis is securely installed in the proper position. The network ports consist of a system network port and a management network port, each of which performs different network communication tasks. The PWR button (Power Button) powers the entire system on and off. To start the system, simply press this button briefly; to shut down the system, press and hold it. The system network port outputs a network signal through the fabric manager 21 and is crucial for remote system maintenance and management. The management network port, on the other hand, outputs a network signal through the baseboard management controller 22 and supports out-of-band remote maintenance and management. The right mounting ear also features a VGA (Video Graphics Array Interface) port, which can be directly connected to a monitor to provide visual output. A USB (Universal Serial Bus) port can be used to connect a keyboard and mouse. These peripherals simplify and facilitate KVM (Keyboard Video Mouse) management. It's worth noting that the system and management network ports are located on two different switch boards 10, and are physically interchangeable.

[0098] Optionally, in some embodiments, two switch boards 10 are respectively provided on a first switch board tray and a second switch board tray, and the first switch board tray and the second switch board tray are locked and fixed to the switch chassis body by a locking mechanism.

[0099] Specifically, to further enhance maintenance and assembly convenience, a forward-pullout switch tray (including a first and second switch tray) is provided. Two switch boards 10 can be mounted on each of the first and second switch trays. Each switch tray is equipped with handles on both sides, allowing the user to easily pull each tray out of or push it into the switch chassis. During installation, once the switch tray is pushed into position, the locking mechanism secures it to the switch chassis.

[0100] The design of the switch board tray greatly improves the convenience of maintenance and assembly. When a switch board needs to be inspected, repaired, or replaced, quick access is provided, reducing maintenance time and workload. The locking mechanism ensures the stability and reliability of the switch board tray within the chassis, preventing it from loosening due to vibration or other external forces, thereby ensuring stable system operation.

[0101] Optionally, in some embodiments, the above-mentioned switch 1 further includes: a first power supply component 30 and a second power supply component 40 arranged in the switch chassis body; in the event of a failure of the first power supply component 30, power is supplied to at least one switch board 10 through the second power supply component 40.

[0102] Specifically, in this embodiment of the present invention, two power supply components (e.g., PSUs) are located on the rear window of the switch chassis: a first power supply component 30 and a second power supply component 40. This provides a 1+1 redundancy design. If one power supply component fails, the other can immediately take over the entire system load and continue to power at least one switch board 10. This ensures the continued stable operation of the switch 1 and prevents system downtime or service interruption caused by a single power supply component failure. This redundant design not only improves system reliability but also reduces maintenance costs.

[0103] Optionally, in some embodiments, the above-mentioned switch 1 further includes: a second heat dissipation assembly arranged on the switch chassis body, wherein the second heat dissipation assembly includes a first heat dissipation unit and a second heat dissipation unit, wherein the first heat dissipation unit and the second heat dissipation unit simultaneously dissipate heat for at least one switch 1, or, in the event of a failure of the first heat dissipation unit, the second heat dissipation unit is used to dissipate heat for at least one switch 1.

[0104] Specifically, the switch 1 also includes some other important components, namely a second heat dissipation component, which is arranged at the rear window of the switch chassis body to ensure that the heat generated by the switch 1 during operation can be effectively dissipated, thereby maintaining the normal operating temperature of the equipment.

[0105] Furthermore, the second heat dissipation assembly is designed with redundancy in mind. It comprises two key components: a first heat dissipation unit and a second heat dissipation unit. Each heat dissipation unit includes two fans, supporting a 2+2 redundancy design. This means that if the first heat dissipation unit fails, the second heat dissipation unit can independently assume heat dissipation responsibility, ensuring that at least one switch 1 still receives adequate cooling, thereby preventing device failure or performance degradation due to overheating.

[0106] Optionally, in some embodiments, the above-mentioned switch 1 further includes: an overcurrent monitoring unit 50, which is used to send an overcurrent signal to the programmable logic module 26 when an overcurrent fault occurs in any switching board 10, so as to disconnect the power supply channel of the switching board 10 corresponding to the overcurrent signal through the programmable logic module 26.

[0107] It will be appreciated that, to ensure stable system operation and safety, embodiments of the present invention may specifically incorporate an overcurrent monitoring unit 50 into the link. In this manner, the baseboard management controller 22 can monitor the current level in real time using I2C signals. Upon detecting that the current exceeds a preset safety threshold, indicating an overcurrent fault, the baseboard management controller 22 can immediately send a command to the programmable logic module 26 via the I2C communication protocol. Upon receiving the command, the programmable logic module 26 shuts down the P12V_SW unit (the power supply unit that provides 12V voltage to the switch board 10), disconnecting the power supply path to the switch board 10 corresponding to the overcurrent signal, thereby effectively protecting the entire system from overcurrent damage.

[0108] Furthermore, the system topology of the entire switch 1 can be as follows Figure 9 As shown, the P12V_PSU voltage output by the first power supply component 30 and the second power supply component 40 is transmitted to the P12V_STBY (Power 12 Volt Standby Unit, a module that provides backup power). This unit can directly convert the P12V_PSU voltage into P5V_STBY, P3V3_STBY, and P1V2_STBY voltages, which can then be used by the management board 20 and the switch board 10. The P12V_STBY unit can ensure stable system operation during startup or low-power mode, reducing startup failures or system instability caused by power supply problems.

[0109] In addition, the P12V_PSU voltage can also be supplied to the P12V_SW unit, and the programmable logic module 26 can enable the P12V_SW unit through the control signals P12V_SW0_EN and P12V_SW1_EN. This design allows the system to dynamically enable or disable the P12V_SW unit as needed, increasing the flexibility of power management. Once the P12V_SW unit is activated, it can output the P12V_SW0 and P12V_SW1 voltages. These voltages are then further converted to the P1V2_SW, P1V0_SW, and P10V9_SW voltages to meet different power requirements.

[0110] Because different components in switch 1 may require different power supply voltages, the system can generate multiple voltages through conversion by the P12V_STBY unit and the P12V_SW unit to meet the different requirements of the management board 20 and the switch board 10. Under the control of the programmable logic module 26, the system can dynamically adjust the power supply enablement and disablement according to actual needs, optimize power management, and reduce unnecessary energy consumption.

[0111] In summary, the switch provided in the embodiments of the present invention has at least the following beneficial effects:

[0112] (1) This invention meticulously designs two CXL switch nodes (i.e., two switch boards) within a 2U switch chassis, ensuring that heat dissipation performance is not compromised. These nodes not only provide extremely high switching computing density but also offer up to 32 high-speed interconnect interfaces. These interfaces support bandwidth data transmission of up to 2048 GB / s, providing a solid technical foundation and hardware guarantee for high-performance computing, data analysis, and other applications requiring powerful computing power.

[0113] (2) In the present invention, the uplink port of the switch can be connected to the server host, while the downlink port can be connected to the memory expansion card. This design allows a single host to connect to multiple CXL memory expansion cards, thereby obtaining higher bandwidth and higher capacity memory resources under the condition of a limited number of PCIe interfaces. This effectively breaks through the limitation of the number of physical PCIe interfaces on traditional motherboards and provides users with more flexible and powerful memory expansion capabilities.

[0114] (3) The switch in the embodiment of the present invention follows the standard 19-inch rack size, which enables it to perfectly adapt to the front and rear rack requirements in the computer room. Its design not only takes into account the convenience of equipment installation, but also takes into account daily deployment and maintenance work, ensuring the efficient operation and long-term stability of the equipment.

[0115] The switch proposed in accordance with an embodiment of the present invention integrates an advanced configuration supporting two switch boards 10 within a 2U-high switch chassis, enabling the chassis to provide up to 32 high-speed interconnect interfaces. These high-speed interconnect interfaces can support bandwidths up to 2048 GB / s, providing users with unprecedented data transfer speeds. Furthermore, this design allows a single host to easily connect multiple CXL memory expansion cards, effectively breaking the limitations of the number of physical PCIe interfaces on traditional motherboards. Through this innovative connection method, users can fully utilize the superior performance of the CXL bus, obtaining high-bandwidth and high-capacity memory resources, greatly improving the overall performance and scalability of the system.

[0116] An embodiment of the present invention also provides a method for powering on a switch.

[0117] like Figure 10 As shown, the switch power-on method is applied to Figure 6 The switch of an embodiment, wherein the method comprises the following steps:

[0118] In step S1001 , when a power-on instruction is received, the fabric manager is controlled to be powered on, and a switch board power-on signal is sent to a baseboard management controller via the fabric manager.

[0119] It is understandable that the power-on command is usually triggered by a user through a management interface or a physical button (ie, a PWR button (power button) of a management board).

[0120] Specifically, when the user presses the PWR button, the management board receives a power-on command. After receiving the power-on command, the management board controls the fabric manager to power on. After the fabric manager powers on, it generates a power-on signal and sends it to the baseboard management controller via the LPC bus or other communication interface.

[0121] In step S1002, a switch board power-on signal is sent to a programmable logic module via a baseboard management controller, so as to close a power supply channel of at least one switch board via the programmable logic module, so that at least one switch board performs an initialization action after being powered on.

[0122] The baseboard management controller (BMC) is responsible for out-of-band management and control of the entire switch system. It monitors and manages out-of-band information for the entire switch, including PSU status, Power VR (Power Voltage Regulator) status, and system temperature. The programmable logic module (PLM) controls the power supply path for the switch boards. The PLM communicates with the BMC over the I2C bus and receives control commands (i.e., power-on signals) from the BMC. The PLM closes the power supply path by controlling the enable signals (such as P12V_SW0_EN and P12V_SW1_EN) of the P12V_SW unit. These enable signals control the output of the P12V_SW unit, providing 12V power to the switch boards. Once the power supply path is closed, the switch boards will perform initialization after powering on. Initialization includes loading firmware, configuring memory devices, and checking hardware status to ensure proper operation of the switch boards.

[0123] Furthermore, in some embodiments, after at least one switching board completes the initialization action, it also includes: in the event that an overcurrent fault occurs in any switching board, an overcurrent signal is sent to the programmable logic module to disconnect the power supply channel of the switching board corresponding to the overcurrent signal through the programmable logic module.

[0124] Specifically, after the switch board completes initialization, the system continuously monitors the current of each switch board. If an overcurrent fault is detected on a switch board, meaning the current exceeds a preset safety threshold, the system generates an overcurrent signal. This signal indicates an abnormality with the switch board and requires action to prevent further damage. The overcurrent signal is sent by the baseboard management controller to the programmable logic module. Based on the received overcurrent signal, the programmable logic module controls the enable signals of the P12V_SW unit (such as P12V_SW0_EN and P12V_SW1_EN), shutting down the output of the P12V_SW unit and disconnecting the power supply path to the corresponding switch board.

[0125] Furthermore, in some embodiments, after determining that any switching board has an overcurrent fault, it also includes: generating an overcurrent fault reminder instruction based on the overcurrent signal; and performing an acoustic overcurrent reminder and / or an optical overcurrent reminder according to the overcurrent fault reminder instruction.

[0126] Specifically, the baseboard management controller can generate an overcurrent fault reminder instruction based on the overcurrent signal. This instruction is used to notify the system administrator or maintenance personnel so that they can take prompt action to resolve the problem. The overcurrent fault reminder instruction can include specific fault information, such as the faulty switch board number, fault type (overcurrent), and fault time. This information helps to quickly locate and resolve the problem. In addition, based on the overcurrent fault reminder instruction, the system can trigger an acoustic reminder (such as a specific sound signal from a buzzer or alarm) or a visual reminder (such as a specific light signal from one or more indicator lights) to attract the attention of the system administrator or maintenance personnel.

[0127] To further understand the power-on method of the switch proposed in the embodiment of the present invention, Figure 11 For further explanation.

[0128] like Figure 11 As shown, the switch power-on method may further include the following steps:

[0129] Step S1101: Connect a power supply unit (PSU) to a 220V AC power source.

[0130] In step S1102 , the system outputs the standby (STBY) power supply, and the baseboard management controller begins to read its internal FLASH memory to complete its own initialization process. At the same time, the programmable logic module is also powered on and completes its initialization.

[0131] Step S1103: After pressing the power button on the front panel of the switch chassis, the fabric manager starts to power on.

[0132] In step S1104, after the system enters the main operation state, a switch board power-on instruction is sent to the baseboard management controller through the low pin count (LPC) interface. The baseboard management controller converts the power-on instruction into an I2C signal and sends it to the programmable logic module, thereby controlling the switch board to perform initialization actions after power-on is completed.

[0133] The switch power-on method proposed in the embodiment of the present invention achieves efficient, stable, and secure switch system startup and operation. This method not only improves system reliability and availability, but also provides network administrators with a more convenient and intelligent management method.

[0134] Figure 12 This is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. The electronic device may include:

[0135] A memory 1201 , a processor 1202 , and a computer program stored in the memory 1201 and executable on the processor 1202 .

[0136] When the processor 1202 executes the program, the steps in any of the above-mentioned embodiments of the power-on method for a switch are implemented.

[0137] Furthermore, the electronic device further includes:

[0138] The communication interface 1203 is used for communication between the memory 1201 and the processor 1202 .

[0139] The memory 1201 is used to store computer programs that can be run on the processor 1202 .

[0140] The memory 1201 may include a high-speed RAM (Random Access Memory) memory, and may also include a non-volatile memory, such as at least one disk memory.

[0141] If the memory 1201, processor 1202, and communication interface 1203 are implemented independently, the communication interface 1203, memory 1201, and processor 1202 can be connected to each other via a bus and communicate with each other. The bus can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus. Buses can be divided into address buses, data buses, control buses, etc. For ease of representation, Figure 12 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0142] Optionally, in a specific implementation, if the memory 1201, the processor 1202 and the communication interface 1203 are integrated on a chip, the memory 1201, the processor 1202 and the communication interface 1203 can communicate with each other through an internal interface.

[0143] The processor 1202 may be a CPU, or an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0144] An embodiment of the present invention further provides a non-volatile computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned embodiments of the switch power-on method when running.

[0145] In an exemplary embodiment, the non-volatile computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory, a mobile hard disk, a magnetic disk, or an optical disk.

[0146] An embodiment of the present invention further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned embodiments of the method for powering on a switch are implemented.

[0147] An embodiment of the present invention further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above-mentioned embodiments of the switch power-on method are implemented.

[0148] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0149] The above describes in detail the switch power-on method provided by the present invention. This document uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are intended only to facilitate understanding of the method and core concepts of the present invention. It should be noted that those skilled in the art will be able to make various improvements and modifications to the present invention without departing from the principles of the present invention, and such improvements and modifications are also within the scope of protection of the claims of the present invention.

Claims

1. A switch board, characterized in that: include: A first layer board, a second layer board, a switching network chip and at least one group of connectors, wherein: The first layer plate includes at least one first expansion port; The second layer plate includes at least one second expansion port; The first layer board and the second layer board are plug-connected via at least one set of the connectors; The switching network chip is provided on the first layer board, and the switching network chip is used to configure and manage at least one of the first extension ports, and / or to configure and manage at least one of the second extension ports through at least one group of the connectors; Among them, each group of connectors includes a first connection unit and a second connection unit, the first connection unit of each group of connectors is set on the first layer board and is connected to the switching network chip, the second connection unit of each group of connectors is set on the second layer board and is correspondingly connected to at least one of the second expansion ports, and the positions of the first connection unit and the second connection unit of each group of connectors are correspondingly set.

2. The switch board according to claim 1, characterized in that: At least one group of the connectors uses a high-density connector and / or a mini edge input and output cable.

3. The switch board according to claim 1, characterized in that: The positions of at least one of the first extension ports and at least one of the second extension ports correspond to each other, and the first extension ports and the second extension ports with corresponding positions are located in the same column.

4. The exchange board according to claim 1, characterized in that Also includes: An Ethernet physical layer interface module, configured to convert a received first signal into a second signal; A network interface is connected to the Ethernet physical layer interface module, and remote system maintenance and remote management are performed through the network interface, and / or out-of-band remote maintenance and management are performed.

5. The exchange board according to claim 1, characterized in that: Also includes: A serial peripheral interface multiplexer, configured to determine a target communication device based on a control signal sent by the switching network chip; The storage unit is used to store firmware parameters and configuration parameters required for the operation of the switching network chip, so that when the switching network chip performs an initialization operation, the firmware parameters and the configuration parameters are read from the storage unit.

6. The exchange board according to claim 1, characterized in that Also includes: A clock generator, used to generate a clock signal that meets preset requirements; A clock buffer is used to process the clock signal to obtain a signal that meets the timing requirements of the switching network chip, so that the switching network chip works based on the signal that meets the timing requirements of the switching network chip.

7. A switch, characterized in that: include: At least one exchange board according to any one of claims 1 to 6; A management board is used to obtain device configuration information of at least one of the switch boards, and send configuration instructions to the switch network chip of at least one of the switch boards according to the device configuration information, so as to complete the memory expansion configuration through the switch network chip of at least one of the switch boards.

8. The switch according to claim 7, wherein: The management board includes: a structure manager and a baseboard management controller, wherein: The fabric manager and the baseboard management controller communicate via a first bus; The baseboard management controller is used to control power-on of at least one of the switch boards according to the power-on information of the structure manager.

9. The switch according to claim 8, characterized in that The structure manager includes: at least one management interface and at least one transmission interface, wherein: The fabric manager obtains device configuration information of at least one of the switch boards through at least one of the management interfaces; The fabric manager sends the configuration instruction to a switching network chip of at least one of the switching boards through at least one of the transmission interfaces.

10. The switch according to claim 7, wherein: The management board further includes: an Ethernet control module, configured to convert the received third signal into a fourth signal; The Ethernet switch is configured to convert the fourth signal into the first signal.

11. The switch according to claim 9, wherein: The management board further includes: An expansion module is used to expand any management interface of the structure manager into at least two management interfaces.

12. The switch according to claim 7, wherein: The management board further includes: a programmable logic module and a first heat dissipation component, wherein: The programmable logic module is used to obtain the actual rotation speed of the first heat dissipation component to adjust the PWM signal of the first heat dissipation component according to the actual rotation speed.

13. The switch according to claim 7, wherein: Also includes: Switch Chassis body, wherein In the case where the switch includes two switch boards, the two switch boards are arranged in an overlapping manner, and after the overlapping manner, they are arranged in sequence with the management board along the first direction on the switch chassis body, and the first direction is the direction from the rear of the switch chassis to the front of the switch chassis.

14. The switch according to claim 13, wherein: The two exchange boards are respectively arranged on a first exchange board tray and a second exchange board tray, and the first exchange board tray and the second exchange board tray are locked and fixed to the switch chassis body through a locking mechanism.

15. The switch according to claim 13, wherein: Also includes: A first power supply component and a second power supply component are provided on the switch chassis body; In the event of a failure of the first power supply component, power is supplied to at least one of the switch boards via the second power supply component.

16. The switch according to claim 13, wherein: Also includes: A second heat dissipation component is provided on the switch chassis body, wherein: The second heat dissipation assembly includes a first heat dissipation unit and a second heat dissipation unit, wherein: The first heat dissipation unit and the second heat dissipation unit dissipate heat for at least one switch simultaneously, or, in the event of a failure of the first heat dissipation unit, the second heat dissipation unit dissipates heat for at least one switch.

17. The switch according to claim 13, wherein: Also includes: The overcurrent monitoring unit is used to send an overcurrent signal to the programmable logic module when an overcurrent fault occurs in any of the switch boards, so as to disconnect the power supply channel of the switch board corresponding to the overcurrent signal through the programmable logic module.

18. A method for powering on a switch, characterized in that: The method is applied to the switch according to any one of claims 7 to 17, wherein the method comprises the following steps: When receiving a power-on instruction, controlling the fabric manager to power on, and sending a switch board power-on signal to the baseboard management controller via the fabric manager; The baseboard management controller sends the switch board power-on signal to the programmable logic module, so as to close the power supply channel of at least one of the switch boards through the programmable logic module, so that at least one of the switch boards performs initialization after being powered on.

19. The method according to claim 18, characterized in that After at least one of the switch boards completes the initialization action, the method further includes: In the event that an overcurrent fault occurs on any of the switch boards, an overcurrent signal is sent to the programmable logic module, so that the programmable logic module disconnects the power supply channel of the switch board corresponding to the overcurrent signal.

20. The method according to claim 19, characterized in that After determining that any of the switch boards has an overcurrent fault, the method further includes: generating an overcurrent fault reminder instruction based on the overcurrent signal; An acoustic overcurrent reminder and / or an optical overcurrent reminder is performed according to the overcurrent fault reminder instruction.

21. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the power-on method of the switch according to any one of claims 18 to 20.

22. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement the power-on method of a switch according to any one of claims 18 to 20.

23. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the power-on method of the switch according to any one of claims 18 to 20 is implemented.

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