Semiconductor structure, preparation method thereof and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor structure, a preparation method thereof and electronic equipment. The preparation method of the semiconductor structure comprises the following steps: providing a substrate, and sequentially and alternately forming first insulating layers and sacrificial layers on one side of the substrate; forming a plurality of first grooves and a plurality of second grooves, wherein the plurality of first grooves divide at least part of the structure of the sacrificial layer into a plurality of sub sacrificial layers; the side wall of the second groove exposes the end parts of the first insulating layer and the plurality of sub sacrificial layers; filling the first groove with a second insulating layer; performing wet etching back on the end parts of the exposed sub sacrificial layers to form a plurality of first transverse grooves; forming a plurality of inner electrodes in the plurality of first transverse grooves according to the shapes of the first transverse grooves; a dielectric layer and an outer electrode are sequentially formed at least in the first transverse groove and the second groove, and the multiple inner electrodes, the dielectric layer and the outer electrode form multiple capacitors. The embodiment of the invention realizes the purpose of reducing the collapse possibility of the inner electrode of the capacitor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology. Specifically, this application relates to a semiconductor structure, a method for manufacturing the same, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are increasingly reduced, and the types and quantities of devices included in a single chip increase accordingly. As a result, minor differences in the process production may affect the device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's Law came out, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the requirements of current products. Summary of the Invention

[0004] This application provides a semiconductor structure, a method for manufacturing the same, and an electronic device. During the manufacturing process, the inner electrode of the capacitor has support, making its structure stable and reducing the possibility of collapse.

[0005] In a first aspect, an embodiment of this application provides a method for manufacturing a semiconductor structure, including:

[0006] Providing a substrate;

[0007] Successively and alternately forming a first insulating layer and a sacrificial layer on one side of the substrate;

[0008] Through patterning, forming a plurality of first trenches arranged at intervals in a first direction parallel to the substrate and second trenches spaced in a second direction parallel to the substrate. The sidewalls of the first trenches expose the first insulating layer and the sacrificial layer. At least part of the structure of the sacrificial layer is separated into a plurality of sub-sacrificial layers by the plurality of first trenches; the second trenches extend in the first direction, and the sidewalls of the second trenches expose the first insulating layer and the ends of the plurality of sub-sacrificial layers. The first direction and the second direction intersect;

[0009] Filling the first trenches with a second insulating layer; performing wet etching back on the exposed ends of the plurality of sub-sacrificial layers to form a plurality of first lateral grooves. The inner walls of each first lateral groove expose the ends of the remaining sub-sacrificial layers after etching back, two adjacent layers of the first insulating layer, and the second insulating layer in the adjacent first trenches;

[0010] Forming a plurality of inner electrodes in the plurality of first lateral grooves according to the shape of the first lateral grooves;

[0011] Successively forming a dielectric layer and an outer electrode at least in the first lateral grooves and the second trenches. The dielectric layer covers the inner electrodes, the first insulating layer, and the second insulating layer, and the outer electrode covers the dielectric layer. The plurality of inner electrodes respectively form a plurality of capacitors with the dielectric layer and the outer electrode.

[0012] In some optional embodiments of the present application, a plurality of first transverse grooves are formed, including:

[0013] The exposed multiple sub-sacrificial layers are wet-etched back in the second trench to form a plurality of first transverse grooves stacked in a direction perpendicular to the substrate and extending in the second direction.

[0014] In some optional embodiments of the present application, a plurality of inner electrodes are formed, including:

[0015] A conductive layer is deposited in the first transverse groove and the second trench, and the conductive layer in the second trench is removed, so that the conductive layers in each first transverse groove are disconnected, forming a plurality of independent inner electrodes located only on the inner wall of the first transverse groove.

[0016] In some optional embodiments of the present application, before removing the conductive layer in the second groove, a dummy film layer is formed on the conductive layer; part of the dummy film layer in the second groove is removed by dry etching; and the conductive layer and the remaining dummy film layer in the second groove are removed by wet etching, thereby separating the conductive layer formed in the multiple first lateral grooves into multiple internal electrodes.

[0017] In some optional embodiments of the present application, after forming the plurality of inner electrodes and before forming the dielectric layer and the outer electrodes, the method for preparing the semiconductor structure further includes:

[0018] The first insulating layer and the second insulating layer on the outer surface of the inner electrode are etched back in the second trench to form a second transverse groove surrounding the outer surface of the inner electrode.

[0019] In some optional embodiments of the present application, a dielectric layer and a first conductive material are deposited in the first transverse groove, the second transverse groove, and the second trench in sequence. The shape of the dielectric layer is adapted to the shape of the inner walls of the first transverse groove and the second transverse groove. The first conductive material covers the dielectric layer to form an external electrode.

[0020] In a second aspect, an embodiment of the present application provides a semiconductor structure, including:

[0021] substrate;

[0022] A plurality of first insulating layers, a plurality of transistors, and a plurality of second insulating layers, wherein the first insulating layers and the transistors are alternately arranged on one side of a substrate, a first trench is provided between the plurality of first insulating layers arranged in sequence along a first direction, and the second insulating layer is provided in the first trench to isolate the first insulating layer from the transistors; the source or drain of the transistor, the first insulating layer, and the second insulating layer form a transverse trench extending along the second direction; the first insulating layer and the second insulating layer form a second trench extending along the first direction, the second trench being located on a side of the transverse trench away from the transistors and being in communication with the transverse trench;

[0023] Multiple capacitors, each capacitor includes an inner electrode, a dielectric layer and an outer electrode, a ring-shaped inner electrode portion of the inner electrode is located in the transverse groove, the inner electrode is in contact with the source or drain of the transistor and the sidewall is exposed, the dielectric layer is distributed at least on the inner wall of the inner electrode, and the outer electrode is arranged at least on the inner wall of the inner electrode and located on the dielectric layer.

[0024] In some optional embodiments of the present application, the outer wall of the inner electrode, the first insulating layer and the second insulating layer form a second transverse groove, the dielectric layer is also arranged on the inner wall of the second transverse groove, and the outer electrode is also arranged on the inner wall of the second transverse groove and located on the dielectric layer.

[0025] In some optional embodiments of the present application, the first insulating layer and the second insulating layer are made of the same material; and / or,

[0026] The inner electrode has a single-layer structure or a multi-layer structure.

[0027] In some optional embodiments of the present application, the inner electrode is cylindrical, and the opening of the inner electrode faces away from the transistor;

[0028] The outer electrode surrounds the outer wall, the inner wall and the bottom of the inner electrode to form an integrated structure.

[0029] In some optional embodiments of the present application, a size of the inner electrode along the second direction is greater than a size of the outer electrode disposed around the outer wall of the inner electrode along the second direction.

[0030] In some optional embodiments of the present application, the external electrode is a conductive layer arranged on the inner wall of the internal electrode and in the second transverse groove, and the semiconductor structure also includes a connection structure, which fills the inner wall of the internal electrode, the second transverse groove and the second groove, and the connection structure is electrically connected to each external electrode exposed in the second groove.

[0031] In a third aspect, an embodiment of the present application provides an electronic device, comprising the above-mentioned semiconductor structure, or comprising a semiconductor structure manufactured using the above-mentioned semiconductor structure preparation method.

[0032] The beneficial technical effects brought about by the technical solutions provided in the embodiments of the present application include:

[0033] In the embodiment of the present application, a plurality of first trenches and second trenches are formed on the first insulating layer and the sacrificial layer stack structure. The plurality of first trenches are arranged at intervals in a first direction in sequence to separate at least part of the structure of the sacrificial layer into a plurality of sub-sacrificial layers. The side walls of the first trenches expose the first insulating layer and the sacrificial layer. The second insulating layer is filled in the first trenches, and the second insulating layer is in contact with the first insulating layer and the sacrificial layer exposed by the first trenches respectively. The plurality of sub-sacrificial layers are arranged in an array in the first direction and the direction perpendicular to the substrate. The first trenches extend in a second direction, the sub-sacrificial layers extend in the second direction, one end of the first trenches in the second direction communicates with the second trenches, the second trenches extend in the first direction, and the side walls of the second trenches expose the first insulating layer and the plurality of sub-sacrificial layers so as to remove the sub-sacrificial layers. After a part of the structure of the plurality of sub-sacrificial layers exposed by the second trenches is removed, a plurality of first transverse grooves are correspondingly formed. The inner walls of each first transverse groove expose the remaining sub-sacrificial layers, the first insulating layer and the second insulating layer. Then, a plurality of inner electrodes are correspondingly formed in the plurality of first transverse grooves. The inner electrodes cover the exposed remaining sub-sacrificial layers, the first insulating layer and the second insulating layer. The first insulating layer and the second insulating layer can well fix the inner electrodes and play a role in supporting the inner electrodes, so as to ensure that the inner electrodes will not collapse. Then, a dielectric layer and an outer electrode are sequentially formed in the first transverse grooves and the second trenches. The dielectric layer covers the inner electrodes, the first insulating layer and the second insulating layer, and the outer electrode covers the dielectric layer. The plurality of inner electrodes respectively form a plurality of capacitors with the dielectric layer and the outer electrode.

[0034] The preparation method of the semiconductor structure according to the embodiment of the present application is simple and feasible. Since the inner electrodes of the capacitors are supported during the manufacturing process, the structure of the inner electrodes is stable, and the possibility of collapse is reduced.

[0035] Additional aspects and advantages of the present application will be given in part in the following description, and these will become obvious from the following description, or can be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and / or additional aspects and advantages of the present application will become obvious and easy to understand from the following description of the embodiments in conjunction with the drawings, wherein:

[0037] Figures 1 to 51 is a schematic structural diagram at different processes in a method for preparing a semiconductor structure provided by an embodiment of the present application;

[0038] Figures 52 to 55 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present application;

[0039] Figure 56 is an equivalent circuit diagram of a semiconductor structure provided by an embodiment of the present application.

[0040] Reference Signs:

[0041] 100 - Semiconductor structure; 10 - Substrate; 11 - Bit line region to be formed; 12 - Transistor region to be formed; 13 - Capacitor region to be formed; 20 - Insulating structure; 21 - First insulating layer; 22 - Second insulating layer; 23 - First initial insulating layer; 24 - Third insulating layer; 30 - Sacrificial layer; 31 - Sub - sacrificial layer; 32 - First partial structure; 33 - Second partial structure; 41 - First trench; 42 - Second trench; 43 - First lateral groove; 44 - Second lateral groove; 50 - Capacitor; 51 - Inner electrode; 52 - Dielectric layer; 53 - Outer electrode; 54 - Conductive layer; 55 - dummy film layer; 56 - Connection structure; 61 - First mask structure; 62 - Second mask structure; 63 - Spacer layer; 64 - Third mask structure; 71 - Word line hole; 72 - dummy word line. Detailed implementation manners

[0042] The embodiments of the present application will be described below with reference to the accompanying drawings in the present application. It should be understood that the embodiments described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application, and do not constitute limitations on the technical solutions of the embodiments of the present application.

[0043] Those skilled in the art of the present technology can understand that, unless specifically stated otherwise, the singular forms "a", "an", "the" and "said" used herein may also include the plural forms. It should be further understood that the term "including" used in the description of the present application means the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the art of the present technology. The term "and / or" used herein means at least one of the items defined by the term, for example, "A and / or B" can be implemented as "A", or implemented as "B", or implemented as "A and B".

[0044] To make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0045] Currently, the preparation scheme of capacitors in semiconductor structures includes making the inner electrode plate into a solid - structure column, and sequentially forming a dielectric layer and an outer electrode plate on the outer periphery of the columnar inner electrode plate to form a capacitor. This scheme has the possibility of collapse of the inner electrode plate.

[0046] The semiconductor structure, its preparation method and electronic device provided by the present application aim to solve the above - mentioned technical problems in the prior art.

[0047] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments. It should be noted that the following embodiments can refer to, draw on, or combine with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0048] The present invention provides a method for preparing a semiconductor structure. The structural diagrams of the semiconductor structure during different processes are shown in FIG. Figures 1 to 51 The method for preparing the semiconductor structure includes:

[0049] S101 , providing a substrate 10 .

[0050] S102, a first insulating layer 21 and a sacrificial layer 30 are alternately formed on one side of the substrate 10, as shown in FIG. Figure 1 As shown. Optionally, the material of the first insulating layer 21 includes, but is not limited to, oxide (e.g., silicon oxide). The material of the sacrificial layer 30 includes, but is not limited to, nitride (e.g., silicon nitride). The first insulating layer 21 and the sacrificial layer 30 alternately form a stacked structure of silicon oxide and silicon nitride.

[0051] S103, such as Figure 3 As shown, through graphical processing, a plurality of first trenches 41 extending along the second direction and spaced apart in sequence along a first direction parallel to the substrate 10 and a second trench 42 extending along the first direction and spaced apart along the second direction parallel to the substrate 10 are formed, the sidewalls of the first trenches 41 expose the first insulating layer 21 and the sacrificial layer 30, and the plurality of first trenches 41 separate at least part of the structure of the sacrificial layer 30 into a plurality of sub-sacrificial layers 31; the second trenches 42 extend along the first direction, and the sidewalls of the second trenches 42 expose the first insulating layer 21 and the end portions of the plurality of sub-sacrificial layers 31, and the first direction and the second direction intersect.

[0052] The first trench 41 is used to isolate adjacent memory cells in a column of memory cells, and the second trench 42 is used to isolate adjacent columns of memory cells.

[0053] The first insulating layer 21 and the sacrificial layer 30 excluding the first trench 41 and the second trench 42 at least include a plurality of memory cell regions extending along the second direction and a bit line region extending along the first direction.

[0054] S104. Fill the first trench 41 with the second insulating layer 22. At the ends of the multiple sub-sacrificial layers 31, remove the exposed portions of the sub-sacrificial layers 31 by wet etching back to form a plurality of first transverse grooves 43. The first transverse grooves 43 are formed by wet etching back the sub-sacrificial layers 31 to a certain depth (corresponding to the depth of the capacitor electrode) in the memory cell area. At this point, the bottom of the first transverse groove 43 is the location where the etching of the sub-sacrificial layer 31 stops. The upper, lower, front, and rear sidewalls of the first transverse groove 43 are the adjacent first insulating layer 21 exposed by the wet etching and the second insulating layer 22 in the adjacent first trench 41.

[0055] Optionally, the material of the second insulating layer 22 is an insulating material, including but not limited to oxide (e.g., silicon oxide). The material of the second insulating layer 22 can be the same as or different from the material of the first insulating layer 21; the material of the second insulating layer 22 is different from the material of the sacrificial layer 30.

[0056] S105. A plurality of internal electrodes 51 are formed in the plurality of first transverse grooves 43 according to the shape of the first transverse grooves. The internal electrodes 51 are formed in various areas of the inner wall of the first transverse groove 43, for example, covering the exposed end of the remaining sub-sacrificial layer 31, the walls of the first insulating layer 21 and the second insulating layer 22 without filling the first transverse groove 43. The internal electrodes 51 in the first transverse grooves 43 of different layers are disconnected from each other and maintained insulated.

[0057] S106. A dielectric layer 52 and an external electrode 53 are sequentially formed at least in the first transverse groove 43 and the second groove 42. The dielectric layer 52 is formed on the inner wall of the first transverse groove 43 to cover the inner electrode 51 and the first insulating layer 21 and the second insulating layer 22 in the second groove 42. The external electrode 53 covers the dielectric layer. Multiple mutually insulated inner electrodes 51 respectively form multiple capacitors 50 with the dielectric layer 52 and the external electrode 53.

[0058] In the embodiment of the present application, the substrate 10 is used to support the first insulating layer 21 , the sacrificial layer 30 , the second insulating layer 22 and the capacitor 50 .

[0059] In the embodiment of the present application, a plurality of first trenches 41 and second trenches 42 are formed on the stacked structure of the first insulating layer 21 and the sacrificial layer 30. The plurality of first trenches 41 are sequentially spaced along the first direction to separate at least a portion of the structure of the sacrificial layer 30 into a plurality of sub-sacrificial layers 31. The sidewalls of the first trenches 41 expose the first insulating layer 21 and the sacrificial layer 30 (the portion of the sacrificial layer 30 exposed by the first trenches 41 includes a portion of the structure of the sacrificial layer 30 that is not separated and the sub-sacrificial layers 31 that are separated). The first trenches 41 are filled with the first trenches 41. The second insulating layer 22 is in contact with the first insulating layer 21 and the sacrificial layer 30 exposed by the first trench 41 respectively; a plurality of sub-sacrificial layers 31 are arranged in an array along the first direction and perpendicular to the substrate 10, the first trench 41 extends along the second direction, the sub-sacrificial layer 31 extends along the second direction, one end of the first trench 41 along the second direction is connected to the second trench 42, the second trench 42 extends along the first direction, and the sidewall of the second trench 42 exposes the first insulating layer 21 and the plurality of sub-sacrificial layers 31, so as to perform After the partial structures of the multiple sub-sacrificial layers 31 exposed by the second grooves 42 are removed, multiple first transverse grooves 43 are correspondingly formed, and the inner wall of each first transverse groove 43 exposes the remaining sub-sacrificial layer 31, the first insulating layer 21 and the second insulating layer 22; then, multiple internal electrodes 51 are formed in the multiple first transverse grooves 43 in a one-to-one correspondence, and the internal electrodes 51 cover the exposed remaining sub-sacrificial layers 31, the first insulating layer 21 and the second insulating layer 22 without filling the first transverse grooves 43. The internal electrodes 51 are hollow cylindrical structures. The first insulating layer 21 and the second insulating layer 22 can well fix the inner electrode 51 and support the inner electrode 51, thereby ensuring that the inner electrode 51 does not collapse; then, a dielectric layer 52 and an outer electrode 53 are sequentially formed in the first transverse groove 43 and the second groove 42, the dielectric layer 52 covers the inner electrode 51, the first insulating layer 21 and the second insulating layer 22, the outer electrode 53 covers the dielectric layer 52 and fills the first transverse groove 43, and the multiple inner electrodes 51 respectively form multiple capacitors 50 with the dielectric layer 52 and the outer electrode 53.

[0060] The manufacturing method of the semiconductor structure of the embodiment of the present application is simple and feasible. Since the inner electrode of the capacitor is supported by the first insulating layer during the manufacturing process, the structure of the inner electrode is stable, reducing the possibility of collapse.

[0061] In the embodiment of the present application, the inner electrode 51 is cylindrical with its opening parallel to the substrate. Optionally, the inner electrode 51 is formed by etching a sacrificial layer between adjacent first insulating layers. The inner electrode 51 has a rectangular or rectangular-like shape in a longitudinal cross-section perpendicular to the substrate 10 and along the direction in which the second trench extends.

[0062] An embodiment of the present application proposes a brand-new method for manufacturing a cylindrical inner electrode capacitor. Since the inner electrode of the capacitor is formed in a groove, and the groove is supported by the upper and lower first insulating layers and has a cylindrical structure, its structure is more stable and not prone to collapse.

[0063] Optionally, the first direction is perpendicular to the second direction.

[0064] Figure 2 It is a top view during the manufacturing process of the semiconductor structure preparation method according to the embodiment of the present application. As Figure 2 shown, in the embodiment of the present application, the a-a direction and the b-b direction are parallel to the second direction, and the c-c direction and the d-d direction are parallel to the first direction.

[0065] In some optional implementation manners of the present application, as Figure 2 shown, after forming the first insulating layer 21 and the sacrificial layer 30 and before forming the first trench 41 and the second trench 42, the semiconductor structure preparation method further includes:

[0066] Through patterning, a word line hole 71 is formed. The orthographic projection of the word line hole 71 on the substrate 10 overlaps with the transistor region 12 to be formed on the substrate 10, and the side walls of the word line hole 71 expose the first insulating layer 21 and the sacrificial layer 30.

[0067] Next, a dummy word line 72 is formed in the word line hole 71, and the dummy word line 72 fills the word line hole 71. The dummy word line 72 needs to be removed after the capacitor 50 is manufactured, and then the gate and word line of the transistor are manufactured at the position where the dummy word line 72 is located.

[0068] Optionally, the material of the dummy word line 72 includes but is not limited to polycrystalline materials (poly), such as polysilicon.

[0069] Figure 3 It is a top view during the manufacturing process of the semiconductor structure preparation method according to the embodiment of the present application.

[0070] In some optional implementation manners of the present application, as Figure 2 and Figure 3 shown, forming the first trench 41 and the second trench 42 includes:

[0071] As Figure 2 shown, a first mask structure 61 is fabricated on the side of the topmost sacrificial layer 30 away from the substrate 10. Optionally, a hard mask (HM) can be fabricated by deposition to form the first mask structure 61.

[0072] Next, as Figure 2 shown, the first mask structure 61 is patterned so that the first mask structure 61 has a first preset pattern (such asFigure 2 As shown, the orthographic projection of the first preset pattern on the substrate 10 overlaps with the bit line region 11 to be formed, the transistor region 12 to be formed, and the capacitor region 13 to be formed on the substrate 10, respectively. The bit line region 11 to be formed extends along a first direction, the transistor region 12 to be formed, and the capacitor region 13 to be formed are sequentially arranged along a second direction, and the capacitor region 13 to be formed is located on the side of the transistor region 12 to be formed away from the bit line region 11 to be formed. The orthographic projection of the first preset pattern on the substrate 10 overlaps with the bit line region 11 to be formed, the transistor region 12 to be formed, and the capacitor region 13 to be formed on the substrate 10, respectively, so as to remove structures in areas other than the bit line region 11 to be formed, the transistor region 12 to be formed, and the capacitor region 13 to be formed. Optionally, the first mask structure 61 can be patterned by photolithography so that the first mask structure 61 has the first preset pattern.

[0073] It should be noted that, in the embodiments of this application, Figure 2 As shown, only one bit line region 11 to be formed, two transistor regions 12 to be formed, and two capacitor regions 13 to be formed are shown for illustration purposes only. It is understood that the semiconductor structure prepared in the embodiment of the present application can have multiple transistor regions 12 to be formed and multiple capacitor regions 13 to be formed arranged in rows and columns in a plane, or can have multiple transistor regions 12 to be formed and multiple capacitor regions 13 to be formed arranged in a three-dimensional stack in a direction perpendicular to the substrate 10. The number and arrangement of the bit line regions 11 to be formed can also be adjusted accordingly, which will not be further described here.

[0074] Then, if Figure 3 As shown, based on the patterned first mask structure 61, the first insulating layer 21 and the sacrificial layer 30 are etched to form a first trench 41 and a second trench 42. Alternatively, STI (shallow trench isolation) trenches can be dry-etched to form the first trench 41 and the second trench 42, thereby separating at least a portion of the sacrificial layer 30 into a plurality of sub-sacrificial layers 31 spaced sequentially along the first direction. The plurality of sub-sacrificial layers 31 are exposed through the second trench 42 located at one end in the second direction, thereby facilitating the subsequent removal of the first portion 32 of the sub-sacrificial layer 31.

[0075] Figure 4 This is an aa-axis cross-sectional view of the semiconductor structure preparation method of the embodiment of the present application during the preparation process. Figure 5 This is a bb-axis cross-sectional view of the semiconductor structure manufacturing method according to an embodiment of the present application during the manufacturing process. Figure 6 This is a cc-direction cross-sectional view of the semiconductor structure manufacturing method according to an embodiment of the present application during the manufacturing process. Figure 7This is a dd-axis cross-sectional view of the semiconductor structure manufacturing method during the manufacturing process of an embodiment of the present application.

[0076] Figure 8 This is a top view of the semiconductor structure manufacturing method during the manufacturing process according to an embodiment of the present application. Figure 9 for Figure 8 The aa-axis cross-section diagram, Figure 10 for Figure 8 Middle bb section, Figure 11 for Figure 8 The cc section diagram, Figure 12 for Figure 8 Mid-dd section view.

[0077] Figure 13 This is a top view of the semiconductor structure manufacturing method during the manufacturing process according to an embodiment of the present application. Figure 14 for Figure 13 The aa-direction cross-section diagram, Figure 15 for Figure 13 Middle bb section, Figure 16 for Figure 13 The cc section diagram, Figure 17 for Figure 13 Mid-dd section view.

[0078] In some optional embodiments of the present application, such as Figures 4 to 17 As shown, the first trench 41 is filled with the second insulating layer 22, including:

[0079] like Figures 4 to 7 As shown, a first initial insulating layer 23 is formed in the first trench 41 and the second trench 42. The first initial insulating layer 23 completely fills the first trench 41 and the second trench 42. Optionally, the material of the first initial insulating layer 23 includes, but is not limited to, oxide (e.g., silicon oxide). The material of the first initial insulating layer 23 can be the same as or different from the material of the first insulating layer 21.

[0080] Then, if Figures 9 to 12 As shown, a third insulating layer 24 is formed on a side of the topmost sacrificial layer 30 away from the substrate 10. The third insulating layer 24 covers the topmost sacrificial layer 30 and the first initial insulating layer 23. Optionally, the material of the third insulating layer 24 includes, but is not limited to, oxide (e.g., silicon oxide). The material of the third insulating layer 24 can be the same as or different from the material of the first insulating layer 21.

[0081] Then, if Figures 8 to 17As shown, the first initial insulating layer 23 and the third insulating layer 24 are patterned to remove a portion of the third insulating layer 24 corresponding to the second groove 42 and the first initial insulating layer 23 filled in the second groove 42, exposing the first insulating layer 21, multiple sub-sacrificial layers 31 and the first initial insulating layer 23 remaining in the first groove 41, wherein: the first initial insulating layer 23 remaining in the first groove 41 forms the second insulating layer 22.

[0082] The exposed sub-sacrificial layers 31 are ends of the sub-sacrificial layers 31 extending along the second direction.

[0083] In some optional embodiments of the present application, such as Figures 4 to 7 As shown, forming a first initial insulating layer 23 includes:

[0084] The first trench 41 and the second trench 42 are filled with insulating material by spin coating. Alternatively, the STI trench can be filled by SOD (Spin-On Dielectric) spin coating.

[0085] Then, the semiconductor device formed with the insulating material is annealed to solidify the insulating material and make it more compact. Optionally, the purpose of solidification and compaction can be achieved by performing high-temperature annealing on the insulating material.

[0086] Next, the insulating material is planarized so that the surface of the insulating material away from the substrate 10 is flush with the surface of the topmost sacrificial layer 30 away from the substrate 10, thereby forming a first initial insulating layer 23. Alternatively, the insulating material (such as silicon oxide) can be planarized by chemical mechanical polishing (CMP).

[0087] In some optional embodiments of the present application, such as Figures 8 to 17 As shown, the first initial insulating layer 23 is patterned, including:

[0088] like Figures 8 to 12 As shown, a second mask structure 62 is formed on a side of the third insulating layer 24 away from the substrate 10. Alternatively, a hard mask (HM) can be formed by deposition to form the second mask structure 62.

[0089] Then, if Figures 8 to 12 As shown, the second mask structure 62 is patterned so that the second mask structure 62 has a second preset pattern (eg Figure 8), the orthographic projection of the second predetermined pattern on the substrate 10 does not overlap with the first initial insulating layer 23 filled in the second trench 42, so as to remove the first initial insulating layer 23 filled in the second trench 42. Optionally, the second mask structure 62 can be patterned by photolithography so that the second mask structure 62 has the second predetermined pattern.

[0090] Then, if Figures 13 to 17 As shown, based on the patterned second mask structure 62, the third insulating layer 24 and the first initial insulating layer 23 are etched to form the second insulating layer 22. Optionally, the third insulating layer 24 and the first initial insulating layer 23 can be dry-etched to remove the first initial insulating layer 23 filling the second trench 42, and the first initial insulating layer 23 remaining in the first trench 41 forms the second insulating layer 22. After the first initial insulating layer 23 filling the second trench 42 is removed, the second trench 42 reappears, and the sidewalls of the second trench 42 expose the first insulating layer 21, the multiple sacrificial sub-layers 31, and the second insulating layer 22.

[0091] Figure 18 This is a top view of the semiconductor structure manufacturing method during the manufacturing process according to an embodiment of the present application. Figure 19 for Figure 18 The aa-direction cross-section diagram, Figure 20 for Figure 18 Middle bb section, Figure 21 for Figure 18 The cc section diagram, Figure 22 for Figure 18 Mid-dd section view.

[0092] In some optional embodiments of the present application, such as Figures 18 to 22 As shown, the exposed portions of the sub-sacrificial layers 31 are removed by wet etching the ends of the sub-sacrificial layers 31 to form a plurality of first transverse grooves 43, including:

[0093] The exposed ends of the multiple sub-sacrificial layers 31 are etched (etch-back) in a direction parallel to the substrate 10 within the second trench 42 to remove the first portion 32 of each sub-sacrificial layer 31 where its orthographic projection on the substrate 10 overlaps with the capacitor region 13 to be formed on the substrate 10. A first transverse groove 43 is formed correspondingly at the location where the first portion 32 of each sub-sacrificial layer 31 is removed. The bottom of the first transverse groove 43 is the end of the sub-sacrificial layer 31 formed after the wet etch-back process, and the sidewalls of the first transverse groove 43 are the surfaces of the upper and lower first insulating layers 21 and the second insulating layer 22 filled with the first trench 41. The multiple first transverse grooves 43 are stacked in a direction perpendicular to the substrate 10 and extend in the second direction.

[0094] Optionally, in the second trench 42, the exposed multiple sub-sacrificial layers 31 can be laterally etched in a direction parallel to the substrate 10 by wet etching to remove the first part of the structure 32. The space vacated after the first part of the structure 32 is removed forms a first lateral groove 43. The position, shape, and size of each first lateral groove 43 are the same as those of the first part of the structure 32 of the removed sub-sacrificial layer 31. The etching depth of the sub-sacrificial layer 31 is the length of the capacitor 50.

[0095] Figure 23 It is a top view during the preparation of the semiconductor structure manufacturing method according to an embodiment of the present application. Figure 24 is Figure 23 the sectional view taken along the a-a direction in Figure 25 is Figure 23 the sectional view taken along the b-b direction in Figure 26 is Figure 23 the sectional view taken along the c-c direction in Figure 27 is Figure 23 the sectional view taken along the d-d direction in

[0096] Figure 28 It is a top view during the preparation of the semiconductor structure manufacturing method according to an embodiment of the present application. Figure 29 is Figure 28 the sectional view taken along the a-a direction in Figure 30 is Figure 28 the sectional view taken along the b-b direction in Figure 31 is Figure 28 the sectional view taken along the c-c direction in Figure 32 is Figure 28 the sectional view taken along the d-d direction in

[0097] Figure 33 It is a top view during the preparation of the semiconductor structure manufacturing method according to an embodiment of the present application. Figure 34 is Figure 33 the sectional view taken along the a-a direction in Figure 35 is Figure 33 the sectional view taken along the b-b direction in Figure 36 is Figure 33 the sectional view taken along the c-c direction in Figure 37 is Figure 33 the sectional view taken along the d-d direction in

[0098] Figure 38 It is a top view during the preparation of the semiconductor structure manufacturing method according to an embodiment of the present application. Figure 39 is Figure 38 the sectional view taken along the a-a direction in Figure 40 is Figure 38 the sectional view taken along the b-b direction in Figure 41 is Figure 38 the sectional view taken along the c-c direction in Figure 42 is Figure 38Mid-dd section view.

[0099] In some optional embodiments of the present application, such as Figures 23 to 42 As shown, a plurality of internal electrodes 51 are formed in a one-to-one correspondence within the plurality of first transverse grooves 43, including:

[0100] like Figures 23 to 27 As shown, a conductive layer 54 and a dummy film layer 55 are sequentially formed in the first transverse groove 43 and the second trench 42. The conductive layer 54 covers the exposed remaining sub-sacrificial layer 31, the first insulating layer 21, the second insulating layer 22, and the third insulating layer 24, and the dummy film layer 55 completely fills the first transverse groove 43 and the second trench 42. Optionally, the conductive layer 54 and the dummy film layer 55 can be formed by a deposition method, and the conductive layer 54 and the dummy film layer 55 are planarized (for example, by CMP) so that the surfaces of the conductive layer 54 and the dummy film layer 55 away from the substrate 10 are flush with the surface of the third insulating layer 24 away from the substrate 10.

[0101] Alternatively, the conductive layer 54 is formed by atomic layer deposition (ALD). The material of the conductive layer 54 includes but is not limited to a single layer structure such as TiN or a multilayer structure such as a stack of TiN and W.

[0102] Optionally, the material of the dummy film layer 55 includes but is not limited to polycrystalline material (poly), such as polysilicon.

[0103] Then, if Figures 28 to 42 As shown, the conductive layer 54 and the dummy film layer 55 are patterned, and the conductive layer 54 and the dummy film layer 55 formed in the second trench 42 are removed. This disconnects the conductive layer 54 within each first transverse groove 43, leaving the conductive layer 54 located only on the inner wall of the first transverse groove 43. The remaining conductive layer 54 within each first transverse groove 43 forms an internal electrode 51, thereby forming multiple independent internal electrodes 51. The multiple first transverse grooves 43 are spaced apart and independent of each other. The multiple internal electrodes 51 formed in the multiple first transverse grooves 43 are separated and independent of each other, facilitating the subsequent formation of multiple capacitors 50.

[0104] In some optional embodiments of the present application, such as Figures 28 to 32 As shown, before forming the dielectric layer 52 and the external electrode 53, the method for preparing the semiconductor structure further includes:

[0105] A spacer 63 is formed on a side of the third insulating layer 24 away from the substrate 10. Optionally, the material of the spacer 63 includes but is not limited to nitride (eg, silicon nitride).

[0106] In some optional embodiments of the present application, such asFigures 28 to 42 As shown, the conductive layer 54 and the dummy film layer 55 are patterned, including:

[0107] like Figures 28 to 32 As shown, a third mask structure 64 is formed on a side of the spacer 63 away from the substrate 10. Alternatively, HM can be formed by deposition to form the third mask structure 64.

[0108] Then, if Figures 28 to 32 As shown, the third mask structure 64 is patterned so that the third mask structure 64 has a third preset pattern (eg Figure 28 As shown, the orthographic projection of the third preset pattern on the substrate 10 does not overlap with the orthographic projections of the conductive layer 54 and the dummy film layer 55 formed in the second trench 42 on the substrate 10, so as to remove the conductive layer 54 and the dummy film layer 55 formed in the second trench 42. Optionally, the third mask structure 64 can be patterned by photolithography so that the third mask structure 64 has a third preset pattern.

[0109] Then, if Figures 33 to 42 As shown, based on the third mask structure 64 after patterning, the conductive layer 54 and the dummy film layer 55 are etched to remove the conductive layer 54 and the dummy film layer 55 formed in the second groove 42, and the remaining conductive layer 54 in each first lateral groove 43 forms an internal electrode 51, thereby forming a plurality of independent internal electrodes 51.

[0110] In some optional embodiments of the present application, such as Figures 33 to 42 As shown, based on the patterned third mask structure 64, the conductive layer 54 and the dummy film layer 55 are etched, including:

[0111] like Figures 33 to 37 As shown, a portion of the dummy film layer 55 formed in the second trench 42 is removed by dry etching, so that a portion of the space in the second trench 42 is vacated.

[0112] Then, if Figures 33 to 37 As shown, the remaining dummy film layer 55 formed in the second trench 42 is wet-etched to expose the conductive layer 54 formed in the second trench 42 , so as to remove the conductive layer 54 formed in the second trench 42 .

[0113] Then, if Figures 38 to 42 As shown, the conductive layer 54 formed in the second trench 42 and the remaining dummy film layer 55 are removed by wet etching, and the conductive layer 54 formed in the plurality of first transverse grooves 43 is separated into a plurality of internal electrodes 51 , and the plurality of internal electrodes 51 are isolated from each other.

[0114] In some optional embodiments of the present application, such as Figures 38 to 42As shown, after forming a plurality of inner electrodes 51 and before forming the dielectric layer 52 and the outer electrode 53, the method for manufacturing a semiconductor structure further includes:

[0115] Removing the dummy film layer 55 filled in the first lateral groove 43 to expose the inner electrode 51. Optionally, the dummy film layer 55 filled in the first lateral groove 43 can be laterally etched by a wet etching method to completely remove the dummy film layer 55 filled in the first lateral groove 43.

[0116] Figure 43 FIG. is a sectional view taken along the a-a direction during the manufacturing process of the method for manufacturing a semiconductor structure according to an embodiment of the present application. Figure 44 FIG. is a sectional view taken along the b-b direction during the manufacturing process of the method for manufacturing a semiconductor structure according to an embodiment of the present application. Figure 45 FIG. is a sectional view taken along the c-c direction during the manufacturing process of the method for manufacturing a semiconductor structure according to an embodiment of the present application. Figure 46 FIG. is a sectional view taken along the d-d direction during the manufacturing process of the method for manufacturing a semiconductor structure according to an embodiment of the present application.

[0117] In some alternative embodiments of the present application, as Figures 43 to 46 shown, after forming a plurality of inner electrodes 51 and before forming the dielectric layer 52 and the outer electrode 53, the method for manufacturing a semiconductor structure further includes:

[0118] Etching the exposed first insulating layer 21, second insulating layer 22, and third insulating layer 24 in the second trench 42 in a direction parallel to the substrate 10 (etch-back process), the etching depth being less than the dimension of the inner electrode 51 in the second direction, so that the remaining first insulating layer 21 and second insulating layer 22 support a part of the inner electrodes 51 among the plurality of inner electrodes 51, and the remaining first insulating layer 21, second insulating layer 22, and third insulating layer 24 support another part of the inner electrodes 51 among the plurality of inner electrodes 51. Second lateral grooves 44 are correspondingly formed at the positions where the etched portions of the first insulating layer 21, second insulating layer 22, and third insulating layer 24 are located. The second lateral grooves 44 surround the outer surface of the inner electrode 51.

[0119] In the embodiment of the present application, since the etching depth of the exposed first insulating layer 21, the second insulating layer 22 and the third insulating layer 24 is smaller than the size of the inner electrode 51 along the second direction, the bottom of the inner electrode 51 (the bottom is located on the side of the inner electrode 51 away from the second groove 42) still has the first insulating layer 21 and the second insulating layer 22 or the first insulating layer 21, the second insulating layer 22 and the third insulating layer 24 remaining on the periphery. The remaining first insulating layer 21 and the second insulating layer 22 can well fix the inner electrode 51 to play a supporting role. The remaining first insulating layer 21, the second insulating layer 22 and the third insulating layer 24 can also well fix the inner electrode 51 to play a supporting role, thereby ensuring that the inner electrode 51 will not collapse.

[0120] In the embodiment of the present application, a second transverse groove 44 is formed corresponding to the position where the etched portions of the first insulating layer 21, the second insulating layer 22 and the third insulating layer 24 are located. The sidewalls of the second transverse groove 44 expose the inner electrode 51, thereby increasing the exposed surface area of the inner electrode 51 and increasing the contact area between the inner electrode 51 and the subsequently manufactured dielectric layer 52 and the outer electrode 53. In this way, under the same size conditions, since the exposed surface area of the capacitor 50 in the embodiment of the present application is larger, the capacitor 50 in the embodiment of the present application has a larger capacity.

[0121] Optionally, the first insulating layer 21, the second insulating layer 22 and the third insulating layer 24 exposed by the second groove 42 can be laterally etched to a certain depth by wet etching. The depth of this etching is a certain distance shorter than the length of the capacitor 50. In this way, the remaining oxide layer (the material of the oxide layer is, for example, silicon oxide, that is, the first insulating layer 21 and the second insulating layer 22, or the first insulating layer 21, the second insulating layer 22 and the third insulating layer 24) can well fix the internal electrode 51 of the capacitor 50 to ensure that the internal electrode 51 does not collapse.

[0122] Figure 47 This is a top view of the semiconductor structure manufacturing method during the manufacturing process according to an embodiment of the present application. Figure 48 for Figure 47 The aa-direction cross-section diagram, Figure 49 for Figure 47 Middle bb section, Figure 50 for Figure 47 The cc section diagram, Figure 51 for Figure 47 Mid-dd section view.

[0123] In some optional embodiments of the present application, such as Figures 47 to 51 As shown, a dielectric layer 52 and an external electrode 53 are sequentially formed in the first transverse groove 43 and the second trench 42, including:

[0124] Meanwhile, a high-k dielectric material and a first conductive material are sequentially deposited in the first horizontal groove 43, the second horizontal groove 44, and the second groove 42. The high-k dielectric material covers the exposed inner electrode 51, the first insulating layer 21, the second insulating layer 22, the third insulating layer 24, and the spacer layer 63. The first conductive material covers the high-k dielectric material. The high-k dielectric material layer forms a dielectric layer 52. The shape of the dielectric layer is adapted to the inner wall shapes of the first horizontal groove and the second horizontal groove. The first conductive material covers the dielectric layer to form an outer electrode 53.

[0125] The orthographic projection of the capacitor 50 on the substrate 10 overlaps with the region 13 on the substrate 10 where the capacitor is to be formed.

[0126] In the embodiment of the present application, as Figures 47 to 51 shown, since the inner wall of the inner electrode 51 facing one side of the first horizontal groove 43 and the outer wall facing one side of the second horizontal groove 44 are both exposed, the exposed surface area of the inner electrode 51 is increased. Therefore, after the dielectric layer 52 and the outer electrode 53 are formed in the first horizontal groove 43 and the second horizontal groove 44, the contact area between the inner electrode 51 and the dielectric layer 52, and between the dielectric layer 52 and the outer electrode 53 is increased, and the relative area between the inner electrode 51 and the outer electrode 53 is increased. Under the same size conditions, the capacitor 50 in the embodiment of the present application has a larger capacitance.

[0127] Optionally, the high-k dielectric material (High-K dielectric material), that is, a dielectric material with a dielectric constant K≥3.9. In some alternative embodiments, the high-k dielectric material may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. (such as silicon oxide). For example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.

[0128] Optionally, the first conductive material includes but is not limited to TiN.

[0129] Optionally, the dielectric layer 52 and the outer electrode 53 can be formed by the ALD method.

[0130] In the embodiment of the present application, the shapes of the dielectric layer 52 in the first horizontal groove 43 and the inner electrode 51 are similar and are adapted to the inner wall shape of the first horizontal groove 43. The outer electrode 53 is formed in each region in the first horizontal groove 43. The outer electrode 53 in the first horizontal groove 43 is a laterally extending columnar structure, and its outer surface is adapted to the inner wall of the first horizontal groove 43.

[0131] After the dielectric layer 52 and the outer electrode 53 are formed, the method for manufacturing the semiconductor structure further includes:

[0132] The first lateral groove 43, the second lateral groove 44, and the second groove 42 are filled with a second conductive material to form a connection structure 56, so that the external electrode 53 is connected to an external device through the connection structure 56.

[0133] Optionally, the second conductive material includes, but is not limited to, a polycrystalline material (Poly), such as polysilicon. The second conductive material may be the same as or different from the first conductive material.

[0134] Optionally, the second conductive material may be deposited to fill the first lateral groove 43, the second lateral groove 44, and the second groove 42, and then the second conductive material is planarized (such as by CMP planarization) to form a connection structure 56. The surface of the connection structure 56 away from the substrate 10 is flush with the surface of the spacer layer 63 away from the substrate 10.

[0135] The embodiment of the present application provides a preparation method for a brand-new semiconductor structure with a cylindrical capacitor, and the process is simple and feasible. Since the bottom of the inner electrode of the capacitor has support and is in a cylindrical structure, its structure is more stable. And under the same size conditions, since the surface area of the capacitor exposed in the embodiment of the present application is larger, it has a larger capacitance.

[0136] The preparation method of the semiconductor structure in the embodiment of the present application can be applied to the field of semiconductor device preparation. Optionally, it can be applied to the field of 3D DRAM (3Dimension Dynamic Random Access Memory), for preparing capacitors. For example, it can be used to prepare In some optional embodiments of the present application, after the capacitor 50 is fabricated, the dummy word line 72 needs to be removed, and then the gate of the transistor and the word line connected to the gate are fabricated at the position where the dummy word line 72 is located; the second part structure 33 of the sub-sacrificial layer 31 is removed, and then a gate insulating layer and a semiconductor layer are sequentially fabricated around the gate of the transistor. The positions of the gate insulating layer and the semiconductor layer correspond to the position of the second part structure 33. The gate insulating layer surrounds the gate, and the semiconductor layer includes a channel surrounding the gate and located on the side of the gate insulating layer away from the gate, a source located on the side of the channel away from the gate, and a drain located on the other side of the channel away from the gate; optionally, the source of the transistor can be connected to the inner electrode 51 of the capacitor 50. The preparation process of the transistor is similar to or the same as the preparation process of the transistor in the prior art, and will not be elaborated here. The part of the sacrificial layer 30 corresponding to the area 11 where the bit line is to be formed is removed, and then the bit line can be formed in the corresponding trench formed, and the bit line is connected to the drain of the transistor.

[0137] Based on the same inventive concept, the embodiment of the present application provides a semiconductor structure. The structural schematic diagram of the semiconductor structure 100 is asFigures 52 to 55 As shown Figure 52 is a cross-sectional view of the semiconductor structure 100 along Figure 47 the a-a direction in Figure 53 is a cross-sectional view of the semiconductor structure 100 along Figure 47 the b-b direction in Figure 54 is a cross-sectional view of the semiconductor structure 100 along Figure 47 the c-c direction in Figure 55 is a cross-sectional view of the semiconductor structure 100 along Figure 47 the d-d direction in. The equivalent circuit diagram of the semiconductor structure 100 is as shown in Figure 56 . The semiconductor structure 100 includes: a substrate 10, a plurality of transistors, an insulating structure 20, and a capacitor 50.

[0138] The insulating structure 20 is disposed on one side of the substrate 10. The insulating structure 20 has a plurality of first lateral grooves 43 arranged in an array along a first direction and a direction perpendicular to the substrate 10 (as shown in Figure 52 and Figure 55 ) and second trenches 42 respectively communicating with the plurality of first lateral grooves 43 (as shown in Figure 52 and Figure 53 ). Each first lateral groove 43 extends along a second direction; the capacitor 50 includes an inner electrode 51, a dielectric layer 52, and an outer electrode 53. The inner electrode 51 is correspondingly disposed on the inner wall of the first lateral groove 43. The dielectric layer 52 is disposed on the wall surface of the plurality of inner electrodes 51 away from the corresponding first lateral groove 43 and the inner wall of the second trench 42. The outer electrode 53 is disposed on the wall surface of the dielectric layer 52 away from the insulating structure 20.

[0139] The semiconductor structure 100 of the embodiment of the present application can be prepared by using the preparation method of the semiconductor structure provided by the embodiment of the present application.

[0140] In the embodiment of the present application, the substrate 10 is used to support the insulating structure 20 and the capacitor 50.

[0141] Optionally, in the embodiment of the present application, the insulating structure 20 includes the above-mentioned first insulating layer 21, second insulating layer 22, and third insulating layer 24.

[0142] Optionally, in the embodiment of the present application, a plurality of first insulating layers 21 and a plurality of transistors are alternately disposed on one side of the substrate 10 in sequence. There is a first trench 41 between several first insulating layers 21 arranged in sequence along the first direction. The second insulating layer 22 is disposed in the first trench 41 to isolate the first insulating layer 21 and the transistor; the source or drain of the transistor, the first insulating layer 21, and the second insulating layer 22 enclose a lateral groove extending along the second direction; the first insulating layer 21 and the second insulating layer 22 enclose a second trench 42 extending along the first direction. The second trench 42 is located on the side of the first lateral groove 43 away from the transistor and communicates with the lateral groove.

[0143] The transverse groove contains a ring-shaped inner electrode portion of the inner electrode. The inner electrode 51 contacts the source or drain of the transistor and has its sidewalls exposed. The dielectric layer 52 surrounds the outer and / or inner walls of the inner electrode 51 . The outer electrode 53 is at least arranged on the inner wall of the inner electrode and located on the dielectric layer 52 .

[0144] Optionally, in an embodiment of the present application, the outer wall of the inner electrode 51, the first insulating layer 21 and the second insulating layer 22, as well as the outer wall of the inner electrode 51, the third insulating layer 24 and the partition layer 63 respectively form a second transverse groove 44, the dielectric layer 52 is also arranged on the inner wall of the second transverse groove 44, and the outer electrode 53 is also arranged in the second transverse groove 44 and located on the dielectric layer 52.

[0145] Optionally, in an embodiment of the present application, the inner electrode 51 is cylindrical, and the opening of the inner electrode 51 faces the side away from the transistor; the outer electrode 53 surrounds the outer wall, inner wall and inner bottom of the inner electrode 51, and the outer electrodes 53 in each area are continuously distributed to form an integrated structure.

[0146] The cylindrical inner electrode opens toward the second trench and includes a sidewall and a bottom. The sidewall is annular and extends toward the second trench, while the bottom is a vertical wall perpendicular to the substrate. The sidewall and bottom constitute the inner or outer wall of the inner electrode. The inner wall includes an inner sidewall and a bottom, while the outer wall includes an outer sidewall and a bottom.

[0147] In the embodiment of the present application, multiple first transverse grooves 43 are arranged in an array along the first direction and perpendicular to the substrate 10, and one end of the multiple first transverse grooves 43 along the second direction is respectively connected to the second groove 42, and multiple internal electrodes 51 are arranged one by one on the inner walls of the multiple first transverse grooves 43. The insulating structure 20 can fix the internal electrodes 51 well and play a role in supporting the internal electrodes 51, thereby ensuring that the internal electrodes 51 will not collapse. The dielectric layer 52 is arranged on the wall surface of the multiple internal electrodes 51 away from the corresponding first transverse groove 43 and the inner wall of the second groove 42. The external electrode 53 is arranged on the wall surface of the dielectric layer 52 away from the insulating structure 20. The multiple internal electrodes 51, the dielectric layer 52 and the external electrode 53 form multiple capacitors 50.

[0148] The semiconductor structure of the embodiment of the present application is simple in structure and easy to manufacture. Since the inner electrode of the capacitor is supported, the structure of the inner electrode is stable, reducing the possibility of collapse.

[0149] In some optional embodiments of the present application, such as Figures 52 to 55 As shown, the insulating structure also has a plurality of second transverse grooves 44 (such as Figure 52 , Figure 53 and Figure 55As shown, the first horizontal groove 43 and the second horizontal groove 44 are alternately arranged in sequence along a direction perpendicular to the substrate 10 and are connected. The dimension of the first horizontal groove 43 along the second direction is larger than that of the second horizontal groove 44 along the second direction, and the bottom of the first horizontal groove 43 protrudes along the second direction from the second horizontal groove 44. The dielectric layer 52 is disposed on the inner wall of the second horizontal groove 44, and the outer electrode 53 is disposed on the wall surface of the dielectric layer 52 on the side away from the inner wall of the second horizontal groove 44. The dimension of the inner electrode 51 along the second direction is larger than that of the outer electrode 53 disposed around the outer wall of the inner electrode 51 along the second direction.

[0150] In the embodiment of the present application, since the dimension of the first horizontal groove 43 along the second direction is larger than that of the second horizontal groove 44 along the second direction, and the bottom of the first horizontal groove 43 protrudes along the second direction from the second horizontal groove 44, therefore, the outer periphery of the bottom of the inner electrode 51 (the bottom is located on the side of the first horizontal groove 43 facing the dummy word line 72) is surrounded by the insulating structure 20. The insulating structure 20 can well fix the inner electrode 51 and play a supporting role, thereby ensuring that the inner electrode 51 will not collapse.

[0151] In the embodiment of the present application, the inner side wall of the inner electrode 51 facing the first horizontal groove 43 and the outer side wall facing the second horizontal groove 44 are both in contact with the dielectric layer 52. The contact area between the inner electrode 51, the dielectric layer 52, and the dielectric layer 52 and the outer electrode 53 increases. Under the same dimension conditions, since the exposed surface area of the capacitor 50 in the embodiment of the present application is larger, the capacitor 50 in the embodiment of the present application has a larger capacitance.

[0152] Optionally, the outer electrode 53 is a conductive layer disposed in the first horizontal groove 43 and the second horizontal groove 44.

[0153] In some alternative embodiments of the present application, as Figures 52 to 55 shown, the semiconductor structure 100 further includes a connection structure 56. The connection structure 56 is located on the side of the outer electrode 53 away from the insulating structure 20 and is disposed in the first horizontal groove 43 and the second groove 42. The outer electrode 53 is connected to an external device through the connection structure 56.

[0154] The embodiment of the present application proposes a brand-new semiconductor structure with a cylindrical inner electrode capacitor, and its manufacturing process is simple and feasible. Since the bottom of the inner electrode of the capacitor has support and is a cylindrical structure, its structure is more stable. And under the same dimension conditions, since the exposed surface area of the capacitor in the embodiment of the present application is larger, it has a larger capacitance.

[0155] Based on the same inventive concept, an embodiment of the present application provides an electronic device, which includes the above-mentioned semiconductor structure, or a semiconductor structure manufactured using the above-mentioned semiconductor structure manufacturing method.

[0156] It should be noted that since the electronic device of the embodiment of the present application includes the semiconductor structure of the embodiment of the present application or the semiconductor structure manufactured by the above-mentioned semiconductor structure preparation method, the electronic device of the embodiment of the present application also has the above-mentioned beneficial effects of the semiconductor structure of the embodiment of the present application or the semiconductor structure manufactured by the above-mentioned semiconductor structure preparation method, which will not be repeated here.

[0157] In some optional embodiments of the present application, the electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include a memory in a computer, etc., which is not limited here.

[0158] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0159] In an embodiment of the present application, a plurality of first grooves and a second groove are formed on a stacked structure of a first insulating layer and a sacrificial layer, the plurality of first grooves are sequentially arranged at intervals along a first direction to separate at least a portion of the structure of the sacrificial layer into a plurality of sub-sacrificial layers, the sidewalls of the first grooves expose the first insulating layer and the sacrificial layer, the first grooves are filled with the second insulating layer, and the second insulating layer is respectively in contact with the first insulating layer and the sacrificial layer exposed by the first grooves; the plurality of sub-sacrificial layers are arranged in an array along the first direction and perpendicular to the substrate direction, the first grooves extend along the second direction, the sub-sacrificial layers extend along the second direction, one end of the first groove along the second direction is connected to the second groove, the second groove extends along the first direction, and the sidewalls of the second grooves expose the first insulating layer and the plurality of sub-sacrificial layers so as to remove the sub-sacrificial layers After the partial structures of the multiple sub-sacrificial layers exposed by the second grooves are removed, multiple first transverse grooves are formed correspondingly, and the inner walls of each first transverse groove expose the remaining sub-sacrificial layer, the first insulating layer and the second insulating layer; then, multiple inner electrodes are formed one by one in the multiple first transverse grooves, and the inner electrodes cover the exposed remaining sub-sacrificial layers, the first insulating layer and the second insulating layer. The first insulating layer and the second insulating layer can fix the inner electrodes well and play a role in supporting the inner electrodes, thereby ensuring that the inner electrodes will not collapse; then, dielectric layers and external electrodes are formed in the first transverse grooves and the second grooves in sequence, the dielectric layer covers the inner electrodes, the first insulating layer and the second insulating layer, and the external electrode covers the dielectric layer, and the multiple inner electrodes form multiple capacitors with the dielectric layer and the external electrode respectively.

[0160] The method for manufacturing the semiconductor structure of the embodiment of the present application is simple and feasible. Since the inner electrode of the capacitor is supported during the manufacturing process, the structure of the inner electrode is stable, reducing the possibility of collapse.

[0161] In the embodiment of the present application, since the etching depth of the exposed first insulating layer, second insulating layer and third insulating layer is smaller than the size of the inner electrode along the second direction, the first insulating layer and the second insulating layer or the first insulating layer, the second insulating layer and the third insulating layer are still retained on the bottom periphery of the inner electrode. The remaining first insulating layer and the second insulating layer can well fix the inner electrode to play a supporting role, and the remaining first insulating layer, the second insulating layer and the third insulating layer can also well fix the inner electrode to play a supporting role, thereby ensuring that the inner electrode will not collapse.

[0162] In the embodiment of the present application, since the inner sidewall of the inner electrode facing the first transverse groove and the outer sidewall facing the second transverse groove are both exposed, the exposed surface area of the inner electrode is increased. Therefore, after the dielectric layer and the outer electrode are formed in the first transverse groove and the second transverse groove, the contact area between the inner electrode and the dielectric layer, and between the dielectric layer and the outer electrode is increased, and the relative area between the inner electrode and the outer electrode is increased. Under the same size conditions, the capacitor in the embodiment of the present application has a larger capacity.

[0163] This embodiment of the present application proposes a novel method for fabricating a semiconductor structure with a tubular capacitor. Because the capacitor's inner electrode has a support at the bottom and is tubular in shape, the structure is more stable. Furthermore, given the same dimensions, the capacitor of this embodiment has a greater exposed surface area, resulting in a higher capacitance.

[0164] Those skilled in the art will appreciate that the steps, measures, and schemes in the various operations, methods, and processes discussed in this application may be interchanged, modified, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted.

[0165] In the description of this application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", and "outside" are exemplary directions or positional relationships based on the accompanying drawings. They are intended to facilitate or simplify the description of the embodiments of this application, and do not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.

[0166] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0167] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any one or more embodiments or examples in a suitable manner.

[0168] The above are only some embodiments of this application. It should be noted that for those of ordinary skill in the art, without departing from the technical concept of the solution of this application, other similar implementation means based on the technical idea of this application also belong to the protection scope of the embodiments of this application.

Claims

1. A method for preparing a semiconductor structure, characterized in that, Comprising: Providing a substrate; Sequentially and alternately forming a first insulating layer and a sacrificial layer on one side of the substrate; Through patterning, forming a plurality of first trenches arranged at intervals in a first direction parallel to the substrate and second trenches spaced in a second direction parallel to the substrate, sidewalls of the first trenches exposing the first insulating layer and the sacrificial layer, and at least part of the structure of the sacrificial layer being separated into a plurality of sub-sacrificial layers by the plurality of first trenches; The second trenches extend in the first direction, sidewalls of the second trenches exposing the first insulating layer and ends of the plurality of sub-sacrificial layers, and the first direction intersects the second direction; Filling the first trenches with a second insulating layer; performing wet etching back on the exposed ends of the plurality of sub-sacrificial layers to form a plurality of first lateral grooves, inner walls of each of the first lateral grooves exposing the ends of the remaining sub-sacrificial layers after etching back, adjacent two layers of the first insulating layer, and the second insulating layer in adjacent first trenches; Forming a plurality of inner electrodes in the plurality of first lateral grooves according to the shape of the first lateral grooves; At least sequentially forming a dielectric layer and an outer electrode in the first lateral grooves and the second trenches, the dielectric layer covering the inner electrodes, the first insulating layer, and the second insulating layer, the outer electrode covering the dielectric layer, and the plurality of inner electrodes respectively forming a plurality of capacitors with the dielectric layer and the outer electrode.

2. The method for preparing a semiconductor structure according to claim 1, wherein Forming a plurality of first lateral grooves, including: Performing wet etching back on the exposed plurality of sub-sacrificial layers in the second trenches to form a plurality of first lateral grooves extending in the second direction and stacked in the direction perpendicular to the substrate.

3. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, Forming a plurality of inner electrodes, including: Depositing a conductive layer in the first lateral grooves and the second trenches, removing the conductive layer in the second trenches, so that the conductive layers in each first lateral groove are disconnected from each other, and forming a plurality of independent inner electrodes only on the inner walls of the first lateral grooves.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein, Before removing the conductive layer in the second trenches, forming a dummy film layer on the conductive layer; removing a part of the dummy film layer in the second trenches by dry etching; Removing the conductive layer and the remaining dummy film layer in the second trenches by wet etching, and separating the conductive layer formed in the plurality of first lateral grooves into a plurality of the inner electrodes.

5. The method for manufacturing a semiconductor structure according to claim 3, wherein, After forming a plurality of inner electrodes and before forming a dielectric layer and an outer electrode, the method for preparing the semiconductor structure further includes: Performing etching back on the first insulating layer and the second insulating layer on the outer surface of the inner electrodes in the second trenches to form second lateral grooves surrounding the outer surfaces of the inner electrodes.

6. The manufacturing method of the semiconductor structure according to claim 5, characterized in that, Simultaneously depositing a dielectric layer and a first conductive material in the first lateral grooves, the second lateral grooves, and the second trenches, the shape of the dielectric layer being adapted to the inner wall shapes of the first lateral grooves and the second lateral grooves, and the first conductive material covering the dielectric layer to form an outer electrode.

7. A semiconductor structure, characterized in that, Comprising: A substrate; A plurality of first insulating layers, a plurality of transistors, and a plurality of second insulating layers, wherein the first insulating layers and the transistors are alternately arranged on one side of the substrate in sequence and are arranged in sequence along a first direction. There is a first trench between several of the first insulating layers arranged in sequence along the first direction, and the second insulating layer is arranged in the first trench to isolate the first insulating layer and the transistor; a source or drain of the transistor, the first insulating layer, and the second insulating layer enclose a lateral groove extending along a second direction; the first insulating layer and the second insulating layer enclose a second trench extending along the first direction, and the second trench is located on a side of the lateral groove away from the transistor and is communicated with the lateral groove. A plurality of capacitors, each capacitor including an inner electrode, a dielectric layer, and an outer electrode. An annular inner electrode portion of the inner electrode is in the lateral groove. The inner electrode is in contact with the source or drain of the transistor and its sidewall is exposed. The dielectric layer is at least distributed on the inner wall of the inner electrode, and the outer electrode is at least arranged on the inner wall of the inner electrode and is located on the dielectric layer.

8. The semiconductor structure according to claim 7, wherein, An outer sidewall of the inner electrode, the first insulating layer, and the second insulating layer enclose a second lateral groove. The dielectric layer is also arranged on the inner wall of the second lateral groove, and the outer electrode is also arranged on the inner wall of the second lateral groove and is located on the dielectric layer.

9. The semiconductor structure according to claim 7, wherein, The materials of the first insulating layer and the second insulating layer are the same; and / or, The inner electrode is a single-layer structure or a multi-layer structure.

10. The semiconductor structure according to claim 8, wherein The inner electrode is in a cylindrical shape, and an opening of the inner electrode faces away from the transistor side; The outer electrode surrounds the outer wall, the inner wall, and the bottom inside the inner electrode to form an integral structure.

11. The semiconductor structure according to claim 8, wherein A dimension of the inner electrode along the second direction is greater than a dimension of the outer electrode arranged around the outer wall of the inner electrode along the second direction.

12. The semiconductor structure according to claim 8, wherein, The outer electrode is a conductive layer arranged on the inner wall of the inner electrode and in the second lateral groove. The semiconductor structure further includes a connection structure, and the connection structure fills the inner wall of the inner electrode, the second lateral groove, and the second trench, and the connection structure is electrically connected to each of the outer electrodes exposed in the second trench respectively.

13. An electronic device, characterized in that, A semiconductor structure including any one of the semiconductor structures according to claims 7-12, or a semiconductor structure manufactured by a manufacturing method including any one of the semiconductor structures according to claims 1-6.

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