SONOS device and manufacturing method thereof
By improving the lithography and etching process, expanding the overlapping area of TUN region and ONO region, the GIDL leakage problem caused by oxide bulging between CG and SG in SONOS devices is solved, and the device reliability and yield are improved.
Patent Information
- Application Number
- CN202510725669.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-30
- Publication Date
- 2025-07-29
AI Technical Summary
In SONOS devices, the GIDL leakage problem in the memory area is caused by the oxide bulge between CG and SG, which affects the device reliability and process stability, especially in the 55/40nm node layout design stage.
By improving the lithography and etching process, expanding the overlapping area of the TUN region and the ONO region, the photolithography and etching process are used to remove oxide bulges between the storage tube and the selection tube, avoiding subsequent process modifications.
Without changing the subsequent process, the oxide bulge is effectively removed, which improves the GIDL leakage of SONOS devices and improves product reliability and yield.
Smart Images
Figure CN120390410A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and particularly to a SONOS device and a manufacturing method thereof. Background Art
[0002] The memory cell structure of a 2T SONOS device includes a memory transistor (CG) and a select transistor (SG). TUN / ONO is an important process step for forming CG and SG in the 40EF characteristic process. In the layout design stage of the 55 / 40nm node, the structural designs of the TUN (Tunnel) region and the ONO (Oxide-Nitride-Oxide structure) region are carried out separately without overlapping. After subsequent process steps, a bulge of the oxide layer remains between CG and SG and cannot be removed, which affects the subsequent LDD process of the 2T SONOS, and further affects the GIDL (gate-induced drain leakage) leakage of the memory area, resulting in serious reliability risks. As the process node is gradually reduced, the distance from SG to CG is further decreased. As shown in Figure 1 The reliability risks of the SONOS device caused by the bulge become non-negligible. In addition, due to certain fluctuations in the process, the position where the bulge exists also fluctuates, which leads to poor process stability. In summary, it is necessary to effectively improve the existing technology.
[0003] It should be noted that the information disclosed in the background art of this invention is only intended to deepen the understanding of the general background technology of the present invention, and should not be regarded as an admission or any form of implication that this information constitutes the prior art known to those skilled in the art. Summary of the Invention
[0004] The purpose of the present invention is to provide a SONOS device and a manufacturing method thereof to solve the problem of GIDL leakage in the memory area.
[0005] To solve the above technical problems, the present invention provides a manufacturing method of a SONOS device, including the following steps:
[0006] Provide a substrate, on which an adjacent ONO region and a protection region are provided;
[0007] Form a second oxide layer, a second nitride layer, and a third oxide layer on the protection region in sequence;
[0008] Form a first nitride layer and a first oxide layer on the ONO region in sequence;
[0009] A first mask layer for photolithography is formed on the first oxide layer, and the area covered by the first mask layer is smaller than the ONO area. The protected area and the area not covered by the first mask layer are TUN areas, and there is partial overlap between the ONO area and the TUN area.
[0010] Preferably, forming the second oxide layer on the protected area includes:
[0011] Forming a second oxide layer on the substrate;
[0012] Forming a second mask layer on the second oxide layer in the protected area, and removing the second oxide layer not covered by the second mask layer.
[0013] Preferably, after removing the second oxide layer not covered by the second mask layer, the remaining second mask layer is also removed to form a second nitride layer and a third oxide layer on the second oxide layer.
[0014] Preferably, silicon nitride is deposited on the second oxide layer and the ONO area to form the second nitride layer and the first nitride layer in the protected area and the ONO area respectively.
[0015] Preferably, silicon oxide is deposited on the first nitride layer and the second nitride layer to form the third oxide layer and the first oxide layer in the protected area and the ONO area respectively.
[0016] Preferably, after forming the first nitride layer, the first oxide layer, the second oxide layer, the second nitride layer and the third oxide layer, the second nitride layer and the third oxide layer are also removed.
[0017] Preferably, after forming the first mask layer for photolithography on the first oxide layer, deposition, photolithography, etching and photoresist stripping processes are performed in the TUN area and the ONO area to fabricate the select tube and the storage tube.
[0018] Preferably, the first mask layer includes at least one layer of photoresist.
[0019] Preferably, the second mask layer includes at least one layer of photoresist.
[0020] A SONOS device is fabricated by using the manufacturing method of the SONOS device as described above.
[0021] In the manufacturing method of the SONOS device provided by the present invention, by improving the photolithography and etching processes, the TUN area and the ONO area are enlarged. The oxide in the overlapping area will be removed during the fabrication of the storage tube and the select tube. In the subsequent chip manufacturing process, the oxide bulge between the storage tube and the select tube can be removed without modifying the process, avoiding GIDL leakage of the memory.
[0022] The SONOS device provided by the present invention and the manufacturing method of the SONOS device provided by the present invention belong to the same inventive concept. Therefore, the SONOS device provided by the present invention has at least all the advantages of the manufacturing method of the SONOS device provided by the present invention, which will not be elaborated herein. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:
[0024] Figure 1 is a top view of the selection tube SG and the storage tube CG in the prior art;
[0025] Figure 2 is a SEM image of the bulge between the selection tube SG and the storage tube CG in the prior art;
[0026] Figure 3 is a schematic diagram of the second oxide layer in the selection tube SG in the prior art;
[0027] Figure 4 is a schematic diagram of the film layers in the ONO region and the TUN region in the prior art;
[0028] Figure 5 is a schematic diagram of the distribution of the ONO region and the TUN region in the prior art;
[0029] Figure 6 is a schematic diagram of the selection tube SG and the storage tube CG in the prior art;
[0030] Figure 7 is a schematic diagram of the second oxide layer in an embodiment of the present invention;
[0031] Figure 8 is a schematic diagram of the film layers in the ONO region and the TUN region in an embodiment of the present invention;
[0032] Figure 9 is a schematic diagram of the etching of the ONO region and the TUN region in an embodiment of the present invention;
[0033] Figure 10 is a schematic diagram of the selection tube SG and the storage tube CG in an embodiment of the present invention;
[0034] Figure 11 is a flowchart of an embodiment of the present invention;
[0035] Figure 12 is a process execution diagram of an embodiment of the present invention;
[0036] Figure 13It is the electron microscope image of the selection tube SG and the storage tube CG in the prior art;
[0037] Figure 14 It is the electron microscope image of the selection tube SG and the storage tube CG in an embodiment of the present invention.
[0038] In the drawings:
[0039] 10. Substrate; 20. ONO region; 21. First nitride layer; 22. First oxide layer; 23. First mask layer; 30. TUN region; 31. Second oxide layer; 32. Second mask layer; 33. Second nitride layer; 34. Third oxide layer; 35. First polysilicon layer; 40. ONO stack; 41. Second polysilicon layer. Detailed implementation manners
[0040] To make the objectives, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in very simplified forms and are not drawn to scale, only for conveniently and clearly assisting in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the emphasis to be shown in each of the accompanying drawings is different, and sometimes different scales are adopted.
[0041] As used in the present invention, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more", in addition, the terms "first", "second", "third" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features. The term "proximal end" generally refers to the end close to the operator, the term "distal end" generally refers to the end close to the patient, "one end" and "the other end" as well as "proximal end" and "distal end" generally refer to two corresponding parts, which include not only the endpoints. The terms "mounted", "connected", "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral body; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements or the interaction relationship between two elements. In addition, as used in the present invention, one element being disposed on another element generally only means that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the two elements may be directly or indirectly connected, coupled, cooperated or transmitted through an intermediate element, and should not be construed as indicating or implying the spatial position relationship between the two elements, that is, one element may be inside, outside, above, below or on one side of the other element, etc. in any orientation, unless otherwise expressly specified in the context. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0042] The inventors have found that, as Figure 1 shown, the distance between the selection tube and the storage tube, during the manufacturing process, the TUN region and the ONO region are respectively used for the selection tube and the storage tube, and the manufacturing processes in the TUN region and the ONO region are operated separately.
[0043] Further research has found that when forming the second oxide layer in the front stage, the two regions are operated separately, but when forming the film layer in the ONO region, due to the film layer overlap between the two regions, the oxide generated in this region cannot be removed in the subsequent process, as Figure 5 and Figure 6 shown, thus an oxide bulge will be formed, affecting the GIDL leakage of the memory, as Figure 6 and Figure 2 shown.
[0044] Based on this, the core idea of the present invention is that by improving the photolithography and etching processes, the TUN region and the ONO region are enlarged, and the oxide in the overlapping region will be removed during the manufacturing of the storage tube and the selection tube. During the subsequent chip manufacturing process, the oxide bulge between the storage tube and the selection tube can be removed without modifying the process, avoiding GIDL leakage of the storage tube.
[0045] Specifically, please refer to Figures 7 - 14 , which is a schematic diagram of an embodiment of the present invention. As Figure 11 shown, a manufacturing method of a SONOS device includes the following steps:
[0046] Step 1: Provide a substrate 10, on which there are adjacent ONO regions 20 and protection regions.
[0047] The substrate 10 in Step 1 includes a bulk semiconductor substrate 10 or a silicon-on-insulator (SOI) substrate 10. The semiconductor of the active layer and the bulk semiconductor usually include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloy, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or their alloys (e.g., Ga x Al1-xAs, Ga x Al1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.) or their combinations. The semiconductor material can be doped or undoped. Other substrates 10 that can be used include multi-layer substrates 10, gradient substrates 10 or mixed-orientation substrates 10.
[0048] Step 2: Sequentially form a second oxide layer 31, a second nitride layer 33 and a third oxide layer 34 on the protection region; sequentially form a first nitride layer 21 and a first oxide layer 22 on the ONO region 20.
[0049] Among them, forming the second oxide layer 31 on the protection region includes:
[0050] Form a second oxide layer 31 on the substrate 10;
[0051] Form a second mask layer 32 on the second oxide layer 31 in the protection region, and remove the second oxide layer 31 not covered by the second mask layer 32.
[0052] As Figure 7As shown, a second oxide layer 31 is formed over the entire surface of the substrate 10, and then a second mask layer 32 is formed. The second mask layer 32 includes at least one layer of photoresist, and it can also be a composite film layer of BARC (Bottom Anti-Reflection Coating) and photoresist. Through a series of steps such as photolithography, development, exposure, and cleaning, a second mask layer 32 that only covers the protection area is formed, and the redundant second oxide layer 31 is etched away to open the ONO area 20.
[0053] In one embodiment, the TUN area 30 is larger than the protection area, and there is an overlap between the ONO area 20 and the TUN area 30. In the previous process, most of the TUN area 30 is protected by the second mask layer 32. Then, a stacked layer composed of a second oxide layer 31, a second nitride layer 33, and a third oxide layer 34 is formed in the protection area, and a first nitride layer 21 and a first oxide layer 22 are formed in the ONO area 20. After removing the redundant second nitride layer 33 and third oxide layer 34 in the TUN area 30, the overlap area between the ONO area 20 and the TUN area 30 is not covered by the first mask layer 23. Then, when etching the selection tube in the TUN area 30 in the subsequent manufacturing process, the oxide bulge in this overlap area will be removed accordingly.
[0054] Specifically, the first mask layer 23 includes at least one layer of photoresist. The second mask layer 32 includes at least one layer of photoresist. It can also be a composite film layer of BARC (Bottom Anti-Reflection Coating) and photoresist. The photoresist is, for example, a sticky photoresist film used in semiconductor chip packaging or printed circuit board manufacturing, usually a photosensitive polymer material, which can be polyimide (PI), bis-BenzoCycloButene (BCB), or P-phenylene-2,6-BenzobisOxazole (PBO).
[0055] It can be understood that the first oxide layer 22, the second oxide layer 31, and the third oxide layer 34 are all silicon oxide, and the first nitride layer 21 and the second nitride layer 33 are all silicon nitride.
[0056] Specifically, after removing the second oxide layer 31 not covered by the second mask layer 32, the remaining second mask layer 32 is also removed to form a second nitride layer 33 and a third oxide layer 34 on the second oxide layer 31. After etching to form the second oxide layer 31 in the protection area, the second mask layer 32 is removed for subsequent processes.
[0057] In one embodiment, silicon nitride is deposited on the second oxide layer 31 and the ONO region 20 to form the second nitride layer 33 and the first nitride layer 21 in the protection region and the ONO region 20, respectively. It can be understood that by depositing a layer of silicon nitride on the protection region and the ONO region 20, the second nitride layer 33 and the first nitride layer 21 are formed in the protection region and the ONO region 20, respectively.
[0058] Similarly, silicon oxide is deposited on the first nitride layer 21 and the second nitride layer 33 to form the third oxide layer 34 and the first oxide layer 22 in the protection region and the ONO region 20, respectively. Continuing to deposit silicon oxide on the second nitride layer 33 and the first nitride layer 21, a stacked structure of three layers and two layers is formed in the protection region and the ONO region 20, respectively, as Figure 8 shown. Obviously, a stacked structure as shown in Figure 8 can also be formed by depositing a layer of silicon nitride and a layer of silicon oxide in the protection region and the ONO region 20, respectively.
[0059] Step 3: A first mask layer 23 for photolithography is formed on the first oxide layer 22, and the area covered by the first mask layer 23 is smaller than the ONO region 20. The protection region and the region not covered by the first mask layer 23 are the TUN region 30, and there is partial overlap between the ONO region 20 and the TUN region 30.
[0060] As Figure 9 shown, after forming the first nitride layer 21, the first oxide layer 22, the second oxide layer 31, the second nitride layer 33, and the third oxide layer 34, the second nitride layer 33 and the third oxide layer 34 are also removed. The second nitride layer 33 and the third oxide layer 34 in the protection region are removed to avoid the formation of oxide bulges at the junction of the ONO region 20 and the TUN region 30. Exemplarily, a mask layer is covered on the ONO region 20, the film layer on the second oxide layer 31 is removed, and then the first mask layer 23 is formed on the first oxide layer 22. The area covered by the first mask layer 23 is the area of the ONO region 20 excluding the part overlapping with the TUN region 30.
[0061] Specifically, after forming the first mask layer 23 for photolithography on the first oxide layer 22, deposition, photolithography, etching, and photoresist stripping processes are performed in the TUN region 30 and the ONO region 20 to fabricate select tubes and memory tubes.
[0062] Exemplarily, polysilicon is continuously deposited on the whole wafer substrate 10. The second polysilicon layer 41 and the first polysilicon layer 35 are respectively formed in the ONO region 20 and the TUN region 30 through etching, thus constituting the select transistor SG and the storage transistor CG. It can be understood that the first nitride layer 21, the first oxide layer 22 formed in the ONO region 20 previously and the oxide layer existing on the surface of the substrate 10 together constitute the ONO stack 40. The ONO stack 40 and the second polysilicon layer 41 form the storage transistor CG, and the second oxide layer 31 in the TUN region 30, together with the oxide layer existing on the surface of the substrate 10 and the first polysilicon layer 35, constitute the select transistor SG. During the processing of forming the overlap at the intersection in the ONO region 20, the bulge between the SG and the CG is eliminated, realizing the improvement of the GIDL effect of the 2T SONOS device. This technology can cover flash memory processes of 28nm and above nodes, which is of great significance for improving product reliability and yield.
[0063] Based on the same technical concept, the present invention also provides a SONOS device, which is fabricated by using the manufacturing method of the SONOS device as described above.
[0064] In a flash memory device process, as Figure 12 , in the layout design stage, the ONO region 20 and the TUN region 30 are designed as an overlapping structure. A wafer for starting the storage area specific process TUN / ONO is provided. The deposition, photolithography, etching and stripping processes of the storage cell SONOS are performed on the wafer by using the TUN / ONO process. The subsequent wafer processing is carried out on the wafer, effectively eliminating the bulge between the storage cells SG and CG of the SONOS device, realizing the improvement of the GIDL effect of the 2T SONOS device, and improving product reliability and yield.
[0065] As Figure 13 and Figure 14 , they are respectively the electron microscope images of the storage transistor and the select transistor using the existing process and the process of the present invention. The process of photolithography and etching is adjusted by covering the region of the mask layer. The TUN region 30 and the ONO region 20 are set as an overlapping structure for the subsequent wafer processing. Without changing the back-end process, the oxide bulge can also be eliminated, the leakage can be improved, and the process flow and performance of the device are not affected.
[0066] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure belong to the protection scope of the technical solution of the present invention.
Claims
1. A manufacturing method of a SONOS device, characterized in that, Comprising the following steps: Providing a substrate, on which there are adjacent ONO regions and protection regions; Successively forming a second oxide layer, a second nitride layer, and a third oxide layer on the protection region; Successively forming a first nitride layer and a first oxide layer on the ONO region; Forming a first mask layer for photolithography on the first oxide layer, and the area covered by the first mask layer is smaller than the ONO region. The protection region and the region not covered by the first mask layer are TUN regions, and there is partial overlap between the ONO region and the TUN region.
2. The manufacturing method of the SONOS device according to claim 1, characterized in that, Forming the second oxide layer on the protection region includes: Forming a second oxide layer on the substrate; Forming a second mask layer on the second oxide layer in the protection region, and removing the second oxide layer not covered by the second mask layer.
3. The manufacturing method of the SONOS device according to claim 2, characterized in that, After removing the second oxide layer not covered by the second mask layer, the remaining second mask layer is also removed to form a second nitride layer and a third oxide layer on the second oxide layer.
4. The manufacturing method of the SONOS device according to claim 1, characterized in that, Depositing silicon nitride on the second oxide layer and the ONO region to form the second nitride layer and the first nitride layer in the protection region and the ONO region respectively.
5. The manufacturing method of the SONOS device according to claim 4, characterized in that, Depositing silicon oxide on the first nitride layer and the second nitride layer to form the third oxide layer and the first oxide layer in the protection region and the ONO region respectively.
6. The manufacturing method of the SONOS device according to claim 1, characterized in that, After forming the first nitride layer, the first oxide layer, the second oxide layer, the second nitride layer, and the third oxide layer, the second nitride layer and the third oxide layer are also removed.
7. The manufacturing method of the SONOS device according to claim 1, characterized in that, After forming the first mask layer for photolithography on the first oxide layer, deposition, photolithography, etching, and photoresist stripping processes are carried out in the TUN region and the ONO region to fabricate select tubes and storage tubes.
8. The manufacturing method of the SONOS device according to claim 1, characterized in that, The first mask layer includes at least one layer of photoresist.
9. The manufacturing method of the SONOS device according to claim 1, characterized in that, The second mask layer includes at least one layer of photoresist.
10. A SONOS device, characterized in that, Manufactured by using the manufacturing method of the SONOS device according to any one of claims 1-9.