Method for manufacturing side wall and semiconductor device
By forming a sacrificial side wall on the gate side wall and releasing space to fill the dielectric material to form an air gap, the capacitance problem between the gate and the lift source/drain in the semiconductor device is solved, and efficient parasitic capacitance reduction and yield improvement are achieved.
Patent Information
- Application Number
- CN202411795075.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-06
- Publication Date
- 2025-07-29
AI Technical Summary
In semiconductor devices, the capacitance between the gate and the lifting source/drain causes excessive parasitic capacitance, affecting the device's working speed and power consumption. Existing methods such as reducing the source/drain epitaxial layer volume or thickening the gate side wall thickness will lead to degradation of DC characteristics, and the air side wall height is similar to the gate, which can easily cause short circuits, affecting yield.
The sacrificial side wall is formed on the side wall of the gate. After forming the source/drain region, the sacrificial side wall is selectively removed, the space between the gate and the source/drain region is released, and the dielectric material is partially filled in the space to form an air gap, forming a half-air side wall, increasing the contact distance and reducing the risk of short circuit.
By forming a half-air side wall, the risk of short circuit between the contact part and the side wall is reduced, the process steps are simplified, resource saving, device working speed is improved and power consumption is reduced.
Smart Images
Figure CN120390446A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a method for manufacturing sidewalls and a semiconductor device. Background Art
[0002] In semiconductor devices such as fully depleted silicon-on-insulator (FDSOI) devices, the capacitance between the gate and the raised source / drain may be a major component of the parasitic capacitance. Reducing this part of the capacitance is crucial for improving the operating speed, radio frequency characteristics, and reducing power consumption of related circuits.
[0003] In the related art, some methods can be used to reduce the capacitance between the gate and the raised source / drain, such as reducing the volume of the source / drain epitaxial layer, increasing the thickness of the gate sidewall, reducing the dielectric constant value (k value) of the gate sidewall, etc. Among these, since the first two methods will cause the degradation of the direct current (DC) characteristics of the device, reducing the k value of the gate sidewall is considered the most effective method at present.
[0004] To reduce the k value of the sidewall, an air sidewall can be formed. However, the height of the air sidewall prepared in the related art is similar to the height of the gate, which is likely to cause a short circuit between the source / drain contact formed on the source / drain and the gate, affecting the yield. Summary of the Invention
[0005] In view of this, the present disclosure provides a method for manufacturing sidewalls and a semiconductor device.
[0006] According to a first aspect of the present disclosure, a method for manufacturing sidewalls is provided, including: forming a gate on a substrate; forming a sacrificial sidewall on the sidewall of the gate; forming source / drain regions on opposite sides of the gate having the sacrificial sidewall on the sidewall, the top surface of the source / drain regions being lower than the top surface of the gate, wherein the sacrificial sidewall is between the gate and the source / drain regions; selectively removing the sacrificial sidewall to release the space between the gate and the source / drain regions; and depositing a dielectric material on the substrate, the dielectric material partially filling the space and leaving an air gap in the space, the top of the air gap being lower than the top surface of the source / drain regions.
[0007] According to an embodiment of the present disclosure, forming the sacrificial sidewall includes: sequentially depositing a first dielectric layer and a second dielectric layer in a substantially conformal manner; performing anisotropic etching on the first dielectric layer and the second dielectric layer to obtain a first sub-sidewall and a second sub-sidewall, respectively.
[0008] According to an embodiment of the present disclosure, the first dielectric layer includes a low-k dielectric material, and the second dielectric layer includes an oxide.
[0009] According to an embodiment of the present disclosure, forming the source / drain regions includes epitaxially growing a semiconductor layer on the substrate.
[0010] According to an embodiment of the present disclosure, depositing a dielectric material includes depositing the dielectric material in a non-conformal manner.
[0011] According to an embodiment of the present disclosure, during the deposition of the dielectric material, the dielectric material grows from the surface defining the above space (e.g., the surface of the first sub-sidewall and the surface of the source / drain region), and closes the opening between the top of the source / drain region and the gate before completely filling the space.
[0012] According to an embodiment of the present disclosure, the dielectric material includes a nitride.
[0013] According to an embodiment of the present disclosure, the substrate includes a SOI substrate.
[0014] According to a second aspect of the present disclosure, a semiconductor device is provided, including: a substrate; a gate formed on the substrate; source / drain regions provided on opposite sides of the gate on the substrate, wherein the top surface of the source / drain region is lower than the top surface of the gate; and sidewalls between the gate and the source / drain regions, wherein an air gap is provided in the sidewalls, and the top of the air gap is lower than the top surface of the source / drain region.
[0015] According to an embodiment of the present disclosure, the sidewall includes: a first sub-sidewall having an L-shaped cross-section on the sidewall of the gate; a dielectric material in the space between the first sub-sidewall and the source / drain region, and the dielectric material partially fills the space to leave an air gap therein, wherein the dielectric material closes the opening between the top of the source / drain region and the first sub-sidewall.
[0016] According to an embodiment of the present disclosure, the method of manufacturing the sidewall forms a sacrificial sidewall on the sidewall of the gate and forms the source / drain region based on the sacrificial sidewall, and then selectively removes the sacrificial sidewall to release the space between the gate and the source / drain region. A dielectric material is partially filled in this space to form an air gap, obtaining a semi-air sidewall with a top lower than the source / drain region, increasing the distance between the semi-air sidewall and the contact portion, and reducing the risk that the contact hole communicates with the semi-air sidewall during etching for forming the contact portion. Moreover, the method of manufacturing the sidewall according to the embodiment of the present disclosure is simple to implement, saves process steps, and reduces the resources consumed in manufacturing the device. Description of the Drawings
[0017] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:
[0018] Figure 1 Schematically shows a flowchart of a method for manufacturing a sidewall according to an embodiment of the present disclosure;
[0019] Figure 2 Schematically shows a schematic diagram of forming a gate and depositing a first dielectric layer and a second dielectric layer according to an embodiment of the present disclosure;
[0020] Figure 3 Schematically shows a schematic diagram of manufacturing a first sub-sidewall and a second sub-sidewall and growing source / drain regions according to an embodiment of the present disclosure;
[0021] Figure 4 Schematically shows a schematic diagram of releasing a space according to an embodiment of the present disclosure;
[0022] Figure 5 Schematically shows a schematic diagram of a semiconductor device according to an embodiment of the present disclosure;
[0023] Figure 6 Shows a scanning electron microscope image of an air sidewall according to the related art. Detailed implementation manners
[0024] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the following detailed description, for the sake of explanation, many specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure. However, it is obvious that one or more embodiments can also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.
[0025] The terms used herein are merely for describing specific embodiments and are not intended to limit the present disclosure. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.
[0026] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.
[0027] In the case of using expressions such as "at least one of A, B, and C, etc.", generally, it should be interpreted according to the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include, but not be limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).
[0028] Embodiments of the present disclosure provide a method for fabricating sidewalls, which can utilize the characteristics of lifted source / drain to form semi-air sidewalls. Specifically, a sacrificial sidewall can be formed on the sidewalls of the gate, and based on the sacrificial sidewall, the source / drain regions can be fabricated. As described above, the source / drain regions can be lifted, so that the source / drain regions can at least partially overlap with the gate in the lateral direction, such that the sacrificial sidewall is interposed between the source / drain regions and the gate. Thereafter, the sacrificial sidewall can be removed, thereby releasing at least part of the space between the source / drain regions and the gate. The dielectric material can be filled in the released space in a manner that leaves air gaps therein.
[0029] The method for fabricating sidewalls according to embodiments of the present disclosure will be described in more detail below with reference to the embodiments.
[0030] Figure 1 A flowchart schematically showing a method for fabricating sidewalls according to embodiments of the present disclosure is shown. Figures 2 to 5 Structures at some stages in the method are schematically shown.
[0031] As Figure 1 shown, the method may include forming a gate on a substrate in operation S110.
[0032] Referring to Figure 2 , a substrate can be provided. The substrate can include various forms of substrates, such as a bulk semiconductor substrate such as a silicon wafer, a silicon-on-insulator (SOI) substrate, etc. Herein, the SOI substrate is taken as an example for description, but the present disclosure is not limited thereto. The SOI substrate can include a base substrate 211, a buried oxide layer 212 on the base substrate 211, and an SOI layer 213 on the buried oxide layer 212.
[0033] In the SOI substrate, active regions can be defined, for example, by shallow trench isolation (STI) 214. Semiconductor devices such as field effect transistors (FETs) can be formed on the active regions.
[0034] A (sacrificial) gate can be formed on the active region. For example, the SOI substrate can be subjected to pre-treatments such as cleaning. Then, an interface layer 221, a gate dielectric layer 222, a work function metal layer 223, and a gate conductor layer 224 can be sequentially formed on the SOI substrate, and then these layers can be patterned using lithography techniques to obtain the gate. The interface layer 221 can include silicon oxide, the gate dielectric layer 222 can include a high-k dielectric such as hafnium oxide, etc., the work function metal layer 223 can include titanium nitride, etc., and the gate conductor layer 224 can include polysilicon or a conductive metal such as tungsten. The structure of the gate is not limited to Figure 2 the example, but can include various other configurations. The gate can even be a sacrificial gate (for example, including a stack of an oxide interface layer and polysilicon), and can subsequently be replaced by a replacement gate process to be the final true gate. In Figure 2Two gates adjacent to each other are schematically shown, but this is merely an example, and the present disclosure is not limited thereto. Fewer or more gates may be formed.
[0035] In addition, in this example, the gate is formed directly on the SOI layer, so that a planar FET will seemingly be obtained subsequently. However, the present disclosure is not limited thereto. For example, fins or nanosheets or nanowires may also be formed on the substrate, and fin field-effect transistors (FinFETs) or nanosheet or nanowire FETs may be formed. The method according to the embodiments of the present disclosure is still applicable.
[0036] The method may further include forming sacrificial sidewalls on the sidewalls of the gate in operation S120.
[0037] Continuing to refer to Figure 2 , the first dielectric layer 231 and the second dielectric layer 232 may be sequentially deposited in a substantially conformal manner. Anisotropic etching such as reactive ion etching (RIE) in the vertical direction is performed on the first dielectric layer 231 and the second dielectric layer 232 to remove their laterally extending portions and leave the vertically extending portions, thereby obtaining the first sub-sidewall 241 and the second sub-sidewall 242 respectively, as Figure 3 shown. For example, the first dielectric layer 231 includes a low-k dielectric material such as silicon nitride, and the second dielectric layer 232 includes an oxide.
[0038] In this example, the first dielectric layer 231 may be used as an etch stop layer when etching the second dielectric layer 232 to form the second sub-sidewall 242. In addition, the second sub-sidewall 242 may be used as a sacrificial sidewall (subsequently removed). In some examples, the second sub-sidewall 242 serving as a sacrificial sidewall may be formed without forming the first sub-sidewall 241 (and thus the formation of the first dielectric layer 231 may be skipped).
[0039] The method may further include forming source / drain regions on opposite sides of the gate having sacrificial sidewalls on the sidewalls in operation S130.
[0040] Continuing to refer to Figure 3 , source / drain regions 251 may be formed on the surface of the SOI layer exposed by the gate by, for example, epitaxial growth. When growing the source / drain regions 251, in-situ doping may be performed to dope the source / drain regions 251 with a conductive type suitable for the FET to be formed, such as n-type or p-type. The source / drain regions 251 may include a suitable semiconductor material, such as an elemental semiconductor material such as silicon or germanium, or a compound semiconductor material such as SiGe. The source / drain regions 251 may be grown to a certain height (resulting in a raised source / drain), but the top surface may be lower than the top surface of the gate. The second sub-sidewall 242 (and additionally the first sub-sidewall 241) serving as a sacrificial sidewall may be interposed between the gate and the source / drain regions 251.
[0041] In Figure 3 the example of Figure 3 , the source / drain regions between two adjacent gates may be integral with each other.
[0042] The method may further include selectively removing the sacrificial sidewall in operation S140 to release the space between the gate and the source / drain region.
[0043] Referring to Figure 4 , the second sub-sidewall 242 serving as the sacrificial sidewall may be removed by selective etching to release the space 243 between the gate and the source / drain region 251. In this example, the first sub-sidewall 241 may still remain in this space. Therefore, in this example, the surface of the first sub-sidewall 241 and the sidewall of the source / drain region 251 jointly enclose the above-mentioned space 243.
[0044] The method may further include depositing a dielectric material on the substrate in operation S150 to partially fill the released space in such a way that an air gap remains in the space.
[0045] Referring to Figure 5 , the dielectric material 261 may be deposited on the substrate, for example, in a non-conformal manner. The dielectric material 261 may include a nitride such as silicon nitride. During the deposition of the dielectric material 261, an air gap 271 may remain in the space 243, for example, due to the bottleneck effect. More specifically, during the deposition, the dielectric material 261 may start growing from the surface defining the space (in this example, the surface of the first sub-sidewall 241 and the sidewall of the source / drain region 251), and close the opening between the top of the source / drain region 251 and the gate (in this example, the first sub-sidewall 241 on the sidewall of the gate) before completely filling the space 243. Thus, an air gap 271 wrapped within the dielectric material 261 and having a top lower than the top surface of the source / drain region 251 may be formed.
[0046] In Figure 5 the example of Figure 5 , an interlayer dielectric layer 281 such as an oxide is also shown.
[0047] As Figure 5 shown, the semiconductor device of this embodiment may include a substrate 211, a gate formed on the substrate 211, source / drain regions 251 disposed on opposite sides of the gate on the substrate 211, and sidewalls between the gate and the source / drain regions 251. The top surface of the source / drain regions 251 may be lower than the top surface of the gate. An air gap 271 may be present within the sidewalls, and the top of the air gap 271 may be lower than the top surface of the source / drain regions 251.
[0048] The sidewall may include a first sub-sidewall 241 with an L-shaped cross-section on the sidewall of the gate, and a dielectric material 261 in a space 243 between the first sub-sidewall 241 and the source / drain region 251. The dielectric material 261 partially fills the space 243, leaving an air gap 271 in the space 243. The dielectric material 261 closes the opening between the top of the source / drain region 251 and the first sub-sidewall 241.
[0049] Figure 6 An electron microscope image of an air sidewall according to the related art is shown.
[0050] As Figure 6 shown, various contact portions can be fabricated, such as contact portions on the source / drain region like self-aligned contacts (SAC), contact portions on the gate like contacts on active gates (COAG), etc. The contact portions can be formed by etching contact holes and filling the contact holes with a conductive material such as metal. If the contact holes communicate with the air sidewall during the etching process (e.g., due to their close positions), the subsequently filled conductive material may enter the air sidewall. For example, in Figure 6 the left half, it is shown that the metal material of the contact portion formed on the drain pattern D may form a conductive path (short circuit path) with the gate on its right due to entering the adjacent air sidewall. Similarly, in Figure 6 the right half, it is shown that the metal material of the contact portion formed on the gate may form a conductive path (short circuit path) with the source / drain region on the right due to entering the air sidewall on the sidewall of the gate.
[0051] According to an embodiment of the present disclosure, a method of manufacturing a sidewall forms a sacrificial sidewall on the sidewall of the gate, forms a source / drain region based on the sacrificial sidewall, and then selectively removes the sacrificial sidewall to release the space between the gate and the source / drain region. A dielectric material is partially filled in this space to form an air gap, resulting in a semi-air sidewall with a top lower than the source / drain region, increasing the distance between the semi-air sidewall and the contact portion, and reducing the risk that the contact hole communicates with the semi-air sidewall during the etching for forming the contact portion. Moreover, the method of manufacturing a sidewall according to the embodiment of the present disclosure is simple to implement, saves process steps, and reduces the resources consumed in manufacturing the device.
[0052] Those skilled in the art can understand that the features described in various embodiments of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in various embodiments of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.
[0053] The embodiments of the present disclosure have been described above. However, these embodiments are merely for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments have been described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present disclosure.
Claims
1. A method of manufacturing a sidewall, comprising: forming a gate on a substrate; forming a sacrificial sidewall on sidewalls of the gate; forming source / drain regions on opposite sides of the gate having the sacrificial sidewall on the sidewalls, wherein a top surface of the source / drain regions is lower than a top surface of the gate, and wherein the sacrificial sidewall is interposed between the gate and the source / drain regions; selectively removing the sacrificial sidewall to release a space between the gate and the source / drain regions; and depositing a dielectric material on the substrate, the dielectric material partially filling the space and leaving an air gap in the space, a top of the air gap being lower than the top surface of the source / drain regions.
2. The method according to claim 1, wherein, Forming the sacrificial sidewall comprises: consecutively and conformally depositing a first dielectric layer and a second dielectric layer; anisotropically etching the first dielectric layer and the second dielectric layer to obtain a first sub-sidewall and a second sub-sidewall, respectively.
3. The method according to claim 2, wherein The first dielectric layer comprises a low-k dielectric material, and the second dielectric layer comprises an oxide.
4. The method according to claim 1, wherein, Forming the source / drain regions comprises epitaxially growing a semiconductor layer on the substrate.
5. The method according to claim 1, wherein Depositing the dielectric material comprises: depositing the dielectric material in a non-conformal manner.
6. The method according to claim 5, wherein During depositing the dielectric material, the dielectric material grows from a surface defining the space and closes an opening between the top of the source / drain regions and the gate before completely filling the space.
7. The method according to claim 5, wherein The dielectric material comprises a nitride.
8. The method according to any one of claims 1 to 7, wherein The substrate comprises a SOI substrate.
9. A semiconductor device, comprising: a substrate; a gate formed on the substrate; source / drain regions provided on opposite sides of the gate on the substrate, wherein a top surface of the source / drain regions is lower than a top surface of the gate; and a sidewall interposed between the gate and the source / drain regions, wherein an air gap is present in the sidewall, a top of the air gap being lower than the top surface of the source / drain regions.
10. The semiconductor device according to claim 9, wherein, The sidewall comprises: a first sub-sidewall having an L-shaped cross-section on a sidewall of the gate; a dielectric material in a space between the first sub-sidewall and the source / drain regions, the dielectric material partially filling the space and thus leaving the air gap in the space, wherein the dielectric material closes an opening between the top of the source / drain regions and the first sub-sidewall.