System-on-chip device

Abstract

The invention discloses a system-on-chip device. The system-on-chip device may include: at least one power domain; and at least one power management unit (PMU, Power Management Unit) for correspondingly controlling the at least one power domain, the power management unit comprising: a first region responsible for processing and controlling, a second region responsible for processing and controlling, a third region responsible for processing and controlling, and a fourth region responsible for processing and controlling; and a second region for physically transmitting a signal, the first region and the second region being independently segmented and respectively present in different structural elements of the system-on-chip device.

Description

Technical Field

[0001] The present invention relates to a system-on-chip device, and more particularly, to a system-on-chip device in which microcontroller units for controlling power domains are arranged in a cluster form in a specific area. Background Art

[0002] Methods for designing a controller for handling the power-up / down sequence of a system-on-chip (SoC) include a method designed by a state machine and a method designed by a microcontroller unit (MCU).

[0003] In the past, the complexity of the system-on-chip was low and the power-up / down sequence was relatively simple, and the power controller was mainly designed by a state machine. The state machine has the advantages of small size and fast operation speed. On the contrary, it can only execute a preset form of sequence, thus having the disadvantage of poor flexibility.

[0004] Therefore, as the system-on-chip becomes more and more complex, the power-up / down sequence also becomes more complex. In order to flexibly handle various abnormal cases generated at the actual silicon level, in recent years, the method of designing a power controller using a microcontroller unit with higher flexibility has become the mainstream trend.

[0005] Prior Art Documents

[0006] Patent Document 1: Korean Patent Publication No. 10-2301639 (September 7, 2021) Summary of the Invention

[0007] Technical Problem

[0008] The object to be solved by the present invention is to provide a system-on-chip device in which all power management units for controlling power domains are arranged in a cluster form in a specific area of the system-on-chip.

[0009] Technical Solution

[0010] A system-on-chip (SoC) device according to an embodiment of the present invention may include: at least one power domain; and at least one power management unit (PMU), respectively corresponding to control the at least one power domain. The power management unit includes: a first area responsible for processing and control; and a second area for physically transmitting signals. The first area and the second area are independently partitioned and exist in different structural elements of the system-on-chip device respectively.

[0011] In the system-on-chip device, corresponding to the at least one power management unit, at least one of the first areas may exist respectively. At least one first area exists in a cluster form in a specific area other than the at least one power domain within the system-on-chip device.

[0012] In the system-on-chip device, a first power domain that always operates when the system-on-chip device is operating may also be included. The at least one power domain can operate selectively as a second power domain when the system-on-chip device is operating. The at least one first area exists in a cluster form in the first power domain.

[0013] In the system-on-chip device, the first power domain may further include a power system manager (PSM), an internal bus, test logic, and a memory.

[0014] In the system-on-chip device, corresponding to the at least one power management unit, at least one of the second areas may exist respectively. At least one second area exists respectively in a non-power gating area of the at least one power domain within the system-on-chip device.

[0015] The system-on-chip device is characterized in that the first area is a micro control unit (MCU), that is, a power domain manager (PDM), for controlling the corresponding power domain, and the second area is a power operating unit (POU).

[0016] In the system-on-chip device, there may also be included a plurality of sub-system-on-chip devices that exist hierarchically at a lower level. Each of the plurality of sub-system-on-chip devices includes a plurality of power domains, and a plurality of first regions that respectively control the plurality of power domains exist in a specific region other than the plurality of power domains in each upper system device in a clustered form. The plurality of first regions in the clustered form respectively correspond to and exist in the plurality of sub-system-on-chip devices.

[0017] In the system-on-chip device, there may also be included a memory. Corresponding to the at least one power management unit, at least one of the first regions exists respectively. The memory is divided according to addresses, and corresponding to at least one first region, independent address regions are respectively allocated.

[0018] In the system-on-chip device, when the programs required for operation of the at least one first region are the same, the programs can be shared and used in a predetermined address region of the memory.

[0019] Effects of the Invention

[0020] According to an embodiment of the present invention, the simplification and high efficiency of the system-on-chip structure can be achieved by arranging power domain managers in a clustered form in a specific region of the system-on-chip.

[0021] Moreover, according to an embodiment of the present invention, by creating a large-sized memory instance instead of setting small-sized micro control units for controlling each power domain in each power domain, the area of the system-on-chip can be reduced. Brief Description of the Drawings

[0022] Figure 1 A diagram showing the structure in which a power controller of a power domain of the present invention exists inside the corresponding power domain.

[0023] Figure 2 For detailed illustration Figure 1 A diagram showing the internal structure of a sub-power management unit inside the power domain in

[0024] Figure 3 A block diagram showing the structure of the system-on-chip device of the present invention.

[0025] Figure 4 A diagram showing the detailed setting structure of the power management unit included in the system-on-chip device according to an embodiment of the present invention.

[0026] Figure 5 A diagram showing the detailed setting structure of the power management unit included in the system-on-chip device according to another embodiment of the present invention.

[0027] Figure 6a andFigure 6b A diagram showing the memory structure included in the system-on-chip device according to another embodiment of the present invention.

[0028] Figure 7 A diagram showing the computing device according to an embodiment of the present invention.

[0029] Description of reference numerals

[0030] 100, 300, 400, 500: System-on-chip device

[0031] 110, 430: Always-on power domain (PD_AON)

[0032] 115, 320, 435: Power management unit (PMU)

[0033] 116, 436: Power system manager (PSM)

[0034] 117, 229, 439: Memory

[0035] 118, 225, 437: Internal bus

[0036] 120, 130, 140, 310, 410_A, 410_B, 410_C: Power domain

[0037] 125, 135, 145: Sub-power management unit

[0038] 210, 422_A, 422_B, 422_C, 621, 622, 623, 624, 661, 662, 663, 664: Power domain manager (PDM)

[0039] 221: Control interface

[0040] 223: Power control signal

[0041] 227, 438: Test logic

[0042] 322: First region

[0043] 324: Second region

[0044] 415_A, 415_B, 415_C: Non-power gating region

[0045] 424_A, 424_B, 424_C: Power operating unit (POU)

[0046] 501, 502, 503: Subsystem

[0047] 611, 612, 613, 614: Memory space

[0048] 651: Specific area Detailed implementation manner

[0049] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art to which the present invention pertains can easily implement it. However, the present invention can be implemented in a variety of different ways and is not limited to the embodiments described herein. In addition, in order to clearly illustrate the present invention in the drawings, parts irrelevant to the description are omitted, and throughout the specification, similar parts are given similar reference numerals.

[0050] In this specification, repeated descriptions of the same structural elements are omitted.

[0051] Moreover, in this specification, it should be understood that when a certain structural element is referred to as "connected" or "contacted" with another structural element, the said structural element may be directly connected or contacted with the said other structural element, but there may also be other structural elements in between. On the contrary, in this specification, when a certain structural element is referred to as "directly connected" or "directly contacted" with another structural element, it should be understood that there are no other structural elements in between.

[0052] Furthermore, the terms used in this specification are only for explaining specific embodiments and are not intended to limit the present invention.

[0053] Moreover, in this specification, unless otherwise clearly indicated in the context, the singular form may include the plural form.

[0054] Moreover, in this specification, it should be understood that terms such as "comprising" or "having" only specify the existence of the features, numbers, steps, operations, structural elements, components or combinations thereof described in the specification, and do not preclude in advance the existence or additional possibility of one or more other features, numbers, steps, operations, structural elements, components or combinations thereof.

[0055] Moreover, in this specification, the term "and / or" includes combinations of multiple recited items or any one of the multiple recited items. In this specification, "A or B" may include "A", "B" or "A and B".

[0056] Moreover, in this specification, detailed descriptions of well-known functions and structures that may obscure the gist of the present invention will be omitted.

[0057] Figure 1 A diagram showing the structure in which the power controller of the power domain of the present invention exists inside the corresponding power domain.

[0058] Refer to Figure 1, the system-on-chip device 100 (SoC, System-on-Chip) of the present invention may include an always-on power domain 110 and multiple power domains 120, 130, 140.

[0059] The always-on power domain 110 (Always On Domain) is used to control the power of the system-on-chip device 100 (SoC), and for this purpose, it includes a power management unit 115 (PMU, Power Management Unit). The power management unit 115 (PMU) includes a power system manager 116 (PSM, Power System Manager), a memory 117, an internal bus 118, etc.

[0060] The multiple power domains 120, 130, 140 (Power Domain, PD) include a power domain A (PD_A) 120, a power domain B (PD_B) 130, and a power domain C (PD_C) 140. In this case, the multiple power domains 120, 130, 140 respectively include sub-power management units 125, 135, 145 in the non-power gating regions (Non-Power Gating regions, Non-PG domains) of the corresponding power domains. Among them, the sub-power management units 125, 135, 145 may be micro control units for power control. Specifically, the non-power gating region of the power domain A (PD_A) 120 includes the sub-power management unit 125, the non-power gating region of the power domain B (PD_B) 130 includes the sub-power management unit 135, and the non-power gating region of the power domain C (PD_C) 140 includes the sub-power management unit 145.

[0061] In order for the micro control unit to operate, a memory for storing instructions (Instruction) and data must be provided. And if there is a memory, correspondingly, a bus interface for downloading a program to the memory and a built-in self-test logic (BIST Logic Insertion) for testing the corresponding memory are required.

[0062] As Figure 1As shown, if the power controller of a certain power domain itself must exist inside the corresponding power domain, it must exist in the non-power gating area of the corresponding power domain. When there is a micro control unit for power control in this area, additional hardware including the memory required for the operation of the micro control unit (such as bus interface, BIST Logic Insertion, etc.) needs to enter together. In this way, it is inefficient in many aspects. For example, the non-power gating area will increase, the top routing will increase, and a separate power supply needs to be provided for the memory.

[0063] Figure 2 To show in detail Figure 1 The figure of the internal structure of the sub-power management unit inside the power domain in

[0064] Specifically, Figure 2 Shows the detailed internal structure of power domain A (PD_A) 120. There is a sub-power management unit 125 for controlling the corresponding power domain A (PD_A) in the non-power gating area (Non-PG domain) inside power domain A (PD_A) 120. The sub-power management unit 125 includes a power domain manager 210 (PDM, Power Domain Manager), a control interface 221, a power control signal 223, an internal bus 225, test logic 227, and a memory 229.

[0065] In this way, all the logic required to control the power domain (PD) exists in the non-power gating area (Non-PG domain). Specifically, the non-power gating area (Non-PG domain) not only includes the power domain manager 210 for actual power sequence control, but also includes the memory 229 used by the power domain manager 210, the BIST logic for testing this memory 229, various related interfaces 221, and various structures such as test logic 227 for controlling how to handle the power control signal 223 in the test mode.

[0066] This structural method will inevitably lead to an increase in design complexity, a continuous increase in the non-power gating area (Non-PG domain), and a large number of signals for controlling interfaces and bus interfaces, etc., resulting in an increase in area overhead.

[0067] And, although the micro control unit for controlling each power domain ( Figure 2The power domain manager 210) in [it] only executes simple small instructions, and the memory capacity required for this is within 1K. However, creating multiple small-sized memory instances and dispersing them in multiple power domains is very inefficient from the perspective of memory management.

[0068] Figure 3 The block diagram showing the structure of the system-on-chip device of the present invention.

[0069] The system-on-chip device 300 (System on Chip, SoC) of the present invention includes products and systems that can be fully driven in one integrated circuit, and the device can be implemented by a chip, a module, or a system.

[0070] The system-on-chip device 300 of the present invention may include a power domain 310 and a power management unit 320.

[0071] The power domain 310 can handle the power-on / power-off sequence of the system-on-chip device 300.

[0072] The system-on-chip device 300 may include at least one power domain 310.

[0073] The power management unit 320 (PMU, Power Management Unit) can respectively correspond to control at least one power domain 310. For this reason, the system-on-chip device 300 may include at least one power management unit 320.

[0074] Specifically, the power management unit 320 may include a first region 322 and a second region 324. The first region 322 is responsible for processing and control, and the second region 324 is used for physically transmitting signals. In this case, the first region 322 and the second region 324 may be independently divided and exist in different structural elements of the system-on-chip device 300 respectively.

[0075] Refer to Figure 3 , the power management unit 320 includes a first region 322 and a second region 324. However, this only conceptually shows the structure of the power management unit 320 in the form of a block diagram. It should be noted that the setting or structure of the first region 322 and the second region 324 in the actual system-on-chip device 300 can be flexibly implemented. For example, both the first region 322 and the second region 324 constitute the power management unit 320, but as described above, they can be independently divided and respectively set in different structural elements of the system-on-chip device 300.

[0076] Corresponding to at least one power management unit 320, there can be at least one first region 322 respectively. According to an example, the first region 322 can be a microcontroller unit (MCU) that controls the corresponding power domain 310, that is, a power domain manager (PDM).

[0077] At least one first region 322 can exist in a clustered form within the system-on-chip device 300 in a specific region other than at least one power domain 310.

[0078] According to an embodiment, at least one first region 322 can exist in a clustered form in an always-on power domain. Specifically, the system-on-chip device 300 can also include a first power domain ( Figure 4 430 in) that always operates when the corresponding system-on-chip device 300 is operating. Among them, the first power domain ( Figure 4 430 in) can be an always-on power domain. And at least one power domain 310, as a second power domain, can operate selectively when the system-on-chip device 300 is operating. In this case, at least one first region 322 can exist in a clustered form in the first power domain ( Figure 4 430 in).

[0079] The first power domain ( Figure 4 430 of) can also include a power system manager (PSM), an internal bus, test logic, and a memory.

[0080] Corresponding to at least one power management unit 320, there can be at least one second region 324 respectively. According to an example, the second region 324 can be a power operating unit (POU).

[0081] At least one second region 324 can exist respectively within the system-on-chip device 300 in the non-power gating regions ( Figure 4 415_A, 415_B, 415_C in) of at least one power domain 310.

[0082] According to an embodiment, the system-on-chip device 300 may be composed of a hierarchical structure, and each subsystem has a power domain manager that controls the power domain in the form of a cluster. Specifically, the system-on-chip device 300 may further include a plurality of sub-system-on-chip devices hierarchically located at a lower level, and each of the plurality of sub-system-on-chip devices includes a plurality of power domains 310. In this case, a plurality of first regions 322 respectively corresponding to control the plurality of power domains 310 may exist in a cluster manner in a specific region other than the plurality of power domains 310 within each of the plurality of sub-system-on-chip devices, and the plurality of first regions 322 in the form of a cluster may respectively correspond to exist in the plurality of sub-system-on-chip devices.

[0083] On the other hand, the system-on-chip device 300 may further include a memory (not shown). Corresponding to at least one power management unit, at least one first region 322 may exist respectively. In this case, the memory (not shown) may be divided according to addresses to respectively correspond to at least one first region 322, and an independent address region may be allocated. According to an embodiment, when the programs that at least one first region 322 needs to operate are the same, the programs may be shared and used in a predetermined address region of the memory (not shown).

[0084] Figure 4 A diagram showing the detailed setting structure of the power management unit included in the system-on-chip device according to an embodiment of the present invention.

[0085] The system-on-chip device 400 according to an embodiment of the present invention may include a power domain 430 that is always on and a plurality of power domains 410_A, 410_B, 410_C.

[0086] The power domain 430 (Always On Domain) that is always on is used to control the power of the system-on-chip device 400 (SoC). For this purpose, it includes a power management unit 435 (PMU, Power Management Unit). The power management unit 435 (PMU) includes a plurality of power domain managers 422_A, 422_B, 422_C respectively corresponding to control the plurality of power domains 410_A, 410_B, 410_C. And, the power management unit 435 (PMU) includes a power system manager 436 (PSM, Power System Manager), an internal bus 437, a test logic 438, and a memory 439, etc. Among them, the power system manager 436 (PSM) is used to control and manage the power of the system-on-chip device 400. The memory 439 stores instructions and data for making the plurality of power domain managers 422_A, 422_B, 422_C operate. The internal bus 437 downloads programs to the memory 439. And, the test logic 438 tests the memory 439.

[0087] The multiple power domains 410_A, 410_B, 410_C include a power domain A (PD_A) 410_A, a power domain B (PD_B) 410_B, and a power domain C (PD_C) 410_C. In this case, the non-power-gated regions 415_A, 415_B, 415_C of the respective power domains of the multiple power domains 410_A, 410_B, 410_C include power operating units (POUs) 424_A, 424_B, 424_C. Among them, the POUs 424_A, 424_B, 424_C can be regions for physically transmitting signals. Specifically, the non-power-gated region 415_A of the power domain A (PD_A) 410_A includes the POU 424_A, the non-power-gated region 415_B of the power domain B (PD_B) 410_B includes the POU 424_B, and the non-power-gated region 415_C of the power domain C (PD_C) 410_C includes the POU 424_C.

[0088] In the system-on-chip device 400 according to an embodiment of the present invention configured as such, a power management unit (PMU) for controlling a specific power domain does not exist within the corresponding power domain, but is arranged in a specific region of the system-on-chip 400 in an all-clustered structure.

[0089] Comparing the structure proposed by the present invention with the existing structure, the biggest difference is that the power management unit (PMU) required to control a certain power domain is separated into a part responsible for processing and control (PDM in Figure 4 ), and a part for physically transmitting signals ( Figure 4 POU in), and they are independently configured. Specifically, various complex parts of the power management unit are all parts related to the power domain manager, and these parts are arranged in a clustered form in a specific region inside the system-on-chip, rather than in the power domain. And only the part for physically transmitting signals according to each power domain is arranged in the Non-PG domain within each power domain.

[0090] Figure 5 FIG. is a diagram showing the detailed setting structure of the power management unit included in the system-on-chip device according to still another embodiment of the present invention.

[0091] The structure in which the complex parts responsible for processing and control (parts related to the PDM) in the power management unit are arranged in a clustered form in a specific region of the system-on-chip rather than in the power domain can be further extended to adapt to the structure of the system-on-chip. In this case, the power domain managers arranged in a clustered form do not only exist in one specific region of the system-on-chip, but multiple ones can be set according to multiple subsystems to adapt to the structure of the system-on-chip.

[0092] That is, although multiple power domains can be set flat under a system-on-chip, for a more complex system-on-chip, rather than being configured flatly, it is more inclined to hierarchically set multiple subsystems (i.e., sub-SOCs) under the system-on-chip, and be configured in a form where multiple power domains are set under the subsystems.

[0093] Refer to Figure 5 , a central processing unit (CPU) subsystem 501, a graphics processing unit (GPU) subsystem 502, and a camera subsystem 503 are set under the system-on-chip 500, and multiple power domains are respectively set under each subsystem. In this case, the power domain managers arranged in a cluster form can be set respectively for the subsystems 501, 502, and 503. Since the structure (architecture) of setting subsystems under the system-on-chip 500 itself means processing the functional features of the system-on-chip in a hierarchical manner, it is very likely that power management is also set according to this structure.

[0094] However, according to an embodiment, the distinction between subsystems can also be ignored, and only one power domain manager arranged in a cluster form is set for the entire system-on-chip. The design of this setting structure may vary according to factors such as software operation strategies.

[0095] Figure 6a and Figure 6b FIG. is a diagram showing the memory structure included in a system-on-chip device according to another embodiment of the present invention.

[0096] For one memory, it can be divided according to the address, and an independent address range is allocated to each microcontroller unit for use.

[0097] Moreover, for more efficient power management and control, when the programs that multiple microcontroller units need to execute are the same, the memory with the same address range can also be shared by multiple microcontroller units.

[0098] In Figure 6aIn the case where the programs to be used by the four power domain managers 621, 622, 623, and 624 are all different, the programs Program A, Program B, Program C, and Program D that the respective power domain managers 621, 622, 623, and 624 can use correspondingly can respectively occupy the allocated memory spaces 611, 612, 613, and 614. In this case, the memory spaces 611, 612, 613, and 614 will be occupied according to the number of the power domain managers 621, 622, 623, and 624.

[0099] However, as Figure 6b shown, when the programs used by the four power domain managers 661, 662, 663, and 664 are the same (i.e., all use Program A), there is no need to store the same program in four locations. Instead, Program A can be stored only in a specific area 651 in one place, so that all the power domain managers 661, 662, 663, and 664 can share the corresponding program. Thus, the required memory capacity can be reduced.

[0100] The structure of the system on chip proposed in this patent can also flexibly respond in certain situations and form a power management structure that meets the requirements of the system on chip.

[0101] The structure proposed by the present invention has the following advantages.

[0102] First, it is the simplification and high efficiency of the structure. The power domain managers arranged in a cluster form like this are centrally set in a specific area of the corresponding system on chip, preferably in one place of the Always on Domain (AON). According to this structure, multiple micro control units are gathered in one place. Even if each power domain does not have its own independent memory, bus interface, test logic, etc., they can share one memory, one bus, one test logic, etc. Therefore, the structure is simpler and more efficient.

[0103] Second, it is the reduction of the area. The control micro control unit ( Figure 4 the PDM in ) only executes simple small instructions. For this reason, the required memory capacity is within 1K. Compared with creating multiple small-sized memory instances and dispersing them in each power domain, creating one large-sized memory instance actually has a much smaller area.

[0104] Thirdly, from the perspective of the role and responsibility in the system-on-chip design, this structure is efficient. Most complex system-on-chips are designed by multiple designers who are respectively responsible for their own power domains. Most of these responsible persons are experts focusing on the functionality of the modules they are in charge of, lacking domain knowledge in the power management of the entire system-on-chip. However, if each power domain has a power controller with a complex interface and structure, it will be difficult for designers to design the modules they are responsible for.

[0105] The proposed structure concentrates all the parts that require power management domain expertise on the main power management unit side. Only the minimum necessary parts for physically transmitting power control signals are retained within each module. The person in charge of each module does not need to concern themselves with the power management within their own module. The person in charge of the power management of the entire system-on-chip only needs to focus on the design of the main power management unit in the AON area, so it is very efficient.

[0106] Figure 7 FIG. for showing the computing device of the embodiment of the present invention. Figure 7 The computing device TN100 can be the system-on-chip device 300 described in this specification.

[0107] In Figure 7 In the embodiment, the computing device TN100 may include at least one processor TN110, a transceiver device TN120, and a memory TN130. And the computing device TN100 may further include a storage device TN140, an input interface device TN150, an output interface device TN160, etc. The structural elements included in the computing device TN100 can be connected through a bus TN170 to communicate with each other.

[0108] The processor TN110 can execute program instructions stored in at least one of the memory TN130 and the storage device TN140. The processor TN110 can refer to a central processing unit (CPU), a graphics processing unit (GPU), or a dedicated processor that can execute the method described in the embodiment of the present invention. The processor TN110 can implement the processes, functions, and methods related to the embodiment of the present invention. The processor TN110 can control each structural element of the computing device TN100.

[0109] The memory TN130 and the storage device TN140 can respectively store various information related to the operation of the processor TN110. The memory TN130 and the storage device TN140 can respectively be constituted by at least one of a volatile storage medium and a non-volatile storage medium. For example, the memory TN130 can be constituted by at least one of a read only memory (ROM) and a random access memory (RAM).

[0110] The transceiver device TN120 can transmit or receive wired signals or wireless signals. The transceiver device TN120 can be connected to a network for communication.

[0111] On the other hand, the embodiments of the present invention are not only implemented by the said device and / or method, but also can be implemented by a program that realizes functions corresponding to the structure of the embodiments of the present invention or a recording medium recording the said program. Those of ordinary skill in the technical field to which the present invention pertains can easily realize such an implementation manner based on the description of the said embodiments.

[0112] The above has described in detail the embodiments of the present invention, but the scope of protection required by the invention of the present invention is not limited thereto. Multiple variations and improvement forms made by those of ordinary skill in the art using the basic concepts of the present invention defined in the scope of protection required by the invention all belong to the scope of protection required by the invention of the present invention.

Claims

1. An on-chip system device, characterized in that, Comprising: At least one power domain; and At least one power management unit, respectively corresponding to control the at least one power domain, The power management unit includes: A first region responsible for processing and control; and A second region for physically transmitting signals, The first region and the second region are independently partitioned and exist in different structural elements of the on-chip system device respectively.

2. The on-chip system device according to claim 1, characterized in that, Corresponding to the at least one power management unit, at least one of the first regions exists respectively, At least one first region exists in a cluster form in a specific region other than the at least one power domain within the on-chip system device.

3. The on-chip system device according to claim 2, characterized in that, It further includes a first power domain that always operates when the on-chip system device is operating, The at least one power domain can selectively operate as a second power domain when the on-chip system device is operating, The at least one first region exists in a cluster form in the first power domain.

4. The system-on-chip device according to claim 3, wherein The first power domain further includes a power system manager, an internal bus, test logic, and a memory.

5. The on-chip system device according to claim 1, characterized in that, Corresponding to the at least one power management unit, at least one of the second regions exists respectively, At least one second region exists respectively in the non-power-gated regions of the at least one power domain within the on-chip system device.

6. The on-chip system device according to claim 1, characterized in that, The first region is a micro-control unit that controls the corresponding power domain, namely a power domain manager, The second region is a power operation unit.

7. The on-chip system device according to claim 1, characterized in that, It further includes a plurality of sub-on-chip system devices existing in a hierarchical manner at a lower level, The plurality of sub-on-chip system devices respectively include a plurality of power domains, A plurality of first regions respectively corresponding to control the plurality of power domains exist in a cluster form in specific regions other than the plurality of power domains within each of the plurality of sub-on-chip system devices, and the plurality of first regions in cluster form respectively correspond to exist in the plurality of sub-on-chip system devices.

8. The on-chip system device according to claim 1, characterized in that, It further includes a memory, Corresponding to the at least one power management unit, at least one of the first regions exists respectively, The memory is divided according to addresses, and corresponding to at least one first region, independent address regions are respectively allocated.

9. The system-on-chip device according to claim 8, wherein When the programs required for the operation of the at least one first region are the same, the programs are shared and used in a predetermined address region of the memory.

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