Semiconductor structure and memory device and method of manufacturing same

Abstract

The invention relates to a semiconductor structure, a memory device and a manufacturing method thereof. The semiconductor structure comprises a first doped region, a second doped region, a first ohmic contact region, a second ohmic contact region and a first dielectric structure. The second doped region is in contact with the first doped region. The first ohmic contact region is in contact with a bottom surface of the first doped region. The second ohmic contact region is in contact with a top surface of the second doped region. The first dielectric structure surrounds each of the first doped region, the second doped region, the first ohmic contact region and the second ohmic contact region. The first doped region is doped with a dopant of a first conductivity type, and the second doped region is doped with a dopant of a second conductivity type opposite the first conductivity type such that a p-n junction is formed between the first doped region and the second doped region.

Description

BACKGROUND OF THE INVENTION

[0002] Related Applications

[0003] This application claims priority to U.S. Provisional Patent Application 63 / 387,972, filed on December 19, 2022, entitled "Structure and Fabrication Process of Vertical Diodes and Memory Cells", which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0004] The present invention relates to semiconductor structures and memory devices and methods of manufacturing the same. In particular, some embodiments of the present disclosure relate to semiconductor structures including vertical PN diodes, memory devices including vertical PN diodes, and methods of manufacturing the same. BACKGROUND ART

[0005] Due to the continuous development of portable devices, the demand for non-volatile memory is increasing. As device sizes decrease, non-volatile memories that are more efficient, have faster memory access, and low power consumption have become a hot topic to meet market demands. However, there are several technical problems that need to be overcome to provide the desired characteristics. First, in conventional non-volatile memory devices, transistors are used as selectors. When the size of the transistors decreases and the integration density increases, the space between these devices also decreases. The space between devices is crucial for the performance of the devices, and when the space is too small, these devices may interfere with each other. Second, transistors have a saturation region, and the current that can be provided is limited by their inherent characteristics. When a non-volatile memory device has high current density requirements, such as a magnetoresistive random access memory (MRAM) device, the size of the transistors capable of providing the current density will be significantly larger. Third, there may be current leakage in the channel region of the transistors formed in the semiconductor substrate, which may reduce efficiency and result in high power consumption.

[0006] When using transistors as selectors for non-volatile memory devices, a compromise must be made to balance the feature size and the space between devices, and the performance of each device may need to be optimized. When more devices are placed in a chip, the parasitic capacitance and power consumption may increase due to the small space between devices and current leakage. There is still a need to improve the structure and process to make the memory device more efficient, have faster memory access, and low power consumption. SUMMARY OF THE INVENTION

[0007] According to the present disclosure, a semiconductor structure is provided. The semiconductor structure includes a first doped region, a second doped region, a first ohmic contact region, a second ohmic contact region, and a first dielectric structure. The second doped region is in contact with the first doped region. The first ohmic contact region is in contact with the bottom surface of the first doped region. The second ohmic contact region is in contact with the top surface of the second doped region. The first dielectric structure surrounds each of the first doped region, the second doped region, the first ohmic contact region, and the second ohmic contact region. The first doped region is doped with a dopant of a first conduction type, and the second doped region is doped with a dopant of a second conduction type opposite to the first conduction type, such that a p-n junction is formed between the first doped region and the second doped region. An ohmic junction is formed between the first doped region and the first ohmic contact region. An ohmic junction is formed between the second doped region and the second ohmic contact region.

[0008] According to the present disclosure, a method for manufacturing a semiconductor structure is provided. The method includes providing a semiconductor substrate including a first substrate and a second substrate on the first substrate (step (a)), forming a first ohmic contact region on a first surface of the second substrate or in the second substrate (step (b)), patterning the second substrate to define a first doped region (step (c)), adding a third substrate to the first surface of the second substrate, wherein the second substrate is between the third substrate and the first substrate (step (d)), removing the first substrate and exposing a second surface of the second substrate opposite to the first surface (step (e)), exposing a second doped region in the second substrate or on the second surface of the second substrate or forming the second doped region in the second substrate or on the second surface of the second substrate (step (f)), and forming a second ohmic contact region on the second surface of the second substrate or in the second substrate (step (g)).

[0009] According to the present disclosure, a semiconductor structure is provided. The semiconductor structure includes a first diode and a second diode. The first diode includes a first doped region and a second doped region on and in contact with the first doped region. The second diode includes a third doped region and a fourth doped region on and in contact with the third doped region. Each of the first doped region and the fourth doped region is doped with a dopant of a first conduction type. Each of the second doped region and the third doped region is doped with a dopant of a second conduction type opposite to the first conduction type. The top surface of the second doped region is higher than the bottom surface of the third doped region. The top surface of the fourth doped region is higher than the bottom surface of the first doped region.

[0010] According to the present disclosure, a method for manufacturing a semiconductor structure. The method includes providing a semiconductor substrate including a first substrate and a second substrate on the first substrate (step (a)), forming a third doped region of a second diode in the second substrate or on a first surface of the second substrate (step (b)), patterning the second substrate to define a first doped region of a first diode and a fourth doped region of the second diode (step (c)), adding a third substrate to the first surface of the second substrate, wherein the second substrate is between the third substrate and the first substrate (step (d)), removing the first substrate and exposing a second surface of the second substrate opposite to the first surface (step (e)), exposing a second doped region of the first diode in the second substrate or on the second surface of the second substrate or forming the second doped region in the second substrate or on the second surface of the second substrate (step (f)).

[0011] According to the present disclosure, a memory device is provided. The memory device includes a memory cell group, an electrode, a first diode pair, and a second diode pair. The memory cell group has a first end and a second end. The electrode extends laterally in a first direction from a first side of the memory cell group to a second side of the memory cell group. The memory cell group is electrically coupled to the electrode from a second end of the memory cell group. The first diode pair is disposed on the first side of the memory cell group. The second diode pair is disposed on the second side of the memory cell group. Each of the first diode pair and the second diode pair includes a first diode and a second diode. Each first diode of the first diode pair and the second diode pair includes a first doped region and a second doped region on and in contact with the first doped region. Each second diode of the first diode pair and the second diode pair includes a third doped region and a fourth doped region on and in contact with the third doped region. Each first doped region of the first diode pair and the second diode pair is doped with a dopant of a first conductivity type. Each second doped region of the first diode pair and the second diode pair is doped with a dopant of a second conductivity type opposite to the first conductivity type. Each third doped region of the first diode pair and the second diode pair is doped with a dopant of the second conductivity type. Each fourth doped region is doped with a dopant of the first conductivity type. In each of the first diode pair and the second diode pair, a top surface of the second doped region is higher than a bottom surface of the third doped region, and a top surface of the fourth doped region is higher than a bottom surface of the first doped region. Each of the first diode and the second diode in the first diode pair is electrically coupled to the electrode at the first side of the memory cell group. Each of the first diode and the second diode in the second diode pair is electrically coupled to the electrode at the second side of the memory cell group. Description of the Drawings

[0012] Figures 1A to 1JIt is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0013] Figures 2A to 2E It is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0014] Figures 3A to 3I It is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0015] Figures 4A to 4F It is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0016] Figures 5A to 5G It is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0017] Figures 6A to 6H It is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0018] Figures 7A to 7D It is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0019] Figures 8A to 8B It is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure.

[0020] Figure 9 It is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure.

[0021] Figures 10A to 10B It is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure.

[0022] Figures 11A to 11B It is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure.

[0023] Figure 12 It is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure.

[0024] Figures 13A to 13B It is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure.

[0025] Figures 14A to 14B It is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure.

[0026] Figure 14C It is an electronic schematic diagram illustrating an embodiment of the present disclosure including, for example, Figure 14A andFigure 14B A memory array of a memory device is shown.

[0027] Figure 14D According to the embodiment of the present disclosure Figure 14C A table of operating voltages for memory cells in the memory array is shown.

[0028] Figure 15 is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure.

[0029] Figures 16A to 16D is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0030] Figures 17A to 17C is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to one embodiment of the present disclosure.

[0031] Figure 18 is a schematic diagram illustrating an embodiment of a semiconductor substrate according to the present disclosure.

[0032] Figure 19 is a schematic diagram illustrating an embodiment of a semiconductor structure according to the present disclosure.

[0033] Figure 20 is a schematic diagram illustrating an embodiment of a semiconductor structure according to the present disclosure. DETAILED DESCRIPTION

[0034] The terms used in the description presented below are intended to be interpreted in their broadest reasonable manner, even when used in conjunction with the detailed description of certain specific embodiments of the technology. Certain terms may even be emphasized below; however, any term intended to be interpreted in any restricted manner will be specifically defined as such in this detailed description. Components and implementations of semiconductor structures or memory devices according to the present disclosure can be illustrated in the following figures and embodiments. However, the size and shape of the semiconductor structures or memory devices shown in the figures do not limit the features of the present disclosure.

[0035] As used in this application, the phrase "on" can mean directly "on" or indirectly "on" through an intermediate element or layer. For ease of description, spatial relative terms such as "below", "beneath", "under", "above", "on" etc. may be used herein to describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device during use or operation. For example, if the device in the figure is flipped, an element described as "below" or "beneath" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both "above" and "below" orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein can be interpreted accordingly.

[0036] Figures 1A to 1I is a schematic diagram showing an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure. As Figure 1A shown, a semiconductor substrate A1 is provided (step (a)). The semiconductor substrate includes a first substrate 10, a second substrate 40, and a bonding layer 20. The second substrate 40 is located on the first substrate 10. The bonding layer 20 is located between the first substrate 10 and the second substrate 40. In an embodiment as Figure 1A shown, the semiconductor substrate A1 further includes an etch stop layer 30 located between the bonding layer 20 and the second substrate 40.

[0037] In one embodiment, each of the first substrate 10 and the second substrate 40 is a wafer having a diameter of 6 inches, 8 inches, 12 inches, or 18 inches. In this case, the first substrate 10 may be referred to as an operating wafer, and the second substrate 40 may be referred to as a device wafer. In some embodiments, the first substrate 10 includes glass, polysilicon, or ceramic. In some other embodiments, the first substrate 10 may include a semiconductor material, for example, a single crystal semiconductor material made of silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). The second substrate 40 may include a layer of semiconductor material. In some embodiments, the second substrate 40 may include, for example, a single crystal semiconductor material made of silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). In some embodiments, the second substrate 40 may be doped with a dopant of a first conductivity type, such as a p-type dopant, such as boron, aluminum, gallium, indium, etc., or a combination thereof, or an n-type dopant, such as phosphorus, arsenic, antimony, bismuth, etc., or a combination thereof. In some embodiments, the doping concentration of the second substrate 40 may be about 1.0×10 14atoms / cm 3 to about 5.0×10 17 atoms / cm 3 。In one embodiment, the thickness of the second substrate 40 can range between 5 nm and 3 μm. These values are merely exemplary and are not intended to be limiting.

[0038] In some embodiments, the etch stop layer 30 can have a high etch selectivity with respect to the bonding layer 20. The etch selectivity of the etch stop layer 30 with respect to the bonding layer 20 can refer to the ratio of the etch rate of the bonding layer 20 to the etch rate of the etch stop layer 30 under the same etch conditions, and when the etch rate of the bonding layer 20 is significantly faster than the etch rate of the etch stop layer 30 under the same etch conditions, the etch stop layer 30 can have a high etch selectivity with respect to the bonding layer 20. In some embodiments, the etch selectivity of the etch stop layer 30 with respect to the bonding layer 20 can be higher than 5:1. In some embodiments, the etch selectivity of the etch stop layer 30 with respect to the bonding layer 20 can be higher than 10:1, 20:1, 30:1, 50:1, 80:1, 100:1, 200:1, or 300:1.

[0039] For example, in one embodiment, the etch stop layer 30 includes silicon nitride, and the bonding layer 20 includes silicon oxide. Under appropriate etch conditions, for example, dilute HF (e.g., a weight ratio of H2O to HF of about 100:1) can be used as an etchant, and the etch stop layer 30 (e.g., silicon nitride) can have an etch rate of about and the bonding layer 20 (e.g., silicon oxide) can have an etch rate of about such that the etch selectivity is about 30:1 (oxide / nitride). The present disclosure is not limited thereto.

[0040] In some embodiments, other materials of the etch stop layer 30 and the bonding layer 20 can be used to achieve a high etch selectivity under appropriate etch conditions in a dry etch process or a wet etch process. The appropriate materials of the etch stop layer 30 and the bonding layer 20 and the appropriate etch conditions can be selected based on the actual needs and characteristics of the materials.

[0041] In some embodiments, the bonding layer 20 includes an oxide, such as silicon oxide, and the etch stop layer 30 may include silicon nitride, silicon oxynitride, doped semiconductor material, undoped semiconductor material, metal, conductive metal compound, or a combination thereof. The doped semiconductor material may be a semiconductor material with a p-type dopant, and the dopant is such as boron, aluminum, gallium, indium, etc., or a combination thereof, or may be a semiconductor material with an n-type dopant, and the dopant is such as phosphorus, arsenic, antimony, bismuth, etc., or a combination thereof. The undoped semiconductor material may be amorphous silicon, polycrystalline silicon, silicon germanium, etc., or a combination thereof. The metal may be aluminum, gold, copper, tungsten, etc., or an alloy thereof. The conductive metal compound may be metal silicide, metal carbide, metal nitride, etc., or a combination thereof. For example, WN, TaN, TaSi, TiN, TiSi, TiSiN, TiAlN, MoN, IrOx, RuOx, or RuTiN. In one embodiment, the thickness of the bonding layer 20 may be in the range between 0.2 nm and 1000 nm. In one embodiment, the thickness of the etch stop layer 30 may be in the range between 0.2 nm and 5 nm. These values are merely examples and are not intended to be restrictive. The semiconductor substrate A1 may be fabricated by a process similar to that described below in conjunction with Figures 3A to 3D The process described.

[0042] As Figure 1B shown, a third doped region 43 (step (b)) of the second diode to be formed is formed in the second substrate 40. The third doped region 43 may be formed to extend from the first surface 40a of the second substrate 40. The third doped region 43 is doped with a dopant of a second conductivity type opposite to the first conductivity type. In some embodiments, the doping concentration of the third doped region 43 may be about 1.0×10 18 atoms / cm 3 to about 3.0×10 20 atoms / cm 3 . In one embodiment, the thickness of the third doped region 43 may be in the range between 2 nm and 100 nm. These values are merely examples and are not intended to be restrictive. The third doped region 43 may be formed by ion implantation or epitaxial growth. In some other embodiments, at least a portion of the third doped region 43 may be formed, for example, by epitaxial growth on the first surface 40a of the second substrate 40.

[0043] The third doped region 43 may include a third heavily doped region 43a. The third heavily doped region 43a may extend from the first surface 40a of the second substrate 40. The third heavily doped region 43a is doped with a dopant of the second conductivity type. In some embodiments, the doping concentration of the third heavily doped region 43a may be higher than the doping concentration of the third doped region 43. In some embodiments, the doping concentration of the third heavily doped region 43a may be about 1.0×1019 atoms / cm 3 to about 5.0×10 20 atoms / cm 3 。In one embodiment, the thickness of the third heavily doped region 43a can range between 1 nm and 50 nm. These values are merely exemplary and are not intended to be limiting. The third heavily doped region 43a can be formed in the third doped region 43 by ion implantation or formed on the surface of the third doped region 43 by epitaxial growth.

[0044] In Figure 1B the illustrated embodiment, a first heavily doped region 41a is formed. The first heavily doped region 41a can be formed to extend from the first surface 40a of the second substrate 40. In one embodiment, the first heavily doped region 41a can be formed by ion implantation or epitaxial growth. The first heavily doped region 41a can be doped with a dopant of the first conductivity type in the same manner as the second substrate 40 described above. In some embodiments, the doping concentration of the first heavily doped region 41a can be higher than the doping concentration of the second substrate 40. In some embodiments, the doping concentration of the first heavily doped region 41a can be about 1.0×10 18 atoms / cm 3 to about 3.0×10 20 atoms / cm 3 。In one embodiment, the thickness of the first heavily doped region 41a can range between 1 nm and 50 nm. These values are merely exemplary and are not intended to be limiting. In some other embodiments, each of the first heavily doped region 41a and the third heavily doped region 43a can be formed on the first surface 40a of the second substrate 40 by epitaxial growth, for example.

[0045] As Figure 1CAs shown, a first ohmic contact region 61 of the first diode and a third ohmic contact region 63 of the second diode can be formed. The first ohmic contact region 61 and the third ohmic contact region 63 can be formed on a first surface 40a of the second substrate 40. The first ohmic contact region 61 and the third ohmic contact region 63 can be formed to contact a first heavily doped region 41a and a third heavily doped region 43, respectively. The third ohmic contact region 63 can be formed on and in contact with the third doped region 43, and an ohmic junction can be formed between the third ohmic contact region 63 and the third heavily doped region 43a. The first ohmic contact region 61 can be formed on and in contact with a region in the second substrate 40 designated to form the first doped region, and an ohmic junction can be formed between the first ohmic contact region 61 and the first heavily doped region 41. Each of the first ohmic contact region 61 and the third ohmic contact region 63 can include a suitable metal, alloy, or conductive metal compound, such as Mo, Ag, TiN, or a combination thereof. In one embodiment, the thickness of the first ohmic contact region 61 can be in the range of 2 nm to 100 nm. In one embodiment, the thickness of the third ohmic contact region 63 can be in the range of 2 nm to 100 nm. These values are merely examples and are not intended to be limiting. In some other embodiments, the first doped region 41 and / or the third doped region 43 can be etched to form trenches, and the first ohmic contact region 61 and / or the third ohmic contact region 63 can be formed in the trenches in the second substrate 40. The composition of the first ohmic contact region 61 and the third ohmic contact region 63 and the doping concentrations of the first heavily doped region 41a, the third heavily doped region 43a, and the third doped region 43 can be adjusted according to the desired diode characteristics.

[0046] In some embodiments, each of the first ohmic contact region 61 and the third ohmic contact region 63 can be formed by deposition (such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD)). In Figure 1C the embodiment shown, each of the first ohmic contact region 61 and the third ohmic contact region 63 can be patterned. In some embodiments, an unpatterned ohmic contact material layer (not shown) can be formed on the first surface 40a of the second substrate 40 and then patterned by any suitable process (e.g., a lithography and etching process) to form the first ohmic contact region 61 and the third ohmic contact region 63. In some embodiments, trenches can be etched through a mask layer (not shown, e.g., a mask element formed of photoresist) on the second substrate 40 to expose the first heavily doped region 41a and the third heavily doped region 43a, and the first ohmic contact region 61 and the third ohmic contact region 63 can be formed in the trenches. Then, the mask layer can be removed after the first ohmic contact region 61 and the third ohmic contact region 63 are formed.

[0047] AsFigure 1D As shown, the second substrate is patterned to define a first doped region 41 of the first diode and a fourth doped region 44 of the second diode (step (c)). The second substrate 40 can be patterned by any suitable process (e.g., photolithography and etching processes). In some embodiments, one or more etching processes can be performed to form trenches 47 through the second substrate 40 such that the third doped region 43 and the fourth doped region 44 are separated from the first doped region 41. In Figure 1C the illustrated embodiment, a portion of the first ohmic contact region 61 and / or the third ohmic contact region 63 can also be removed before and / or during the patterning of the second substrate 40. In some embodiments, the etch stop layer 30 can function as an etch stop layer in the etching process used to pattern the second substrate 40.

[0048] As Figure 1E shown, a first dielectric structure 21 can be formed before adding the third substrate. The first dielectric structure 21 can surround each of the first doped region 41, the third doped region 43, the fourth doped region 44, the first ohmic contact region 61, and the third ohmic contact region 63. The first dielectric structure 21 can include one or more stacked dielectric layers. The first dielectric structure 21 can include dielectric materials such as silicon oxide, silicon oxynitride, low dielectric constant (low-k) materials, combinations thereof, and / or other suitable materials, and can be formed by deposition (such as CVD, PVD, or ALD), spin coating, or any suitable method. The first dielectric structure 21 can fill the trenches 47 such that each of the first diode 45 and the second diode 46 to be formed subsequently is surrounded by the first dielectric structure 21.

[0049] Alternatively, in some other embodiments, the first doped region 41 and the fourth doped region 44 can be defined before forming the first ohmic contact region 61 and / or the third ohmic contact region 63. For example, the first dielectric structure 21 can be formed in the trenches 47 that separate the third doped region 43 and the fourth doped region 44 from the first doped region 41, and the first ohmic contact region 61 and / or the third ohmic contact region 63 can be formed in the first dielectric structure 21 using damascene process or dual damascene process or any suitable method to form Figure 1E the illustrated structure.

[0050] As Figure 1E shown, an interconnect structure 80 is formed on the first dielectric structure 21. The interconnect structure 80 can include conductive features (e.g., conductive lines and vias). In Figure 1E the illustrated embodiment, the interconnect structure 80 can be electrically coupled to the first ohmic contact region 61 and / or the third ohmic contact region 63. In some embodiments, the interconnect structure 80 can be electrically connected to other devices such as control circuits, memory cell arrays, etc. AsFigure 1E As shown, the interconnect structure 80 is formed on the first surface 40a of the second substrate 40. The conductive features of the interconnect structure 80 may include titanium nitride, tantalum nitride, tungsten, ruthenium, aluminum, copper, some or certain other suitable materials, or combinations of the foregoing, and may be formed by using a damascene process or a dual damascene process or any suitable method.

[0051] In some other embodiments, rather than forming the interconnect structure 80 on the first ohmic contact region 61 and the third ohmic contact region 63, at least a portion of the interconnect structure 80 may be formed in the same layer as the first ohmic contact region 61 and the third ohmic contact region 63. In some other embodiments, the interconnect structure 80 may be omitted. For example, rather than forming an additional wiring layer, the first ohmic contact region 61 and / or the third ohmic contact region 63 may extend laterally and provide electrical connections between them and / or between the devices formed in the second substrate 40.

[0052] As Figure 1F shown, a third substrate 90 is added to the first surface 40a of the second substrate 40, where the second substrate 40 is located between the third substrate 90 and the first substrate 10 (step (e)). As Figure 1F shown, the interconnect structure 80 may be located between the second substrate 40 and the third substrate 90.

[0053] In one embodiment, the third substrate 90 is a wafer with a diameter of 6 inches, 8 inches, 12 inches, or 18 inches. The third substrate 90 can be an operating wafer or a device wafer. In some embodiments, the third substrate 90 can include glass, polysilicon, or ceramic. In some embodiments, the third substrate 90 can include semiconductor materials such as those made of silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). In some embodiments, the third substrate 90 can include single-crystalline semiconductor materials. In one embodiment, the thickness of the third substrate 90 can range between 20 μm and 700 μm. These values are merely examples and are not intended to be limiting. The third substrate 90 can include semiconductor devices, including but not limited to transistors, diodes, capacitors, and resistors. In some embodiments, the interconnect structure and / or the semiconductor devices (not shown) in the third substrate 90 can be electrically coupled to the first ohmic contact region 61 and / or the third ohmic contact region 63. In one embodiment, the interconnect structure 80 can be omitted, and the interconnect structure (not shown) in the third substrate 90 can be electrically coupled to the first ohmic contact region 61 and / or the third ohmic contact region 63. In some embodiments, the third substrate 90 can be bonded to the second substrate 40 by performing suitable processes such as adhesive bonding or direct bonding. In some embodiments, the third substrate 90 can be formed on the second substrate 40 by epitaxial growth, CVD, PVD, and / or ALD. The third substrate 90 can provide mechanical support to the semiconductor structure to avoid fractures and cracks during subsequent manufacturing processes.

[0054] As Figure 1G shown, the first substrate 10 and the bonding layer 20 are removed to expose the etch stop layer 30. The first substrate 10 and the bonding layer 20 can be removed by performing suitable processes such as grinding, chemical mechanical polishing (CMP), and etching processes. In one embodiment, the first substrate 10 is removed by grinding and / or CMP processes, and the bonding layer 20 can be removed by applying a first etchant (e.g., dilute HF (e.g., with a weight ratio of H2O to HF of about 100:1)). In one embodiment, when using dilute HF as the etchant, due to the etch selectivity, the etch stop layer 30 (e.g., silicon nitride) can be exposed after removing the bonding layer 20 (e.g., silicon oxide). In Figure 1G the embodiment shown, the etch stop layer 30 can protect the structures in the first dielectric structure 21 and the second substrate 40 from the etching process.

[0055] As Figure 1HAs shown, at least a portion of the etch stop layer 30 is removed. The etch stop layer 30 can be removed by oxide etching, plasma etching, hydrogen peroxide etching, etc. and / or any suitable method. In one embodiment, the etch stop layer 30 including silicon nitride can be removed by applying a second etchant (e.g., hot phosphoric acid). The present disclosure is not limited thereto. After removing the etch stop layer 30, at least a portion of the second surface 40b of the second substrate 40 is exposed. By the method disclosed herein, the exposed second surface 40b of the second substrate 40 can have better flatness, so that the height of the formed diode can be more uniform and more controllable. Moreover, the endpoint of the etching process for removing the bonding layer 20 can be more easily controlled. In Figure 1H the illustrated embodiment, the etch stop layer 30 is completely removed. However, in other embodiments, only a portion of the etch stop layer 30 (e.g., the portion of the etch stop layer 30 overlapping with the first diode 45 and the second diode 46) can be removed by a suitable method (such as photolithography and etching processes). For example, when the etch stop layer 30 includes silicon nitride, dry etching can be performed using NF3 as an etch gas by remote plasma to remove only a portion of the etch stop layer 30.

[0056] As Figure 1I shown, after removing the bonding layer 20 and exposing the second surface 40b of the second substrate 40, a second doped region 42 of the first diode 45 is formed in the second substrate 40 (step (f)). The second doped region 42 can be formed to extend from the second surface 40b of the second substrate 40. The second doped region 42 can be formed in a region on the first doped region 41 such that the second doped region 42 is formed in contact with the first doped region 41. In some embodiments, the second doped region 42 can be doped with a dopant of a second conductivity type. In some embodiments, the doping concentration of the second doped region 42 can be about 1.0×10 18 atoms / cm 3 to about 3.0×10 20 atoms / cm 3 . In one embodiment, the thickness of the second doped region 42 can be in the range between 2 nm and 100 nm. These values are merely examples and are not intended to be limiting. The second doped region 42 can be formed by ion implantation or epitaxial growth. In some other embodiments, at least a portion of the second doped region 42 can be formed on the second surface 40b of the second substrate 40 by epitaxial growth, for example. The details and formation method of the second doped region 42 can be substantially similar to the details and formation method of the third doped region 43 described above in connection with Figure 1B the description.

[0057] The second doped region 42 can include a second heavily doped region 42a. InFigure 1I In the illustrated embodiment, the second heavily doped region 42a may be formed to extend from the second surface 40b of the second substrate 40. In some embodiments, the second heavily doped region 42a may be doped with a dopant of a second conductivity type. In some embodiments, the doping concentration of the second heavily doped region 42a may be higher than the doping concentration of the second doped region 42. In some embodiments, the doping concentration of the second heavily doped region 42a may be about 1.0×10 19 atoms / cm 3 to about 5.0×10 20 atoms / cm 3 . In one embodiment, the thickness of the second heavily doped region 42a may be in the range between 1 nm and 50 nm. These values are merely examples and are not intended to be limiting. The details and formation method of the second heavily doped region 42a may be substantially similar to the details and formation method of the third heavily doped region 43a described above in conjunction with Figure 1B .

[0058] The fourth heavily doped region 44a may be formed on the second surface 40b of the second substrate 40. The fourth heavily doped region 44 may be formed after exposing the second surface 40b of the second substrate 40. In some embodiments, the fourth heavily doped region 44a may be doped with a dopant of the same first conductivity type as the second substrate 40. In some embodiments, the doping concentration of the fourth heavily doped region 44a may be higher than the doping concentration of the second substrate 40 (and the fourth doped region 44). In some embodiments, the doping concentration of the fourth heavily doped region 44a may be about 1.0×10 19 atoms / cm 3 to about 5.0×10 20 atoms / cm 3 . In one embodiment, the thickness of the fourth heavily doped region 44a may be in the range between 1 nm and 50 nm. These values are merely examples and are not intended to be limiting. The details and formation method of the fourth heavily doped region 44a may be substantially similar to the details and formation method of the first heavily doped region 41a described above in conjunction with Figure 1B .

[0059] In some embodiments, the second doped region 42 and the third doped region 43 may have similar doping concentrations, and the second heavily doped region 42 and the third heavily doped region 43 may have similar doping concentrations. In some embodiments, the fourth heavily doped region 44a and the first heavily doped region 41a may have similar doping concentrations.

[0060] As Figure 1JAs shown, a second ohmic contact region 62 and a fourth ohmic contact region 64 can be formed. The second ohmic contact region 62 and the fourth ohmic contact region 64 can be formed on the second surface 40b of the second substrate 40. Each of the second ohmic contact region 62 and the fourth ohmic contact region 64 can be patterned. In Figure 1J the embodiment shown, the second ohmic contact region 62 can be formed on and overlap with the first ohmic contact region 61. The second ohmic contact region 62 can be formed on and in contact with the second doped region 42, and an ohmic junction can be formed between the second ohmic contact region 62 and the second heavily doped region 42a. In Figure 1J the embodiment shown, the fourth ohmic contact region 64 can be formed on and overlap with the third ohmic contact region 63. The fourth ohmic contact region 64 can be formed on and in contact with the fourth doped region 44, and an ohmic junction can be formed between the fourth ohmic contact region 64 and the fourth heavily doped region 44a. In one embodiment, the thickness of the second ohmic contact region 62 can be in the range between 2 nm and 100 nm. In one embodiment, the thickness of the fourth ohmic contact region 64 can be in the range between 2 nm and 100 nm. These values are merely examples and are not intended to be limiting. In some embodiments, the second ohmic contact region 62 and the fourth ohmic contact region 64 can have similar thicknesses.

[0061] Each of the second ohmic contact region 62 and the fourth ohmic contact region 64 can be formed using materials and a method similar to those described above in conjunction with Figure 1C the first ohmic contact region 61 and the third ohmic contact region 63. In some embodiments, one or more stacked dielectric layers of the first dielectric structure 21 can be formed on the second surface 40b of the second substrate 40, and the second ohmic contact region 62 and / or the fourth ohmic contact region 64 can be formed in the first dielectric structure 21 using an inlay process or a dual inlay process or any suitable method. In some other embodiments, the second doped region 42 and / or the fourth doped region 44 can be etched to form trenches, and the fourth ohmic contact region 64 and / or the second ohmic contact region 62 can be formed in the trenches in the second substrate 40. In some embodiments, the second ohmic contact region 62 and the fourth ohmic contact region 64 can have the same composition; however, in some other embodiments, the second ohmic contact region 62 and the fourth ohmic contact region 64 can have different compositions according to actual needs. The compositions of the second ohmic contact region 62 and the fourth ohmic contact region 64 and the doping concentrations of the second heavily doped region 42a and the fourth heavily doped region 44a can be adjusted according to the desired diode characteristics.

[0062] As Figure 1J shown, a memory cell group 100 is formed (step (h)). The memory cell group 100 can have a first end 101 and a second end 102. InFigure 1J In the illustrated embodiment, the memory cell group 100 is formed on the wiring layer 72. The wiring layer 72 may include conductive features (e.g., conductive lines or vias) connected to both the first diode 45 and the second diode 46, and the memory cell group 100 may be electrically coupled to the conductive features from the second end 102 of the memory cell group 100 such that the memory cell group 100 is electrically coupled to both the first diode 45 and the second diode 46 through the wiring layer 72. The wiring layer 72 may include Pt, Pd, Ir, Ru, Cu, W, some or certain other suitable materials, or a combination of the foregoing, and may be formed in the first dielectric structure 21 using a damascene process or a dual damascene process or any suitable method. In some embodiments, the second ohmic contact region 62 of the first diode 45 may be connected to the fourth ohmic contact region 64 of the second diode 46 such that an additional wiring layer (e.g., Figure 1J the wiring layer 72 in ) may not be required, and the memory cell group 100 contacts the second ohmic contact region 62 and / or the fourth ohmic contact region 64 at the second end 102 of the memory cell group 100.

[0063] The memory cell group 100 may include a magnetic tunnel junction (MTJ) structure, a phase change material, or a resistive random access memory (RRAM) material. The MTJ structure may include a free magnetic layer, a fixed magnetic layer, and a tunnel barrier layer located between the free magnetic layer and the fixed magnetic layer. The fixed magnetic layer may have a fixed magnetization, and the free magnetic layer may have a magnetization that can be switched by a program current. The magnetization orientation in the free magnetic layer relative to the magnetization orientation of the fixed magnetic layer may determine whether the MTJ structure is in a high resistance state or a low resistance state (e.g., whether the memory cell group stores a "1" or a "0"). For example, if the magnetizations of the free magnetic layer and the fixed magnetic layer are in a parallel orientation, the MTJ structure may be in a low resistance state (e.g., the "0" state); and if the magnetizations of the free magnetic layer and the fixed magnetic layer are in an opposite (antiparallel) orientation, the MTJ structure may be in a high resistance state (e.g., the "1" state). Data writing may be performed by switching the orientation of the magnetization of the free magnetic layer. In some embodiments, to enhance the performance of the MTJ structure, the free magnetic layer and / or the fixed magnetic layer may include a multilayer structure. In some embodiments, an antiferromagnetic (AFM) layer may be added between the electrode and the fixed magnetic layer, which allows cancellation of the dipole field around the free magnetic layer. The MTJ structure may be formed by any suitable method and any material suitable for each of its layers. In Figure 1J the illustrated embodiment, the memory cell group 100 is formed after the second ohmic contact region 62 and the fourth ohmic contact region 64 are formed. However, the present disclosure is not limited thereto.

[0064] As Figure 1JAs shown, a bit line 75 is formed on a memory cell group 100. The memory cell group 100 can be electrically coupled to the bit line 75 from a first end 101 of the memory cell group 100. The bit line 75 can include Pt, Pd, Ir, Ru, Cu, W, some or certain other suitable materials, or a combination of the foregoing. In some embodiments, the bit line 75 can be formed in a first dielectric structure 21 using a damascene process or a dual damascene process or any suitable method.

[0065] Reference Figure 1J , a semiconductor structure 104 including a first diode 45 and a second diode 46 is provided. The first diode 45 includes a first doped region 41 and a second doped region 42. The second doped region 42 is disposed on and in contact with the first doped region 41 such that a top surface 42TS of the second doped region 42 is higher than a bottom surface 41BS of the first doped region 41. The second diode 46 includes a third doped region 43 and a fourth doped region 44. The fourth doped region 44 is disposed on and in contact with the third doped region 43 such that a top surface 44TS of the fourth doped region 44 is higher than a bottom surface 43BS of the third doped region 43. Each of the first doped region 41 and the fourth doped region 44 can be doped with a dopant of a first conductivity type (such as the second substrate 40 described above), and each of the second doped region 42 and the third doped region 43 is doped with a dopant of a second conductivity type opposite to the first conductivity type.

[0066] For ease of description, the expressions “top surface”, “bottom surface” and “higher than” herein describe the relationship of one element or feature relative to another or more elements or features as Figure 1J illustrated. It should be understood that, in addition to the orientation depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device during use or operation. For example, if the device in the figure is flipped, an element described as “higher than” other elements or features will be oriented “lower than” other elements or features. The structure can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptive terms used herein are accordingly interpreted.

[0067] As Figure 1J shown, the top surface 42TS of the second doped region 42 is higher than the bottom surface 43BS of the third doped region 43; and the top surface 44TS of the fourth doped region 44 is higher than the bottom surface 41BS of the first doped region 41. In other words, the first diode 45 can be located at substantially the same level as the second diode 46, while the first diode 45 and the second diode 46 are arranged in opposite directions.

[0068] Generally, adjacent PN diodes located in substantially the same layer are formed, for example, by forming a semiconductor material layer and / or a metal layer and subsequent patterning processes, and are arranged in the same direction. However, by the method disclosed herein, adjacent PN diodes located in substantially the same layer can be formed to be arranged in opposite directions. In other words, the diodes in a pair of PN diodes arranged in opposite directions can be formed at substantially the same level, which can simplify the routing of the semiconductor structure and reduce the thickness.

[0069] In Figure 1J the illustrated embodiment, the bottom surface 41BS of the first doped region 41 can be substantially flush with the bottom surface 43BS of the third doped region 43. The top surface of the second doped region 42 can be substantially flush with the top surface 44TS of the fourth doped region 44.

[0070] In Figure 1J the illustrated embodiment, each of the first doped region 41 and the fourth doped region 44 can include a single-crystalline semiconductor material. Each of the second doped region 42 and the third doped region 43 can also include a single-crystalline semiconductor material. The single-crystalline semiconductor material can be made of, for example, silicon, germanium, silicon-germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN).

[0071] In some embodiments, the doping concentrations of the first doped region 41 and the fourth doped region 44 can both be about 1.0×10 18 atoms / cm 3 to about 3.0×10 20 atoms / cm 3 . In some embodiments, the doping concentrations of the second doped region 42 and the third doped region 43 can both be about 1.0×10 18 atoms / cm 3 to about 3.0×10 20 atoms / cm 3 . In some embodiments, the thickness of the first doped region 41 can be in the range between 2 nm and 100 nm. In some embodiments, the thickness of the fourth doped region 44 can be in the range between 2 nm and 100 nm. In some embodiments, the thickness of the second doped region 42 can be in the range between 2 nm and 100 nm. In some embodiments, the thickness of the third doped region 43 can be in the range between 2 nm and 100 nm. These values are merely examples and are not intended to be limiting. In some embodiments, the first doped region 41 and the third doped region 43 can have substantially the same thickness. In some embodiments, the second doped region 42 and the fourth doped region 44 can have substantially the same thickness.

[0072] AsFigure 1J As shown, the first diode 45 may further include a first ohmic contact region 61 in contact with the bottom surface 41BS of the first doped region 41, and the second diode 46 may further include a fourth ohmic contact region 64 in contact with the top surface 44TS of the fourth doped region 44. In some embodiments, the first diode 45 may further include a second ohmic contact region 62 in contact with the top surface 42TS of the second doped region 42, and the second diode 46 may further include a third ohmic contact region 63 in contact with the bottom surface 43BS of the third doped region 43.

[0073] The first doped region 41 may further include a first heavily doped region 41a extending from the bottom surface 41BS of the first doped region 41. The fourth doped region 44 may further include a fourth heavily doped region 44a extending from the top surface 44TS of the fourth doped region 44. Each of the first heavily doped region 41a and the fourth heavily doped region 44a is doped with a dopant of a first conductivity type. An ohmic junction may be formed between the first ohmic contact region 61 and the first heavily doped region 41a, and an ohmic junction may be formed between the fourth ohmic contact region 64 and the fourth heavily doped region 44a.

[0074] The second doped region 42 may further include a second heavily doped region 42a extending from the top surface 42TS of the second doped region 42. The third doped region 43 may further include a third heavily doped region 43a extending from the bottom surface 43BS of the third doped region 43. Each of the second heavily doped region 42a and the third heavily doped region 43a is doped with a dopant of a second conductivity type. An ohmic junction may be formed between the second ohmic contact region 62 and the second heavily doped region 42a, and an ohmic junction may be formed between the third ohmic contact region 63 and the third heavily doped region 43a.

[0075] In Figure 1J the embodiment shown, the first doped region 41 and the second doped region 42 of the first diode 45 are aligned in the vertical direction, and the first doped region 41 is in contact with the second doped region 42 such that the first doped region 41 and the second doped region 42 can be used together as a vertical PN diode. The third doped region 43 and the fourth doped region 44 of the second diode 46 are aligned in the vertical direction, and the third doped region 43 is in contact with the fourth doped region 44 such that the third doped region 43 and the fourth doped region 44 can be used together as a vertical PN diode. As Figure 1J shown in the embodiment, the sidewalls of the first doped region 41 and the second doped region 42 may be substantially aligned, and the sidewalls of the third doped region 43 and the fourth doped region 44 may be substantially aligned. This can minimize the size of a unit cell. However, the present disclosure is not limited thereto.

[0076] Reference Figure 1J , a semiconductor structure 105 is provided. The semiconductor structure 105 includes the first diode 45 and the second diode 46 as described above, and a memory cell group 100. In some embodiments, the memory cell group 100 may include a magnetic tunnel junction (MTJ) structure. The memory cell group 100 may have a first end 101 and a second end 102. In Figure 1J the illustrated embodiment, the memory cell group 100 is electrically coupled to both the first diode 45 and the second diode 46 simultaneously from the second end 102 of the memory cell group 100. The memory cell group 100 may be electrically coupled to the second doped region 42 of the first diode 45 and the fourth doped region 44 of the second diode 46 simultaneously. In some other embodiments, the memory cell group 100 may include a phase change material.

[0077] Figure 1J The illustrated semiconductor structure 105 may be a spin transfer torque type MRAM (STT-MRAM) device. For example, for a data writing process, the program current may flow along a first current flow path from the second diode 46 through the wiring layer 72 and the memory cell group 100 to the bit line 75; or, the program current may flow along a second current flow path from the bit line 75 through the memory cell group 100 and the wiring layer 72 to the first diode 45. Although Figures 1A to 1J only one memory cell is illustrated herein, multiple memory cells or a memory cell array may be fabricated simultaneously using the methods disclosed herein.

[0078] In Figures 1A to 1J the illustrated embodiment, the methods disclosed herein may be used to fabricate a memory device including a pair of PN diodes as selectors. By including the first diode 45 and the second diode 46 arranged in opposite directions and located at substantially the same level as discussed above in connection with Figure 1J , the memory device disclosed herein may have a simplified routing structure and a reduced cell size, and may be easy to fabricate. Compared with a memory device using a transistor as a selector, the memory device disclosed herein may also provide a higher current density and may have desired characteristics such as higher efficiency, faster memory access, and low power consumption.

[0079] Figures 2A to 2E is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure. As Figure 2A shown, a third doped region 43, a third heavily doped region 43a, a first heavily doped region 41a, a first ohmic contact region 61, and a third ohmic contact region 63 are formed, and the first doped region 41 and the third doped region 43 are defined by patterning the second substrate 40. Figure 2AThe details and formation method of the semiconductor structure shown can be substantially similar to those described above in connection with Figures 1A to 1D The details and formation method described, where like reference numerals indicate like elements.

[0080] As Figure 2B shown, a first dielectric structure 21 is formed. The first dielectric structure 21 can be formed of similar materials and processes as described above in connection with Figure 1E The description thereof is omitted for the sake of brevity.

[0081] Alternatively, in some other embodiments, the first doped region 41 and the fourth doped region 44 can be defined before forming the first ohmic contact region 61 and / or the third ohmic contact region 63. For example, the first dielectric structure 21 can be formed in a trench 47 that separates the third doped region 43 and the fourth doped region 44 from the first doped region 41, and the first ohmic contact region 61 and / or the third ohmic contact region 63 can be formed in the first dielectric structure 21 using an inlay process or a dual inlay process or any suitable method to form the Figure 2B Structure shown.

[0082] As Figure 2B shown, a memory cell group 100 is formed (step (h)). The details and formation method of the memory cell group 100 can be similar to those described above in connection with Figure 1J The description thereof is omitted for the sake of brevity. In the Figure 2B embodiment shown, the memory cell group 100 is simultaneously electrically coupled to the first diode 45 and the second diode 46 from the second end 102 of the memory cell group 100. The memory cell group 100 can be electrically coupled to the first ohmic contact region 61. The memory cell group 100 can also be electrically coupled to the third ohmic contact region 63. In the Figure 2B embodiment shown, a wiring layer 72 coupled to the first ohmic contact region 61 and the third ohmic contact region 63 is formed, and the memory cell group 100 is formed on the wiring layer 72. The materials and processes for forming the wiring layer 72 can be similar to those described above in connection with Figure 1J The description thereof is omitted for the sake of brevity. In some embodiments, the first ohmic contact region 61 can be connected to the third ohmic contact region 63 such that an additional wiring layer (e.g., Figure 2B the wiring layer 72 in

[0083] As Figure 2B shown, a bit line 75 is formed on the memory cell group 100. The bit line 75 can be formed of similar materials and processes as described above in connection with Figure 1J The description thereof is omitted for the sake of brevity.

[0084] As Figure 2CAs shown, a third substrate 90 is added to the first surface 40a of the second substrate 40, where the second substrate 40 is located between the third substrate 90 and the first substrate 10 (step (d)). The method and details of forming and / or attaching the third substrate 90 can be similar to those of the forming and / or attaching method and details described above in connection with Figure 1F and the relevant description is omitted for the sake of brevity. As Figure 2C shown, the memory cell group 100 can be located between the second substrate 40 and the third substrate 90.

[0085] As Figure 2D shown, the first substrate 10 and the bonding layer 20 are removed to expose the etch stop layer 30. The removal of the first substrate 10 and the bonding layer 20 can be substantially similar to the process described above in connection with Figure 1G and the relevant description is omitted for the sake of brevity. Moreover, as Figure 2D shown, at least a portion of the etch stop layer 30 is removed. The removal of the etch stop layer 30 can be substantially similar to the process described above in connection with Figure 1H and the relevant description is omitted for the sake of brevity.

[0086] As Figure 2D shown, after removing the bonding layer 20 and exposing the second surface 40b of the second substrate 40 (step (e)), a second doped region 42 of the first diode is formed in the second substrate 40 (step (f)). The second doped region 42 can further include a second heavily doped region 42a extending from the second surface 40b of the second substrate 40. A fourth heavily doped region 44a can also be formed extending from the second surface 40b of the second substrate 40. The details and forming method of the second doped region 42, the second heavily doped region 42a, and the fourth heavily doped region 44a can be substantially similar to the details and forming method described above in connection with Figure 1I and the relevant description is omitted for the sake of brevity.

[0087] As Figure 2E shown, a second ohmic contact region 62 of the first diode 45 and a fourth ohmic contact region 64 of the second diode 46 can be formed on the second surface 40b of the second substrate 40 (step (f)). The details and forming method of the second ohmic contact region 62 and the fourth ohmic contact region 64 can be substantially similar to the details and forming method described above in connection with Figure 1J and the relevant description is omitted for the sake of brevity.

[0088] As Figure 2E shown, an interconnect structure 80 can be formed on the first dielectric structure 21. The interconnect structure 80 can include conductive features (e.g., conductive lines and vias). In Figure 2EIn the illustrated embodiment, the interconnect structure 80 can be electrically coupled to the second ohmic contact region 62 and / or the fourth ohmic contact region 64. In some embodiments, the interconnect structure 80 can include a plurality of word lines. In some embodiments, the interconnect structure 80 can be electrically connected to other devices, such as control circuits, memory cell banks, etc. As Figure 2E shown, the interconnect structure 80 is formed on the second surface 40b of the second substrate 40. The interconnect structure 80 can include titanium nitride, tantalum nitride, tungsten, ruthenium, aluminum, copper, some or certain other suitable materials, or a combination of the foregoing, and can be formed by using a damascene process or a dual damascene process or any suitable method.

[0089] In some other embodiments, instead of forming the interconnect structure 80 on the second ohmic contact region 62 and the fourth ohmic contact region 64, the interconnect structure can be formed in the same layer as the second ohmic contact region 62 and the fourth ohmic contact region 64. In some other embodiments, the interconnect structure 80 can be omitted. For example, instead of forming an additional wiring layer, the second ohmic contact region 62 and / or the fourth ohmic contact region 64 can extend between devices and provide electrical connections.

[0090] Referring to Figure 2E , a semiconductor structure 104 including a first diode 45 and a second diode 46 is provided. Figure 2E The illustrated semiconductor structure 104 can be substantially similar to the semiconductor structure 104 described above in connection with Figure 1I , where like reference numerals indicate like elements. If applicable, the relevant details of the semiconductor structure 104 described above can apply here.

[0091] Referring to [[ID=1 , a semiconductor structure 130 is provided. The semiconductor structure 130 includes the first diode 45 and the second diode 46 as described above, and a memory cell bank 100. The memory cell bank 100 can have a first end 101 and a second end 102. In ​ the illustrated embodiment, the memory cell bank 100 is electrically coupled to both the first diode 45 and the second diode 46 simultaneously from the second end 102 of the memory cell bank 100. ​ The illustrated semiconductor structure 130 can be an STT-MRAM device. For example, for a data write process, a program current can flow along a first current flow path from the first diode 45 through the wiring layer 72 and the memory cell bank 100 to the bit line 75; alternatively, the program current can flow along a second current flow path from the bit line 75 through the memory cell bank 100 and the wiring layer 72 to the second diode 46. If applicable, ​ all other descriptions of the illustrated semiconductor structure 105 can apply here.

[0092] In​ In the illustrated embodiment, the methods disclosed herein can be used to fabricate a memory device including a pair of PN diodes as selectors, which can provide additional options for fabricating a memory device including vertical PN diodes.

[0093] ​ is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure. As ​ shown, a first structure 200A and a second structure 200B are provided. The first structure 200A includes a first substrate 10. The second structure 200B includes a second substrate 40 and an etch stop layer 30 on the second substrate 40. ​ The first substrate 10 and the second substrate 40 shown can be substantially similar to the first substrate 10 and the second substrate 40 described above in connection with ​ and, if applicable, the relevant details described above in connection with ​ can be applicable here.

[0094] The etch stop layer 30 can include silicon nitride, silicon oxynitride, doped semiconductor material, undoped semiconductor material, metal, conductive metal compound, or a combination thereof. The etch stop layer 30 can have a high etch selectivity with respect to ​ the bonding layer 20 shown, and, if applicable, other relevant details of the etch stop layer 30 described above in connection with ​ can be applicable here. The etch stop layer 30 can be formed on the second surface 40b of the second substrate 40. In one embodiment, the etch stop layer 30 can be formed by epitaxial growth or by deposition (such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD)). In one embodiment, the etch stop layer 30 can be formed by sputtering or evaporation.

[0095] In ​ the illustrated embodiment, the second substrate 40 further includes an implanted hydrogen layer 110 inside the second substrate 40. The implanted hydrogen layer 110 is implanted to a certain depth inside the second substrate 40, and then the first structure 200A and the second structure 200B are bonded. The implantation can be performed before or after the formation of the etch stop layer 30, as long as the implanted hydrogen layer 110 is not damaged by subsequent processes. For example, if the formation of the etch stop layer 30 requires high temperature (e.g., an annealing process), then hydrogen may should be implanted after the formation of the etch stop layer 30. In one embodiment, with an implantation energy of 50 KeV to 150 KeV, using 1×10 16 ions / cm 2 to 2×10 17 ions / cm 2The dose injects hydrogen ions into the second substrate 40. A larger substrate can use a larger dose. The hydrogen implantation layer 110 can be formed at a depth of about 4×10 -5 inches to about 8×10 -5 inches (1 to 2 μm) from the second surface 40b of the second substrate 40. These values are merely exemplary and are not intended to be limiting. In one embodiment, since the thickness of the etch stop layer 30 (and in some embodiments, ​ the second dielectric layer 122 shown) is known, an appropriate implantation voltage can be selected to cause the peak of the implanted hydrogen to occur at a desired depth below the etch stop layer 30. In one embodiment, when the etch stop layer 30 includes a metal, the implantation can be performed before forming the etch stop layer 30.

[0096] As ​ shown, the second substrate 40 further includes a second doped region 42 of the second diode 46 extending from the second surface 40b of the second substrate 40. The second doped region 42 can include a second heavily doped region 42a extending from the second surface 40b of the second substrate 40. The second substrate 40 can further include a fourth heavily doped region 44a extending from the second surface 40b of the second substrate 40. The materials and formation methods of the second doped region 42, the second heavily doped region 42a, and the fourth heavily doped region 44a can be similar to those described above in connection with ​ and the related description is omitted for brevity. In some embodiments, the formation of the second doped region 42, the second heavily doped region 42a, and the fourth heavily doped region 44a involves a high-temperature annealing process such that the second doped region 42, the second heavily doped region 42a, and the fourth heavily doped region 44a can be formed before the hydrogen layer implantation. In some embodiments, the second doped region 42, the second heavily doped region 42a, and the fourth heavily doped region 44a can be formed before forming the etch stop layer 30.

[0097] As ​ shown, before bonding the first structure 200A and the second structure 200B, a first dielectric layer 121 is formed on the first substrate 10, and a second dielectric layer 122 is formed on the etch stop layer 30. In one embodiment, only one of the first dielectric layer 121 and the second dielectric layer 122 is formed before bonding the first structure 200A and the second structure 200B. In one embodiment, the first dielectric layer 121 and / or the second dielectric layer 122 can be formed by thermal oxidation or deposition (such as CVD, PVD, or ALD). In some embodiments, the first dielectric layer 121 and / or the second dielectric layer 122 includes silicon oxide. In some embodiments, the implantation process for forming the implanted hydrogen layer 70 can be performed after forming the second dielectric layer 122.

[0098] As​ As shown, the second structure 200B is flipped and bonded to the first structure 200A through the bonding layer 20 to form a bonded structure 200C. In ​ the illustrated embodiment, the first dielectric layer 121 and the second dielectric layer 122 are bonded to form the bonding layer 20. In an embodiment where only one of the first dielectric layer and the second dielectric layer is formed before bonding, that one of the first dielectric layer 121 and the second dielectric layer 122 forms the bonding layer 20. ​ The illustrated bonding layer 20 can be substantially similar to the bonding layer 20 described above in connection with ​ and the related description is omitted for the sake of brevity. For example, the second structure 200B can be bonded to the first structure 200A by a fusion bonding process such as a hydrophilic fusion bonding process. In one embodiment, both the first dielectric layer 121 and the second dielectric layer 122 are cleaned by conventional cleaning techniques such as RCA wafer cleaning procedures. The cleaning process removes surface impurities and particles from the surfaces of the dielectric layers 121 and 122. In one embodiment, due to the presence of atomic charges, hydroxyl groups (OH-) are formed on the surfaces to be bonded. Hydrogen bonds can be formed between the first dielectric layer 121 and the second dielectric layer 122, and an annealing process can be performed to form chemical bonds (e.g., Si-O bonds) between the surfaces of the first dielectric layer 121 and the second dielectric layer 122.

[0099] As ​ shown, a portion of the second substrate 40 is removed from the bonded structure 200C substantially to the hydrogen implantation layer 110. That portion of the second substrate 40 can be removed by heating the bonded structure 200C to a first temperature. The first temperature is generally lower than 400 °C to avoid causing any damage to the semiconductor device or its parts (if any) fabricated in the second substrate 40. In some embodiments, a portion of the second substrate 40 can be removed by other methods as long as that portion of the second substrate 40 has been sufficiently weakened by the aforementioned hydrogen implantation and some subsequent annealing. For example, the bonded structure 200C can be cleaved by applying mechanical pressure to the second substrate 40 or by immersing the bonded structure 200C in liquid nitrogen and quenching.

[0100] Based on the implantation depth of the implanted hydrogen layer 110, the remaining portion of the second substrate 40 on the bonding structure 200C can be less than 3 μm. The thickness of the remaining portion of the second substrate 40 can also depend on the semiconductor manufacturing technology nodes applied to fabricate various semiconductor devices. After removal, a first surface 40a of the second substrate 40 is formed. The exposed surface of the second substrate 40 typically has a roughness on the order of several hundred angstroms. The exposed surface of the second substrate 40 can be polished by chemical mechanical polishing (CMP) to planarize and minimize non-uniformities, thereby forming the first surface 40a. Other methods such as etching can be used for the same purpose. When etching is used to planarize and minimize non-uniformities to form the first surface 40a of the second substrate 40, it may be necessary to deposit another etch stop layer (not shown) in advance. Thus, a semiconductor substrate 200 is provided (step (a)). The semiconductor substrate 200 can be substantially similar to the semiconductor substrate A1 described above in conjunction with ​ where like reference numerals indicate like elements. The semiconductor structure 200 can be used to fabricate various types of semiconductor devices as described below.

[0101] As ​ shown, a third doped region 43 of the second diode 46 is formed in the second substrate 40 (step (b)), and the third doped region extends from the first surface 40a of the second substrate 40. The third doped region 43 can further include a third heavily doped region 43a that extends from the first surface 40a of the second substrate 40. The second substrate 40 can further include a first heavily doped region 41a that extends from the first surface 40a of the second substrate 40. The details and processes for forming the first heavily doped region 41a, the third doped region 43, and the third heavily doped region 43a can be substantially similar to the details and processes described above in conjunction with ​ and the related descriptions are omitted for the sake of brevity.

[0102] In ​ the illustrated embodiment, a first ohmic contact region 61 of the first diode and a third ohmic contact region 63 of the second diode are formed on the first surface 40a of the second substrate 40. The details and processes for forming the first ohmic contact region 61 and the third ohmic contact region 63 can be substantially similar to the details and processes described above in conjunction with ​ and the related descriptions are omitted for the sake of brevity.

[0103] As ​ shown, the second substrate 40 is patterned to define a first doped region 41 of the first diode 45 and a fourth doped region 44 of the second diode 46 (step (c)). The patterning process can be substantially similar to the patterning process described above in conjunction with ​ and the related descriptions are omitted for the sake of brevity.

[0104] As shown ​ , a first dielectric structure 21 is formed. An interconnect structure 80 can be formed on the first dielectric structure 21. The materials and processes for forming the first dielectric structure 21 and the interconnect structure 80 can be substantially similar to those described above in connection with ​ the materials and processes, and the related description is omitted for the sake of brevity.

[0105] Alternatively, in some other embodiments, the first doped region 41 and the fourth doped region 44 can be defined before forming the first ohmic contact region 61 and / or the third ohmic contact region 63. For example, the first dielectric structure 21 can be formed in a trench 47 that separates the third doped region 43 and the fourth doped region 44 from the first doped region 41, and the first ohmic contact region 61 and / or the third ohmic contact region 63 can be formed in the first dielectric structure 21 using an inlay process or a dual inlay process or any suitable method to form ​ the structure shown.

[0106] As shown ​ , a third substrate 90 is added to the first surface 40a of the second substrate 40, where the second substrate 40 is located between the third substrate 90 and the first substrate 10 (step (d)). The method and details of forming and / or attaching the third substrate 90 can be similar to those described above in connection with ​ the forming and / or attaching method and details, and the related description is omitted for the sake of brevity.

[0107] As shown ​ , the first substrate 10 and the bonding layer 20 are removed to expose the etch stop layer 30. The removal of the first substrate 10 and the bonding layer 20 can be substantially similar to the process described above in connection with ​ the process, and the related description is omitted for the sake of brevity. Then, at least a portion of the etch stop layer 30 is removed to expose the second surface 40b of the second substrate 40. As shown ​ , after removing the bonding layer 20, the second doped region 42 of the first diode 45 extending from the second surface 40b of the second substrate 40 can be exposed (step (f)). The fourth heavily doped region 44a extending from the second surface 40b of the second substrate 40 can also be exposed. The removal of the etch stop layer 30 can be substantially similar to the process described above in connection with ​ the process, and the related description is omitted for the sake of brevity.

[0108] In ​In the illustrated embodiment, a second ohmic contact region 62 and a fourth ohmic contact region 64 are formed on a second surface 40b of the second substrate 40. The details and formation method of the second ohmic contact region 62 and the fourth ohmic contact region 64 can be substantially similar to those described above in connection with ​ The details and formation method, and the related description is omitted for the sake of brevity.

[0109] As ​ shown, a memory cell group 100 is formed (step (h)). The details and formation method of the memory cell group 100 can be similar to those described above in connection with ​ The details and formation method, and the related description is omitted for the sake of brevity. In ​ the illustrated embodiment, a wiring layer 72 coupled to the second ohmic contact region 42 and the fourth ohmic contact region 64 is formed, and the memory cell group 100 is formed on the wiring layer 72. The material and process for forming the wiring layer 72 can be similar to those described above in connection with ​ The material and process, and the related description is omitted for the sake of brevity. Bit lines 75 can be formed on the memory cell group 100. The material and process for forming the bit lines 75 can be similar to those described above in connection with ​ The material and process, and the related description is omitted for the sake of brevity. In some embodiments, instead of forming the first ohmic contact region 61 and the third ohmic contact region 63 before patterning the second substrate 40, the first ohmic contact region 61 and the third ohmic contact region 63 can be formed in the first dielectric structure 21 using an inlay process or a dual inlay process or any suitable method.

[0110] Referring to ​ , a semiconductor structure 104 including a first diode 45 and a second diode 46 is provided. ​ The illustrated semiconductor structure 104 can be substantially similar to the semiconductor structure 104 described above in connection with ​ wherein like reference numerals indicate like elements. If applicable, the related details described above in connection with ​ can be applicable here.

[0111] Referring to ​ , a semiconductor structure 105 is provided. The semiconductor structure 105 includes the first diode 45 and the second diode 46 as described above, and the memory cell group 100. ​ The illustrated semiconductor structure 105 can be substantially similar to the semiconductor structure 105 described above in connection with ​ wherein like reference numerals indicate like elements. If applicable, the related details of the semiconductor structure 105 described above can be applicable here.

[0112] In ​In the illustrated embodiment, the methods disclosed herein can be used to fabricate a memory device that includes a pair of PN diodes as selectors, which can provide additional options for fabricating a memory device that includes vertical PN diodes. Specifically, subsequent high-temperature processes after implantation and / or epitaxial processes may damage earlier fabricated devices and / or metal layers. However, by using the processes described herein, the high-temperature annealing process is completed at an earlier stage (e.g., forming the second doped region 42, the second heavily doped region 42a, and the fourth heavily doped region 44a in the stage shown in ​ ), such that high-temperature processes at a later stage can be avoided.

[0113] ​ is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure. As ​ shown, a first structure 200A and a second structure 300B are provided. The first structure 200A and the second structure 300B can be substantially similar to the first structure 200A and the second structure 200B described above, where like reference numerals indicate like elements, and the relevant details described above in connection with ​ apply herein if applicable. ​

[0114] As ​ shown, the second substrate 40 includes a second doped region 42r extending from the second surface 40b of the second substrate 40. The second doped layer 42r can be a locally unpatterned layer. For example, the second doped layer 42r can extend laterally across a predetermined device region DR1 in which device units are to be formed. The second doped layer 42r can further include a second heavily doped layer 42ar. In the embodiment shown in ​ , the second heavily doped layer 42a is aligned with the second doped layer 42r in the vertical direction. The second substrate 40 can further include a fourth heavily doped layer 44ar. As ​ shown, each of the second heavily doped layer 42ar and the fourth heavily doped layer 44ar can also be a locally unpatterned layer. For example, the second heavily doped layer 42ar can extend laterally across the device region DR1, and the fourth heavily doped layer 44ar can extend laterally across a continuous device region DR2 in which another device unit is to be formed. Thus, a heavily doped layer is formed on the surface of the second substrate 40, which includes a plurality of continuous doped layers (e.g., the second heavily doped layer 42ar and the fourth heavily doped layer 44ar) that can be doped with dopants of different conductive types. The materials and formation methods of the second doped layer 42r and the second heavily doped layer 42ar can be substantially similar to those described above in connection with ​ ​the second doped region 42, the second heavily doped region 42a, and the heavily doped region 44a; and the material and formation method of the fourth heavily doped layer 44ar can be substantially similar to those described above in connection with ​ the fourth heavily doped region 44a.

[0115] As ​ shown, the second structure 300B is flipped and bonded to the first structure 200A through the bonding layer 20 to form a bonded structure. The details and process of the bonding process can be similar to those described above in connection with ​ the details and process, and the related description is omitted for the sake of brevity. Then, a portion of the second substrate 40 is removed from the bonded structure approximately to the hydrogen implantation layer 110. The removal process and related details can be substantially similar to those described above in connection with ​ the removal process and related details, and the related description is omitted for the sake of brevity. Thus, a semiconductor substrate 300 is provided (step (a)). The semiconductor substrate 300 can be substantially similar to the semiconductor substrate 200 described above in connection with ​ wherein like reference numerals indicate like elements.

[0116] As ​ shown, a third doped layer 43r is formed in the second substrate 40. The third doped layer 43r can be formed to extend from the first surface 40a of the second substrate 40. The third doped layer 43r can be a locally unpatterned layer. For example, the third doped layer 43r can extend laterally across the device region DR2. The third doped layer 43r can further include a third heavily doped layer 43ar. The third heavily doped layer 43ar can extend from the first surface 40a of the second substrate 40. In ​ the embodiment shown, the third doped layer 43r and the third heavily doped layer 43ar can be aligned with the fourth heavily doped layer 44ar in the vertical direction. The second substrate 40 can further include a first heavily doped layer 41ar. The first heavily doped layer 41ar can extend from the first surface 40a of the second substrate 40. As ​ shown, each of the first heavily doped layer 41ar and the third heavily doped layer 43ar can be a locally unpatterned layer. For example, the first heavily doped layer 41ar can extend laterally across the device region DR1, and the third heavily doped layer 43ar can extend laterally across the continuous device region DR2. Thus, a heavily doped layer is formed on the surface of the second substrate 40, and the heavily doped layer includes a plurality of continuous doped layers (e.g., the first heavily doped layer 41ar and the third heavily doped layer 43ar) that can be doped with dopants of different conductivity types. In ​ the embodiment shown, the first heavily doped layer 41ar is aligned with the second doped layer 42 in the vertical direction.

[0117] In some embodiments, each of the first heavily doped layer 41ar, the third doped region 43, and the third heavily doped layer 43ar may be formed in the second substrate 40 by a suitable method (e.g., implantation process and epitaxial growth). The materials and formation methods of the third doped layer 43r and the third heavily doped layer 43ar may be substantially similar to those of the third doped region 43 and the third heavily doped region 43a described above in connection with ​ the materials and formation methods of the third doped region 43 and the third heavily doped region 43a; and the materials and formation methods of the first heavily doped layer 41ar may be substantially similar to those of the first heavily doped layer 41a described above in connection with ​ the materials and formation methods of the first heavily doped layer 41a.

[0118] In ​ the illustrated embodiment, an ohmic contact material layer 60r may be formed on the first surface of the second substrate 40. The ohmic contact material layer 60r may be an unpatterned layer (or at least extend across a plurality of device regions, e.g., device regions DR1 and contiguous device region DR2). In ​ the illustrated embodiment, the ohmic contact layer 60r extends across the third doped layer 43 and the first heavily doped layer 43ar. The ohmic contact material layer 60r may include a metal, alloy, or conductive metal compound suitable for forming an ohmic contact region, such as Mo, Ag, TiN, or a combination thereof. The ohmic contact material layer 60r may be formed by deposition (such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD)).

[0119] As ​ illustrated, the ohmic contact layer 60r may be patterned to form a first ohmic contact region 61 of the first diode and a third ohmic contact region 63 of the second diode. ​ The first ohmic contact region 61 and the third ohmic contact region 63 illustrated may be substantially similar to the first ohmic contact region 61 and the third ohmic contact region 63 described above in connection with ​ the first ohmic contact region 61 and the third ohmic contact region 63. The patterning process and related details may be substantially similar to the patterning process and related details described above in connection with ​ the patterning process and related details, and the related description is omitted for brevity.

[0120] Alternatively, in some other embodiments, the ohmic contact layer 60r illustrated may not be formed, and the first doped region 41 and the fourth doped region 44 may be defined before forming the first ohmic contact region 61 and / or the third ohmic contact region 63. For example, ​ as ​The first dielectric structure 21 therein can be formed in the trench 47 separating the third doped region 43 and the fourth doped region 44 from the first doped region 41, and the first ohmic contact region 61 and / or the third ohmic contact region 63 can be formed in the first dielectric structure 21 using a damascene process or a dual damascene process or any suitable method to form ​ the structure shown.

[0121] As ​ shown, the second substrate 40 is patterned to define the first doped region 41 of the first diode and the fourth doped region 44 of the second diode (step (c)). In ​ the embodiment shown, the first heavily doped layer 41ar can be patterned to form the first heavily doped region 41a of the first doped region 41, and the fourth heavily doped layer 44ar can be patterned to form the fourth heavily doped region 44a of the fourth doped region 44. ​ The first doped region 41, the first heavily doped region 41a, the fourth doped region 44, and the fourth heavily doped region 44a shown can be respectively substantially similar to those described above in connection with ​ those.

[0122] In ​ the embodiment shown, the second doped layer 42r can be patterned to form the second doped region 42 of the first diode, and the third doped layer 43r can be patterned to form the third doped region 43 of the second diode. The second heavily doped layer 42ar can be patterned to form the second heavily doped region 42a of the second doped region 42, and the third heavily doped layer 43ar can be patterned to form the third heavily doped region 43a of the third doped region 43. ​ The second doped region 42, the second heavily doped region 42a, the third doped region 43, and the third heavily doped region 43a shown can be respectively substantially similar to those described above in connection with ​ those.

[0123] As ​ shown, a semiconductor structure 105 is provided. ​ The structure shown can be formed by a process similar to the processes described above in connection with ​ and ​ those, and the related description is omitted for brevity.

[0124] Referring to ​ , a semiconductor structure 104 including a first diode 45 and a second diode 46 is provided. ​ The semiconductor structure 104 shown can be substantially similar to that described above in connection with ​The semiconductor structure 104 described above, where like reference numerals indicate like elements. If applicable, the relevant details of the semiconductor structure 104 described above ​ may be applicable here.

[0125] Referring ​ , a semiconductor structure 105 is provided. The semiconductor structure 105 includes the first diode 45 and the second diode 46 described above, and a memory cell array 100. ​ The semiconductor structure 105 shown may be substantially similar to the semiconductor structure 105 described above in connection with ​ where like reference numerals indicate like elements. If applicable, the relevant details of the semiconductor structure 105 described above may be applicable here.

[0126] In ​ the illustrated embodiment, the method disclosed herein may be used to fabricate a memory device including a pair of PN diodes as selectors, where the ion implantation process may be completed during the fabrication of a semiconductor substrate (e.g., semiconductor substrate 300), and the first doped region 41, the second doped region 42, the third doped region 43, and the fourth doped region 44 may be formed by patterning a second substrate 40, as ​ shown, without performing other implantation processes. Further, by the method disclosed herein, the first heavily doped region 41a may be formed to be vertically aligned with the first ohmic contact region 61, and the third heavily doped region 43a may be formed to be vertically aligned with the third ohmic contact region 63.

[0127] ​ is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure. As ​ shown, a first structure 200A and a second structure 400B are provided. The first structure 200A includes a first substrate 10. The first structure 200A and the second structure 400B may be substantially similar to the first structure 200A and the second structure 400B described above in connection with ​ except that the second structure 400B does not include an etch stop layer on the second substrate 40. Specifically, the second structure 400B includes a third doped region 43, a third heavily doped region 43a, and a first heavily doped region 41a. The details and processes for forming the third doped region 43, the third heavily doped region 43a, and the first heavily doped region 41a may be substantially similar to the details and processes described above in connection with ​ and the related descriptions are omitted for brevity. If applicable, other relevant details described above in connection with ​ may be applicable here.

[0128] As ​As shown, a first ohmic contact region 61 and a third ohmic contact region 63 are formed on a second surface 40b of a second substrate 40. In some embodiments, a dielectric structure 21a may be formed on the second surface 40b of the second substrate 40, and the first ohmic contact region 61 and the third ohmic contact region 63 may be formed in the dielectric structure 21a using a damascene process, a dual damascene process, or any suitable method. However, the present disclosure is not limited thereto. The dielectric structure 21a may include a dielectric material such as silicon oxide, silicon oxynitride, a low dielectric constant (low-k) material, combinations thereof, and / or other suitable materials, and may be formed by deposition (such as CVD, PVD, or ALD), spin coating, or any suitable method. If applicable, other details of the first ohmic contact region 61 and the third ohmic contact region 63 described above in connection with ​ may be applicable herein.

[0129] As ​ shown, an interconnect structure 80 is formed on the first dielectric structure 21a. The formation process and related details of the interconnect structure 80 may be substantially similar to the formation process and related details described above in connection with ​ and the related description is omitted for the sake of brevity.

[0130] As ​ shown, a first dielectric layer 121 is formed on the first substrate 10 and a second dielectric layer 122 is formed on the interconnect structure 80 before the first structure 200A and the second structure 400B are bonded. The details and processes for forming the first dielectric layer 121 and the second dielectric layer 122 may be substantially similar to the details and processes described above in connection with ​ and the related description is omitted for the sake of brevity.

[0131] As ​ shown, the second structure 400B is flipped and bonded to the first structure 200A through a bonding layer 20 to form a bonded structure. The details and bonding of the first structure 200A and the second structure 400B may be similar to the details and bonding described above in connection with ​ and the related description is omitted for the sake of brevity. Then, a portion of the second substrate 40 is removed from the bonded structure approximately to the hydrogen implantation layer 110. The removal process and related details may be substantially similar to the removal process and related details described above in connection with ​ and the related description is omitted for the sake of brevity. Thus, a semiconductor substrate 400 is provided (step (a)).

[0132] As ​As shown, a second doped region 42 of the first diode is formed in the second substrate 40 (step (b)). The second doped region 42 may be formed to extend from a first surface 40a of the second substrate 40. The second doped region 42 may further include a second heavily doped region 42a that extends from the first surface 40a of the second substrate 40. A fourth heavily doped region 44a may also be formed in the second substrate 40. The fourth heavily doped region 44a may be formed to extend from the first surface 40a of the second substrate 40. The details and processes for forming the fourth heavily doped region 44a, the second doped region 42, and the second heavily doped region 42a may be substantially similar to the details and processes described above in connection with ​ and the related description is omitted for the sake of brevity.

[0133] As ​ shown, a second ohmic contact region 62 of the first diode and a fourth ohmic contact region 64 of the second diode are formed on the first surface 40a of the second substrate 40. The details and processes for forming the second ohmic contact region 62 and the fourth ohmic contact region 64 may be substantially similar to the details and processes described above in connection with ​ and the related description is omitted for the sake of brevity.

[0134] As ​ shown, the second substrate 40 is patterned to define a first doped region 41 of the first diode and a fourth doped region of the second diode 46 (step (c)). The patterning process may be substantially similar to the patterning process described above in connection with ​ and the related description is omitted for the sake of brevity. In the embodiment shown in ​ , the dielectric structure 21a may act as an etch stop layer in the etching process for patterning the second substrate 40.

[0135] As ​ shown, a first dielectric structure 21 is formed. The first dielectric structure 21 may surround the first doped region 41 and the second doped region 42 of the first diode and the third doped region 43 and the fourth doped region 44 of the second diode. As ​ shown, the first dielectric structure 21 may fill the trench 47 such that each of the first diode and the second diode is surrounded by the first dielectric structure 21. The materials and processes for forming the first dielectric structure 21 may be substantially similar to the materials and processes described above in connection with ​ and the related description is omitted for the sake of brevity.

[0136] As ​ shown, a memory cell group 100 is formed (step (h)). The details and formation method of the memory cell group 100 may be similar to those described above in connection with ​ and ​The details and formation methods described above are omitted for brevity. In ​ the illustrated embodiment, a wiring layer 72 is formed that is coupled to the second ohmic contact region 62 and the fourth ohmic contact region 64, and a memory cell group 100 is formed on the wiring layer 72. The materials and processes for forming the wiring layer 72 may be similar to those described above in connection with ​ the materials and processes, and the related descriptions are omitted for brevity. Bit lines 75 may be formed on the memory cell group 100. The materials and processes for forming the bit lines 75 may be similar to those described above in connection with ​ the materials and processes, and the related descriptions are omitted for brevity.

[0137] Referring to ​ , a semiconductor structure 104 including a first diode 45 and a second diode 46 is provided. ​ The illustrated semiconductor structure 104 may be substantially similar to the semiconductor structure 104 described above in connection with ​ where like reference numerals indicate like elements. If applicable, the related details described above in connection with ​ may be applicable here.

[0138] Referring to ​ , a semiconductor structure 105 is provided. The semiconductor structure 105 includes the first diode 45 and the second diode 46 as described above, and a memory cell group 100. ​ The illustrated semiconductor structure 105 may be substantially similar to the semiconductor structure 105 described above in connection with ​ where like reference numerals indicate like elements. If applicable, the related details of the semiconductor structure 105 described above may be applicable here.

[0139] In ​ to the embodiment shown in FIGS. 5H, the methods disclosed herein can be used to fabricate a memory device including a pair of PN diodes as selectors, which can provide additional options for fabrication and can further reduce process steps and processing time.

[0140] ​ is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure. As ​ shown, a first structure 200A and a second structure 500B are provided. The first structure 200A includes a first substrate 10. The first structure 200A and the second structure 500B may be substantially similar to the first structure 200A and the second structure 300B described above in connection with ​ where like reference numerals indicate like elements, except that the second structure 500B does not include an etch stop layer on the second substrate 40. If applicable, the above in connection with​ The other relevant details described above may apply here.

[0141] As ​ , a semiconductor substrate 500 is provided (step (a)). The semiconductor substrate 500 may be substantially similar to the semiconductor substrate 300 described above in connection with ​ , where like reference numerals indicate like elements, except that the semiconductor substrate 500 does not include an etch stop layer. The semiconductor substrate 500 may be formed by the processes described above in connection with ​ and ​ , and the related description is omitted for brevity.

[0142] As ​ shown, a third doped layer 43r is formed in the second substrate 40 (step (b)). The third doped layer 43r may further include a third heavily doped layer 43ar. A first heavily doped layer 41ar may also be formed. The details and formation methods of the third doped layer 43r, the third heavily doped layer 43ar, and the first heavily doped layer 41ar may be similar to the details and formation methods described above in connection with ​ , and the related description is omitted for brevity. An ohmic contact material layer 60r may be formed on the second substrate 40. The details and formation methods of the ohmic contact material layer 60r may be similar to the details and formation methods described above in connection with ​ , and the related description is omitted for brevity.

[0143] As ​ shown, the ohmic contact layer 60r may be patterned to form a first ohmic contact region 61 of the first diode 45 and a third ohmic contact region 63 of the second diode 46. The details and formation methods of the first ohmic contact region 61 and the third ohmic contact region 63 may be substantially similar to the details and formation methods described above in connection with ​ , and the related description is omitted for brevity.

[0144] As ​ shown, the second substrate 40 is patterned to define a first doped region 41 of the first diode and a fourth doped region 44 of the second diode (step (c)). In ​In the illustrated embodiment, the bonding layer 20 can act as an etch stop layer in the etching process for patterning the second substrate 40. The second doped layer 42r can be patterned to form the second doped region 42, the second heavily doped layer 42ar can be patterned to form the second heavily doped region 42a, and the first heavily doped layer 41ar can be patterned to form the first heavily doped region 41a. The third doped layer 43r can be patterned to form the third doped region 43, the third heavily doped layer 43ar can be patterned to form the third heavily doped region 43a, and the fourth heavily doped layer 41ar can be patterned to form the fourth heavily doped region 41a. The patterning process and related details can be substantially similar to the patterning process and related details described above in connection with ​ and ​ and the related description is omitted for the sake of brevity.

[0145] As ​ shown, a conformal etch stop layer 31 is formed after patterning the second substrate 40. The conformal etch stop layer 31 can be formed on the sidewalls of the first doped region 41, the second doped region 42, the third doped region 43, and the fourth doped region 44. In the embodiment shown in ​ , the conformal etch stop layer 31 can also be formed on the bonding layer 20. The conformal etch stop layer 31 can have a high etch selectivity with respect to the bonding layer 20. The conformal etch stop layer 31 can be made of a material similar to the etch stop layer 30 discussed above in connection with ​ . For example, in one embodiment, the conformal etch stop layer 31 can include silicon nitride, and the bonding layer 20 includes silicon oxide. In one embodiment, the thickness of the conformal etch stop layer 31 can be in the range between 0.2 nm and 5 nm. These values are merely examples and are not intended to be limiting. In one embodiment, the conformal etch stop layer 31 can be formed by epitaxial growth or by deposition (such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD)). In one embodiment, the conformal etch stop layer 31 can be formed by sputtering or evaporation. In some embodiments, a portion of the conformal etch stop layer formed on the first ohmic contact region 61 and / or the third ohmic contact region 63 (if any) can be removed to ensure electrical connection to the devices and / or conductive features that will subsequently be formed on the second substrate 40 (e.g., ​ shown interconnect structure 80).

[0146] As ​ shown, the first dielectric structure 21 is formed, and the interconnect structure 80 can be formed on the first dielectric structure 21. The details and formation method of the first dielectric structure 21 and the interconnect structure 80 can be similar to those described above in connection with ​The details and forming methods described above are omitted for the sake of brevity.

[0147] Alternatively, in some other embodiments, the first ohmic contact region 61 and / or the third ohmic contact region 63 may be formed after the first dielectric structure 21. For example, the first dielectric structure 21 may be formed in a trench between portions of the conformal etch stop layer 31 surrounding the first diode 45 and the second diode 46, and the first ohmic contact region 61 and / or the third ohmic contact region 63 may be formed in the first dielectric structure 21 using a damascene process or a dual damascene process or any suitable method to form ​ the structure shown.

[0148] As ​ shown, a third substrate 90 is added to the first surface 40a of the second substrate 40, where the second substrate 40 is located between the third substrate 90 and the first substrate 10 (step (d)). The forming and / or attaching method and details of the third substrate 90 may be similar to those described above in connection with ​ the forming and / or attaching method and details described above, and the related description is omitted for the sake of brevity.

[0149] As ​ shown, the first substrate 10 and the bonding layer 20 are removed to expose the second surface 40b of the second substrate 40. The removal of the first substrate 10 and the bonding layer 20 may be substantially similar to the process described above in connection with ​ that described above. Specifically, in ​ the embodiment shown, the bonding layer 20 may be removed to expose the second surface 40b of the second substrate 40 and the conformal etch stop layer 31. After removing the bonding layer 20, the second doped region 42 of the first diode and the fourth doped region 44 of the second diode may be exposed (step (f)). In ​ the embodiment shown, the second heavily doped region 42a of the second doped region 42 and the fourth heavily doped region 44a of the fourth doped region 44 are exposed. The materials of the conformal etch stop layer 31 and the bonding layer 20 may be selected such that the conformal etch stop layer 31 can act as an etch stop layer having a higher etch selectivity relative to the bonding layer and / or can act as an etch stop layer under more desirable etching conditions. In some embodiments, the material of the second substrate 40 may be selected such that the first heavily doped regions 42a and 44a can act as an etch stop layer having a higher etch selectivity relative to the bonding layer 20.

[0150] As ​As shown, a second ohmic contact region 62 of the first diode 45 and a fourth ohmic contact region 64 of the second diode 46 are formed on a second surface 40b of the second substrate 40 (step (f)). Details and formation methods of the second ohmic contact region 62 and the fourth ohmic contact region 64 can be substantially similar to those of the second ohmic contact region 62 and the fourth ohmic contact region 64 described above in conjunction with Figure 1J the second ohmic contact region 62 and the fourth ohmic contact region 64.

[0151] As Figure 6H shown, a second dielectric structure 22 is formed. The second dielectric structure 22 can include one or more stacked dielectric layers. The second dielectric structure 22 can include dielectric materials such as silicon oxide, silicon oxynitride, low-k materials, combinations thereof, and / or other suitable materials, and can be formed by deposition (such as CVD, PVD, or ALD), spin coating, or any suitable method. In some embodiments, the second ohmic contact region 62 and the fourth ohmic contact region 64 can be formed using a damascene process, a dual damascene process, or any suitable method after the second dielectric structure 22 is formed.

[0152] As Figure 6H shown, a memory cell group 100 is formed (step (h)). Details and formation methods of the memory cell group 100 can be similar to those described above in conjunction with Figure 1J and related descriptions are omitted for the sake of brevity. In the embodiment shown in Figure 6H , a wiring layer 72 coupled to the second ohmic contact region 62 and the fourth ohmic contact region 64 can be formed, and the memory cell group 100 can be formed in the second dielectric structure 22 and on the wiring layer 72. The wiring layer 72 can be formed in the second dielectric structure 22 using a damascene or dual damascene process or any suitable method. Materials and processes for forming the wiring layer 72 can be similar to those described above in conjunction with Figure 1J .

[0153] As Figure 6H shown, bit lines 75 can be formed on the memory cell group 100. The bit lines 75 can be formed in the second dielectric structure 22 using a damascene process, a dual damascene process, or any suitable method. Materials and processes for forming the bit lines 75 can be similar to those described above in conjunction with Figure 1J .

[0154] Referring to Figure 6H , a semiconductor structure 104 including the first diode 45 and the second diode 46 is provided. Figure 6H The semiconductor structure 104 shown can be substantially similar to the semiconductor structure 104 described above in conjunction with Figure 1J wherein like reference numerals indicate like elements. If applicable, relevant details described above in conjunction with Figure 1J can be applicable here.

[0155] Reference Figure 6H Figure 6H , a semiconductor structure 160 is provided. The semiconductor structure 160 includes the first diode 45 and the second diode 46 as described above, and a memory cell array 100. Figure 6H The illustrated semiconductor structure 160 may be substantially similar to the semiconductor structure 105 described above in connection with Figure 1J where like reference numerals indicate like elements. In Figure 6H the illustrated embodiment, a conformal etch stop layer 31 is disposed on the sidewalls of the first doped region 41, the second doped region 42, the third doped region 43, and the fourth doped region 44. The conformal etch stop layer 31 may also be disposed between the first dielectric structure 21 and the second dielectric structure 22. The conformal etch stop layer 31 can protect these features from an etch process used to remove the bonding layer 20. This reduces the difficulty of manufacturing the semiconductor structure 160.

[0156] In Figures 6A to 6H the illustrated embodiment, the methods disclosed herein can be used to fabricate a memory device including a pair of PN diodes as selectors, which can provide additional options for fabrication and can further reduce process steps and processing time. For example, a removal process of the etch stop layer 30 as Figure 1H illustrated can be omitted. In addition, the conformal etch stop layer can act as a diffusion barrier for the metal portions (e.g., ohmic contact regions, etc.) of the semiconductor structure 160.

[0157] Figure 7A FIGS. 21 to 7E are schematic diagrams illustrating intermediate stages in the fabrication of a semiconductor structure according to an embodiment of the present disclosure. As Figure 7A illustrated, a second doped region 42, a second heavily doped region 42a, a third doped region 43, a third heavily doped region 43a, a first ohmic contact region 61, and a third ohmic contact region 63 are formed, and the first doped region 41 and the fourth doped region 44 are defined by patterning the second substrate 40. Figure 7A The details and formation methods of the illustrated semiconductor structure may be substantially similar to the details and formation methods described above in connection with Figures 6A to 6D where like reference numerals indicate like elements.

[0158] As Figure 7B illustrated, a first dielectric structure 21 is formed, and an interconnect structure 80 may be formed on the first dielectric structure 21. The details and formation methods of the first dielectric structure 21 and the interconnect structure 80 may be similar to the details and formation methods described above in connection with Figure 1E and the related description is omitted for brevity.

[0159] As Figure 7BAs shown, a third substrate 90 is added to the first surface 40a of the second substrate 40, where the second substrate 40 is located between the third substrate 90 and the first substrate 10 (step (d)). The method and details of forming and / or attaching the third substrate 90 may be similar to those described above in connection with Figure 1F the method and details of forming and / or attaching, and the related description is omitted for the sake of brevity.

[0160] As Figure 7C shown, the first substrate 10 and the bonding layer 20 are removed to expose the second surface 40b of the second substrate 40. The removal of the first substrate 10 may be substantially similar to the process described above in connection with Figure 1G the above. Specifically, in the embodiment shown in Figure 7C , only a part of the bonding layer 20 on the second doping region 42 and the fourth doping region 44 is removed. Grooves may be formed in the bonding layer 20 using suitable methods (such as photolithography and etching techniques). After removing the first substrate 10 and the bonding layer 20, the second doping region 42a of the first diode and the fourth doping region 64a of the second diode in the second substrate 40 are exposed (step (f)). In the embodiment shown in Figure 7C , the second heavily doped region 42a of the second doping region 42 and the fourth heavily doped region 44a of the fourth doping region 44 are exposed. In some embodiments, the material of the second substrate 40 may be selected such that the second heavily doped region 42a and the fourth heavily doped region 44a can act as an etch stop layer having a higher etch selectivity relative to the bonding layer 20.

[0161] As Figure 7D shown, a second ohmic contact region 62 and a fourth ohmic contact region 64 are formed on the second surface 40b of the second substrate 40. In the embodiment shown in Figure 7D , the second ohmic contact region 62 and the fourth ohmic contact region 64 may be formed in the grooves extending through the bonding layer 20. The materials and forming methods of the second ohmic contact region 62 and the fourth ohmic contact region 64 may be substantially similar to those described above in connection with Figure 1J the above, and the related description is omitted for the sake of brevity.

[0162] As Figure 7D shown, a second dielectric structure 22 is formed. The second dielectric structure 22 may include one or more stacked dielectric layers. The details and forming methods of the second dielectric structure 22 may be substantially similar to those described above in connection with Figure 6H the above, and the related description is omitted for the sake of brevity. In some embodiments, the first ohmic contact region 62 and the fourth ohmic contact region 64 may be formed in the second dielectric structure 22 using an inlay process or a dual inlay process or any suitable method.

[0163] As Figure 7D shown, a memory cell group 100 is formed (step (h)). The details of the memory cell group 100 and the forming method can be similar to the details and forming method described above in connection with Figure 1J and the related description is omitted for the sake of brevity. In the embodiment shown in FIG. 7E, a wiring layer 72 coupled to the second ohmic contact region 62 and the fourth ohmic contact region 64 can be formed, and the memory cell group 100 can be formed in the second dielectric structure 22 and on the wiring layer 72. The wiring layer 72 can be formed in the second dielectric structure 22 and / or the bonding layer 20 using a damascene process or a dual damascene process or any suitable method. The materials and processes for forming the wiring layer 72 can be similar to the materials and processes described above in connection with Figure 1J . As Figure 7D shown, bit lines 75 can be formed on the memory cell group 100. The materials and processes for forming the bit lines 75 are described above in connection with Figure 1J and the related description is omitted for the sake of brevity.

[0164] Referring to Figure 7D , a semiconductor structure 104 including a first diode 45 and a second diode 46 is provided. Figure 7D The semiconductor structure 104 shown can be substantially similar to the semiconductor structure 104 described above in connection with Figure 1J , where like reference numerals indicate like elements. If applicable, the related details described above in connection with Figure 1J can apply here.

[0165] Referring to Figure 7D , a semiconductor structure 170 is provided. The semiconductor structure 170 includes the first diode 45 and the second diode 46 as described above, and the memory cell group 100. Figure 7D The semiconductor structure 170 shown can be substantially similar to the semiconductor structure 105 described above in connection with Figure 1J , where like reference numerals indicate like elements. If applicable, the related details of the semiconductor structure 105 described above can apply here.

[0166] In Figures 7A to 7D the embodiment shown, a memory device including a pair of PN diodes as selectors can be manufactured using the methods disclosed herein, which can provide additional options for manufacturing and can further reduce process steps and processing time.

[0167] Figures 8A to 8B is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure. As Figure 8A and Figure 8BAs shown, a memory device 1001 is provided. The memory device 1001 includes a memory cell array 100, an electrode 103, a first diode pair 111, and a second diode pair 112. The memory cell array 100 may have a first end 101 and a second end 102. The memory cell array 100 is electrically coupled to the electrode 103 from the second end 102 of the memory cell array 100.

[0168] The electrode 103 extends laterally from a first side 100a of the memory cell array 100 to a second side 100b of the memory cell array 100 in a first direction 102a. As Figure 8A and Figure 8B shown, the electrode 103 may be disposed between the memory cell array 100 and the first diode pair 111 in a vertical direction. The electrode 103 may be disposed between the memory 100 and the second diode pair 112 in a vertical direction. However, the present disclosure is not limited thereto. In some embodiments, the electrode 103 includes a material having a high spin Hall effect, for example, β-tantalum (β-Ta), β-tungsten (β-W), Ta, W, Pt, Cu doped with elements such as Ir, Bi, etc., and any element that can exhibit high spin-orbit coupling. The electrode 103 may be formed in the first dielectric structure 21 using a damascene process or a dual damascene process or any suitable method.

[0169] The memory cell array 100 may include a magnetic tunnel junction (MTJ) structure. The details and formation method of the memory cell array 100 may be substantially similar to the details and formation method described above in connection with Figure 1J and the related description is omitted for the sake of brevity.

[0170] As Figure 8A and Figure 8B shown, each of the first diode pair 111 and the second diode pair 112 includes a first diode and a second diode. In some embodiments, the first diode 245 and the second diode 246 in the second diode pair 112 are arranged along the first direction 102a.

[0171] As Figure 8A and Figure 8BAs shown, the first diode pair 111 can be disposed on the first side 100a of the memory cell group 100. Each of the first diode 111 and the second diode 112 in the first diode pair 111 is electrically coupled to an electrode at the first side 100a of the memory cell group 100. In some embodiments, the first diode 145 and the second diode 146 in the first diode pair 111 are arranged along the first direction 102a. The first diode 145 in the first diode pair 111 includes a first doped region 141 and a second doped region 142. The second doped region 142 is disposed on and in contact with the first doped region 141. The second diode 146 in the first diode pair 111 includes a third doped region 143 and a fourth doped region 144. The fourth doped region 144 is disposed on and in contact with the third doped region 143. The top surface of the second doped region 142 is higher than the bottom surface of the third doped region 143, and the top surface of the fourth doped region 144 is higher than the bottom surface of the first doped region 141. Each of the first doped region 141 and the fourth doped region 144 is doped with a dopant of a first conductivity type, and each of the second doped region 142 and the third doped region 143 is doped with a dopant of a second conductivity type opposite to the first conductivity type.

[0172] Details and formation methods of the first diode pair 111 and its first diode 145 and second diode 146 can be substantially similar to those of the semiconductor structures 105, 160 or 170 and their first diodes 45 and second diodes 46 described herein in connection with Figures 1A to 1J , Figures 2A to 2E , Figures 3A to 3I , Figures 4A to 4F , Figures 5A to 5G , Figures 6A to 6H , Figures 7A to 7D , Figures 16A to 16D , and Figures 17A to 17C where like reference numerals indicate like elements.

[0173] As Figure 8A and Figure 8BAs shown, the second diode pair 112 is disposed on the second side 100b of the memory cell group 100. Each of the first diode 245 and the second diode 246 in the second diode pair 112 is electrically coupled to an electrode at the second side 100b of the memory cell group 100. In some embodiments, the first diode 245 and the second diode 246 in the second diode pair 112 are arranged along the first direction 102a. The first diode 245 in the second diode pair 112 includes a first doped region 241 and a second doped region 242. The second doped region 242 is disposed on and in contact with the first doped region 241. The second diode 246 in the second diode pair 112 includes a third doped region 243 and a fourth doped region 244. The fourth doped region 244 is disposed on and in contact with the third doped region 243. The top surface of the second doped region 242 is higher than the bottom surface of the third doped region 243, and the top surface of the fourth doped region 244 is higher than the bottom surface of the first doped region 241. Each of the first doped region 241 and the fourth doped region 244 is doped with a dopant of a first conductivity type, and each of the second doped region 242 and the third doped region 243 is doped with a dopant of a second conductivity type opposite to the first conductivity type.

[0174] Details and formation methods of the second diode pair 112 and its first diode 245 and second diode 246 can be substantially similar to those of the semiconductor structures 105, 160 or 170 and their first diodes 45 and second diodes 46 described herein in connection with Figures 1A to 1J , Figures 2A to 2E , Figures 3A to 3I , Figures 4A to 4F , Figures 5A to 5G , Figures 6A to 6H , Figures 7A to 7D , Figures 16A to 16D , and Figures 17A to 17C where like reference numerals indicate like elements. In some embodiments, the second diode pair 112 can be fabricated simultaneously during the fabrication of the first diode pair 111. The memory device 1001 or a similar semiconductor structure can be formed by a process similar to the processes described herein in connection with Figures 1A to 1J , Figures 2A to 2E , Figures 3A to 3I , Figures 4A to 4F , Figures 5A to 5G , Figures 6A to 6H , Figures 7A to 7D , Figures 16A to 16D , and Figures 17A to 17C described.

[0175] As Figure 8AAs shown, the first diode 145 in the first diode pair 111 may further include a first ohmic contact region 161 and a second ohmic contact region 162. The first ohmic contact region 161 may be in contact with the bottom surface of the first doped region 141 of the first diode pair 111. The second ohmic contact region 162 may be in contact with the top surface of the second diode region 142. The second diode 146 in the first diode pair 111 may further include a third ohmic contact region 163 and a fourth ohmic contact region 164. The third ohmic contact region 163 may be in contact with the bottom surface of the third doped region 143. The fourth ohmic contact region 164 may be in contact with the top surface of the fourth doped region 144. The first diode 245 in the first diode pair 112 may further include a first ohmic contact region 261 and a second ohmic contact region 242. The first ohmic contact region 261 may be in contact with the bottom surface of the first doped region 241. The second ohmic contact region 262 may be in contact with the top surface of the second doped region 242. The second diode 246 in the second diode pair 112 may further include a third ohmic contact region 263 and a fourth ohmic contact region 264. The third ohmic contact region 263 may be in contact with the bottom surface of the third doped region 243. The fourth ohmic contact region 264 may be in contact with the top surface of the fourth doped region 244.

[0176] In some embodiments, the first doped region 141 may further include a first heavily doped region 141a. The second doped region 142 may further include a second heavily doped region 142a. The third doped region 143 may further include a third heavily doped region 143a. The fourth doped region 144 may further include a fourth heavily doped region 144a. An ohmic junction may be formed between the first ohmic contact region 161 and the first heavily doped region 141a, an ohmic junction may be formed between the second ohmic contact region 162 and the second heavily doped region 142a, an ohmic junction may be formed between the third ohmic contact region 163 and the third heavily doped region 163a, and an ohmic junction may be formed between the fourth ohmic contact region 164 and the fourth heavily doped region 164a.

[0177] In some embodiments, the first doped region 241 may further include a first heavily doped region 241a. The second doped region 242 may further include a second heavily doped region 242a. The third doped region 243 may further include a third heavily doped region 243a. The fourth doped region 244 may further include a fourth heavily doped region 244a. An ohmic junction may be formed between the first ohmic contact region 261 and the first heavily doped region 261a, an ohmic junction may be formed between the second ohmic contact region 262 and the second heavily doped region 262a, an ohmic junction may be formed between the third ohmic contact region 263 and the third heavily doped region 263a, and an ohmic junction may be formed between the fourth ohmic contact region 264 and the fourth heavily doped region 264a.

[0178] As Figure 8A and Figure 8B shown, each of the first diode 145 in the first diode pair 111 and the second diode 146 can be electrically coupled to the electrode 103 at the first side 100a of the memory cell group 100, and each of the first diode 245 and the second diode 246 in the second diode pair 112 can be electrically coupled to the electrode at the second side 100b of the memory cell group 100. In Figure 8A and Figure 8B the illustrated embodiment, the memory cell group 100 is electrically coupled to the second ohmic contact region 162 of the second diode 146 in the first diode pair 111 and the second contact layer 262 of the first diode 162 in the second diode pair 112. The memory cell group 100 can also be electrically coupled to the fourth ohmic contact region 164 of the first diode 145 in the first diode pair 111 and the fourth ohmic contact region 264 of the second diode 246 in the second diode pair 112. In an embodiment where the second ohmic contact region 162 of the first diode pair 111 and the second ohmic contact region 262 of the second diode pair 112 are omitted, the memory cell group 100 can be electrically coupled to the second doped region 142 of the first diode pair 111 and the second doped region 242 of the second diode pair 112. In an embodiment where the fourth ohmic contact region 164 of the first diode pair 111 and the fourth ohmic contact region 264 of the second diode pair 112 are omitted, the memory cell group 100 can be electrically coupled to the fourth doped region 144 of the first diode pair 111 and the fourth doped region 242 of the second diode pair 112. In some other embodiments, the arrangements of the first diode pair 111 and the second diode pair 112 can be interchangeable. In some other embodiments, the arrangements of the first diode 145 and the second diode 146 in the first diode pair 111 can be interchangeable. In some other embodiments, the arrangements of the first diode 145 and the second diode 146 in the second diode pair 112 can be interchangeable.

[0179] As Figure 8A and Figure 8B shown, a bit line 75 is formed on the memory cell group 100. The memory cell group 100 can be electrically coupled to the bit line 75 from the first end 101 of the memory cell group 100. The bit line 75 can extend laterally in the second direction 102b. The second direction 102b is different from the first direction 102a. The materials and processes for forming the bit line 75 can be similar to those described above in connection with Figure 1J and the related description is omitted for brevity.

[0180] As Figure 8A and Figure 8BAs shown, both the first diode 145 and the second diode 146 in the first diode pair 111 are electrically coupled to the first word line WL1. The first word line WL1 extends in the second direction 102b. However, the present disclosure is not limited thereto. In some embodiments, the first word line WL1 may be electrically coupled to the first ohmic contact region 161 of the first diode 145 and the third ohmic contact region 163 of the second diode 146. In some embodiments, the first word line WL1 may be disposed in the same layer as the first ohmic contact region 161 and the third ohmic contact region 163 and disposed between the first ohmic contact region and the third ohmic contact region. In embodiments where the first ohmic contact region 161 of the first diode 145 is connected to the third ohmic contact region 163 of the second diode 146, an extended portion of the first ohmic contact region 161 and / or the third ohmic contact region 163 may function as a word line, and an additional wiring structure (e.g., Figure 8A the first word line WL1 in

[0181] As Figure 8A and Figure 8B shown, the second diode 246 in the second diode pair 112 is electrically coupled to the third word line WL3, and the first diode 245 in the second diode pair 112 is electrically coupled to the fourth word line WL4. The third word line WL3 and the fourth word line WL4 both extend in the first direction 102a. However, the present disclosure is not limited thereto. In some embodiments, the third word line WL3 may be electrically coupled to the third ohmic contact region 253 of the first diode 246, and the fourth word line WL4 may be electrically coupled to the first ohmic contact region 261 of the first diode 245.

[0182] The word lines WL1, WL3, and WL4 may include Pt, Pd, Ir, Ru, Cu, W, some or certain other suitable materials, or a combination of the foregoing, and may be formed in the first dielectric structure 21 using a damascene process or a dual damascene process or any suitable method. The terms "word line" and "bit line" in the present disclosure are used only for clarity and are not intended to limit the present disclosure. For example, in some instances, Figure 8A and Figure 8B shown, the word lines WL3 and WL4 may be referred to as "bit lines", while the word line WL1 is referred to as a word line; in some instances, Figure 8A and Figure 8B shown, the word line WL1 may be referred to as "bit line", while the word lines WL3 and WL4 are referred to as word lines; or, in some instances, Figure 8A and Figure 8B shown, the bit line 75 may be referred to as a "read line".

[0183] When the memory cell group 100 includes a magnetic tunnel junction (MTJ) structure, Figure 8A and Figure 8BThe illustrated memory device 1001 can be a spin-orbit torque type MRAM device (SOT-MRAM). When a program current flows through electrode 103, the spin Hall effect (SHE) of electrode 103 generates spin injection into the free magnetic layer of the MTJ structure. A larger spin Hall effect can provide sufficient spin injection to switch the magnetization orientation of the free magnetic layer. A larger spin Hall effect can be achieved by using a suitable material with a high spin Hall effect (high spin injection efficiency) for electrode 103 or by passing a larger program current through electrode 103.

[0184] For example, for a data write process, the program current can flow along a first current flow path from the first word line WL1 through the second diode 146 in the first diode pair 111, electrode 103, and the first diode 245 in the second diode pair 112 to the fourth word line WL4; alternatively, the program current can flow along a second current flow path from the third word line WL3 through the second diode 246 in the second diode pair 112, electrode 103, the first diode 145 in the first diode pair 145 to the first word line WL1. The flow and direction of the program current can be controlled by the voltage applied to the word lines. Although Figure 8A only one memory cell is illustrated, multiple memory cells or a memory cell array can be fabricated simultaneously using the methods disclosed herein.

[0185] Figure 8B is Figure 8A a perspective view of the illustrated memory device 1001, which is disposed in the memory array MA1. As Figure 8B shown, the memory device 1001 and the adjacent memory device 1001' are arranged along the second direction 102b and are serially connected via the bit line 75 and the first word line WL1. The adjacent memory device 1001' can be substantially similar to the memory device 1001, where like reference numerals indicate like elements.

[0186] As Figure 8B shown, the memory device 1001 can have cell sizes of 8F and 4F in the first direction 102a and the second direction 102b, respectively, which provides a cell size of 32 feature squares (F 2 ). The symbol "F" herein represents the minimum feature size (or half of the minimum feature pitch) typically associated with a specific lithography process.

[0187] In Figure 8A and Figure 8BIn the illustrated embodiments, the methods disclosed herein can be used to fabricate a memory device including two pairs of PN diodes as selectors. Both the first diode pair 111 and the second diode pair 112 include two diodes arranged in opposite directions and are located at substantially the same level as described above. Thus, the memory device disclosed herein can include a simplified wiring structure and can have a reduced cell size. In addition, the SOT-MRAM memory device disclosed herein can have a lower programming voltage, a lower write error rate, and a lower current flow path resistance than the STT-MRAM memory device, and can switch faster (e.g., in less than 10 ns). The memory device disclosed herein can also provide a higher current density than a memory device using transistors as selectors and can have desired characteristics such as higher efficiency, faster memory access, and low power consumption.

[0188] Figure 9 is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure. Figure 9 is Figure 8A a perspective view of the illustrated memory device 1001, which is disposed in the memory array MA2. Figure 9 The illustrated memory array MA2 can be substantially similar to the memory array MA1 described above in connection with Figure 8A and Figure 8B where like reference numerals indicate like elements. Referring to Figure 9 , the third word line WL3' of the memory device 1001' can overlap with the third word line WL3 of the memory device 1001 in the vertical direction (e.g., in a third direction perpendicular to both the first direction 102a and the second direction 102b). As Figure 9 shown, the arrangement of the memory array MA2 can further reduce the cell sizes of the memory devices 1001 and 1001' in the first direction 102a and the second direction 102b to 8F and 3F, respectively, which provides a cell size of 24 feature squares (F 2 ).

[0189] Figures 10A to 10B is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure. As Figure 10A and Figure 10B shown, a memory device 1002 is provided. Figure 10A and Figure 10B The illustrated memory device 1002 can be substantially similar to the memory device 1001 described above in connection with Figure 8A , Figure 8B and Figure 9 where like reference numerals indicate like elements.

[0190] As Figure 10A andFigure 10B As shown, the first diode 145 in the first diode pair 111 is electrically coupled to the first word line WL1, and the second diode 146 in the first diode pair 111 is electrically coupled to the second word line WL2. Both the first word line WL1 and the second word line WL2 extend in the second direction 102b. In some embodiments, the first word line WL1 may be electrically coupled to the first ohmic contact region 161 of the first diode 145 in the first diode pair 111, and the second word line WL2 may be electrically coupled to the third ohmic contact region 163 of the second diode 146 in the first diode pair 111. In some embodiments, the first word line WL1 may be disposed in the same layer as the first ohmic contact region 161. In some embodiments, the second word line WL2 may be disposed in the same layer as the third ohmic contact region 163. In some embodiments, the extended portion of the first ohmic contact region 161 may function as a word line, such that an additional wiring layer (e.g., Figure 10A the first word line WL1 in Figure 10A ) may not be required. In some embodiments, the extended portion of the third ohmic contact region 163 may function as a word line, such that an additional wiring layer (e.g., Figure 8A the second word line WL2 in Figure 8A ) may not be required. The first word line WL1 and the second word line WL2 may be formed using materials and methods similar to those described above in connection with Figure 8B the word lines WL1, WL3, and WL4. If applicable, the descriptions of the bit line 75, the third word line WL3, and the fourth word line WL4 in connection with

[0191] When the memory cell group 100 includes a magnetic tunnel junction (MTJ) structure, Figure 10A and Figure 10B the memory device 1002 shown may be a SOT-MRAM device. The relevant details of the SOT-MRAM device may be substantially similar to the SOT-MRAM device described above in connection with Figure 8A , where like reference numerals indicate like elements. In Figure 10AIn the illustrated embodiment, for the data writing process, the program current can flow along a first current flow path from the first word line WL2 through the second diode 146 in the first diode pair 111, the electrode 103, and the first diode 245 in the second diode pair 112 to the fourth word line WL4; alternatively, the program current can flow along a second current flow path from the third word line WL3 through the second diode 246 in the second diode pair 112, the electrode 103, and the first diode 145 in the first diode pair 111 to the second word line WL1. The flow and direction of the program current can be controlled by the voltage applied to the word lines. Although Figure 10A only one memory cell is illustrated, multiple memory cells or an array of memory cells can be fabricated simultaneously using the methods disclosed herein.

[0192] Figure 10B is Figure 10A a perspective view of the memory device 1002 shown, which is disposed in the memory array MA3. As Figure 10B shown, the memory device 1002 and the adjacent memory device 1002' are arranged along the second direction 102b and are connected in series via the bit line 75, the first word line WL1, and the second word line WL2. The adjacent memory device 1002' can be substantially similar to the memory device 1002, where like reference numerals indicate like elements. By Figure 10B the arrangement shown, the memory device 1002 can have a cell size of 8F and 3F in the first direction 102a and the second direction 102b, respectively, which provides a cell size of 24 feature squares (F 2 ).

[0193] Compared with Figures 8A to 8B and Figure 9 the four-terminal memory device 1001 shown (e.g., connected to the first word line WL1, the third word line WL3, the fourth word line WL4, and the bit line 75), the memory device 1002 is a five-terminal memory device (e.g., connected to the first word line WL1, the second word line WL2, the third word line WL3, the fourth word line WL4, and the bit line 75). The five-terminal memory device 1002 can provide additional options for controlling the voltage of each line and can enable different operation modes and / or improve the performance of the memory device.

[0194] Figures 11A to 11B is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure. As Figure 11A and Figure 11B shown, the memory device 1003 is provided. Figure 11A and Figure 11B The memory device 1003 shown can be substantially similar to that described above in connection with Figure 8A and Figure 8BThe memory device 1001 described above, where like reference numerals indicate like elements.

[0195] As Figure 11A and Figure 11B shown, the fourth word line WL4 is disposed on the electrode 103 such that the memory cell group 100 is disposed vertically between the fourth word line WL4 and the electrode 103. In some embodiments, the fourth word line WL4 is disposed on the memory cell group 100. If applicable, the descriptions of the bit line 75, word lines WL1, WL3, and WL4 in conjunction with Figure 8A and Figure 8B may apply here. In some other embodiments, the settings of the first diode pair 111 and the second diode pair 112 may be interchangeable. In some other embodiments, the settings of the first diode 145 and the second diode 146 in the first diode pair 111 may be interchangeable. In some other embodiments, the settings of the first diode 245 and the second diode 246 in the second diode pair 112 may be interchangeable. In some other embodiments, similar to Figure 10A and Figure 10B the memory device 1002 shown, the first diode 145 may be electrically coupled to the first word line WL1, and the second diode 146 may be electrically coupled to the second word line WL2.

[0196] When the memory cell group 100 includes a magnetic tunnel junction (MTJ) structure, Figure 11A and Figure 11B the memory device 1003 shown may be a SOT-MRAM device. The relevant details of the SOT-MRAM device may be substantially similar to the SOT-MRAM device described above in conjunction with Figure 8A where like reference numerals indicate like elements.

[0197] Figure 11B is ​ a perspective view of the memory device 1003 shown, which is disposed in the memory array MA4. The memory device 1003 and the adjacent memory device 1003' are arranged along the second direction 102b and are serially connected via the bit line 75 and the first word line WL1. The adjacent memory device 1003' may be substantially similar to the memory device 1003, where like reference numerals indicate like elements. As ​ shown, the third word line WL3 and the fourth word line WL4 are aligned vertically. Specifically, the third word line WL3, the fourth word line WL4, and the electrode 103 may be aligned vertically such that the cell size of the memory device 1003 can be further reduced. By ​In the arrangement shown, the memory device 1003 may have cell sizes of 10F and 2F in the first direction 102a and the second direction 102b, respectively, which provides a cell size of 20 feature squares (F 2 ). The structures of the memory devices 1003 and 1003' and the arrangement of the memory array MA4 may further reduce the cell sizes of the memory devices 1003 and 1003'.

[0198] ​ is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure. ​ is ​ a perspective view of the memory device 1003 shown, which is disposed in the memory array MA5. The memory device 1003 and another adjacent memory device 1003” are arranged along the first direction 102a and are connected in series via the third word line WL3. The adjacent memory device 1003” may be substantially similar to the memory device 1003, where like reference numerals indicate like elements. As ​ shown, the memory devices 1003 and 1003” may share the fourth word line WL4. By ​ the arrangement shown, the memory device 1003 may have cell sizes of 9F and 2F in the first direction 102a and the second direction 102b, respectively, which provides a cell size of 18 feature squares (F 2 ). The arrangement of the memory array MA5 may further reduce the cell sizes of the memory devices 1003 and 1003'.

[0199] ​ is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure. As ​ and ​ shown, a memory device 3001 is provided. ​ and ​ The memory device 3001 shown may be substantially similar to the memory device 1002 described above in connection with ​ and ​ , where like reference numerals indicate like elements.

[0200] As ​ and ​ shown, both the first diode 245 and the second diode 246 in the second diode pair 112 are electrically coupled to the third word line WL3. The third word line WL3 extends in the first direction 102a. In some embodiments, the third word line WL3 may be electrically coupled to the first ohmic contact region 261 of the first diode 245 in the second diode pair 112 and the third ohmic contact region 263 of the second diode 246 in the second diode pair 112. The third word line WL3 may be used in connection with the above ​The materials and methods described are formed using similar materials and methods. If applicable, in combination with ​ and ​ The description of the bit line 75, the first word line WL1, and the second word line WL2 may be applicable here. In some other embodiments, the arrangements of the first diode pair 111 and the second diode pair 112 may be interchangeable. In some other embodiments, the arrangements of the first diode 145 and the second diode 146 in the first diode pair 111 may be interchangeable. In some other embodiments, the arrangements of the first diode 245 and the second diode 246 in the second diode pair 112 may be interchangeable.

[0201] When the memory cell group 100 includes a magnetic tunnel junction (MTJ) structure, ​ and ​ the memory device 3001 shown may be a SOT-MRAM device. The relevant details of the SOT-MRAM device may be substantially similar to the SOT-MRAM device described above in connection with ​ where like reference numerals indicate like elements. In ​ the embodiment shown, for the data writing process, the program current may flow along a first current flow path from the second word line WL2 through the second diode 146 in the first diode pair 111, the electrode 103, and the first diode 245 in the second diode pair 112 to the third word line WL3; alternatively, the program current may flow along a second current flow path from the third word line WL3 through the second diode 246 in the second diode pair 112, the electrode 103, and the first diode 145 in the first diode pair 111 to the first word line WL1. The flow and direction of the program current may be controlled by the voltage applied to the word lines. Although ​ only one memory cell is illustrated, multiple memory cells or a memory cell array may be fabricated simultaneously using the methods disclosed herein.

[0202] ​ is ​ a perspective view of the memory device 3001 shown, which is disposed in the memory array MA6. As ​ shown, the memory device 3001 and the adjacent memory device 3001' are arranged along the second direction 102b and are connected in series via the bit line 75, the first word line WL1, and the second word line WL2. The adjacent memory device 3001' may be substantially similar to the memory device 3001, where like reference numerals indicate like elements. As ​ shown, the third word line WL3 may be disposed below the electrode 103, the first word line WL1, and the second word line WL2 in the vertical direction. The third word line WL3 and the electrode 103 may be aligned in the vertical direction. By as ​For the layout of the memory array MA6 shown, the cell sizes of the memory devices 3001 and 3001' in the first direction 102a and the second direction 102b can be further reduced to 8F and 2F respectively, which provides a cell size of 16 feature squares (F 2 ).

[0203] ​ is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure. ​ is an electronic schematic diagram illustrating a memory array including a memory device as ​ shown. ​ is as ​ shown, an operating voltage diagram of a storage cell in the memory array. As ​ and ​ shown, the memory device 3002 is provided. ​ and ​ The memory device 3002 shown can be substantially similar to the memory device 1001 and the memory device 3001 described above in connection with ​ and ​ and ​ where like reference numerals indicate like elements.

[0204] As ​ and ​ shown, both the first diode 145 and the second diode 146 are electrically coupled to the first word line WL1. If applicable, the description of the first word line WL1 in connection with ​ and ​ above can apply here. As ​ and ​ shown, both the first diode 245 and the second diode 246 are electrically coupled to the third word line WL3. If applicable, the description of the third word line WL3 in connection with ​ and ​ above can apply here. In some other embodiments, the settings of the first diode pair 111 and the second diode pair 112 can be interchangeable. In some other embodiments, the settings of the first diode 145 and the second diode 146 in the first diode pair 111 can be interchangeable. In some other embodiments, the settings of the first diode 245 and the second diode 246 in the second diode pair 112 can be interchangeable.

[0205] When the memory cell group 100 includes a magnetic tunnel junction (MTJ) structure, ​ and ​ the memory device 3002 shown can be a SOT-MRAM device. The relevant details of the SOT-MRAM device can be substantially similar to those described above in connection with ​The SOT-MRAM device described, where like reference numerals indicate like elements. In ​ the illustrated embodiment, for a data write process, the program current can flow along a first current flow path from the first word line WL1 through the second diode 146 in the first diode pair 111, the electrode 103, and the first diode 245 in the second diode pair 112 to the third word line WL3; or, the program current can flow along a second current flow path from the third word line WL3 through the second diode 246 in the second diode pair 112, the electrode 103, and the first diode 145 in the first diode pair 111 to the first word line WL1. The flow and direction of the program current can be controlled by the voltage applied to the word lines. Although ​ only one memory cell is illustrated, multiple memory cells or memory cell arrays can be fabricated simultaneously using the methods disclosed herein.

[0206] ​ is ​ a perspective view of the memory device 3002 shown, which is disposed in the memory array MA7. As ​ shown, the memory device 3002 and the adjacent memory device 3002' are arranged along the second direction 102b and are connected in series via the bit line 75 and the first word line WL1. The adjacent memory device 3002' can be substantially similar to the memory device 3002, where like reference numerals indicate like elements. As ​ shown, the third word line WL3 can be disposed below the electrode 103 and the first word line WL1 in the vertical direction. The third word line WL3 and the electrode 103 can be aligned in the vertical direction. By the arrangement of the memory array MA6 as ​ shown, the cell sizes of the memory devices 3002 and 3002' in the first direction 102a and the second direction 102b can be 8F and 2F, respectively, which provides a cell size of 16 feature squares (F 2 ). ​ The arrangement of the memory array MA7 shown can further reduce the memory cell size of the memory device.

[0207] Compared with ​ the four-terminal memory device 3001 shown (e.g., connected to the first word line WL1, the second word line WL2, the third word line WL3, and the bit line 75), the memory device 3002 is a three-terminal memory device (e.g., connected to the first word line WL1, the third word line WL3, and the bit line 75). The three-terminal memory device 3002 can provide additional options for voltage control and can simplify the routing of power rails and / or signal lines while having a relatively small memory cell size.

[0208] ​is an electrical schematic diagram showing a memory array including memory devices such as ​ and ​ shown. As ​ shown, memory devices 3002 and 3002' as shown in ​ and a plurality of memory devices similar to memory device 3002 are arranged in rows and columns within memory array MA7. Although sixteen memory devices are shown in ​ , the number of memory devices included in memory array MA7 is not limited to this.

[0209] In the ​ illustrated embodiment, memory array MA7 is controlled by a plurality of bit lines BL, BL', BL” and BL”', a plurality of first word lines WL1, WL1', WL1” and WL1”', and a plurality of third word lines WL3, WL3', WL3” and WL3”'. The number of bit lines and word lines is not limited to this.

[0210] ​ An exemplary table of the operating voltages of the memory cells (e.g., memory device 3002) in memory array MA7 as shown in ​ is shown.

[0211] Referring to the second row 1402 of Table 1400, when memory device 3002 is selected for a first write operation (e.g., writing “1”), a write voltage (Vw) is applied to the third word line WL3, the first word line WL1 is grounded (GND), and the bit line BL is electrically floating, while the other lines (e.g., the first word lines WL1', WL1” and WL1”', the third word lines WL3', WL3” and WL3”', and the bit lines BL', BL” and BL”') are electrically floating.

[0212] Referring to the third row 1403 of Table 1400, when memory device 3002 is selected for a second write operation (e.g., writing “0”), a write voltage (Vw) is applied to the first word line WL1, the third word line WL3 is grounded (GND), and the bit line BL is electrically floating, while the other lines (e.g., the first word lines WL1', WL1” and WL1”', the third word lines WL3', WL3” and WL3”', and the bit lines BL', BL” and BL”') are electrically floating.

[0213] Referring to the fourth row 1404 of Table 1400, when the memory device 3002 is selected for reading, a read voltage (Vr) is applied to the bit line BL, the first word line WL1 is electrically floating, and the other lines (e.g., the first word lines WL1', WL1", and WL1"', the third word lines WL3', WL3", and WL3"', and the bit lines BL', BL", and BL"') are electrically floating. The state of the memory cell group can be determined by sensing the voltage of the third word line WL3. Table 1400 shows a set of possible operating voltages of the memory device. However, the present disclosure is not limited thereto.

[0214] ​ is a schematic diagram illustrating an embodiment of a memory device according to the present disclosure. As ​ shown, a memory device 4000 is provided. ​ The memory device 4000 shown can be substantially similar to the memory device 3002 described above in connection with ​ and ​ where like reference numerals indicate like elements.

[0215] As ​ shown, the first diode 145 and the second diode 146 in the first diode pair 111 are arranged along a second direction 102b different from the first direction 102a. The first diode 245 and the second diode 246 in the second diode pair 112 are arranged along the second direction 102b. In ​ the embodiment shown, the bit line 75 extends in the first direction 102a. However, the present disclosure is not limited thereto. In some other embodiments, the arrangements of the first diode pair 111 and the second diode pair 112 can be interchangeable. In some other embodiments, the arrangements of the first diode 145 and the second diode 146 in the first diode pair 111 can be interchangeable. In some other embodiments, the arrangements of the first diode 245 and the second diode 246 in the second diode pair 112 can be interchangeable.

[0216] When the memory cell group 100 includes a magnetic tunnel junction (MTJ) structure, ​ the memory device 4000 shown can be a SOT-MRAM device. The relevant details of the SOT-MRAM device can be substantially similar to the SOT-MRAM device described above in connection with ​ where like reference numerals indicate like elements. In ​In the illustrated embodiment, for the data write process, the program current can flow along a first current flow path from the first word line WL1 through the second diode 146 in the first diode pair 111, the electrode 103, and the first diode 245 in the second diode pair 112 to the third word line WL3; alternatively, the program current can flow along a second current flow path from the third word line WL3 through the second diode 246 in the second diode pair 112, the electrode 103, the first diode 146 in the first diode pair 111 to the first word line WL1. The flow and direction of the program current can be controlled by the voltage applied to the word line.

[0217] Figure 15 is a perspective view of the memory device 4000 disposed in the memory array MA7. As Figure 15 shown, the memory device 4000 and the adjacent memory device 4000' are arranged along the first direction 102a and are connected in series via the bit line 75 and the first word line WL1. The adjacent memory device 4000' can be substantially similar to the memory device 4000, where like reference numerals indicate like elements. By the arrangement of the memory array MA8 as Figure 15 shown, the cell sizes of the memory devices 4000 and 4000' in the first direction 102a and the second direction 102b can be 4F and 4F respectively, which provides a cell size of 16 feature squares (F 2 ). The three-terminal memory device 4000 can provide additional options for voltage control and can simplify the routing of power rails and / or signal lines while having a relatively small memory cell size.

[0218] Figures 16A to 16D is a schematic diagram illustrating an intermediate stage in the manufacture of a semiconductor structure according to an embodiment of the present disclosure. As Figure 16A shown, a semiconductor substrate A1' is provided (step (a)). The semiconductor substrate A1' includes a first substrate 10 and a second substrate 40 on the first substrate 10. The first substrate 10 and the second substrate 40 can be substantially similar to the first substrate 10 and the second substrate 40 described above in connection with Figure 1A and the related description is omitted for brevity. The semiconductor substrate A1' further includes an etch stop layer 30 between the first substrate 10 and the second substrate 40. The etch stop layer 30 can have a high etch selectivity with respect to the first substrate 10.

[0219] In Figure 16AIn the illustrated embodiment, the first substrate 10 may include silicon or germanium. In some other embodiments, the first substrate 10 may include glass, polysilicon, or ceramic. The etch stop layer 30 may include silicon germanium (SiGe). The second substrate 40 may include a semiconductor material, such as silicon or germanium. In some embodiments, the etch stop layer 30 and the second substrate 40 may be sequentially formed on the first substrate 10, for example, by epitaxial growth, thereby forming the semiconductor substrate A1'.

[0220] As Figure 16B shown, a third substrate 90 is added to the first surface 40a of the second substrate 40, wherein the second substrate 40 is located between the third substrate 90 and the first substrate 10 (step (d)). Figure 16B The structure shown can be formed by a process substantially similar to the process described above in connection with Figures 1A to 1F which like reference numerals indicate like elements.

[0221] As Figure 16C shown, the first substrate 10 is removed to expose the etch stop layer 30. The first substrate 10 can be removed by performing a suitable process, such as grinding, chemical mechanical polishing (CMP), and an etching process. In one embodiment, a portion of the first substrate 10 is removed by a grinding and / or CMP process, and the remaining portion of the first substrate 10 can be removed by one or more etching processes. In Figure 16C the illustrated embodiment, the etch stop layer 30 can protect the fourth doped region 44, the region in the second substrate 40 where the second doped region is to be formed, and the first dielectric structure 21 from the etching process.

[0222] As Figure 16D shown, at least a portion of the etch stop layer 30 is removed. The etch stop layer 30 can be removed by oxide etching, plasma etching, hydrogen peroxide etching, etc. and / or any suitable method. After removing the etch stop layer 30, at least a portion of the second surface 40b of the second substrate 40 is exposed. By the method disclosed herein, the exposed second surface 40b of the second substrate 40 can have better flatness, so that the height of the diodes formed in the second substrate 40 can be more uniform and more controllable. Moreover, the endpoint of the etching process for removing the first substrate 10 can be more easily controlled. A semiconductor structure substantially similar to the semiconductor structures 104 and 105 described above can be formed from Figure 16D the structure shown by a process similar to the process described above in connection with Figures 1H to 1J which. In some embodiments, the manufacturing process described above in connection with Figures 2A to 2E can start from Figure 16A the semiconductor substrate A1' shown.

[0223] Figures 17A to 17C is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure. As Figure 17A shown, a semiconductor substrate A1” is provided (step (a)). The semiconductor substrate A1” includes a first substrate 10 and a second substrate 40 on the first substrate. The first substrate 10 and the second substrate 40 may be substantially similar to the first substrate 10 and the second substrate 40 described above in connection with Figure 1A which, for the sake of brevity, the related description is omitted.

[0224] In Figure 17A the illustrated embodiment, the first substrate 10 may include silicon or germanium. In some other embodiments, the first substrate 10 may include glass, polysilicon, or ceramic. The second substrate 40 may include silicon germanium (SiGe). In some embodiments, the second substrate 40 may be formed on the first substrate 10 by epitaxial growth, thereby forming the semiconductor substrate A1”.

[0225] As Figure 17B shown, a third substrate 90 is added to a first surface 40a of the second substrate 40, where the second substrate 40 is located between the third substrate 90 and the first substrate 10 (step (d)). Figure 17B The illustrated structure may be formed by a process substantially similar to the process described above in connection with Figures 1A to 1F which, like reference numerals indicate like elements.

[0226] As Figure 17C shown, the first substrate 10 is removed to expose the second substrate 40. The first substrate 10 may be removed by performing a suitable process such as grinding, chemical mechanical polishing (CMP), and etching processes. After removing the first substrate 10, at least a portion of a second surface 40b of the second substrate 40 is exposed. In one embodiment, a portion of the first substrate 10 is removed by grinding and / or CMP processes, and the remaining portion of the first substrate 10 may be removed by one or more etching processes. A semiconductor structure substantially similar to the semiconductor structures 104 and 105 described above may be formed from the structure shown in FIG. 17D by a process similar to the process described above in connection with Figures 1H to 1J which. In some embodiments, the manufacturing process described above in connection with Figures 2A to 2E may start from the Figure 17A shown semiconductor substrate A1”.

[0227] Figure 18 is a schematic diagram illustrating an embodiment of a semiconductor substrate according to the present disclosure. As Figure 18As shown, a semiconductor substrate B1 is provided. The semiconductor substrate B1 can be used as the semiconductor substrate in step (a) of the method discussed above. The semiconductor substrate B1 can include a first region R1 and a second region R2. The first region R1 of the semiconductor substrate B1 can be substantially similar to the semiconductor substrate A1” described above in connection with Figure 17A and the second region R2 of the semiconductor substrate B1 can be substantially similar to the semiconductor substrate A1' described above in connection with Figure 16A where like reference numerals indicate like elements. In the Figure 18 embodiment shown, the first substrate 10 can include silicon or germanium. The etch stop layer 30 can include silicon germanium (SiGe). The second substrate 40I in the first region R1 can include silicon germanium (SiGe). The second substrate 40II in the second region R2 can include a semiconductor material such as silicon or germanium. In some embodiments, the etch stop layer 30, the second substrate 40I, and the second substrate 40II can be formed by epitaxial growth on the first substrate 10 using a mask, thereby forming the semiconductor substrate B1. In one embodiment, semiconductor devices such as the first diode 45, the second diode 46, the semiconductor structure 104, and / or the semiconductor structure 105, etc., described above can be formed in the first region R1. In one embodiment, peripheral devices such as control devices, word line selection devices, and bit line selection devices can be formed in the second region R2.

[0228] Figure 19 is a schematic diagram illustrating an embodiment of a semiconductor structure according to the present disclosure. As Figure 19 shown, a semiconductor structure 180A is provided. The semiconductor structure 180A can be similar to the semiconductor structure 105 described above in connection with Figure 1J , Figure 3I , Figure 4F , Figure 5G , Figure 6H and Figure 7D where like reference numerals indicate like elements. The semiconductor structure 180A or a similar semiconductor structure can be formed by a process similar to the process described above in connection with Figures 1A to 1J , Figures 2A to 2E , Figures 3A to 3I , Figures 4A to 4F , Figures 5A to 5G , Figures 6A to 6H , Figures 7A to 7D , Figures 16A to 16D and Figures 17A to 17C If applicable, the relevant details above can apply here.

[0229] The semiconductor structure 180A includes a first doped region 41 and a second doped region 42. Figure 19 The first doped region 41 and the second doped region 42 shown can be substantially similar to those described above in connection withFigures 1A to 1J The first doping region 41 and the second doping region 42 are described above, and related descriptions are omitted for simplicity. The second doping region 42 is disposed on and in contact with the first doping region 41. The first doping region 41 is doped with a dopant of a first conductivity type, and the second doping region 42 is doped with a dopant of a second conductivity type opposite to the first conductivity type. In Figure 19 the illustrated embodiment, the first doping region 41 is doped with an n-type dopant, and the second doping region 42 is doped with a p-type dopant, and a p-n junction is formed between the first doping region 41 and the second doping region 42. In one embodiment, each of the first doping region 41 and the second doping region 42 includes a single crystal semiconductor material. As Figure 19 shown, the sidewalls of the first doping region 41 and the second doping region 42 are aligned in the vertical direction.

[0230] In Figure 19 the illustrated embodiment, the first doping region 41 includes a first heavily doped region 41a extending from the bottom surface 41BS of the first doping region 41. The first heavily doped region 41a is doped with a dopant of a first conductivity type (e.g., an n-type dopant). In Figure 19 the illustrated embodiment, the second doping region 42 includes a second heavily doped region 42a extending from the top surface 42TS of the second doping region 42. The second heavily doped region is doped with a dopant of a second conductivity type (e.g., a p-type dopant). Figure 19 The first heavily doped region 41a and the second heavily doped region 42a shown can be respectively substantially similar to the first heavily doped region 41a and the second heavily doped region 42a described above in connection with Figures 1A to 1J and related descriptions are omitted for simplicity.

[0231] As Figure 19 shown, the semiconductor structure 180A further includes a first ohmic contact region 61 and a second ohmic contact region 62. The first ohmic contact region 61 is disposed in contact with the bottom surface of the first doping region 41. An ohmic junction is formed between the first doping region 41 and the first ohmic contact region 61. The second ohmic contact region 62 is disposed in contact with the top surface of the second doping region 42. An ohmic junction is formed between the second doping region 42 and the second ohmic contact region 62. Figure 19 The first ohmic contact region 61 and the second ohmic contact region 62 shown can be respectively substantially similar to the first ohmic contact region 61 and the second ohmic contact region 62 described above in connection with Figures 1A to 1J and related descriptions are omitted for simplicity.

[0232] As Figure 19As shown, the semiconductor structure 180A further includes a first dielectric layer 21. The first dielectric layer 21 is disposed to surround each of the first doped region 42, the second doped region 42, the first ohmic contact region 61, and the second ohmic contact region 62. Figure 19 The illustrated first dielectric layer 21 may be substantially similar to the first dielectric layer 21 described above in connection with Figures 1A to 1J and relevant descriptions are omitted for the sake of brevity.

[0233] In Figure 19 the illustrated embodiment, the semiconductor structure 180A may further include a memory cell group 100. The memory cell group 100 has a first end 101 and a second end 102. The memory cell group 100 is electrically coupled to the first ohmic contact region 61 from the second end 102 of the memory cell group 100. Figure 19 The illustrated memory cell group 100 may be substantially similar to the memory cell group 100 described above in connection with Figure 1J and relevant descriptions are omitted for the sake of brevity. In one embodiment, the memory cell group 100 may include a magnetic tunnel junction (MTJ) structure, or a phase change material, or a resistive random access memory (RRAM) material. Figure 19 The illustrated semiconductor structure 180A may be a phase change random access memory (PcRAM) device or a resistive random access memory (RRAM) device. Although Figure 19 only one memory cell is illustrated, multiple memory cells or a memory cell array may be fabricated simultaneously using the methods disclosed herein.

[0234] Figure 20 is a schematic diagram illustrating an embodiment of a semiconductor structure in accordance with the present disclosure. As Figure 20 shown, a semiconductor structure 180B is provided. Figure 20 The illustrated semiconductor structure 180B may be substantially similar to the semiconductor structure 105 described above in connection with Figure 1J , Figure 3I , Figure 4F , Figure 5G , Figure 6H and Figure 7D where like reference numerals indicate like elements. The semiconductor structure 180B or a similar semiconductor structure may be formed by a process similar to the processes described above in connection with Figures 1A to 1J , Figures 2A to 2E , Figures 3A to 3I , Figures 4A to 4F , Figures 5A to 5G , Figures 6A to 6H , Figures 7A to 7D , Figures 16A to 16D and Figures 17A to 17C If applicable, the relevant details above may apply here.

[0235] The semiconductor structure 180B includes a third doped region 43 and a fourth doped region 44.Figure 20 The third doped region 43 and the fourth doped region 44 shown can be substantially similar to the third doped region 43 and the fourth doped region 44 described above respectively, and the related descriptions are omitted for the sake of brevity. The fourth doped region 44 is disposed on and in contact with the third doped region 43. The third doped region 43 is doped with a dopant of a first conductivity type, and the fourth doped region 44 is doped with a dopant of a second conductivity type opposite to the first conductivity type. In Figures 1A to 1J the embodiment shown, the third doped region 43 is doped with a p-type dopant, and the fourth doped region 44 is doped with an n-type dopant, and a p-n junction is formed between the third doped region 43 and the fourth doped region 44. In one embodiment, each of the third doped region 43 and the fourth doped region 44 includes a single-crystal semiconductor material. As Figure 20 shown, the sidewalls of the third doped region 43 and the fourth doped region 44 are aligned in the vertical direction. Figure 20 shown, the sidewalls of the third doped region 43 and the fourth doped region 44 are aligned in the vertical direction.

[0236] In Figure 20 the embodiment shown, the third doped region 43 includes a third heavily doped region 43a extending from the bottom surface 43BS of the third doped region 43. The third heavily doped region 43a is doped with a dopant of a first conductivity type (e.g., a p-type dopant). In Figure 20 the embodiment shown, the fourth doped region 44 includes a fourth heavily doped region 44a extending from the top surface 44TS of the fourth doped region 44. The fourth heavily doped region 44a is doped with a dopant of a second conductivity type (e.g., an n-type dopant). Figure 20 The third heavily doped region 43a and the fourth heavily doped region 44a shown can be substantially similar to the third heavily doped region 43a and the fourth heavily doped region 44a described above respectively, and the related descriptions are omitted for the sake of brevity. Figures 1A to 1J the third heavily doped region 43a and the fourth heavily doped region 44a described above respectively, and the related descriptions are omitted for the sake of brevity.

[0237] As Figure 20 shown, the semiconductor structure 180B further includes a third ohmic contact region 63 and a fourth ohmic contact region 64. The third ohmic contact region 63 is disposed in contact with the bottom surface of the third doped region 43. An ohmic junction is formed between the third doped region 43 and the third ohmic contact region 63. The fourth ohmic contact region 64 is disposed in contact with the top surface of the fourth doped region 44. An ohmic junction is formed between the fourth doped region 44 and the fourth ohmic contact region 64. Figure 19 The third ohmic contact region 63 and the fourth ohmic contact region 64 shown can be substantially similar to the third ohmic contact region 63 and the fourth ohmic contact region 64 described above respectively, and the related descriptions are omitted for the sake of brevity. Figures 1A to 1J the third ohmic contact region 63 and the fourth ohmic contact region 64 described above respectively, and the related descriptions are omitted for the sake of brevity.

[0238] As Figure 20As shown, the semiconductor structure 180B further includes a first dielectric layer 21. The first dielectric layer 21 is disposed to surround each of the third doped region 43, the fourth doped region 44, the third ohmic contact region 63, and the fourth ohmic contact region 64. Figure 20 The first dielectric layer 21 shown can be substantially similar to the first dielectric layer 21 described above in conjunction with Figures 1A to 1J the first dielectric layer 21, and the related description is omitted for the sake of brevity.

[0239] In Figure 20 the illustrated embodiment, the semiconductor structure 180B can further include a memory cell group 100. The memory cell group 100 has a first end 101 and a second end 102. The memory cell group 100 is electrically coupled to the fourth ohmic contact region 64 from the second end 102 of the memory cell group 100. Figure 20 The memory cell group 100 shown can be substantially similar to the memory cell group 100 described above in conjunction with Figure 1J the memory cell group 100, and the related description is omitted for the sake of brevity. In one embodiment, the memory cell group 100 can include a magnetic tunnel junction (MTJ) structure, or a phase change material, or a resistive random access memory (RRAM) material. Figure 20 The semiconductor structure 180B shown can be a phase change random access memory (PcRAM) device or a resistive random access memory (RRAM) device. Although Figure 20 only one memory cell is illustrated, multiple memory cells or a memory cell array can be fabricated simultaneously using the methods disclosed herein.

[0240] The foregoing description of the embodiments has been provided to enable those skilled in the art to make and use the subject matter. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the novel principles and subject matter disclosed herein can be applied to other embodiments without the need for creative effort. The claimed subject matter set forth in the claims is not intended to be limited to the embodiments shown herein, but rather should be accorded the widest scope consistent with the principles and novel features disclosed herein. Additional embodiments are envisioned within the spirit and true scope of the disclosed subject matter. Accordingly, it is intended that the invention cover modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor structure, comprising: A first doped region; A second doped region, the second doped region being on and in contact with the first doped region; A first ohmic contact region, the first ohmic contact region being in contact with the bottom surface of the first doped region; A second ohmic contact region, the second ohmic contact region being in contact with the top surface of the second doped region; And A first dielectric structure, the first dielectric structure surrounding each of the first doped region, the second doped region, the first ohmic contact region, and the second ohmic contact region; Wherein, the first doped region is doped with a dopant of a first conductivity type, and the second doped region is doped with a dopant of a second conductivity type opposite to the first conductivity type, such that a p-n junction is formed between the first doped region and the second doped region; and wherein, an ohmic junction is formed between the first doped region and the first ohmic contact region, and an ohmic junction is formed between the second doped region and the second ohmic contact region.

2. The semiconductor structure according to claim 1, wherein, The first doped region includes a first heavily doped region extending from the bottom surface of the first doped region; and the first heavily doped region is doped with the dopant of the first conductivity type.

3. The semiconductor structure according to claim 1, wherein, The second doped region includes a second heavily doped region extending from the top surface of the second doped region; and the second heavily doped region is doped with the dopant of the second conductivity type.

4. The semiconductor structure according to claim 1, wherein, Each of the first doped region and the second doped region includes a single crystal semiconductor material.

5. The semiconductor structure as claimed in claim 1, wherein, The sidewalls of the first doped region and the sidewalls of the second doped region are aligned in the vertical direction.

6. The semiconductor structure according to claim 1, further comprising a memory cell group having a first end and a second end, wherein, The memory cell group is electrically coupled to the first ohmic contact region from the second end of the memory cell group.

7. The semiconductor structure as claimed in claim 6, wherein, The memory cell group includes a magnetic tunnel junction (MTJ) structure, or a phase change material, or a resistive random access memory material.

8. A method for manufacturing a semiconductor structure, comprising: (a) Providing a semiconductor substrate, the semiconductor substrate including a first substrate and a second substrate on the first substrate; (b) Forming a first ohmic contact region on a first surface of the second substrate or in the second substrate; (c) Patterning the second substrate to define a first doped region; (d) Adding a third substrate to the first surface of the second substrate, wherein the second substrate is between the third substrate and the first substrate; (e) Removing the first substrate and exposing a second surface of the second substrate opposite to the first surface; (f) Exposing a second doped region in the second substrate or on the second surface of the second substrate or forming the second doped region in the second substrate or on the second surface of the second substrate; (g) Forming a second ohmic contact region on the second surface of the second substrate or in the second substrate.

9. The method according to claim 8, wherein The second substrate is doped with a dopant of a first conductivity type.

10. The method according to claim 8, wherein, The second doped region is doped with a dopant of a second conductivity type opposite to the first conductivity type.

11. The method according to claim 8, wherein, The semiconductor substrate further includes a bonding layer between the first substrate and the second substrate; and step (e) further includes removing the bonding layer.

12. The method according to claim 11, wherein, The semiconductor substrate further includes an etch stop layer between the second substrate and the bonding layer; and step (e) further includes removing at least a portion of the etch stop layer.

13. The method according to claim 8, wherein, The semiconductor substrate further includes an etch stop layer between the first substrate and the second substrate; and step (e) further includes removing at least a portion of the etch stop layer.

14. The method according to claim 8, wherein, Step (b) further includes forming a first heavily doped region.

15. The method according to claim 8, wherein, The second doped region includes a second heavily doped region.

16. The method according to claim 8, further comprising: (h) Forming a memory cell group after step (f), wherein the memory cell group is electrically coupled to the second ohmic contact region.

17. The method according to claim 8, wherein, The second substrate includes a single crystal semiconductor material.

18. The method according to claim 8, further comprising: Depositing a first dielectric structure around the first doped region before step (d).

19. A semiconductor structure, comprising: A first diode, the first diode including a first doped region and a second doped region on and in contact with the first doped region; And A second diode, the second diode including a third doped region and a fourth doped region on and in contact with the third doped region; Wherein each of the first doped region and the fourth doped region is doped with a dopant of a first conductivity type, and each of the second doped region and the third doped region is doped with a second conductivity type opposite to the first conductivity type; and The top surface of the second doped region is higher than the bottom surface of the third doped region, and the top surface of the fourth doped region is higher than the bottom surface of the first doped region.

20. The semiconductor structure according to claim 19, wherein, The bottom surface of the first doped region is substantially flush with the bottom surface of the third doped region.

21. The semiconductor structure according to claim 19, wherein, The top surface of the second doped region is substantially flush with the top surface of the fourth doped region.

22. The semiconductor structure according to claim 19, wherein, The first diode further includes a first ohmic contact region in contact with the bottom surface of the first doped region, and the second diode further includes a fourth ohmic contact region in contact with the top surface of the fourth doped region.

23. The semiconductor structure according to claim 19, wherein, The first diode further includes a second ohmic contact region in contact with the top surface of the second doped region, and the second diode further includes a third ohmic contact region in contact with the bottom surface of the third doped region.

24. The semiconductor structure according to claim 19, wherein, The first doped region includes a first heavily doped region extending from the bottom surface of the first doped region, and the fourth doped region includes a fourth heavily doped region extending from the top surface of the fourth doped region; each of the first heavily doped region and the fourth heavily doped region is doped with the dopant of the first conductivity type.

25. The semiconductor structure as described in claim 19, wherein, The second doped region includes a second heavily doped region extending from a top surface of the second doped region, and the third doped region includes a third heavily doped region extending from a bottom surface of the third doped region; each of the second heavily doped region and the third heavily doped region is doped with a dopant of the second conductivity type.

26. The semiconductor structure as described in claim 19, further comprising a first dielectric structure, wherein, Each of the first diode and the second diode is surrounded by the first dielectric structure.

27. The semiconductor structure according to claim 19, wherein, Each of the first doped region and the fourth doped region includes a single crystal semiconductor material.

28. The semiconductor structure as described in claim 19, wherein, Each of the second doped region and the third doped region includes a single crystal semiconductor material.

29. The semiconductor structure according to claim 19, wherein, Sidewalls of the first doped region and the second doped region of the first diode are aligned in a vertical direction, and sidewalls of the third doped region and the fourth doped region of the second diode are aligned in a vertical direction.

30. The semiconductor structure as described in claim 19 further includes a memory cell group, the memory cell group having a first end and a second end, wherein, The memory cell group is electrically coupled to the first diode and the second diode simultaneously from a second end of the memory cell group.

31. The semiconductor structure according to claim 30, wherein, The memory cell group is electrically coupled to the second doped region of the first diode and the fourth doped region of the second diode simultaneously.

32. The semiconductor structure as described in claim 30, wherein, The memory cell group includes a magnetic tunnel junction (MTJ) structure, or a phase change material, or a resistive random access memory material.

33. A method for manufacturing a semiconductor structure, comprising: (a) providing a semiconductor substrate including a first substrate and a second substrate on the first substrate; (b) forming a third doped region of a second diode in the second substrate or on a first surface of the second substrate; (c) patterning the second substrate to define a first doped region of a first diode and a fourth doped region of the second diode; (d) adding a third substrate to the first surface of the second substrate, wherein the second substrate is between the third substrate and the first substrate; (e) removing the first substrate and exposing a second surface of the second substrate opposite to the first surface; (f) exposing a second doped region of the first diode in the second substrate or on the second surface of the second substrate or forming the second doped region in the second substrate or on the second surface of the second substrate.

34. The method according to claim 33, wherein, The second substrate is doped with a dopant of a first conductivity type.

35. The method according to claim 34, wherein, Each of the second doped region and the third doped region is doped with a dopant of a second conductivity type opposite to the first conductivity type.

36. The method according to claim 33, wherein, The semiconductor substrate further includes a bonding layer between the first substrate and the second substrate; and the step (e) further includes removing the bonding layer.

37. The method according to claim 36, wherein, The semiconductor substrate further includes an etch stop layer between the second substrate and the bonding layer; and the step (e) further includes removing at least a portion of the etch stop layer.

38. The method according to claim 33, wherein The semiconductor substrate further includes an etch stop layer between the first substrate and the second substrate; and the step (e) further includes removing at least a portion of the etch stop layer.

39. The method according to claim 33, wherein, Step (b) further includes forming a first ohmic contact region of the first diode and a third ohmic contact region of the second diode on a first surface of the second substrate or in the second substrate.

40. The method according to claim 33, wherein, Step (f) further includes forming a second ohmic contact region of the first diode and a fourth ohmic contact region of the second diode on a second surface of the second substrate or in the second substrate.

41. The method according to claim 33, wherein, Step (b) further includes forming a first heavily doped region.

42. The method according to claim 33, wherein, Step (f) further includes exposing or forming a fourth heavily doped region.

43. The method according to claim 33, wherein, The second doped region includes a second heavily doped region.

44. The method according to claim 33, wherein, The third doped region includes a third heavily doped region.

45. The method according to claim 33, further comprising: (h) Forming a memory cell group before step (d), wherein the memory cell group is electrically coupled to the first diode and the second diode simultaneously.

46. The method according to claim 33, further comprising: (h) Forming a memory cell group after step (f), wherein the memory cell group is electrically coupled to the first diode and the second diode simultaneously.

47. The method according to claim 33, further comprising: After step (c), a conformal etch stop layer is formed on sidewalls of the first doped region, the third doped region, and the fourth doped region.

48. The method according to claim 33, wherein, The second substrate includes a single crystal semiconductor material.

49. A memory device, comprising: A memory cell group having a first end and a second end; An electrode that laterally extends in a first direction from a first side of the memory cell group to a second side of the memory cell group, wherein the memory cell group is electrically coupled to the electrode from the second end of the memory cell group; A first diode pair disposed on a first side of the memory cell group; and A second diode pair disposed on a second side of the memory cell group; Wherein each of the first diode pair and the second diode pair includes a first diode and a second diode, each first diode in the first diode pair and the second diode pair includes a first doped region and a second doped region on and in contact with the first doped region, each second diode in the first diode pair and the second diode pair includes a third doped region and a fourth doped region on and in contact with the third doped region, each first doped region of the first diode pair and the second diode pair is doped with a dopant of a first conduction type, each second doped region of the first diode pair and the second diode pair is doped with a dopant of a second conduction type opposite to the first conduction type, each third doped region of the first diode pair and the second diode pair is doped with a dopant of the second conduction type, and each fourth doped region is doped with a dopant of the first conduction type; and Wherein, in each of the first diode pair and the second diode pair, a top surface of the second doped region is higher than a bottom surface of the third doped region, and a top surface of the fourth doped region is higher than a bottom surface of the first doped region; and Each of the first diode and the second diode in the first diode pair is electrically coupled to the electrode at a first side of the memory cell group, and each of the first diode and the second diode in the second diode pair is electrically coupled to the electrode at a second side of the memory cell group.

50. The memory device according to claim 49, wherein, The electrode is disposed between the memory cell group and the first diode pair in a vertical direction.

51. The memory device according to claim 49, wherein, The electrode is disposed between the memory cell group and the second diode pair in a vertical direction.

52. The memory device according to claim 49, wherein, The memory cell group includes a magnetic tunnel junction (MTJ) structure.

53. The memory device according to claim 49, wherein, The memory cell group is electrically coupled to a bit line from a first end of the memory cell group.

54. The memory device as claimed in claim 53, wherein, The bit line extends laterally in a second direction different from the first direction.

55. The memory device according to claim 49, wherein, The first diode and the second diode in the first diode pair are arranged along the first direction.

56. The memory device according to claim 49, wherein, The first diode and the second diode in the second diode pair are arranged along the first direction.

57. The memory device according to claim 49, wherein, Both the first diode and the second diode in the first diode pair are electrically coupled to a first word line, and the first word line extends laterally in a second direction different from the first direction.

58. The memory device according to claim 49, wherein, The first diode in the first diode pair is electrically coupled to a first word line, the second diode in the first diode pair is electrically coupled to a second word line, and both the first word line and the second word line extend laterally in a second direction different from the first direction.

59. The memory device according to claim 49, wherein, The first diode in the second diode pair is electrically coupled to a third word line, the second diode in the second diode pair is electrically coupled to a fourth word line, and both the third word line and the fourth word line extend in the first direction.

60. The memory device according to claim 59, wherein, The memory cell group is disposed between the fourth word line and the electrode in a vertical direction.

61. The memory device according to claim 49, wherein, Both the first diode and the second diode in the second diode pair are electrically coupled to a third word line, and the third word line extends in the first direction.

62. The memory device according to claim 49, wherein, The first diode and the second diode in the first diode pair are arranged laterally in a second direction different from the first direction.

63. The memory device according to claim 49, wherein, The first diode and the second diode in the second diode pair are arranged laterally in a second direction different from the first direction.

64. The memory device according to claim 49, wherein, The memory device has a cell size between approximately 16 feature squares (F 2 ) and approximately 32 feature squares (F 2 ).

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