Digital-to-analog converter circuitry for stimulator devices with non-linear amplitude adjustment

Abstract

The invention discloses a digital-to-analog converter circuitry for a stimulator device with non-linear amplitude adjustment. The DAC circuitry produces an output current whose amplitude varies as a function of the amplitude value provided by the digital amplitude bus. The relationship of the output current to the amplitude (Iout (A)) may be linear or non-linear, depending on the current-voltage characteristics of the circuits in the DAC selected for use. For example, if a resistor is selected, the output current will change linearly with amplitude; if a p-n diode is selected, the output current will exponentially vary with the amplitude. The shape of the Iout (A) affects the resolution of the output current, and the resolution may be made constant, or at least more constant, over the dynamic range of the DAC circuitry according to the selected circuitry. The DAC circuitry is further beneficial in its ability to be programmed with minimum and maximum output currents.

Description

[0001] This application is a divisional application of an application with application number 2021800101621, filing date February 25, 2021, and invention title "Digital-to-Analog Converter Circuit System for a Stimulator Device with Nonlinear Amplitude Adjustment". Technical Field

[0002] This application relates to implantable stimulator devices and, in particular, to current source circuit systems for providing therapeutic current at the electrodes of the device. Background Art

[0003] Implantable nerve stimulator devices are devices that generate electrical stimulation and deliver it to nerves and tissues for the therapy of various biological diseases, such as pacemakers for treating arrhythmias, defibrillators for treating atrial fibrillation, cochlear stimulators for treating deafness, retinal stimulators for treating blindness, muscle stimulators for generating coordinated limb movement, spinal cord stimulators for treating chronic pain, cortical and deep brain stimulators for treating movement and psychological disorders, and other nerve stimulators for treating urinary incontinence, sleep apnea, shoulder subluxation, etc. The following description generally focuses on the use of the present invention in a spinal cord stimulation (SCS) system or a deep brain stimulation (DBS) system. However, the present invention can be applied to any implantable nerve stimulator device system.

[0004] An SCS or DBS system generally includes Figure 1 the implantable pulse generator (IPG) 10 shown in. The IPG 10 includes a biocompatible device housing 12 that houses the circuit system and a battery 14 for providing power for the operation of the IPG. The IPG 10 is coupled to the tissue stimulation electrode 16 via one or more electrode leads forming an electrode array 17. For example, one or more percutaneous leads 15 with annular or open annular electrodes 16 carried on a flexible body 18 can be used. In another example, paddle leads 19 provide electrodes 16 positioned on one of their generally flat surfaces. The lead wires 20 within the leads are coupled to the electrodes 16 and to proximal contacts 21 that can be inserted into a lead connector 22 fixed in a head 23 on the IPG 10, which can include, for example, epoxy resin. Once inserted, the proximal contacts 21 connect to head contacts 24 within the lead connector 22, which in turn are coupled to the stimulation circuit system 28 within the housing 12 via feedthrough pins 25 through a housing feedthrough 26.

[0005] In the illustrated IPG 10, there are 32 electrodes (E1 to E32) separated among four percutaneous leads 15 or incorporated on a single paddle lead 19, and thus the head 23 can include an 8-electrode lead connector 22 in a 2×2 array. However, the type and number of leads, lead connectors, and electrodes in the IPG are application-specific and can thus vary. The conductive housing 12 can also include an electrode (Ec). In SCS applications, the electrode lead(s) are typically implanted in the patient's spine near the dura mater in the spinal cord, while the IPG is typically implanted subcutaneously in the buttock region. In DBS applications, the electrode lead(s) are typically implanted in specific regions of the brain, while the IPG is typically implanted subcutaneously under the clavicle (or collarbone). In other examples of IPGs designed for direct implantation at the site requiring stimulation, the IPG can be leadless, with the electrodes 16 instead appearing on the body of the IPG 10 for contacting the patient's tissue. In other solutions, the lead(s) of the IPG can be integrated with and permanently connected to the IPG 10. The goal of the neuromodulation therapy is to provide electrical stimulation from the electrodes 16 to alleviate the patient's symptoms, such as chronic back pain in SCS applications or tremors in DBS applications.

[0006] The IPG 10 can include an antenna 27a, allowing it to communicate bidirectionally with a plurality of external devices for programming or monitoring the IPG, such as a handheld patient remote or a clinician programmer. See, for example, U.S. Patent Application Publications 2015 / 0360038 and 2015 / 0231402. The illustrated antenna 27a includes a conductive coil within the housing 12, although a coil antenna 27a can also be present in the head 23. When the antenna 27a is configured as a coil, communication with the external device preferably occurs using near-field magnetic induction. The IPG 10 can also include a Radio-Frequency (RF) antenna 27b. In Figure 1 the figure, the RF antenna 27b is shown within the head 23, but it can also be within the housing 12. The RF antenna 27b can include a patch, slot, or wire and can operate as a monopole or dipole. The RF antenna 27b preferably communicates using far-field electromagnetic waves and can operate according to any number of known RF communication standards, such as Bluetooth, Zigbee, MICS, etc. If the battery 14 is rechargeable, the IPG 10 can further include a charging coil (not shown) to wirelessly receive energy from an external charging device.

[0007] Stimulation in the IPG 10 is typically provided by pulses, and each pulse can include multiple phases, as Figure 2Aas shown in the example. The stimulation parameters of the pulses generally include amplitude (current I, although voltage amplitude V can also be used); frequency (F); pulse width (PW) of the pulse or its individual phases; the electrodes 16 selected to provide the stimulation; and the polarities of these selected electrodes, i.e., whether they act as anodes supplying current to the tissue or cathodes absorbing current from the tissue. Together with other possible stimulation parameters that may be employed, these stimulation parameters comprise a stimulation program, and the stimulation circuitry 28 in the IPG 10 can execute the stimulation program to provide therapeutic stimulation to the patient.

[0008] In Figure 2A the example, electrode E4 has been selected as the anode (during its first phase 30a), and thus provides a pulse supplying a positive current of amplitude +I to the tissue. Electrode E5 has been selected as the cathode (again during the first phase 30a), and thus provides a corresponding negative current of amplitude -I that absorbs from the tissue. This is an example of bipolar stimulation, where only two lead-based electrodes are used to provide stimulation to the tissue (one anode, one cathode). However, more than one electrode can be selected to act as the anode at a given time, and more than one electrode can be selected to act as the cathode at a given time. In the case of a so-called monopolar scenario, the case electrode Ec(12) can also be selected as an electrode or current return.

[0009] As mentioned above, the IPG 10 includes stimulation circuitry 28 to form the prescribed stimulation at the tissue of the patient. Figure 3A An example of the stimulation circuitry 28 is shown, which includes a digital-to-analog converter (DAC) that provides an analog current at the electrodes according to the specified amplitude, as further explained below. The depicted stimulation circuitry 28 includes a plurality of current source circuits (PDAC) and a plurality of current sink circuits (NDAC), so named according to the positive (supplied, anode) current and negative (sunk, cathode) current they respectively emit. In the example shown, the NDACi / PDACi pairs are dedicated to (hardwired to) specific electrode nodes ei, and for reasons explained below, each of the electrode nodes ei is connected to one of the electrodes Ei 16 via a DC blocking capacitor Ci 38. The stimulation circuitry 28 in this example also supports selecting the conductive case 12 as an electrode (Ec 12), which is typically selected for monopolar stimulation. Although it is assumed in the present disclosure that the PDAC and NDAC include current sources capable of providing a prescribed constant current, they can also include voltage sources capable of providing a prescribed constant voltage.

[0010] The power for the stimulation circuitry 28 is provided by the compliance voltage VH. As described in further detail in U.S. Patent Application Publication 2013 / 0289665, the compliance voltage VH can be generated by a compliance voltage generator 29, which can include circuitry for boosting the voltage of the battery 14 (Vbat) to the voltage VH sufficient to drive a prescribed current I through the tissue R. The compliance voltage generator 29 can include an inductor-based boost converter or can include a capacitor-based charge pump, as explained, for example, in U.S. Patent Application Publication 2018 / 0071512. Since the resistance of the tissue is variable, VH can also be variable and can be up to 18 volts in one example. Although not shown, U.S. Patent Application Publication 2018 / 0071520 explains that the PDAC and NDAC can be powered by different power domains. For example, a first power domain can be used to power the PDAC, the first power domain including VH as the high power and VH - Vcc as the low power (both of which can vary since VH can vary). The NDAC can be powered using a second power domain, the second power domain including Vcc as the high power and ground (GND) as the low power.

[0011] Proper control of the stimulation circuitry 28 allows any of the electrodes 16 to act as an anode or a cathode to produce a current through the patient's tissue R, desirably with a good therapeutic effect. The magnitude of the current provided by each NDACi is via the digital magnitude bus <ani>Control so as to allow its associated electrode Ei to act as a cathode to absorb a current of a specified magnitude from the tissue. Similarly, the magnitude of the current provided by each PDACi is via a digital magnitude bus <api>Control is thus enabled such that its associated electrode Ei acts as an anode to supply a current of a specified magnitude to the tissue.

[0012] Digital magnitude bus <ani>and <api>And other digital control signals for the DAC can be issued by the digital control circuitry 40 in the IPG 10. The digital control circuitry 40 can include a microcontroller, such as part number MSP430 manufactured by Texas Instruments, which is described in the data sheet at http: / / www.ti.com / lsds / ti / microcontroller / 16-bit_msp430 / overview.page?DCMP=MCU_other&HQS=msp430. More generally, the control circuitry 40 can include a microprocessor, a field programmable gate array, a programmable logic device, a digital signal processor, or similar device, and can include a central processing unit capable of executing instructions, where the instructions are stored in volatile or non-volatile memory within or associated with the control circuitry. The digital control circuitry 40 can be separate from the stimulation circuitry 28; for example, each can be formed in its own integrated circuit. Alternatively, the digital control circuitry 40 and the stimulation circuitry 28 can also be integrated on the same integrated circuit, such as an application specific integrated circuit (ASIC). Various examples of the digital control circuitry 40 and the stimulation circuitry 28, and how they are connected or integrated, are provided in U.S. Patent Application Publications 2008 / 0319497, 2012 / 0095529, 2018 / 0071513, 2018 / 0071520, or 2019 / 0083796.

[0013] Figure 3A Illustrates the programming of the stimulation circuitry 28 necessary for the first phase 30a of creating Figure 2A where electrodes E4 and E5 are selected as the anode and cathode, respectively, to create a current of magnitude I through the tissue. In this example, the digital magnitude bus serving the PDAC4 <ap4>is set to have an amplitude value X corresponding to the desired current amplitude I, the bus serving NDAC5 <an5>The same applies. These buses will be asserted at specific times to generate the desired current I with the correct timing (e.g., according to the specified frequency F and pulse width PWa). During the second phase 30b (PWb), PDAC5 and NDAC4 will be via the digital amplitude bus <ap5>and <an4>are similarly programmed to reverse the polarity of the current, which is useful during the generation of the biphasic pulses discussed further below. Other digital amplitude buses for programming the PDACs and NDACs associated with other inactive electrodes (e.g., associated with PDAC1 and NDAC1 at electrode E1) <ap1>And <an1>) will be set to zero, or these PDACs or NDACs can be deactivated by other means. By appropriate control of the DAC, more than one anode and more than one cathode can be selected at a time, and thus current can flow through the tissue R between two or more of the electrodes 16.

[0014] Figure 3A Also shown is a DC blocking capacitor Ci 38 in the electrode current path placed in series between each of the electrode nodes ei 39 and the electrode Ei 16 (including the case electrode Ec 12). The DC blocking capacitor 38 serves as a safety measure to prevent DC current from being injected into the patient's body, such as would occur if there were a circuit fault in the stimulation circuitry 28.

[0015] Although not shown, the circuitry in the IPG 10 including the stimulation circuitry 28 may also be included in an external test stimulator (ETS) device for simulating the operation of the IPG during a test period and prior to implantation of the IPG 10. The ETS is typically used after the electrode array 17 has been implanted in the patient. The proximal ends of the leads in the electrode array 17 pass through an incision in the patient's body and are connected to the externally worn ETS, thereby allowing the ETS to provide stimulation to the patient during the test period. Similar to the IPG 10, the ETS may include various antennas for communicating with external devices. Additional details regarding the ETS device are described in USP9,259,574 and U.S. Patent Application Publication 2019 / 0175915.

[0016] Referring again to Figure 2A , the shown stimulation pulses are biphasic, where each pulse at each electrode includes a first phase 30a, followed by a second phase 30b of opposite polarity. Biphasic pulses are useful for actively recovering any charge that may be stored in capacitive elements (such as the DC blocking capacitor 38) in the electrode current path, at the electrode / tissue interface, or within the tissue itself. To recover all charge at the end of the second pulse phase 30b of each pulse (Vc4 = Vc5 = 0V), the first and second phases 30a and 30b are preferably charge balanced at each electrode, where these phases include equal amounts of charge but opposite polarities. In the example shown, this charge balance is achieved by using the same pulse width (PWa = PWb) and the same amplitude (|+I| = |-I|) for each of the pulse phases 30a and 30b. However, as is known, the pulse phases 30a and 30b can also be charge balanced if the product of the amplitude and pulse width of the two phases 30a and 30b is equal.

[0017] Figure 3A It is shown that the stimulation circuitry 28 may include a passive recovery switch 41 i , which is further described in U.S. Patent Application Publications 2018 / 0071527 and 2018 / 0140831. The passive recovery switch 41 i can be attached to each of the electrode nodes 39 and is used to passively recover any remaining charge, such as the charge that may remain on the DC-blocking capacitor Ci 38 after the second pulse phase 30b. Passive charge recovery occurs without using the DAC circuitry to actively drive current and can be prudent because non-idealities in the stimulation circuitry 28 may result in active charge recovery that is not perfectly charge-balanced. By closing the passive recovery switch 41 that is connected to the electrode node 39 at one end i , passive charge recovery typically occurs during phase 30c( Figure 2A ), which can include a portion of the silent period between pulses. The other end of the switch 41 i is connected to a common reference voltage, which in this example includes the voltage Vbat of the battery 14, although another reference voltage can be used. As explained in the references cited above, by shunting the capacitor between the reference voltage (Vbat) and the patient's tissue, passive charge recovery tends to balance the charge on the DC-blocking capacitor 38 and other capacitive elements in the output current path. Note that in Figure 2A , during 30c, passive charge recovery is illustrated as a small exponential decay curve, which can be positive or negative depending on whether the pulse phase 30a or 30b imparted charge dominance at a given electrode. Although not shown, the control of the passive recovery switch can be via a signal output by the digital control circuitry 40.

[0018] Other designs of the stimulation circuitry 28 can be used in the IPG 10, and Figure 3A is just one example. In another example shown in Figure 3B , the PDAC and NDAC may not be dedicated to working with a specific electrode. Instead, a switch matrix (SM Pi) can be interposed between each PDACi and the electrode node ei 39, and a switch matrix (SM Ni) can be interposed between each NDACi and the electrode node ei 39. Each switch matrix can be controlled by a digital switch bus (e.g., <sp1> 、 <sn1>etc.) to control the electrode nodes (e.g., PDAC1, NDAC1, etc.) to which the output of its associated DAC should be connected. Depending on the design, and different from what is shown in Figure 3B The stimulation circuitry 28 may include only one PDAC (and one switch matrix SMP) and one NDAC (and one switch matrix SMN), different from what is shown in Figure 3B However, providing more than one PDAC and more than one NDAC (e.g., as shown by each being "x" in Figure 3B allows for the formation of more complex stimulations, such as stimulations that require simultaneous control of current at more than one anode or cathode, or stimulations formed in different time channels. In the example of <ap1> 、 <an1>etc.) and digital switch buses for each switch matrix (e.g., <sp1> 、 <sn1>etc.). Other variations of the stimulation circuitry 28 are possible and different options are disclosed in USP 6,181,969, 8,606,362, 8,620,436 and U.S. Patent Application Publications 2018 / 0071520 and 2019 / 0083796.

[0019] Figure 4 An example circuitry for a given NDAC and PDAC (such as Figure 3A and 3B those used in) is shown, although as explained in the references just cited, the PDAC and NDAC can also be constructed differently. The magnitude of the current output by the NDAC as described above is controlled by the digital magnitude bus <An[8:1]>, which in this example includes eight digital control signals An[8] to An[1] capable of representing 256 different magnitude values. Each of these digital control signals is input to a selection transistor 56n, and each of the selection transistors is serially connected to a different number of transistors 54n connected in parallel. A reference current Iref is generated by a generator 50n and is supplied to a transistor 52n, which mirrors its current to each of the transistors 54n. (This current mirroring occurs because, as is well known, the gates of the transistor 52n and the transistors 54n are connected to the drain of the transistor 52n).

[0020] The number of parallel transistors 54n varies in binary such that An[1] controls the connection of one transistor 54n to provide Iref; An[2] controls the connection of two transistors 54n to provide 2*Iref together; An[3] controls the connection of four transistors 54n to provide 4*Iref together, and so on, while [8] controls the connection of 128 transistors 54n to provide 128*Iref together. Since the selection transistor 56n is an N-channel transistor in this example, the digital control signal An[i] is preferably active high. Thus, for example, if the digital magnitude bus <An[8:1]> = '00110101', i.e., the number 53 in binary form, the control signals An[6], An[5], An[3], and An[1] are asserted to close their associated selection transistors 56n. These control signals respectively cause 32*Iref, 16*Iref, 4*Iref, and Iref to be absorbed into the NDAC (e.g., from the associated electrode node of the NDAC ( Figure 3A ) or absorbed into the associated switch matrix of the NDAC ( Figure 3B )) for a total of 53 * Iref. If we assume Iref = 0.1 mA, the absorbed current Iout will be equal to 5.3 mA. In short, by asserting various digital control signals in the digital magnitude bus <An[8:1]>, the output current Iout in the dynamic range from Iref = 0.0 mA ('00000000') to 255 * Iref = 25.5 mA ('1111111') can be absorbed into the NDAC in increments of Iref = 0.1 mA. Iref can of course include an amplitude different from 0.1 mA, and the amplitude An can include a different number of increments from 256.

[0021] The PDAC is largely similar in construction to the NDAC, although it operates to supply current. Again, the select transistor 56p is controlled by the digital magnitude bus <Ap[8:1]>, where each transistor 56p controls the current from a different number of parallel transistors 54p. The Iref generated by the generator 50p is mirrored by the transistor 52p to the transistor 54p. Since the select transistor 56p is a P-channel transistor, the digital control signal Ap[i] is preferably active low. Thus, for example, if the digital magnitude bus <Ap[8:1]> = '11001010', which is the two's complement of 53 in binary form, the control signals Ap[6], Ap[5], Ap[3], and An[1] are asserted to close their associated select transistors 56p, which respectively cause 32 * Iref, 16 * Iref, 4 * Iref, and Iref to be supplied for a total of 53 * Iref. Again assuming Iref = 0.1 mA, the supplied current Iout (e.g., supplied to the electrode node of the PDAC ( Figure 3A )) or the switch matrix ( Figure 3B )) will be equal to 5.3 mA (note that Iref can be fine-tuned at the generators 50p and 50n to ensure proper balance of the currents generated by the PDAC and NDAC). Similarly, by asserting various digital control signals in the digital magnitude bus <Ap[8:1]>, the output current Iout in the dynamic range from Iref = 0.0 mA ('11111111') to 255 * Iref = 25.5 mA ('0000000') can be supplied from the PDAC in 256 increments of Iref = 0.1 mA. SUMMARY OF THE INVENTION

[0022] A stimulator device is disclosed, which may include: a plurality of electrode nodes, each electrode node being configured to be coupled to a corresponding electrode configured to contact a patient's tissue; and a digital-to-analog converter (DAC) circuitry, the digital-to-analog converter circuitry being controllable by a digital amplitude bus configured to specify a plurality of amplitude values, wherein the DAC circuitry is configured to set an amplitude of an output current at at least one of the electrode nodes according to the amplitude value carried by the digital amplitude bus, wherein the amplitude of the output current increases non-linearly as the amplitude value increments through the plurality of amplitude values.

[0023] In one example, as the amplitude value increases through a plurality of amplitude values, the amplitude of the output current varies parabolically. In one example, the DAC circuit system includes at least one MOS diode having a current-voltage characteristic that is parabolic. In one example, as the amplitude value increases through a plurality of amplitude values, the amplitude of the output current varies exponentially. In one example, the DAC circuit system includes at least one p-n diode having a current-voltage characteristic that is exponential. In one example, as the amplitude value increases through a plurality of amplitude values, the resolution of the output current is constant. In one example, the resolution includes the percentage change in the amplitude of the output current as the amplitude value increases. In one example, the DAC circuit system is also controlled by at least one function selection signal, where the at least one function selection signal sets a relationship that specifies how the amplitude of the output increases as the amplitude value increases through a plurality of amplitude values. In one example, the at least one function selection signal causes the amplitude of the output to either (i) increase parabolically as the amplitude value increases through a plurality of amplitude values, or (ii) increase exponentially as the amplitude value increases through a plurality of amplitude values. In one example, the DAC circuit system includes an input stage configured to receive a digital amplitude bus and generate a third voltage; and an output stage configured to receive the third voltage and generate an output current. In one example, the third voltage varies linearly with the amplitude value. In one example, the third voltage is applied to a third circuit in the output stage having a non-linear current-voltage characteristic, where the output current is formed through the third circuit according to the non-linear current-voltage characteristic. In one example, the third circuit is selectable. In one example, the input stage includes a first bias stage configured to generate a first voltage that varies with a first current. In one example, the first current is programmable to set the maximum amplitude of the output current. In one example, the first bias stage includes a first circuit configured to receive the first current, where the first voltage is generated according to the non-linear current-voltage characteristic of the first circuit. In one example, the first circuit is selectable. In one example, the non-linear current-voltage characteristic of the first circuit is the same as the non-linear current-voltage characteristic of the third circuit. In one example, the third voltage is generated as a function of the first voltage. In one example, the input stage includes a first bias stage configured to generate a first voltage that varies with a first current, and a second bias stage configured to generate a second voltage that varies with a second current. In one example, the first current is programmable to set the maximum amplitude of the output current, and where the second current is programmable to set the minimum amplitude of the output current. In one example, the first bias stage includes a first circuit configured to receive the first current, where the first voltage is generated according to the non-linear current-voltage characteristic of the first circuit, where the second bias stage includes a second circuit configured to receive the second current, where the second voltage is generated according to the non-linear current-voltage characteristic of the second circuit. In one example, the first and second circuits are selectable.In one example, the non-linear current-voltage characteristics of the first, second, and third circuits are the same. In one example, the third voltage is generated as a function of the first and second voltages. In one example, the third voltage is equal to or between the first and second voltages.

[0024] A stimulator device is disclosed that may include: a plurality of electrode nodes, each electrode node configured to be coupled to a corresponding electrode configured to contact a patient's tissue; and a digital-to-analog converter (DAC) circuitry controllable by a digital amplitude bus configured to specify a plurality of amplitude values, wherein the DAC circuitry is configured to set the amplitude of an output current at at least one of the electrode nodes according to the amplitude value carried by the digital amplitude bus, wherein the DAC circuitry is further controlled by at least one function selection signal, wherein the at least one function selection signal is configured to set a relationship that specifies how the amplitude of the output current varies as the amplitude value increases through the plurality of amplitude values.

[0025] In one example, at least one function selection signal is configured to set the amplitude of the output current to vary parabolically as the amplitude value increases through a plurality of amplitude values. In one example, at least one function selection signal is configured to select at least one MOS diode having a current-voltage characteristic that is parabolic. In one example, at least one function selection signal is configured to set the amplitude of the output current to vary exponentially as the amplitude value increases through a plurality of amplitude values. In one example, at least one function selection signal is configured to select at least one p-n diode having an exponential current-voltage characteristic. In one example, at least one function selection signal is configured to set the amplitude of the output current to vary linearly as the amplitude value increases through a plurality of amplitude values. In one example, at least one function selection signal is configured to select at least one resistor having a linear current-voltage characteristic. In one example, at least one function selection signal is configured to set the amplitude of the output to increase (i) linearly, (ii) parabolically, or (iii) exponentially as the amplitude value increases through a plurality of amplitude values. In one example, a DAC circuit system includes an input stage configured to receive a digital amplitude bus and generate a third voltage; and an output stage configured to receive the third voltage and generate an output current. In one example, the third voltage varies linearly with the amplitude value. In one example, the third voltage is applied to one of a plurality of third circuits in the output stage selected according to at least one function selection signal, wherein each of the third circuits has a different current-voltage characteristic. In one example, the output current is formed through the selected third circuit according to the current-voltage characteristic of the selected third circuit. In one example, the input stage includes a first bias stage configured to generate a first voltage that varies with a first current, wherein the third voltage varies with the first voltage. In one example, the first current is programmable to set the maximum amplitude of the output current. In one example, the first bias stage includes a plurality of first circuits each having a different current-voltage characteristic. In one example, the first voltage is generated on one of the first circuits according to at least one function selection signal. In one example, the first voltage is generated according to the current-voltage characteristic of the selected first circuit. In one example, the input stage includes a first bias stage configured to generate a first voltage that varies with a first current, and a second bias stage configured to generate a second voltage that varies with a second current, wherein the third voltage varies with the first voltage. In one example, the first current is programmable to set the maximum amplitude of the output current, and wherein the second current is programmable to set the minimum amplitude of the output current. In one example, the first bias stage includes a plurality of first circuits each having a different current-voltage characteristic, and wherein the second bias stage includes a plurality of second circuits each having a different current-voltage characteristic.In one example, a first voltage is generated on a selected one of the first circuits based on at least one function selection signal, and wherein a second voltage is generated on a selected one of the second circuits based on at least one function selection signal. In one example, the first voltage is generated based on the current-voltage characteristic of the selected first circuit, and wherein the second voltage is generated based on the current-voltage characteristic of the selected second circuit. In one example, a third voltage is generated as a function of the first and second voltages. In one example, the third voltage is equal to or between the first and second voltages.

[0026] A stimulator device is disclosed that may include: a plurality of electrode nodes, each electrode node configured to be coupled to a corresponding electrode configured to contact a patient's tissue; and a digital-to-analog converter (DAC) circuitry controllable by a digital amplitude bus configured to specify a plurality of amplitude values, wherein the DAC circuitry is configured to set the amplitude of an output current that affects the electrode current at at least one of the electrode nodes, wherein the output current is equal to a maximum amplitude and a minimum amplitude or ranges between the maximum amplitude and the minimum amplitude according to the amplitude value carried by the digital amplitude bus, and wherein the DAC circuitry is further programmable to set the maximum amplitude and the minimum amplitude.

[0027] In one example, the DAC circuit system is configured to provide an output current as an electrode current at at least one of the electrode nodes. In one example, the DAC circuit system includes an amplification stage configured to amplify the output current to an electrode current. In one example, the DAC circuit system can be programmed by a first bus to set a maximum magnitude of the output current, and wherein the DAC circuit system can be programmed by a second bus to set a minimum magnitude of the output current. In one example, the DAC circuit system includes: in one example, an input stage configured to receive a digital magnitude bus and generate a third voltage, and an output stage configured to receive the third voltage and generate an output current. In one example, the third voltage varies linearly with the magnitude value. In one example, the third voltage is applied to a third circuit in the output stage, wherein the third circuit includes a current-voltage characteristic. In one example, the output current is formed by the third circuit according to the current-voltage characteristic of the third circuit. In one example, the third circuit is selectable. In one example, the input stage includes a first bias stage configured to generate a first current according to the set maximum magnitude, and a second bias stage configured to generate a second current according to the set minimum magnitude. In one example, the first bias stage is configured to generate a first voltage that varies with the first current, and wherein the second bias stage is configured to generate a second voltage that varies with the second current. In one example, the first bias stage includes a first circuit configured to receive the first current, wherein the first voltage is generated according to the current-voltage characteristic of the first circuit, and wherein the second bias stage includes a second circuit configured to receive the second current, wherein the second voltage is generated according to the current-voltage characteristic of the second circuit. In one example, the first and second circuits are selectable. In one example, the third voltage is generated as a function of the first and second voltages. In one example, the third voltage is equal to the first and second voltages or between the first and second voltages. In one example, the third voltage varies linearly with the magnitude value.

[0028] A stimulator device is disclosed that can include: a plurality of electrode nodes, each electrode node configured to be coupled to a corresponding electrode configured to contact patient tissue; and a digital-to-analog converter (DAC) circuit system configured to provide stimulation to at least one of the plurality of electrode nodes, including: a first bias stage configured to generate a first voltage that varies with a first current; a resistor block configured to receive the first voltage and a second voltage, wherein the resistor block can be controlled by a digital magnitude bus to generate a third voltage equal to or between the first and second voltages according to a magnitude value carried by the digital magnitude bus; and an output stage configured to receive the third voltage and generate an output current that varies with the third voltage.

[0029] In one example, the first current is programmable. In one example, the second voltage is grounded. In one example, the amplitude value is set equal to the amplitude of the output current that is zero and the first current zero or ranges between zero and the first current. In one example, the output current varies linearly with the amplitude value. In one example, the output current varies parabolically with the amplitude value. In one example, the output current varies exponentially with the amplitude value. In one example, the first bias stage includes a first circuit configured to receive the first current, wherein a first voltage is generated according to the current-voltage characteristic of the first circuit. In one example, the output stage includes a third circuit having the same current-voltage characteristic as the first circuit, wherein the third circuit receives a third voltage to generate an output current according to its current-voltage characteristic. In one example, the first bias stage includes a plurality of first circuits selectively configurable to receive the first current and generate the first voltage, wherein the current-voltage characteristics of the plurality of first circuits are different from each other, and wherein the first voltage is generated according to the current-voltage characteristic of the selected first circuit. In one example, the output stage includes a plurality of selectable third circuits, wherein the current-voltage characteristics of the plurality of third circuits are different from each other, and wherein the selected third circuit receives a third voltage to generate an output current according to its current-voltage characteristic. In one example, the DAC circuit further includes a second bias stage configured to generate a second voltage, wherein the second voltage varies with a second current. In one example, the first and second currents are programmable. In one example, the amplitude value is set equal to the amplitude of the output current that is the second current and the first current or ranges between the second current and the first current. In one example, the output current varies linearly with the amplitude value. In one example, the output current varies parabolically with the amplitude value. In one example, the output current varies exponentially with the amplitude value. In one example, the first bias stage includes a first circuit configured to receive the first current, wherein a first voltage is generated according to the current-voltage characteristic of the first circuit, and wherein the second bias stage includes a second circuit configured to receive the second current, wherein a second voltage is generated according to the current-voltage characteristic of the second circuit. In one example, the output stage includes a third circuit having the same current-voltage characteristic as the first and second circuits, wherein the third circuit receives a third voltage to generate an output current according to its current-voltage characteristic. In one example, the first bias stage includes a plurality of first circuits selectively configurable to receive the first current and generate the first voltage, wherein the current-voltage characteristics of the plurality of first circuits are different from each other, and wherein the first voltage is generated according to the current-voltage characteristic of the selected first circuit, and wherein the second bias stage includes a plurality of second circuits selectively configurable to receive the second current and generate the second voltage, wherein the current-voltage characteristics of the plurality of second circuits are different from each other, and wherein the second voltage is generated according to the current-voltage characteristic of the selected second circuit.In one example, the output stage includes a plurality of selectable third circuits, wherein the current-voltage characteristics of the plurality of third circuits are different from each other, and wherein the selected third circuit receives a third voltage to generate an output current according to its current-voltage characteristics. In one example, the third voltage varies linearly with the magnitude value between the first and second voltages. In one example, the output current is provided to at least one of the electrode nodes. In one example, the output current is amplified before being presented to at least one of the electrode nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Shows an implantable pulse generator (IPG) according to the prior art.

[0031] Figure 2A and Figure 2B Shows an example of a stimulation pulse that can be generated by an IPG according to the prior art.

[0032] Figure 3A and Figure 3B Shows different examples of a stimulation circuitry including a PDAC and an NDAC that can be used in an IPG according to the prior art.

[0033] Figure 4 Shows that can be used in according to the prior art Figure 3A and Figure 3B circuit details of the PDAC and the NDAC in the stimulation circuitry of.

[0034] Figures 5A to 5C Shows an improved design of an NDAC that can select an output current through a circuit with different I-V characteristics and vary between a maximum and a minimum current according to the magnitude value specified on a digital magnitude bus.

[0035] Figures 6A to 6B Shows how the output current from the NDAC varies as a function of the magnitude value when different circuits are selected. Figure 6C and Figure 6D Show the resulting current increments and resolutions as a function of the magnitude value when different circuits are selected, respectively.

[0036] Figure 7A and Figure 7B Shows an improved design of a PDAC that is structurally and functionally similar to the NDAC.

[0037] Figure 8 Shows a modification in which the outputs of the improved NDAC and PDAC are amplified.

[0038] Figure 9 Shows a modification in which the improved NDAC and PDAC lack a minimum current bias stage.

[0039] Figure 10 Shows a modification in which improved NDAC and PDAC use a single non-selectable circuit to determine how the output current will vary according to the amplitude value.

[0040] Figures 11A to 11C Shows the use of improved NDAC and PDAC to provide an output current between a maximum and a minimum current.

[0041] Figure 12A and Figure 12B Shows an example of a stimulation circuitry in an IPG that uses any one of the previously described improved NDAC and PDAC.

[0042] Figure 13 Shows a graphical user interface that can be reproduced on an external device capable of programming the IPG, where the GUI includes options for programming the improved NDAC and PDAC circuitry. Detailed Description

[0043] The stimulation circuitry as described above is beneficial because it is programmable to provide a current of a specified amplitude and polarity at the electrode. However, the inventors have found certain drawbacks in its digital-to-analog (DAC) circuitry (e.g., Figure 4 ). As previously mentioned, the amplitude Iout of the current provided by the DAC can be incremented in constant units Iref (e.g., 0.1 mA), such that the amplitude (digital amplitude bus <ap>or <an>)For every increase or decrease of 1, the output current increases or decreases by Iref. In other words, the output current varies linearly with the amplitude value, i.e., Iout(An) = Iref * An and Iout(Ap) = Iref * Ap. However, this increment is more significant at the lower end of the current dynamic range that the DAC can produce, and less significant at the higher end of this range.

[0044] This can be undesirable when one considers that the amplitude of the optimal current for providing effective therapy can vary. Sometimes lower currents (e.g., 1 mA) are needed. For example, an SCS patient whose electrode array 17 is relatively close to the spinal cord may require a lower current. Lower currents can also be ensured for different types of stimulation therapies. For example, DBS applications typically require lower currents than SCS applications. Other times, higher currents (e.g., 10 mA) are needed. For example, an SCS patient whose electrode array 17 is relatively far from the spinal cord may require a higher current.

[0045] In these different situations, the need for the DAC circuitry to provide a suitable current amplitude complicates its design. For patients or therapies that require lower currents, a constant current increment of 0.1 mA may be too coarse for adjusting the current. This increment works at a 10% resolution for a lower current amplitude of 1 mA (0.1 mA / 1 mA), such that incrementing the amplitude (i.e., incrementing the digital amplitude bus) will increase the current to 1.1 mA, and decrementing the amplitude will decrease the current to 0.9 mA. When lower currents are needed, this can include too large a change. If a patient requires a lower current, such as 1 mA, a smaller current adjustment may result in a meaningful change to the therapy. Thus, it may alternatively be desirable to adjust the current at a lower resolution, such as 3% (increments of 0.03 mA), such that incrementing the amplitude will increase the current to 1.03 mA, while decrementing the amplitude will decrease the current to 0.97 mA. Providing better resolution at lower currents will allow the clinician (via the clinician programmer) or the patient (via the patient remote control) to more flexibly adjust the current to achieve the appropriate therapy.

[0046] For patients or therapies that require higher currents, a constant current increment of 0.1 mA may be too fine to meaningfully adjust the current. This increment only works at a resolution of 1% for a higher current amplitude of 10 mA (0.1 mA / 10 mA), such that incrementing the amplitude will increase the current to 10.1 mA, and decrementing the amplitude will decrease the current to 9.9 mA. When higher currents are needed, this may represent too small of a change, as this increment may not meaningfully affect the treatment. In such cases, it may be desirable to adjust the current at a higher resolution, such as (again) 3% (increments of 0.3 mA), such that incrementing the amplitude will increase the current more significantly to 10.3 mA, and decrementing the amplitude will decrease the current more significantly to 9.7 mA.

[0047] Thus, designing a DAC circuitry (such as the Figure 4 illustrated DAC circuitry) that can handle stimulation at both lower and higher currents may involve undesirable trade - offs. If the DAC circuitry is designed to provide good resolution (e.g., 3%) for higher currents (e.g., 10 mA), a current increment of 0.3 mA is required. But this will provide an inappropriately high resolution (e.g., 30%) at lower currents (1 mA), as well as too coarse of an adjustment. In contrast, if the DAC circuitry is designed to provide good resolution (e.g., 3%) for lower currents (e.g., 1 mA), a current increment of 0.03 mA is required. This will not only result in an undesirable low resolution (0.3%) at higher currents (e.g., 10 mA), but also complicate the DAC circuitry design. For example, if it is assumed that the DAC circuitry should have a dynamic range of 25.5 mA, a current increment of 0.03 will require the amplitude to be controllable in 850 increments (25.5 mA / 0.03 mA). Considering the binary nature of the PDAC and NDAC ( Figure 4 ), the digital amplitude bus now requires additional signals, such as 10 signals instead of 8 signals, to correctly form the current. (Ten signals provide 2 10 = 1024 different amplitudes, sufficient to handle the required 850). This complicates the DAC design and may result in invalid amplitude bus values (those from 851 to 1024).

[0048] Another disadvantage associated with DAC circuit systems with a constant current increment is that for a given application, it may not be necessary to use its entire dynamic range. For example, assume that it is known that a given SCS patient requires a current on the order of 4 mA to provide effective treatment for their symptoms. It may never be guaranteed that the current amplitude for this patient is below 3 mA or above 5 mA, such that for this patient, the effective range of the DAC circuit system is from 3 mA to 5 mA. In this example, most of the dynamic range of the DAC circuit system (A < 3 mA; 5 < A < 25.5 mA) is effectively wasted on this patient. Further, since the current increment is constant across all amplitude values (e.g., 0.1 mA), the patient can only effectively adjust the current to 21 out of 256 possible amplitude values (e.g., from 3.0 mA to 5.0 mA), which is limiting. It may be desirable to allow the patient to more finely adjust the output current within the effective range that they need.

[0049] In short, the previously described DAC circuit systems may be too inflexible. Instead, it is desirable to provide a DAC circuit system design that can more meaningfully increment and decrement the current based on the amplitude of that current. For example, at lower amplitudes (e.g., 1 mA), the current increment should be lower (e.g., 0.03 mA), while at higher amplitudes (e.g., 10 mA), the current increment should be higher (e.g., 0.3 mA). In short, a design that provides a constant or at least more constant resolution within the dynamic range is desired.

[0050] Further, it is desirable to provide a DAC circuit system design that allows for setting the dynamic range for a particular patient or application while still retaining the ability to finely increment the current across the entire amplitude value range within that range.

[0051] Finally, it is desirable to be able to select different circuits with different current-voltage (I-V) characteristics in the DAC circuit system to control the shape of the output current. This is because, as explained below, within the dynamic range, different I-V characteristics have different effects on the way the output current increments and thus also on the resolution of the current regulation.

[0052] To support these goals, starting from Figure 5A a more flexible DAC circuit system design 100 is disclosed. More specifically, Figure 5A a new NDAC circuit system design is shown that can absorb the output current Iout from the cathode. Figure 7A And Figure 7B changes to the circuit system to form a PDAC 100 that can supply the output current Iout to the anode are described later. The new DAC circuit system design can exist as part of a stimulation circuit system in an IPG or similar device, such as the ETS device described previously.

[0053] As shown, the NDAC circuit system 100 receives a digital amplitude bus <an>and generates an analog output current Iout that is a function of a specified amplitude An carried on the bus. However, as further described below and depending on how the NDAC 100 is programmed, the output current Iout may not necessarily be linearly proportional to the amplitude An. That is, Iout(An) may not increase by a constant current increment (such as Iref) as An increases, and thus Iout may not necessarily be linearly proportional to A, as occurs in the DAC circuitry described in the introduction. Digital amplitude bus <an>Shown as a parallel bus including a plurality of signal lines (e.g., eight signal lines An[8] to An[1]), but may also include a serial bus including a single signal line.

[0054] As Figure 5A The NDAC 100 shown includes an input stage 101 and an output stage 104. The input stage in this example includes two bias stages 102a and 102b. These bias stages 102a / b may be similar in design and are used to set the maximum value (Imax) and minimum value (Imin) of the current to be generated at the output Iout. Each bias stage 102a / b includes a current source 106a / b programmable to generate Imax / Imin. In this regard, the control circuitry 40 of the IPG may issue a digital bus as needed <imax>and <imin>Program the current sources 106a / b to produce Imax and Imin. As with other digital buses, these buses <imax>And <imin>It may include a parallel or serial bus. Note that the current sources 106a / b may include any design of a programmable current source. For example, the current sources 106a / b may be constructed as shown previously Figure 4 or may include other designs such as those disclosed in USP 6,181,969, 8,606,362, 8,620,436 and U.S. Patent Application Publications 2018 / 0071520 and 2019 / 0083796.

[0055] In this example, the maximum and minimum currents Imax and Imin are provided to the current-voltage (I-V) selection blocks 108a and 108b (generally 108i), which are shown in more detail in Figure 5B . The I-V selection block 108i allows different circuits 109i to be selected to receive Imax and Imin generated by the current sources 106a / b. Preferably, each of the different circuits 109i has different current-voltage (I-V) characteristics, and three different circuits 109i are shown in Figure 5B . In this example, the three circuits 109i shown include a single device, although this is just for simplicity. In other examples, the circuits 109i may include one or more devices, i.e., a network of devices, that together provide the desired I-V characteristics.

[0056] The first circuit in the circuit 109L includes a resistor, and the current IL through it is linearly proportional to the voltage across its two ends: IL ~ kV, where k is equal to the conductance (1 / R) of the resistor. The second circuit in the circuit 109S includes a MOS diode, which can be formed by connecting the drain of a MOS transistor to its gate as shown. As is well known, the current IS flowing through this MOS diode is proportional to the square of the voltage across its two ends: IS ~ k(V - Vt) 2 , where k is a constant, and Vt includes the threshold voltage of the MOS transistor. The third circuit in the circuit 109E includes a p-n diode, which in one example can be formed by connecting the collector of a bipolar junction transistor to its base. As is well known, the current IE flowing through this p-n diode is exponentially proportional to the voltage V across its two ends: IE ~ m*e n*V , where m and n are constants.

[0057] By closing switches 111L, 111S, and 111E connected in series with each other, any one of these circuits 109L, 109S, and 109E can be selected for use within the I-V selection block 108i. These switches are controlled by control signals L (linear), S (square), and E (exponential) respectively, and these signals together constitute a function selection signal. These function selection signals are issued by the control circuitry 40, and in the example shown, different function selection signals a, b, and c are used to control the selection of the circuits 109i in the I-V selection block 108a, the I-V selection block 108b, and the third I-V selection block 108c that appears in the output stage 104, which will be discussed later. Preferably, but not necessarily, the control circuitry 40 will select the same circuit 109i in each of the I-V selection blocks 108a, 108b, and 108c. In this regard, and although not shown, the control circuitry 40 can issue only a single set of function control signals (i.e., a single set of L, S, and E control signals), which will be received by each of the I-V selection blocks 108a, 108b, and 108c.

[0058] In the bias stage 102a, Imax is provided to the selected circuit 109i within the I-V selection block 108a, which in turn generates a voltage Vmax that is governed by the I-V characteristics of the selected circuit. For example, if the resistor 109L is selected, Vmax will be equal to Imax * R. If the MOS diode 109S is selected, Vmax will be proportional to SQRT(Imax). If the p-n diode 109E is selected, Vmax will be proportional to ln(Imax). Vmax is provided to the voltage follower 110a to generate a buffered version of Vmax at its output. The bias stage 102b is similar, where Imin is provided to the selected circuit 109i within the I-V selection block 108b, which in turn generates a voltage Vmin that is governed by the I-V characteristics of the selected circuit. Vmin is provided to the voltage follower 110b to generate a buffered version of Vmin at its output.

[0059] The buffered Vmax and Vmin are provided to the resistor block 112 in the input stage 101, which is controlled by the digital amplitude bus An to generate a voltage V(An) that varies with the amplitude value An carried by the bus. An example of the resistor block 112 is shown in more detail in Figure 5C and includes a demultiplexer (demux) 120 and a resistor ladder 122. This example assumes that the digital amplitude bus <an>Includes eight control signals An[8] to An[1], and can thus specify 256 different amplitude values. As Figure 5C shown in the table in, demux120 asserts one of 256 possible X control signals according to the value of An. For example, if An = 0( <an>== '00000000'), then demux 120 asserts signal X0; if An == 1( <an>='00000001'), then the demux asserts signal X1, and so on, where when An = 255( <an>Assert X255 when it equals ‘1111111’

[0060] Except for the case where An = 0 (discussed further below), the asserted X control signal closes the switches 124 in the resistor ladder 122 to set V(An) to be equal to Vmax and Vmin or a value between Vmax and Vmin. In this example, the resistor ladder 122 comprises a series connection of 254 resistors, preferably all having the same value r. Considering the way the switches 124 are connected to the resistors, the voltage V(An) = [(An - 1) / 254]*[Vmax - Vmin] + Vmin. Thus, when An = 1, assert X1, which sets V(An) = Vmin. When An = 255, assert X255, which sets V(An) = Vmax. For other values of An, V(An) scales linearly between Vmin and Vmax.

[0061] It may be desirable to reserve the amplitude at which the specified NDAC 100 should not provide an output (i.e., Iout should equal zero (rather than Imin)). For the case when An = 0 ( <an>In the example depicted when =‘00000000’), this case is retained. In this case, demux 120 asserts signal X0, which controls the switch 126 that connects V(An) to ground. This sets V(An) to zero, which in turn sets Iout to zero, as will be explained later.

[0062] Referring again to Figure 5A , V(An) is provided to the output stage 104 of NDAC 100. Specifically, V(An) is provided to the non-inverting input of the operational amplifier (op amp) 114, and the output of this operational amplifier is provided to the gate of the output transistor 116. The inverting input of op amp 114 is connected to the top of the I-V selection block 108c. Feedback will force the output transistor 116 to conduct to the extent necessary to make the voltage at the input of the op amp the same; thus, V(An) will drop across the I-V selection block 108c. Depending on the I-V characteristics of the circuit 109i ( Figure 5B ) selected in block 108c, this voltage drop V(An) induces the current Iout through the I-V selection block 108c and the output transistor 116.

[0063] Referring to Figure 5A and Figures 6A to 6D explains the operation of NDAC 100 and the relevance of selecting different circuits 109i. In the example shown, it is assumed that Imax is set (via <imax>) is 25.5 mA and Imin is set (via <imin>) is 0.1 mA. As previously mentioned, it is preferred that the circuit 109i selected in each of the I-V selection blocks 108a-c is the same, and Figures 6A to 6D shows an example where a resistor 109L, a MOS diode 109S, and a p-n diode 109E are selected in each block via control signals L, S, and E, respectively.

[0064] When the amplitude value An changes, each of the selectable circuits 109i in the I-V selection block 108i provides a different scaling of the current Iout. In other words, the selected circuit 109i changes the shape of Iout(An).

[0065] For example, the selection of the resistor 109L provides a linear response of Iout as a function of the amplitude An. This is because the V(An) generated by the resistor block 112 will be equal to V(An) = [R(An - 1) / 254]*[Imax - Imin] + R*Imin, where R is equal to the resistance of the resistor 109L. When V(An) is applied across the resistor R in the I-V selection block 108c in the output stage 104, a current Iout = [(An - 1) / 254]*[Imax - Imin] + Imin is generated. In other words, Iout is linearly proportional to the amplitude An, as Figure 6A best shown. Note that the range of Iout is from Imin = 0.1 mA (An = 1) to Imax = 25.5 mA (An = 255), except when An = 0 (which results in V(A) being zero, which sets Iout to zero).

[0066] The selection of the MOS diode 109S provides a quadratic or parabolic response of Iout as a function of the amplitude An. This is because the V(An) generated by the resistor block 112 will be proportional to [(An - 1) / 254]*[SQRT(Imax) - SQRT(Imin)] + SQRT(Imin), as specified by the I-V characteristics of the MOS diode 109S. V(An) is applied across the MOS diode 109S in the I-V selection block 108c in the output stage 104, which results in a current Iout that is generally 2 proportional to An. The mathematics here is more complex and may be further complicated by other secondary effects inherent in the I-V characteristics of the MOS diode (such as considering its threshold voltage). Nevertheless, Iout generally varies 2 proportionally with An, as Figure 6A and Figure 6B shown. Similarly, the range of Iout is from Imin = 0.1 mA (An = 1) to Imax = 25.5 mA (An = 255) (except when An = 0, which sets Iout to zero).

[0067] The selection of the p-n diode 109E provides an exponential response of Iout as a function of the amplitude An. This is because V(An) generated by the resistor block 112 will be proportional to [(An - 1) / 254]*[ln(Imax) - ln(Imin)] + ln(Imin), as specified by the I-V characteristics of the p-n diode 109S. V(An) is applied across the p-n diode 109E in the I-V selection block 108c in the output stage 104, which results in a current Iout that is proportional to Imin*(Imax / Imin)^((An - 1) / 254)). In other words, Iout is exponentially proportional to the amplitude An. Figure 6B This is best illustrated in, which plots the logarithm of Iout versus An. Also, Iout ranges from Imin = 0.1 mA (An = 1) to Imax = 25.5 mA (An = 255) (except when An = 0, which sets Iout to zero).

[0068] Figure 6C Shows the amount by which the output current Iout increases as An is incremented. Mathematically, this plot effectively shows Figure 6A and Figure 6B the derivative d(Iout) / dAn of the curve provided in.

[0069] When the resistor 109L is selected, each increment in the amplitude An provides a constant increment to the output current Iout, which in this example is equal to 0.1 mA. (Note that from a calculus perspective, this makes sense: since Iout varies linearly with A when using a resistor, d(Iout) / dAn should be constant). This response is similar to the stimulation circuit system described previously ( Figure 4 ), which also provides a constant current increment (Iref), and thus provides an output current (Iout = Iref*An) that scales linearly with the amplitude. For a given implementation, this may be okay, but as mentioned previously, a DAC that only allows the output current to be adjusted in constant increments has drawbacks: the increment may be too large to provide good resolution at lower amplitudes of Iout, and too small to provide good resolution at higher amplitudes. This resolution (increment / Iout) is in Figure 6D Quantification is performed in [the text]. It can be seen that when a constant increment is used (resistor 109L is selected), the resulting resolution is inversely proportional to A. For example, when An = 10 (corresponding to Iout = 1 mA), the resolution is 10% (0.1 mA / 1 mA) and is higher at lower An values. When An = 100 (corresponding to Iout = 10 mA), the resolution is 1% (0.1 mA / 10 mA), and is lower at much higher An values. As previously discussed, this resolution may be too high at lower currents, which inhibits the ability to make finer adjustments to the current that may be required for patient treatment. Similarly, at higher currents, the resolution may be too low, resulting in insignificant incremental changes to the current.

[0070] At this point, it may be useful to select the non-linear circuit 109i to shape the output current Iout, as this circuit provides smaller current increments at lower magnitudes of Iout and larger increments at higher magnitudes. This provides a constant or at least more constant resolution within the dynamic range of the NDAC 100.

[0071] For example, Figure 6C shows that when the MOS diode 109S is selected, the increment scales linearly with An. (Again, this makes sense: since Iout is generally proportional to An 2 in a proportional relationship, d(Iout) / dAn should generally vary proportionally with An). At lower current values, the current increment is less than 0.1 mA, and is approximately 0.1 mA in the middle of the dynamic range of the NDAC 100 (at An ~ 127). The increment increases at higher An values, eventually reaching approximately 0.2 mA at Amax = 255. Figure 6D Shows the resolution produced using this non-constant increment, which is generally between 1% and 8% across the entire dynamic range of the NDAC 100. Note that due to secondary effects inherent in the I-V characteristics of the MOS diode, the resolution may not follow a simple trend. However, when using the MOS diode 109S, and when compared to using the resistor 109L, the resolution is more reasonable across the entire dynamic range of the NDAC 100, with smaller resolution at lower currents and higher resolution at higher currents.

[0072] When the p-n diode 109E is selected, the increment varies exponentially with A, as Figure 6C shown. (Again, this makes sense: since Iout varies proportionally with e An in a proportional relationship, d(Iout) / dAn should also vary proportionally with e An in a proportional relationship). Since Iout also varies exponentially with An, the resulting resolution ( Figure 6D ) is constant, about 2.2% in this example. In other words, each incremental magnitude adjustment of the output current increases or decreases Iout by 2.2%. For example, when An = 100, Iout = 1 mA( Figure 6B ), then when An increases to 101, Iout will be equal to 1.022 mA. If Iout = 10 mA when An = 215, then when An increases to 216, Iout will be equal to 10.22 mA, and so on. Note that using non-linear increments in this example solves the problem emphasized previously because the resolution is constant (e.g., 2.2%) across the entire dynamic range of the stimulation circuitry.

[0073] NDAC 100 is beneficial in its ability to resolve possible variations and will thus perform predictably even in the presence of such variations. For example, there may be variations inherent in the manufacturing process used to fabricate NDAC 100 (e.g., on an ASIC), which may alter the I-V characteristics of circuit 109i. Further, and particularly with regard to the use of MOS diode 109S or p-n diode 109E, the I-V characteristics may depend on temperature. Such variations will ultimately affect the voltages Vmax and Vmin generated by I-V selection blocks 108a and 108b. However, because these voltages Vmax and Vmin are subtracted in resistor block 112 when forming V(An), and because V(An) is applied to circuit 109i in I-V selection block 108c which is similarly affected by such variations, the variations are eliminated or mitigated, resulting in a predictable Iout value.

[0074] Although it is preferred to select the same circuit 109i in each of the I-V selection blocks 108i, different circuit 109i can also be selected. As will be understood by those skilled in the art, using different types of circuits will result in different shapes of Iout as a function of the magnitude( Figure 6A and Figure 6B ), thus providing different Iout current increments( Figure 6C ) and resolutions( Figure 6D ) across the entire dynamic range of the DAC. For example, bias stages 102a and 102b can be controlled to select the use of p-n diode 109E, while output stage 104 is controlled to select the use of resistor 109L, which may be beneficial in a given embodiment.

[0075] Figure 7A and Figure 7B shows an example of PDAC 100 capable of supplying current Iout from the anode, and as will be understood by those skilled in the art, this circuitry is very similar to that of NDAC 100 and functions similarly. Receiving a digital magnitude bus <ap>, which forms a voltage V(Ap), which voltage forms a supply current Iout, which supply current can vary linearly, quadratically, exponentially with Ap according to the selected circuit 109i. The devices used in the PDAC 100 can have different polarities. For example, P-channel or NPN transistors can be used instead of the N-channel or PNP transistors used in the NDAC 100. Additionally, digital control signals (e.g., <imax> 、 <imin> 、 <ap>, function selection signals L, S, and E, etc.) may also be complementary (active low). Further still, and as explained in U.S. Patent Application Publication 2018 / 0071520, NDAC100 and PDAC 100 may be powered by different power domains. For example, while as Figure 5A and Figure 5B shown, the power domain Vcc / GND can be used to power the NDAC, and while as Figure 7A and Figure 7B shown, the power domain VH / VH-Vcc can be used to power the PDAC.

[0076] Many modifications to the disclosed DAC circuitry are possible, and some different modification examples are shown in Figures 8 to 10 . Figure 8 NDAC 100’ and PDAC 100’ are shown, which include NDAC 100 and PDAC 100 as described above, but which also include additional amplification stages 110n and 110p. For example, NDAC 100’ includes NDAC 100, which receives amplitude An (via bus <an>)、Maximum and minimum currents Imax and Imin (via the bus <imin>and <imax>) and a function selection signal (L, S, E) for selecting the circuit 109i having the desired I-V characteristics. The NDAC 100 outputs, as described above, a current Iout between Imin and Imax that varies as a function of An (linearly, quadratically, or exponentially). This output current is then supplied to an amplification stage 110n which, in this example, linearly amplifies Iout by a scalar Jn to produce an output current IJ = Jn * Iout between Jn * Imin and Jn * Imax at the cathode. In the example shown, the scalar Jn is accessible via an amplification bus <jn>Programmed (which can be provided by control circuitry 40), but amplifier stage 110n can also provide a fixed amplification of Jn and is non-programmable. Amplifier stage 110n can employ a current mirror to provide the desired scalar Jn and can be constructed, for example, as shown previously Figure 4 PDAC 100’ is constructed similarly and operates similarly to supply current IJ = Jp * Iout at the anode.

[0077] Figure 9 The modification shown above illustrates the use of a DAC circuitry having only a single maximum current biasing stage 102a in the input stage 101. This example is shown in the context of NDAC 100, but PDAC 100 ( Figure 7A ) can be modified similarly. Biasing stage 102a is programmed as previously to produce Imax and, in turn, Vmax that is provided to resistor block 112. When compared with Figure 5A , note that there is no minimum current biasing stage 102b and, instead, the other end of resistor block 112 is grounded. This is equivalent to setting Imin = Vmin = 0 in biasing stage 102b. In effect, this modification provides an output current Iout that is equal to zero and Imax or ranges between zero and Imax, which may be useful in applications where it is desired to extend the current of the dynamic range that can be produced by NDAC 100 down to zero. The same effect can be achieved by setting Imax = 0 in biasing stage 102b in Figure 5A . Note that in this example, control circuitry 40 does not issue <imin>and the function selection signals b(L,S,E), since these signals are not relevant when the bias stage 102b is missing.

[0078] Figure 10 shows that the DAC circuit system may not have different selectable circuits 109i with different I-V characteristics. This example is again shown in the context of the NDAC 100, but the PDAC 100 ( Figure 7A ) can be modified similarly. In Figure 10 , the NDAC 100 includes a single non-selectable circuit 109i having the I-V characteristics necessary to provide the desired response of Iout when the amplitude changes. Specifically, Figure 10 shows the use of a p-n diode 109E in the DAC (i.e., instead of the I-V selection stage 108i), although other circuits (resistor 109L, MOS diode 109S) can also be shown. Using a single non-selectable circuit 109i reduces the DAC flexibility in selecting how Iout will vary with amplitude, but limiting this flexibility can still be a reasonable design choice. For example, if an exponential relationship between Iout and amplitude is desired to produce a constant resolution over the entire dynamic range of the DAC ( Figure 6D ), then using the p-n diode 109E is a reasonable choice. Further, although not shown, the non-selectable circuit can be different in terms of stages 102a, 102b, and 104. Note that in this example, the control circuit system 40 does not issue function selection signals since these signals are not relevant.

[0079] The disclosed DAC circuit system is further advantageous in its ability to limit the dynamic range of the output current Iout between a minimum value Imax and a maximum value Imin, which is useful in a given application. Take the previously proposed example of an SCS patient who requires a current on the order of 4 mA. As previously mentioned, it may never be guaranteed that the current amplitude for this patient is below 3 mA or above 5 mA. In a DAC circuit system with a fixed increment (e.g., 0.1 mA), the patient is effectively limited to a smaller number of amplitude adjustments within this dynamic range, such as 21 out of 256 possible values.

[0080] The current DAC design does not have this limitation, and instead the amplitude can still vary in 256 increments within the desired dynamic range, thus providing greater flexibility for the patient to adjust the current within this range. This is shown in Figures 11A to 11C . In this example, Imin and Imax are programmed to 3 mA and 5 mA respectively (via the bus <imin>And <imax>) to provide the desired effective dynamic range. A type of circuit 109i is selected, namely resistor 109L, MOS diode 109S, or p-n diode 190E, to provide the desired relationship between Iout and amplitude An, as explained previously. Note that restricting the dynamic range of Iout can flatten the response, as Figure 11A shown, although these responses remain linear (resistor 109L), squared (MOS diode 190S), and exponential (p-n diode 190E), as mentioned before. Figure 11B and Figure 11C show the resulting increments and resolutions as a function of amplitude An, which show the same basic responses mentioned above (although again flattened). As Figure 11B shown, when using resistor 109L, the current increment of Iout is constant (~0.0078 mA); it generally increases linearly when using MOS diode 109S; and it increases exponentially when using p-n diode 109E. As Figure 11C shown, when using resistor 109L, the resolution decreases conversely, and it is constant (~0.2%) when using pn junction diode 109E. (For simplicity, Figure 11C the resolution of MOS diode 109S is not shown.)

[0081] Figure 12A and Figure 12B show the integration of the disclosed NDAC 100 and PDAC 100 in a stimulation circuit system 128 for providing current to the electrodes of the IPG. These stimulation circuit systems 128 are similar to the stimulation circuit systems shown previously in Figure 3A and Figure 3B and show an example where the PDACi / NDACi pair is dedicated to a specific electrode node ei ( Figure 12A ) and where the PDAC and NDAC can control the current at different electrodes through switch matrices SM Pi and SM Ni ( Figure 12B ). Also shown are the control signals received by various components, which, as mentioned before, can be issued from the control circuit system 40 of the IPG. In the example shown, each PDACi and NDACi receives a digital amplitude bus <api>And <ani>。Each PDACi and NDACi can also receive control signals specific to the disclosed DAC designs, such as setting maximum and minimum currents ( <imaxpi> 、 <iminpi> 、 <imaxni> 、 <iminni>)The signals unique to it, and the function selection signals (L, S, E(pi) and L, S, E(ni)) for shaping Iout. In one example, for each of PDAC and NDAC, the maximum and minimum currents and the function selection signals can be the same. In this regard, the control circuitry 40 may only need to issue one set of such signals (i.e., <imax> 、 <imin>and L, S, or E), and each PDACi and NDACi can receive a set of such signals. In Figure 12B as before, the switch matrices SM Pi and SW Ni additionally receive switch matrix control signals <spi>and <sni>。

[0082] Figure 13 A graphical user interface (GUI 150) is shown that can be used to program and control the operation of the disclosed DAC circuitry. Those skilled in the art will understand that GUI 150 can be reproduced on the display of an external device (such as a handheld patient remote or a clinician programmer) used to program or monitor the IPG. Software for reproducing GUI 150 and receiving input from a user can be stored in a non-transitory computer-readable medium, such as in the memory of the external device.

[0083] GUI 150 can include a DAC circuitry control interface 152 that allows selection and programming of one or more of the PDAC and NDAC. In Figure 13 , it is assumed that the IPG stimulation circuitry 128 includes four PDACs and four NDACs, although this number can vary depending on the design of the stimulation circuitry. DAC programming can include options for specifying the maximum and minimum currents (Imax and Imin) generated by the associated (s) DAC, and options for selecting the shape of Iout relative to the amplitude (such as linearly, squared, or exponentially), which will respectively select the use of resistor 109L, MOS diode 109S, and p-n diode 109E in the stimulation circuitry 128. Such programming can be transferred from the external device to the IPG to allow the control circuitry 40 of the IPG to form a bus for each or all of the DACs <imax> 、 <imin>and function select signals L, S, and E. (In other DAC designs, <imin>The function selection signal may be irrelevant (see Figure 9 and Figure 10 ), in which case, the control of these variables may be omitted from the GUI 150).

[0084] Because the external device can be programmed using the relevant I-V characteristics of the circuit 109i used in the DAC circuitry, the external device can calculate the current Iout corresponding to each amplitude value (Iout(A)) given Imin, Imax, and the selected Iout shape. In fact, the external device can determine the data required to form the graph previously shown in Figure 6A , which shows Iout versus A. If necessary or useful, Iout(A) can be displayed as a table of values in the GUI 150, or it can be plotted as in Figure 6A . Based on the Iout(A) data, the external device can further determine the range of increments and resolution or both, as described above. In fact, the external device can determine the data required to form the graphs previously shown in Figure 6C and Figure 6D , and can plot such data again. Displaying such information in the GUI 150 is useful for reference and can help the user select a suitable Iout shape given Imin and Imax. For example, the user can refer to the resolution provided within the dynamic range of selectable amplitudes to ensure that each amplitude increment will provide a significant adjustment to Iout.

[0085] Establishing Iout(A) in the external device enables the external device to convert the desired current amplitude into a digital amplitude bus ( <ap> ， <an>)The carried amplitude value A can also be useful. In this regard, the GUI 150 can include an electrode programming interface 154 that allows a user (patient or clinician) to specify the current I to be generated at each of the electrodes in the IPG electrode array 17. In a practical implementation, the electrode programming interface 154 can be significantly more complex and can include additional options for specifying the stimulation that the patient will receive. For example, the frequency and pulse width of the pulses can also be specified, but for simplicity, this is not shown.

[0086] In the example shown, the user selects electrodes E1 and E3 to act as anodes, where each anode supplies +2.0 mA of current to the patient's tissue. The user also selects electrode E2 to act as a cathode to absorb -4.0 mA of current from the patient tissue. Knowing how Iout scales with the amplitude (Iout(A)) of the selected Iout shape, the external device can determine the amplitude value A required to establish the desired current I, and this can be done using the amplitude conversion module 130 stored in the external device in association with the software of the GUI 150. For example, assume the use of Figure 12A the stimulation circuit system 128 architecture (where each electrode Ei has a dedicated PDACi / NDACi pair), and the user has programmed the DAC to provide an exponential response for Iout. As described above, the external device can determine Iout(A) and provide it to the amplitude conversion module 130 such that the amplitude value A can be determined for each of the specified currents I. Referring to Figure 6C the graph of Iout versus A in, when the exponential shape is selected, we can see that current values of 2 mA and 4 mA correspond to amplitude values of 138 and 170, respectively. Thus, the amplitude conversion module can digital amplitude bus <ap1>(Serving PDAC1 and electrode E1) is set to 138 (‘01110101’, 138 active low), driving the digital amplitude bus <an2>(Serving NDAC2 and electrode E2) is set to 170 (‘10101010’, 170 active high), and the digital amplitude bus <ap3>(Serving PDAC3 and electrode E3) is set to 138 (‘01110101’, 138 active low). Then, these amplitude values can be transmitted from an external device to the IPG along with other relevant data to allow the control circuitry 40 in the IPG to form the control signals required for the stimulation circuitry 128 to form the desired stimulation.

[0087] Alternatively, the external device can transmit the desired current amplitude to the IPG 10, causing the IPG 10 to convert these currents into amplitude values. In this regard, the control circuitry 40 of the IPG can also include an amplitude conversion module 130, as Figure 12A and Figure 12B shown. Thus, the control circuitry 40 in the IPG 10 can determine Iout (A) given other user selections (Imin, Imax, Iout shape, etc.) in a given GUI 150, or Iout (A) can also be telemetered to the IPG. In either case, the module 130 can determine the amplitude value A required to form the desired current I at each of the electrodes. < / an> < / ap> < / imin> < / imin> < / imax> < / sni> < / spi> < / imin> < / imax> < / iminni> < / imaxni> < / iminpi> < / imaxpi> < / ani> < / api> < / imax> < / imin> < / imin> < / jn> < / imax> < / imin> < / an> < / ap> < / imin> < / imax> < / ap> < / imin> < / imax> < / an> < / an> < / an> < / an> < / an> < / imin> < / imax> < / imin> < / imax> < / an> < / an> < / an> < / ap> < / sp1> < / ap1> < / sp1> < / api> < / ani> < / api> < / ani>

Claims

1. A stimulator device, comprising: a plurality of electrode nodes, each electrode node being configured to be coupled to a corresponding electrode configured to contact a patient's tissue; and a digital-to-analog converter (DAC) circuitry that can be controlled by a digital amplitude bus configured to specify a plurality of amplitude values, wherein the DAC circuitry is configured to set an amplitude of an output current that affects an electrode current at at least one of the electrode nodes, wherein the output current is equal to a maximum amplitude and a minimum amplitude or ranges between the maximum amplitude and the minimum amplitude according to the amplitude values carried by the digital amplitude bus, wherein the DAC circuitry can also be programmed to set the maximum amplitude and the minimum amplitude.

2. The stimulator device according to claim 1, wherein the DAC circuitry is configured to provide the output current as the electrode current at the at least one of the electrode nodes.

3. The stimulator device according to claim 1, wherein the DAC circuitry includes an amplification stage configured to amplify the output current into the electrode current.

4. The stimulator device according to any one of claims 1 to 3, wherein the DAC circuitry can be programmed by a first bus to set a maximum amplitude of the output current, and wherein the DAC circuitry can be programmed by a second bus to set a minimum amplitude of the output current.

5. The stimulator device according to any one of claims 1 to 4, wherein the DAC circuitry includes: an input stage configured to receive the digital amplitude bus and generate a third voltage, and an output stage configured to receive the third voltage and generate the output current.

6. The stimulator device according to claim 5, wherein the third voltage is applied to a third circuit in the output stage, wherein the third circuit includes a current-voltage characteristic.

7. The stimulator device according to claim 6, wherein the output current is formed by the third circuit according to the current-voltage characteristic of the third circuit.

8. The stimulator device according to claim 7, wherein the third circuit is selectable.

9. The stimulator device according to claim 5, wherein the input stage includes a first bias stage configured to generate a first current according to the set maximum amplitude, and a second bias stage configured to generate a second current according to the set minimum amplitude.

10. The stimulator device according to claim 9, wherein the first bias stage is configured to generate a first voltage that varies with the first current, and wherein the second bias stage is configured to generate a second voltage that varies with the second current.

11. The stimulator device according to claim 10, wherein the first biasing stage includes a first circuit configured to receive the first current, wherein the first voltage is generated according to the current-voltage characteristic of the first circuit, wherein the second biasing stage includes a second circuit configured to receive the second current, wherein the second voltage is generated according to the current-voltage characteristic of the second circuit.

12. The stimulator device according to claim 11, wherein the first circuit and the second circuit are selectable.

13. The stimulator device according to any one of claims 10 to 12, wherein the third voltage is generated as a function of the first voltage and the second voltage.

14. The stimulator device according to claim 13, wherein the third voltage is equal to the first voltage and the second voltage or between the first voltage and the second voltage.

15. The stimulator device according to claim 14, wherein the third voltage varies linearly with the amplitude value.

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