Peak holding device and method for near-infrared ultrashort wave pulse optical signal detection

Abstract

The invention relates to a near-infrared ultrashort wave pulse optical parameter testing device and method, in particular to a peak holding device and method for near-infrared ultrashort wave pulse optical signal detection, and solves the problem that an existing peak holding device is difficult to accurately detect near-infrared pulse optical signals with the pulse width smaller than 10 ns and low power density. And the circuit is complex in structure, large in area and not suitable for development of a high-spatial-resolution detector array. The device comprises an FPGA module, n detection units and a plurality of connectors, wherein n is greater than or equal to 1; each detection unit comprises a photoelectric detector circuit, a current-voltage conversion circuit, a biasing circuit, a peak holding circuit and a data acquisition circuit; the near-infrared pulse optical signal with the front edge smaller than 2 ns, the pulse width smaller than 10 ns and the repetition frequency ranging from 10 Hz to 100 KHz can be accurately detected; according to the method, the peak value of the ultra-short wave pulse laser signal can be kept, then subsequent processing analysis is carried out, the requirement for rear-end collection can be effectively lowered, and reliable measurement of nanosecond magnitude pulse laser parameters is achieved.

Description

Technical Field

[0001] The present invention relates to a near-infrared ultra-short wave pulsed light parameter testing device and method, and specifically to a peak holding device and method for detecting near-infrared ultra-short wave pulsed light signals. Background Art

[0002] With the rapid development of laser technology, the performance of lasers has been continuously improved. The testing of nanosecond-level pulsed laser parameters has attracted much attention. Therefore, new requirements are put forward for the development of testing equipment, which need to have the ability to collect nanosecond-level and low-power-density pulsed laser parameters. The peak holding device can hold the peak value of the ultra-short wave pulsed signal and then perform subsequent processing and analysis, so as to realize the reliable measurement of nanosecond-level pulsed laser parameters. However, it is difficult to accurately detect near-infrared pulsed light signals with a pulse width less than 10 ns and low power density, and the circuit structure is complex and the area is large, which is not suitable for the development of high-spatial-resolution detector arrays. The array detection method is an important method for realizing laser parameter testing. High-spatial-resolution detector arrays usually have a large number of detectors with a very small interval, leaving limited space for the circuit. Therefore, a peak holding device with a simple structure and small spatial volume is needed, which is suitable for its development. Summary of the Invention

[0003] The purpose of the present invention is to solve the technical problems that the existing peak holding device is difficult to accurately detect near-infrared pulsed light signals with a pulse width less than 10 ns and low power density, and the circuit structure is complex and the area is large, which is not suitable for the development of high-spatial-resolution detector arrays, and to provide a peak holding device and method for detecting near-infrared ultra-short wave pulsed light signals.

[0004] In order to achieve the above purpose, the present invention adopts the following technical solutions:

[0005] A peak holding device for detecting near-infrared ultra-short wave pulsed light signals, characterized in that it includes an FPGA module, n detection units and a plurality of connectors, n≥1;

[0006] Each detection unit includes a photodetector circuit, a current-voltage conversion circuit, a bias circuit, a peak holding circuit, and a data acquisition circuit; the input ends of the current-voltage conversion circuit are respectively connected to the output end of the photodetector circuit and the output end of the bias circuit, and the output end of the current-voltage conversion circuit is connected to the input end of the peak holding circuit; the output end of the peak holding circuit is connected to the input end of the data acquisition circuit through the corresponding connector, and a plurality of acquisition channels are formed;

[0007] The data acquisition circuit and the FPGA module are both arranged on the PCB board; the input end of the FPGA module is connected to the output end of the connected data acquisition circuit, the control end is connected to the trigger end of the peak holding circuit and the control end of the data acquisition circuit respectively through the connector, and the output end is used to connect to external equipment;

[0008] The photodetector circuit is used to collect near-infrared ultra-short wave pulsed optical signals and convert them into current signals;

[0009] The current-voltage conversion circuit is used to convert the current signal into a pulsed voltage signal;

[0010] The bias circuit is used to generate a bias voltage VCC_VREF, and then raise the pulsed voltage signal;

[0011] The peak holding circuit is used to hold the peak of the raised pulsed voltage signal according to a preset time to obtain a widened signal;

[0012] The data acquisition circuit is used to collect the widened signal and convert it into a digital signal;

[0013] The FPGA module is used to process and output the digital signal, and at the same time generate a front-end drive signal to be sent to the peak holding circuit so that its peak holding time is adjusted according to the pulse width of the near-infrared ultra-short wave pulsed optical signal to be measured.

[0014] [[ID=2))0]]Furthermore, the data acquisition circuit includes an analog switch module, a signal conditioning module and an ADC module;

[0015] The input end of the analog switch module is connected to the output end of the corresponding peak holding circuit through a connector, and a plurality of acquisition channels are formed, and the output end is connected to the input end of the signal conditioning module; the output end of the signal conditioning module is connected to the input end of the ADC module;

[0016] The input end of the FPGA module is connected to the output end of the ADC module, the control end of the FPGA module is respectively connected to the control end of the analog switch module and the control end of the ADC module, and is connected to the trigger end of the peak holding circuit through a connector, and is used to send a drive signal RST_CTRL to the trigger end of the peak holding circuit, send a drive signal MUX_CTRL to the control end of the analog switch module, and send a drive signal ADC_CTRL to the control end of the ADC module;

[0017] The analog switch module is used to scan the acquisition channels after receiving the drive signal MUX_CTRL and send the scanned widened signal to the signal conditioning module;

[0018] The signal conditioning module is used to filter and amplify the widened signal to obtain a filtered and amplified signal, and send the filtered and amplified signal to the ADC module;

[0019] The ADC module is used to convert the filtered and amplified signal into a digital signal and send it to the FPGA module after receiving the drive signal ADC_CTRL.[[ID=)))6]]

[0020] Furthermore, the number of acquisition channels is 96.

[0021] Further, the photodetector circuit includes a photodetector D1 and a current-limiting resistor R1;

[0022] The positive electrode of the photodetector D1 is connected to the negative power supply VCC5V_N through the current-limiting resistor R1, and the negative electrode is connected to the input end of the current-voltage conversion circuit.

[0023] Further, the bias circuit includes an emitter follower U2, a resistor R3, a resistor R4, a resistor R6, and a capacitor C9;

[0024] The non-inverting input terminal of the emitter follower U2 is respectively connected to one end of the resistor R3 and one end of the resistor R4; the other end of the resistor R3 is connected to the power supply VCC5V; the output terminal of the emitter follower U2 is connected to its inverting input terminal and one end of the resistor R6; the other end of the resistor R6 is connected to one end of the capacitor C9, and serves as the output terminal of the bias circuit to be connected to the input end of the current-voltage conversion circuit for outputting VCC_VREF; the other end of the resistor R4 and the other end of the capacitor C9 are grounded.

[0025] Further, the current-voltage conversion circuit includes an operational amplifier U1, a resistor R2, and a capacitor C6;

[0026] The non-inverting input terminal of the operational amplifier U1 is connected to the output terminal of the bias circuit for receiving VCC_VREF; the inverting input terminal is respectively connected to the negative electrode of the photodetector D1, one end of the capacitor C1, one end of the resistor R2, and one end of the capacitor C6; the output terminal of the operational amplifier U1 is respectively connected to the other end of the resistor R2, the other end of the capacitor C6, and the input end of the peak-holding circuit for outputting a pulse voltage signal; the other end of the capacitor C1 is grounded.

[0027] Further, the peak-holding circuit includes an amplifier U3, a Schottky diode D2, a triode Q1, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, and a thin-film capacitor C10; the amplifier U3 is a peak-holding unit;

[0028] The E end of amplifier U3 is connected to the input end of the data acquisition circuit through resistor R14 for outputting the widening signal; the B end is connected to the cathode of Schottky diode D2, one end of film capacitor C10 and one end of resistor R12 respectively through resistor R10; the anode of Schottky diode D2 is connected to Chold end; the Shin+ end is connected to one end of resistor R7 and the output end of operational amplifier U1 through resistor R9 for receiving the pulse voltage signal; the Shin- end is connected to pin 2 through resistor R15 to form a feedback loop; the IQ_AD end is connected to the ... The negative power supply VCC5V_N is connected to the resistor R11 for controlling the working current; the Hold terminal is connected to the positive power supply VCC5V_P through the resistor R8 for locking the output; the base b of the transistor Q1 is respectively connected to one end of the resistor R13 and the output end of the FPGA module (54) for receiving the drive signal RST_CTRL, and the collector c is connected to the other end of the resistor R12; the emitter e of the transistor Q1, the C end of the amplifier U3, the other end of the film capacitor C10, the other end of the resistor R7, and the other end of the resistor R13 are grounded.

[0029] Furthermore, the photodetector D1 is an InGaAs photodiode;

[0030] The value of resistor R3 is 22KΩ;

[0031] The value of resistor R4 is 1.5KΩ;

[0032] The operational amplifier U1 is OPA659IDBVR with a slew rate of 2550V / μs.

[0033] The model of emitter follower U2 is AD8605ARTZ_REEL;

[0034] The model of amplifier U3 is OPA615IDR;

[0035] The model of Schottky diode D2 is BAT17_215;

[0036] The model of transistor Q1 is MMBT3904LT1G;

[0037] The film capacitor C10 is a holding capacitor, its model is ECHU1C103JX5, and its capacitance value is 10Nf.

[0038] At the same time, the present invention also provides a method for detecting near-infrared ultrashort wave pulse light signals, which is based on the above-mentioned peak holding device for detecting near-infrared ultrashort wave pulse light signals, and is special in that it includes the following steps:

[0039] Step 1: Use the photodetector circuit to collect the near-infrared ultrashort wave pulse light signal and convert it into a current signal and transmit it to the current-voltage conversion circuit;

[0040] Step 2: The current-voltage conversion circuit converts the current signal into a pulse voltage signal and transmits it to the peak holding circuit;

[0041] Step 3: Use the bias circuit to generate a bias voltage VCC_VREF to raise the pulse voltage signal; the peak holding circuit holds the peak of the raised pulse voltage signal for a preset time to obtain a widened signal;

[0042] Step 4: The data acquisition circuit acquires the widened signal and converts it into a digital signal;

[0043] Step 5: The FPGA module is used to process the digital signal and generate a front-end drive signal according to the pulse width of the near-infrared ultra-short wave pulse optical signal to be measured, and transmits it to the peak holding circuit to control its peak holding time.

[0044] Advantages of the present invention:

[0045] 1. The peak holding device of the present invention can accurately detect near-infrared pulse optical signals with a leading edge less than 2 ns, a pulse width less than 10 ns, and a repetition frequency of 10 Hz - 100 KHz. The FPGA module is used to control the peak holding time, making the peak holding time adjustable and having strong versatility.

[0046] 2. The peak holding device of the present invention has a measurement dynamic range greater than 1000 times. The bias circuit is used to correct the peak holding circuit, eliminating the sampling error caused by the photodetector D1, and solving the problem of large distortion of the widened signal when the input signal Vin of the peak holding circuit is less than 0.3 V, meeting the requirement of accurate laser parameters under low power density irradiation.

[0047] 3. The peak holding device of the present invention has a simpler circuit structure, fewer components, a smaller occupied area, stable operation, and strong anti-interference ability compared with the traditional peak holding device, effectively solving the problems of large circuit area and insufficient space existing in compact and high-spatial-resolution detection arrays.

[0048] 4. The peak holding device of the present invention has an expansion ability, and can expand channels by replicating the front-end circuit and increasing the number of analog switch modules, signal conditioning modules, and ADC modules at the same time.

[0049] 5. The data acquisition circuit in the peak holding device of the present invention has an expansion function. When the number of input widened signal channels is no more than 96, only connecting 1 connector, 1 analog switch module, 1 signal conditioning module, 1 ADC module, and 1 FPGA module on the PCB board can meet the requirements; when the number of input widened signal channels is more than 96, increasing the number of connectors, analog switch modules, signal conditioning modules, and ADC modules and making connections on the PCB board can complete the expansion. The data acquisition circuit can collect up to 1536 widened signals through expansion.

[0050] 6. For the development of the detector array in the peak holding device of the present invention, by replicating the front-end photodetector circuit, current-voltage conversion circuit, bias circuit, and peak holding circuit, and at the same time increasing the number of analog switch modules, signal conditioning modules, and ADC modules and making connections on the PCB board to expand its channels, the construction of the detector array can be quickly completed.

[0051] 7. The method for detecting near-infrared ultra-short wave pulse optical signals of the present invention can hold the peak of the ultra-short wave pulse laser signal and then perform subsequent processing and analysis, which can effectively reduce the requirements for backend acquisition and achieve reliable measurement of the parameters of nanosecond-level pulsed lasers. Description of the Drawings

[0052] Figure 1 It is a schematic structural diagram of the peak holding device for detecting near-infrared ultra-short wave pulse optical signals of the present invention;

[0053] Figure 2 It is a circuit diagram of the photodetector circuit and the current-voltage conversion circuit in the embodiment of the present invention;

[0054] Figure 3 It is a circuit diagram of the bias circuit in the embodiment of the present invention;

[0055] Figure 4 It is a circuit diagram of the peak holding circuit in the embodiment of the present invention;

[0056] Figure 5 It is a schematic structural diagram of the data acquisition circuit in the embodiment of the present invention.

[0057] Description of the Reference Numerals:

[0058] 1 - Photodetector circuit, 2 - Current-voltage conversion circuit, 3 - Bias circuit, 4 - Peak holding circuit, 5 - Data acquisition circuit, 51 - Analog switch module, 52 - Signal conditioning module, 53 - ADC module, 54 - FPGA module. Detailed Embodiments

[0059] As Figure 1As shown in the figure, a peak holding device for detecting near-infrared ultra-short wave pulse optical signals includes an FPGA module 54, n detection units and multiple connectors, where n≥1; each detection unit includes a photodetector circuit 1, a current-voltage conversion circuit 2, a bias circuit 3, a peak holding circuit 4, and a data acquisition circuit 5; the data acquisition circuit 5 includes an analog switch module 51, a signal conditioning module 52, and an ADC module 53; the input ends of the current-voltage conversion circuit 2 are respectively connected to the output end of the photodetector circuit 1 and the output end of the bias circuit 3, and the output end of the current-voltage conversion circuit 2 is connected to the input end of the peak holding circuit 4; the output end of the peak holding circuit 4 is connected to the input end of the data acquisition circuit 5 through a corresponding connector, and 96 acquisition channels are formed; both the data acquisition circuit 5 and the FPGA module 54 are arranged on the PCB bottom board; the input end of the analog switch module 51 is connected to the output end of the corresponding peak holding circuit 4 through a connector, and 96 acquisition channels are formed, and the output end is connected to the input end of the signal conditioning module 52; the output end of the signal conditioning module 52 is connected to the input end of the ADC module 53; the input end of the FPGA module 54 is connected to the output end of the ADC module 53, and the control end of the FPGA module 54 is respectively connected to the control end of the analog switch module 51 and the control end of the ADC module 53, and is connected to the trigger end of the peak holding circuit 4 through a connector, and is used to deliver a driving signal RST_CTRL to the trigger end of the peak holding circuit 4, deliver a driving signal MUX_CTRL to the control end of the analog switch module 51, and deliver a driving signal ADC_CTRL to the control end of the ADC module 53; the output end of the FPGA module 54 is used to connect to an external device.

[0060] The photodetector circuit 1 is used to collect near-infrared ultra-short wave pulse optical signals and convert them into current signals; the current-voltage conversion circuit 2 is used to convert the current signals into pulse voltage signals; the bias circuit 3 is used to generate a bias voltage VCC_VREF, and then raise the pulse voltage signal. The bias voltage VCC_VREF = VCC_5V / (R3 + R4)*R4 = 5V / (22K + 1.5K)×1.5K = 0.319V; the peak hold circuit 4 is used to hold the peak of the raised pulse voltage signal according to a preset time to obtain a widened signal; the analog switch module 51 is used to scan the acquisition channels after receiving the drive signal MUX_CTRL and deliver the scanned widened signal to the signal conditioning module 52; the signal conditioning module 52 is used to filter and amplify the widened signal to obtain a filtered and amplified signal and deliver the filtered and amplified signal to the ADC module 53; the ADC module 53 is used to convert the filtered and amplified signal into a digital signal after receiving the drive signal ADC_CTRL and deliver it to the FPGA module 54; the FPGA module 54 is used to process the digital signal and output it, and at the same time generate a front-end drive signal and deliver it to the peak hold circuit 4 to adjust the peak hold time according to the pulse width of the near-infrared ultra-short wave pulse optical signal to be measured.

[0061] In this embodiment, the current-voltage conversion circuit 2 is an operational amplifier type I-V conversion circuit, and the amplitude of the maximum collected signal is 5V. The resistor R2 is used to realize the conversion of current to voltage. The operational amplifier U1 is a high-speed operational amplifier with a slew rate of 2550V / μs; the bias circuit 3 stabilizes the output bias voltage through the series voltage division of the resistor R3 and the resistor R4 and the emitter follower U2, raises the voltage input to the peak hold circuit 4, and solves the problem that when the input signal of the peak hold circuit 4 is less than 0.3V, the output signal is distorted greatly; the data acquisition circuit 5 has the ability to expand. By increasing the number of analog switch modules 51, the number of signal conditioning modules 52, and the number of ADC modules 53 and wiring on the PCB bottom board, the acquisition channels can be expanded; at the same time, the front-end photodetector circuit 1, the current-voltage conversion circuit 2, the bias circuit 3, and the peak hold circuit 4 are replicated to expand the channels of the system, and the construction of the detector array can be quickly completed.

[0062] As Figure 3As shown, the bias circuit 3 includes an emitter follower U2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a capacitor C7, a capacitor C8, and a capacitor C9. The non-inverting input terminal (pin 3) of the emitter follower U2 is respectively connected to one end of the resistor R3 and one end of the resistor R4. The pin 5 is respectively connected to one end of the capacitor C7, one end of the capacitor C8, and one end of the resistor R5. The other end of the resistor R5 is respectively connected to the other end of the resistor R3 and the power supply VCC 5V. The output terminal (pin 1) is respectively connected to the inverting input terminal (pin 4) and one end of the resistor R6. The other end of the resistor R6 is respectively connected to the capacitor C9 and the input terminal of the current-voltage conversion circuit 2, for outputting the bias voltage VCC_VREF. The other end of the resistor R4, the other end of the capacitor C7, the other end of the capacitor C8, the other end of the capacitor C9, and the pin 2 are respectively grounded. The model of the emitter follower U2 is AD8605ARTZ_REEL. The value of the resistor R3 is 22KΩ. The value of the resistor R4 is 1.5KΩ.

[0063] As Figure 2 shown, the photodetector circuit 1 includes a photodetector D1 and a current-limiting resistor R1. The positive electrode of the photodetector D1 is connected to the negative power supply VCC5V_N through the current-limiting resistor R1, and the negative electrode is connected to the input terminal of the current-voltage conversion circuit 2. The current-voltage conversion circuit 2 includes an operational amplifier U1, a resistor R2, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, and a capacitor C6. The non-inverting input terminal (pin 3) of the operational amplifier U1 is connected to the output terminal of the bias circuit 3 for receiving the bias voltage VCC_VREF. The inverting input terminal (pin 4) is respectively connected to the negative electrode of the photodetector D1, one end of the capacitor C1, one end of the resistor R2, and one end of the capacitor C6. The output terminal (pin 1) is respectively connected to the other end of the resistor R2, the other end of the capacitor C6, and the input terminal of the peak-holding circuit 4, for outputting a pulse voltage signal (i.e., the output signal Pulse). The pin 2 is respectively connected to the negative power supply VCC5V_N, one end of the capacitor C4, and one end of the capacitor C5. The pin 5 is respectively connected to VCC5V_P, one end of the capacitor C2, and one end of the capacitor C3. The other ends of the capacitor C1, the capacitor C2, the capacitor C3, the capacitor C4, and the capacitor C5 are respectively grounded. The photodetector D1 is an InGaAs photodiode. The model of the operational amplifier U1 is OPA659IDBVR. The resistor R2 is an amplification resistor.

[0064] As Figure 4As shown, the peak holding circuit 4 includes an amplifier U3, a Schottky diode D2, a triode Q1, resistors R7, R8, R9, R10, R11, R12, R13, R14, R15, a thin-film capacitor C10, capacitors C11, C12, C13, C14; the E terminal (pin 2) of the amplifier U3 is connected to the input terminal of the analog switch module 51 through the resistor R14 for outputting a widened signal (i.e., the output signal Vout); the resistor R14 is a current-limiting resistor; the B terminal (pin 3) is connected to the negative electrode of the Schottky diode D2, one end of the thin-film capacitor C10, and one end of the resistor R12 through the resistor R10 respectively; the positive electrode of the Schottky diode D2 is connected to the Chold terminal (pin 4); the Shin+ terminal (pin 10) is connected to one end of the resistor R7 and the output terminal (pin 1) of the operational amplifier U1 through the resistor R9 respectively for receiving the input signal Vin (pulse voltage signal); the resistor R7 is an input resistor, and the resistor R9 is a current-limiting resistor; the Shin- terminal (pin 11) is connected to the E terminal (pin 2) through the resistor R15 to form a feedback loop, and R15 is a feedback resistor; the IQ_AD terminal (pin 1) is connected to the negative power supply VCC5V_N through the resistor R11 for controlling the working current; the Hold terminal (pin 7) is connected to the positive power supply VCC5V_P through the resistor R8 for locking the output; the power supply V- (pin 5) is connected to the negative power supply VCC5V_N; the power supply V+ (pin 13) is connected to the positive power supply VCC5V_P; the NC1 terminal (pin 6), the NC2 terminal (pin 8), and the NC2 terminal (pin 14) are not connected; the base b of the triode Q1 is connected to one end of the resistor R13 and the output terminal of the FPGA module 54 respectively for receiving the driving signal RST_CTRL, and the collector c is connected to the other end of the resistor R12; the resistor R13 is an input resistor; the emitter e of the triode Q1, the GND terminal (pin 9), the C terminal (pin 12), the other end of the thin-film capacitor C10, the other end of the resistor R7, and the other end of the resistor R13 are grounded.

[0065] Preferably, the negative power supply VCC5V_N is respectively connected to one end of the capacitor C11 and one end of the capacitor C12 for filtering; the positive power supply VCC5V_P is respectively connected to one end of the capacitor C13 and one end of the capacitor C14 for filtering; the other ends of the capacitor C11, the capacitor C12, the capacitor C13, and the capacitor C14 are all grounded.

[0066] In this embodiment, the amplifier U3 is a dedicated peak holding chip, with the model number OPA615IDR. When the internal switch of it is enabled, the output current is very large and can quickly charge the thin film capacitor C10. When the switch is turned off, the off-resistance is very large, so that the charge on the thin film capacitor C10 can be kept as unchanged as possible. The thin film capacitor C10 is a holding capacitor, with the model number ECHU1C103JX5 and the capacitance value of 10Nf. The Schottky diode D2 is a detection diode, with the model number BAT17_215. The model number of the triode Q1 is MMBT3904LT1G, which is used to control the discharge of the holding capacitor C10 according to a preset time. The drive signal RST_CTRL is generated by the 5FPGA module 54 of the data acquisition circuit.

[0067] The working principle of the peak holding circuit 4 is as follows:

[0068] The input signal Vin is input from pin 10 of the amplifier U3, and the widened signal is output from pin 2 of the amplifier U3.

[0069] When the widened signal is less than or equal to the input signal Vin, the amplifier U3 amplifies the difference between the input signal Vin and the widened signal, that is, the voltage difference between pin 10 and pin 11. The amplified signal is output from pin 4. At this time, the Schottky diode D2 conducts, and the holding capacitor C10 is charged through the loop composed of pin 4, the Schottky diode D2, and the holding capacitor C10. The voltage across the holding capacitor C10 gradually increases. At the same time, a loop is formed by pin 3, the resistor R10, and the capacitor C10, and the voltage of pin 3 also gradually increases. When the voltage rises to 0.7V, pin 2 conducts, and the voltage across the capacitor C10 is output through the resistor R14 and fed back to pin 11 through the resistor R15. At this time, the widened signal is equal to the voltage across the holding capacitor C10.

[0070] When the widened signal is greater than the input signal Vin, the amplified signal output from pin 4 is negative, the Schottky diode D2 is cut off, and the holding capacitor C10 stops charging, that is, the widened signal remains unchanged, completing peak holding until the drive signal RST_CTRL of the FPGA module 54 arrives. The drive signal RST_CTRL is input to the base b of the triode Q1, the triode Q1 conducts, and a loop is formed by the holding capacitor C10, the resistor R12, and the triode Q1. The holding capacitor C10 quickly discharges and waits for the next pulse to arrive to perform peak holding again.

[0071] As Figure 5As shown, a single connector can receive up to 96 widened signals and output 1 control signal RST_CTR. Under the control of the drive signal RST_CTRL, the peak hold circuit 4 delivers the output widened signals to the analog switch module 51 through the connector. The analog switch module 51 scans the input channels under the control of the drive signal MUX_CTRL and delivers the widened signals to the signal conditioning module 52. A single analog switch module 51 can scan up to 96 input channels ch1 to ch96. The signal conditioning module 52 conditions and amplifies the input widened signals and delivers them to the ADC module 53. A single signal conditioning module 52 can condition and amplify up to 6 widened signals com1 to com6. The ADC module 53 converts the conditioned and amplified widened signals into digital signals data under the control of the drive signal ADC_CTRL and delivers them to the FPGA module 54. A single ADC module 53 can convert up to 6 filtered and amplified signals an1 to an6 into digital signals data. Under the control of the drive signal RST_CTRL, the peak hold circuit 4 controls the peak hold discharge time. Under the control of the drive signal MUX_CTRL, the analog switch module 51 completes channel scanning. Under the control of the drive signal ADC_CTR, the ADC module 53 completes analog-to-digital conversion. After receiving the digital signal data at the input end of the FPGA module 54, it processes the signal and outputs it to an external device through an interface.

[0072] The data acquisition circuit 5 in the present invention has an expansion function. When the number of widened signal channels input is no more than 96, only connecting 1 connector, 1 analog switch module 51, 1 signal conditioning module 52, 1 ADC module 53, and 1 FPGA module on the PCB board can meet the requirements. When the number of widened signal channels input is greater than 96, increasing the number of connectors, analog switch modules 51, signal conditioning modules 52, and ADC modules 53 and making connections on the PCB board can complete the expansion. The data acquisition circuit 5 can collect up to 1536 widened signals through expansion. For the development of a detector array, by replicating the front-end photodetector circuit 1, current-voltage conversion circuit 2, bias circuit 3, and peak hold circuit 4, and at the same time increasing the number of analog switch modules 51, signal conditioning modules 52, and ADC modules 53 and making connections on the PCB board to expand its channels, the construction of the detector array can be quickly completed.

[0073] The present invention also provides a method for detecting near-infrared ultra-short wave pulse optical signals, based on the above-mentioned peak hold device for detecting near-infrared ultra-short wave pulse optical signals, including the following steps:

[0074] Step 1: Use the photodetector circuit 1 to collect near-infrared ultra-short wave pulse optical signals and convert them into current signals and deliver them to the current-voltage conversion circuit 2;

[0075] Step 2: The current-voltage conversion circuit 2 converts the current signal into a pulsed voltage signal and transmits it to the peak-holding circuit 4;

[0076] Step 3: The bias circuit 3 is used to generate a bias voltage VCC_VREF to raise the pulsed voltage signal; the peak-holding circuit 4 holds the peak of the raised pulsed voltage signal for a preset time to obtain a widened signal;

[0077] Step 4: The data acquisition circuit 5 acquires the widened signal and converts it into a digital signal;

[0078] Step 5: The FPGA module 54 is used to process the digital signal and generate a front-end drive signal according to the pulse width of the near-infrared ultra-short wave pulsed optical signal to be measured and transmit it to the peak-holding circuit 4 to control its peak-holding time.

Claims

1. A peak holding device for detecting near-infrared ultra-short wave pulse optical signals, characterized in that: It includes an FPGA module (54), n detection units and multiple connectors, where n≥1; Each detection unit includes a photodetector circuit (1), a current-voltage conversion circuit (2), a bias circuit (3), a peak hold circuit (4), and a data acquisition circuit (5); the input ends of the current-voltage conversion circuit (2) are respectively connected to the output end of the photodetector circuit (1) and the output end of the bias circuit (3), and the output end of the current-voltage conversion circuit (2) is connected to the input end of the peak hold circuit (4); the output end of the peak hold circuit (4) is connected to the input end of the data acquisition circuit (5) through the corresponding connector, and multiple acquisition channels are formed; Both the data acquisition circuit (5) and the FPGA module (54) are arranged on the PCB board; the input end of the FPGA module (54) is connected to the output end of the connected data acquisition circuit (5), the control end is respectively connected to the trigger end of the peak hold circuit (4) and the control end of the data acquisition circuit (5) through the connector, and the output end is used to connect to external devices; The photodetector circuit (1) is used to collect near-infrared ultra-short wave pulse optical signals and convert them into current signals; The current-voltage conversion circuit (2) is used to convert the current signal into a pulse voltage signal; The bias circuit (3) is used to generate a bias voltage VCC_VREF, and then raise the pulse voltage signal; The peak hold circuit (4) is used to hold the peak of the raised pulse voltage signal for a preset time to obtain a widened signal; The data acquisition circuit (5) is used to collect the widened signal and convert it into a digital signal; The FPGA module (54) is used to process and output the digital signal, and at the same time generate a front-end drive signal and send it to the peak hold circuit (4) so that its peak hold time is adjusted according to the pulse width of the near-infrared ultra-short wave pulse optical signal to be measured.

2. The peak hold device for detecting near-infrared ultra-short wave pulse optical signals according to claim 1, wherein: The data acquisition circuit (5) includes an analog switch module (51), a signal conditioning module (52) and an ADC module (53); The input end of the analog switch module (51) is connected to the output end of the corresponding peak hold circuit (4) through the connector, and multiple acquisition channels are formed, and the output end is connected to the input end of the signal conditioning module (52); the output end of the signal conditioning module (52) is connected to the input end of the ADC module (53); the input end of the FPGA module (54) is connected to the output end of the ADC module (53), and the control end of the FPGA module (54) is respectively connected to the control end of the analog switch module (51) and the control end of the ADC module (53), and is connected to the trigger end of the peak hold circuit (4) through the connector, and is used to send a drive signal RST_CTRL to the trigger end of the peak hold circuit (4), send a drive signal MUX_CTRL to the control end of the analog switch module (51), and send a drive signal ADC_CTRL to the control end of the ADC module (53); The analog switch module (51) is used to scan and collect channels after receiving the driving signal MUX_CTRL, and convey the widened signal obtained by scanning to the signal conditioning module (52); The signal conditioning module (52) is used to filter and amplify the widened signal to obtain a filtered and amplified signal, and convey the filtered and amplified signal to the ADC module (53); The ADC module (53) is used to convert the filtered and amplified signal into a digital signal after receiving the driving signal ADC_CTRL and convey it to the FPGA module (54).

3. The peak holding device for detecting near-infrared ultra-short wave pulse optical signals according to claim 2, characterized in that: The number of acquisition channels is 96.

4. The peak holding device for detecting near-infrared ultra-short wave pulse optical signals according to any one of claims 1-3, characterized in that: The photodetector circuit (1) includes a photodetector D1 and a current limiting resistor R1; The positive electrode of the photodetector D1 is connected to the negative power supply VCC5V_N through the current limiting resistor R1, and the negative electrode is connected to the input end of the current-voltage conversion circuit (2).

5. The peak holding device for detecting near-infrared ultra-short wave pulse optical signals according to claim 4, characterized in that: The bias circuit (3) includes an emitter follower U2, a resistor R3, a resistor R4, a resistor R6, and a capacitor C9; The non-inverting input terminal of the emitter follower U2 is respectively connected to one end of the resistor R3 and one end of the resistor R4; the other end of the resistor R3 is connected to the power supply VCC5V; the output terminal of the emitter follower U2 is connected to its inverting input terminal and one end of the resistor R6; the other end of the resistor R6 is connected to one end of the capacitor C9, serving as the output terminal of the bias circuit (3) to be connected to the input end of the current-voltage conversion circuit (2) for outputting VCC_VREF; the other end of the resistor R4 and the other end of the capacitor C9 are grounded.

6. The peak holding device for detecting near-infrared ultra-short wave pulse optical signals according to claim 5, characterized in that: The current-voltage conversion circuit (2) includes an operational amplifier U1, a resistor R2, and a capacitor C6; The non-inverting input terminal of the operational amplifier U1 is connected to the output terminal of the bias circuit (3) for receiving VCC_VREF; the inverting input terminal is respectively connected to the negative electrode of the photodetector D1, one end of the capacitor C1, one end of the resistor R2, and one end of the capacitor C6; the output terminal of the operational amplifier U1 is respectively connected to the other end of the resistor R2, the other end of the capacitor C6, and the input end of the peak holding circuit (4) for outputting a pulse voltage signal; the other end of the capacitor C1 is grounded.

7. The peak holding device for detecting near-infrared ultra-short wave pulse optical signals according to claim 6, characterized in that: The peak holding circuit (4) includes an amplifier U3, a Schottky diode D2, a triode Q1, resistors R7, R8, R9, R10, R11, R12, R13, R14, R15, and a thin film capacitor C10; the amplifier U3 is a peak holding unit; The E terminal of the amplifier U3 is connected to the input terminal of the data acquisition circuit (5) through the resistor R14, and is used to output a widened signal; the B terminal is respectively connected to the negative electrode of the Schottky diode D2, one end of the thin film capacitor C10, and one end of the resistor R12 through the resistor R10; the positive electrode of the Schottky diode D2 is connected to the Chold terminal; the Shin+ terminal is respectively connected to one end of the resistor R7 and the output terminal of the operational amplifier U1 through the resistor R9, and is used to receive the pulse voltage signal; the Shin- terminal is connected to the pin 2 through the resistor R15 to form a feedback loop; the IQ_AD terminal is connected to the negative power supply VCC5V_N through the resistor R11, and is used to control the working current; the Hold terminal is connected to the positive power supply VCC5V_P through the resistor R8, and is used to lock the output; the base b of the triode Q1 is respectively connected to one end of the resistor R13 and the output terminal of the FPGA module (54), and is used to receive the drive signal RST_CTRL, and the collector c is connected to the other end of the resistor R12; the emitter e of the triode Q1, the C terminal of the amplifier U3, the other end of the thin film capacitor C10, the other end of the resistor R7, and the other end of the resistor R13 are grounded.

8. The peak hold device for detecting near-infrared ultra-short wave pulse optical signals according to claim 7, characterized in that: The photodetector D1 is an InGaAs photodiode; The resistance value of the resistor R3 is 22 KΩ; The resistance value of the resistor R4 is 1.5 KΩ; The model of the operational amplifier U1 is OPA659IDBVR, and the slew rate is 2550 V / μs; The model of the emitter follower U2 is AD8 ​ ​ ​ ​ 9. A method for detecting near-infrared ultra-short wave pulsed optical signals, based on the peak holding device for detecting near-infrared ultra-short wave pulsed optical signals according to any one of claims 1 to 8, characterized in that, ​ ​ ​ ​ ​ ​

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