Chip aging test method and system based on thermal migration analysis

Abstract

The invention discloses a chip aging test method based on thermal migration analysis. The method comprises the following steps: acquiring power consumption distribution data, material attribute data and manufacturing process data; discrete mapping and dynamic adjustment are carried out on the power consumption distribution data by adopting finite element network nodes to obtain an initial heat distribution diagram; processing the initial thermal distribution diagram based on a thermal imaging technology to generate a temperature mapping diagram of the surface of the chip; performing network division based on the temperature mapping graph, and generating a heat transfer path graph in combination with a gradient tracking algorithm; based on the heat transfer path diagram, screening a potential area through a preset temperature threshold value, and generating a potential heat distribution diagram through clustering analysis; performing microstructure analysis on the abnormal area according to the potential thermal distribution diagram to generate an abnormal analysis report; and solving high-temperature region distribution according to the manufacturing process data and the anomaly analysis report, and performing region analysis to generate a thermal identification report. According to the method, the problem that the heat transfer path cannot be accurately captured and the hot spot area cannot be identified under the non-destructive test can be solved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip aging testing, and particularly to a chip aging testing method and system based on thermal migration analysis. Background Art

[0002] Currently, chip aging testing mainly relies on thermal imaging technology and power consumption data analysis to track the heat transfer path inside the chip and identify hot spots. However, in the prior art, the internal structure of the chip is complex, including multiple layers of metal interconnections, insulating layers, and semiconductor materials, and the heat transfer methods in these materials are different, resulting in difficulty in accurately capturing the thermal migration path. In addition, when the chip is working, the power consumption distribution in different regions is uneven, and the dynamically changing working mode will further exacerbate the complexity of the heat distribution. The prior art cannot effectively solve this problem.

[0003] There is a problem in the prior art that the resolution of traditional thermal imaging technology is limited, which makes it difficult to capture the details of heat transfer at the microscale, resulting in deviations in the identification of hot spots. Moreover, the heat diffusion mode inside the chip is also affected by multiple factors such as material properties, structural design, and manufacturing processes. A single thermal imaging technology cannot comprehensively reveal the whole picture of heat diffusion. In addition, high-resolution thermal imaging technology has extremely high requirements for equipment accuracy and environmental stability, while microscale material analysis requires destroying the chip structure or performing complex sample preparation, which makes it difficult to combine the two in the same test process.

[0004] There is a problem in the prior art that it is impossible to accurately capture the heat transfer path inside the chip and accurately identify hot spots in non-destructive testing. Summary of the Invention

[0005] The present invention provides a chip aging testing method and system based on thermal migration analysis to solve the problem of being unable to accurately capture the heat transfer path and identify hot spots in non-destructive testing.

[0006] In a first aspect, to solve the above technical problems, the present invention provides a chip aging testing method based on thermal migration analysis, including: Obtaining the power consumption distribution data of the chip in the working state, the material property data of the chip layer structure, and the manufacturing process data of the chip; Discretely mapping the power consumption distribution data by using finite element network nodes, and iteratively adjusting based on a temperature threshold and a preset dynamic mode feedback to obtain an initial thermal distribution map of the chip surface; Performing pixel-level denoising processing on the initial thermal distribution map, enhancing the resolution through spatial interpolation and combining with a temperature gradient algorithm, and finally generating a temperature mapping map of the chip surface through color coding conversion; Based on the temperature mapping diagram, apply the Fourier heat conduction formula for finite element network division, and combine the gradient tracking algorithm to generate the heat transfer path diagram of the target chip layer; Based on the heat transfer path diagram, screen the potential area grid points through a preset temperature threshold, and determine the hot spot spatial coordinates through spatial clustering analysis to generate the potential heat distribution diagram of the potential hot spots; According to the potential heat distribution diagram, analyze and locate the highest temperature area, and conduct microstructure feature analysis on the abnormal area to generate an abnormal analysis report containing lattice defect parameters; Based on a preset material property library, solve the high-temperature area distribution according to the manufacturing process data and the abnormal analysis report, and combine the regional clustering algorithm with process defects for correlation analysis to generate a heat recognition report with a visual mapping.

[0007] Preferably, the power consumption distribution data is discretely mapped by finite element network nodes, and based on the temperature threshold and combined with a preset dynamic mode feedback iteration adjustment, the initial heat distribution diagram of the chip surface is obtained, including: Adopt the finite element analysis method to map the power consumption distribution data to the chip surface network nodes to obtain discrete power consumption data; According to the discrete power consumption data, calculate the boundary conditions by combining the frequency change parameters in the preset dynamic mode to obtain the boundary conditions; Based on the heat conduction characteristics of the chip surface, combine the power consumption distribution data and the boundary conditions, and perform heat distribution calculation through the heat conduction equation to obtain the initial heat distribution result; According to the initial heat distribution result, perform a distribution diagram generation operation to obtain the initial heat distribution diagram of the chip surface; When the initial heat distribution result is greater than the preset temperature threshold, adjust the frequency change parameters in the preset dynamic mode and recalculate the boundary conditions.

[0008] Preferably, perform pixel-level denoising processing on the initial heat distribution diagram, enhance the resolution through spatial interpolation and combine the temperature gradient algorithm, and finally generate the temperature mapping diagram of the chip surface through color coding conversion, including: Adopt high-resolution thermal imaging technology to perform pixel-level processing on the initial heat distribution diagram to obtain denoised temperature data; Adopt the interpolation algorithm to perform spatial interpolation on the denoised temperature data to obtain interpolated temperature data; According to the interpolated temperature data, combine the temperature gradient algorithm to calculate the temperature change amount of each point on the chip surface; Adopt the temperature mapping algorithm to perform color coding conversion on the temperature change amount to obtain the temperature mapping diagram of the chip surface.

[0009] Preferably, based on the temperature mapping diagram, the finite element network is divided by applying Fourier's heat conduction formula, and the heat transfer path diagram of the target chip layer is generated in combination with the gradient tracking algorithm, including: Extract discrete temperature data from the temperature mapping diagram; Extract the thermal conductivity of the target chip layer from the material property data; According to the discrete temperature data, calculate the temperature difference between adjacent regions to obtain the temperature gradient value; According to the material property data, perform a coordinate establishment operation to obtain a three-dimensional coordinate system reflecting the chip body structure; Based on Fourier's heat conduction formula, map the temperature gradient value to the three-dimensional coordinate system to obtain a heat transfer model; Set the heat flow boundary condition in the heat transfer model, and perform a network division operation on the heat transfer model based on the finite element analysis method in combination with the thermal conductivity to obtain a heat division network; Calculate the heat transfer amount in the target chip layer in the heat division network by using the heat conduction equation; Generate a temperature field distribution diagram of the target chip layer according to the transfer amount; Based on the temperature field distribution diagram, use the gradient tracking algorithm to determine the heat diffusion path in the target chip layer; According to the diffusion path, perform a path drawing operation to obtain a heat transfer path diagram of the heat in the target chip layer.

[0010] Preferably, based on the heat transfer path diagram, potential area grid points are screened by a preset temperature threshold, and the spatial coordinates of hot spots are determined through spatial clustering analysis to generate a potential heat distribution diagram of potential hot spots, including: Extract the temperature gradient value from the heat transfer path diagram; When the temperature gradient value is greater than the preset temperature threshold, mark the area corresponding to the temperature gradient value as a potential area; Perform spatial clustering analysis on the grid point coordinates corresponding to the potential area by spatial coordinates to obtain the spatial coordinates of the hot spot area; According to the spatial coordinates, perform a distribution diagram construction operation to obtain a potential heat distribution diagram of potential hot spots.

[0011] Preferably, according to the potential heat distribution diagram, analyze and locate the highest temperature area, and perform microstructural feature analysis on the abnormal area to generate an abnormal analysis report including lattice defect parameters, including: According to the potential heat distribution diagram, perform a temperature extraction operation to obtain temperature spatial data; Based on the temperature spatial data, perform gradient calculation to obtain a temperature gradient result, and extract the temperature value with the highest temperature from the temperature gradient result to obtain the highest temperature value; Determine the area corresponding to the highest temperature value as an abnormal area, and extract the characteristic numbers of the abnormal area; Process the characteristic numbers using micro-material analysis technology to obtain material characteristic data; Determine the microscopic structure characteristics of the abnormal area according to the material characteristic data; Generate an abnormal analysis report including three-dimensional coordinates of defects and material phase change characteristics based on the lattice defect density and dislocation distribution parameters in the microscopic structure characteristics.

[0012] Preferably, based on a preset material characteristic library, solve the high-temperature area distribution according to the manufacturing process data and the abnormal analysis report, and perform a correlation analysis by combining the region clustering algorithm and process defects to generate a heat recognition report with visual mapping, including: According to the abnormal analysis report, determine whether the thermal conductivity of the chip material has changed; When the thermal conductivity changes, adjust the boundary conditions by combining the preset material characteristic library to obtain an updated heat transfer equation; Solve the updated heat transfer equation to obtain updated temperature data; Extract the highest temperature value from the updated temperature data to obtain the highest updated temperature, and determine the area corresponding to the highest updated temperature as the high-temperature area; Use the region clustering algorithm to group the high-temperature areas to obtain the boundaries of the hot spot areas; Based on a preset visualization library, perform a distribution map rendering output operation on the boundaries of the hot spot areas to obtain an updated distribution map; According to the manufacturing process data and the updated distribution map, determine the correlation between the high-temperature area and process defects to obtain area abnormal characteristics; Classify the area abnormal characteristics, and generate a heat recognition report of the chip on the correlation between the hot spot area and process defects based on the distribution law of process defects.

[0013] In a second aspect, the present invention provides a chip aging test system based on heat migration analysis, including: A data acquisition module for acquiring power consumption distribution data of the chip in the working state, material property data of the chip layer structure, and manufacturing process data of the chip; A power consumption analysis module for discretely mapping the power consumption distribution data using finite element network nodes, and based on a temperature threshold and combined with preset dynamic mode feedback iteration adjustment to obtain an initial heat distribution map on the chip surface; A temperature mapping module, which is used to perform pixel-level denoising processing on the initial thermal distribution map, enhance the resolution through spatial interpolation and combine with a temperature gradient algorithm, and finally generate a temperature mapping map of the chip surface through color coding conversion; A path determination module, which is used to perform finite element network division based on the temperature mapping map by applying the Fourier heat conduction formula, and generate a heat transfer path map of the target chip layer by combining with a gradient tracking algorithm; A potential identification module, which is used to screen potential area grid points based on the heat transfer path map through a preset temperature threshold, and determine the spatial coordinates of hot spots through spatial clustering analysis to generate a potential thermal distribution map of potential hot spots; An anomaly analysis module, which is used to analyze and locate the highest temperature area according to the potential thermal distribution map, and perform microstructure feature analysis on the abnormal area to generate an anomaly analysis report containing lattice defect parameters; A report generation module, which is used to solve the high-temperature area distribution based on a preset material property library according to the manufacturing process data and the anomaly analysis report, and perform a correlation analysis on the regional clustering algorithm and process defects to generate a heat identification report with a visual mapping.

[0014] In a third aspect, the present invention further provides an electronic device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the chip aging test method based on thermal migration analysis described in any one of the above.

[0015] In a fourth aspect, the present invention further provides a computer-readable storage medium, which includes a stored computer program. When the computer program runs, it controls the device where the computer-readable storage medium is located to execute the chip aging test method based on thermal migration analysis described in any one of the above.

[0016] Compared with the prior art, the present invention has the following beneficial effects: (1) Through the dynamic adjustment of the frequency parameter triggered by the temperature threshold, the present invention realizes the real-time iterative optimization of the heat conduction equation. Combining with the gradient tracking algorithm of the three-dimensional heat conduction equation, it not only effectively captures the spatial distribution characteristics of transient heat flow, but also significantly reduces the thermal field simulation error caused by the solidification of boundary conditions in traditional methods, providing a more accurate physical model basis for the analysis of the microscopic heat accumulation effect of nanoscale chips.

[0017] (2) From the pixel-level denoising process of high-resolution thermal imaging in the present invention, to the heat transfer path tracking of the Fourier heat conduction model, and finally extending to the lattice defect detection in microscale material analysis, a complete correlation link between macroscopic thermal anomalies and microscale material failures is formed. In particular, the nested application of the spatial clustering algorithm and the process defect correlation model enables the three-dimensional coordinates of the hot spot area (such as the coordinate deviation of the metal interconnect layer) to be directly mapped to typical process defects such as lithography mask offset and uneven deposition thickness.

[0018] (3) Through the visual mapping of the thermal identification report and the interactive verification of the process parameter library, the present invention constructs a multi-dimensional database of thermodynamic properties - material properties - manufacturing processes. This technology can not only warn of early aging risks caused by electromigration and hot carrier injection (such as channel thermal degradation of FinFET devices), but also reverse-optimize key parameters such as deposition rate and annealing temperature of the sputtering process based on the lattice defect parameters in the anomaly analysis report.

[0019] In summary, the present invention can solve the problem of being unable to accurately capture the heat transfer path and identify the hot spot area under non-destructive testing. Brief Description of the Drawings

[0020] Figure 1 is a schematic flowchart of a chip aging test method based on thermal migration analysis provided by the first embodiment of the present invention; Figure 2 is a schematic structural diagram of a chip aging test system based on thermal migration analysis provided by the second embodiment of the present invention. Detailed Embodiments

[0021] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0022] Refer to Figure 1 , the first embodiment of the present invention provides a chip aging test method based on thermal migration analysis, including the following steps: S11, obtain the power consumption distribution data of the chip in the working state, the material property data of the chip layer structure, and the manufacturing process data of the chip; S12, discretely map the power consumption distribution data by using finite element network nodes, and iteratively adjust based on the temperature threshold in combination with a preset dynamic mode feedback to obtain an initial thermal distribution map of the chip surface; S13. Perform pixel-level denoising on the initial heat distribution map, enhance the resolution through spatial interpolation, and combine with the temperature gradient algorithm. Finally, generate a temperature mapping of the chip surface through color-coded conversion. S14. Based on the temperature mapping, apply the Fourier heat conduction formula for finite element network division, and combine with the gradient tracking algorithm to generate a heat transfer path map of the target chip layer. S15. Based on the heat transfer path map, screen potential area grid points through a preset temperature threshold, and determine the spatial coordinates of hot spots through spatial clustering analysis to generate a potential heat distribution map of potential hot spots. S16. According to the potential heat distribution map, analyze and locate the highest temperature area, and perform microstructure feature analysis on the abnormal area to generate an abnormal analysis report containing lattice defect parameters. S17. Based on a preset material property library, solve the high-temperature area distribution according to the manufacturing process data and the abnormal analysis report, and combine the regional clustering algorithm with process defects for correlation analysis to generate a heat recognition report with visual mapping.

[0023] In step S11, it is necessary to obtain the power consumption distribution data of the chip in the working state, the material property data of the chip layer structure, and the manufacturing process data of the chip, including: First, it is necessary to obtain the power consumption distribution data of the chip in the working state. The power consumption distribution of the chip is non-uniform among its various functional units and regions. Different load patterns (such as compute-intensive, image processing, network transmission, etc.) will cause different power consumption distributions in different parts of the chip. To accurately obtain the power consumption data of the chip in the working state, it can be measured by various means. First, dedicated power monitoring devices such as precise power meters or power consumption probes can be used to directly monitor the power consumption in various regions of the chip. For example, power consumption sensors can be installed in the main regions such as the CPU, GPU, memory controller, and I / O module respectively to collect the power consumption data of each region in real time. By recording the power consumption under different loads (such as load peak, idle state, standby mode, etc.), the power consumption distribution of the chip can be obtained comprehensively and accurately. For example, when performing image processing, the GPU will show a relatively high power consumption, while when performing text processing, the CPU is the main power consumption source.

[0024] In a specific embodiment, obtaining the material property data of the chip layer structure is an important step in thermal migration analysis. Different layers and materials of the chip play different roles in the heat transfer process. Therefore, it is necessary to understand in detail the thermal properties of each layer of material, such as thermal conductivity and specific heat capacity. The chip consists of multiple functional layers, such as metal interconnect layers, insulating layers, semiconductor materials, etc. Each layer of material has different performances in the heat conduction process. For example, copper material has a high thermal conductivity and is suitable for use as a metal interconnect layer; while materials such as silicon, aluminum, or tantalum are commonly used in different semiconductor layers or packaging layers and have different heat conduction characteristics. There are two ways to obtain the thermal data of these materials: one is to obtain the properties of these materials through the chip design documents, and the other is to verify through experimental measurement data. The specific thickness, thermal conductivity, and specific heat capacity of each layer need to be listed in detail and used in the calculation of the subsequent heat transfer model. Taking the metal layer as an example, if the thermal conductivity of copper is 400 W / m·K, while the thermal conductivity of an insulating layer such as silicon dioxide is only 1.4 W / m·K, the difference in heat transfer capacity between the two will cause heat accumulation, thus affecting the temperature distribution of the chip.

[0025] In a specific embodiment, obtaining the manufacturing process data of the chip is an essential part of realizing thermal migration analysis. The manufacturing process of the chip directly affects its heat conduction performance, especially when special materials and structures are involved. For example, with the development of semiconductor technology, more and more chips adopt 3D stacking technology or more complex packaging processes. These processes not only change the structure of the chip but also affect the heat diffusion path of the chip. In this process, the thickness of each layer, process selection (such as multi-layer metal deposition, oxidation treatment, packaging layer material, etc.), and the thermal conductivity of different packaging methods included in the manufacturing documents are all very crucial. In addition, some packaging technologies, such as flip-chip packaging, system-in-package (SiP), etc., will cause heat to accumulate in specific areas. Therefore, special attention needs to be paid to the thermal properties of the packaging materials and structures. By combining the manufacturing process data of the chip and the detailed information in the design documents, the heat transfer path of the chip under different process conditions can be accurately simulated. For example, in some high-integration chips, the interlayer thermal contact, thermal resistance, and selection of packaging materials need to be considered, which will directly affect the heat transfer efficiency from the internal layers to the surface.

[0026] In step S12, it is necessary to use the finite element network nodes to discretely map the power consumption distribution data, and based on the temperature threshold, combine the preset dynamic mode feedback iteration adjustment to obtain the initial thermal distribution map of the chip surface, including: Using the finite element analysis method, map the power consumption distribution data to the chip surface network nodes to obtain the discrete power consumption data; Calculate the boundary conditions based on the discrete power consumption data and combined with the frequency change parameters in the preset dynamic mode to obtain the boundary conditions; Based on the heat conduction characteristics of the chip surface, combined with the power consumption distribution data and the boundary conditions, perform heat distribution calculations through the heat conduction equation to obtain the initial heat distribution result; According to the initial heat distribution result, perform an operation to generate a distribution map to obtain the initial heat distribution map of the chip surface; When the initial heat distribution result is greater than the preset temperature threshold, adjust the frequency change parameters in the preset dynamic mode and recalculate the boundary conditions.

[0027] First, according to the power consumption distribution data, using the Finite Element Analysis (FEA) method, map the power consumption data to the network nodes on the chip surface. The power consumption distribution data is obtained through measurement data or simulation calculations under the chip's working state, and is represented by the power density (unit: watt per square meter) in two-dimensional or three-dimensional space. Assume the power consumption data is P(x, y), where x and y are the spatial coordinates on the chip surface. For the convenience of calculation, the chip surface needs to be discretized into multiple small grid cells, and each grid represents a region on the chip surface.

[0028] Specifically, through the finite element method, these power consumption data will be mapped to the discrete grid nodes on the chip surface. For example, if the chip surface is divided into N small cells, the power consumption Pi of each cell is assigned to the corresponding network node (xi, yi), forming a discrete power consumption data set: {P1, P2,..., PN}, and these discrete data will be used as the input for subsequent heat transfer calculations.

[0029] In a specific embodiment, calculate the boundary conditions based on the discrete power consumption data and combined with the frequency change parameters in the preset dynamic mode. The preset dynamic mode includes the power consumption change situation of the chip under different loads and working frequencies. The frequency change parameters in the dynamic mode can represent the power consumption change of the chip under different working states. For example, when the chip is in a high-load state, the core frequency is higher and the power consumption increases; while in a low-load state, the chip's frequency is lower and the power consumption is smaller.

[0030] Specifically, assume that the working state of the chip is determined by the frequency f(t) and time t, and the preset dynamic mode f(t) is a time-varying function that describes the change of the chip's working frequency with time under load. For a given frequency change f(t), the boundary conditions can be calculated through the following formula : where, is the dynamic power consumption increment (unit: watt), is the time step, is the heat capacity (unit: joules / °C). The boundary conditions represent the distribution of heat on the chip surface at a given frequency, which directly affects the heat transfer calculation.

[0031] It should be noted that in the boundary condition calculation in dynamic mode, the frequency change parameter f(t) is used as a time-varying control variable to drive the solution of the thermodynamic equation through the power consumption-frequency coupling model. Specifically, the frequency change parameter f(t) acts on the thermal boundary condition in the following way: based on the voltage-frequency curve characteristics of the chip, the discrete time step is The corresponding instantaneous frequency value Converted to dynamic power consumption increment: in, is the dynamic power consumption increment, is the process-related power coefficient, is the discrete time step The corresponding instantaneous frequency value is, is a nonlinear exponential factor, typically 1< ≤3.

[0032] For example, if a preset dynamic mode indicates that the chip's processing core will increase its operating frequency from 2.5 GHz to 3.0 GHz during peak load, the corresponding change in power consumption will affect the heat distribution and lead to changes in the heat transfer path. Based on this dynamic mode, the computational boundary conditions are adjusted to accurately simulate the thermal behavior of high-frequency operation.

[0033] Specifically, in the dynamic mode, the boundary conditions of the calculation are adjusted. First, the real-time frequency monitoring module is used to set the time step. (usually 1-10ms) to collect the instantaneous operating frequency of the chip, and then calculate the dynamic power consumption increment Calculate the instantaneous power consumption increment. After mapping the updated power consumption value to the finite element mesh node, use the iterative algorithm to recalculate the heat flow boundary conditions. The specific expression is: heat flux density = dynamic temperature gradient × thermal conductivity + frequency change rate weighted term. In view of the transient characteristics of thermal response under high-frequency conditions, the thermal relaxation time constant is introduced. The boundary temperature is corrected by low-pass filtering to suppress the numerical oscillation caused by frequency mutation. The correction coefficient is Finally, the convergence judgment module monitors the temperature difference between adjacent iteration cycles and terminates the adjustment process when the temperature fluctuation amplitude is less than the set threshold (typical value 0.5°C), thereby ensuring that the boundary condition update response time is controlled within 3 under high-frequency working conditions (such as when the frequency jump reaches 2 times the reference value). Within , the transient self-heating effect of the chip is simulated.

[0034] In a specific embodiment, after determining the boundary conditions, based on the heat conduction characteristics of the chip surface, combining the power consumption distribution data and the boundary conditions, the heat conduction equation is used to calculate the heat distribution. The heat conduction equation is based on Fourier's law and describes the process of heat propagation in materials. For heat conduction in a two-dimensional plane, it can be expressed as: where is the temperature at a certain point on the chip surface, is the thermal diffusivity, is the thermal conductivity, is the power density at this point. This equation describes how heat propagates from the inside of the chip to the surface and how it diffuses along the chip surface.

[0035] Specifically, using the finite element method (FEA), this equation can be discretized, and the temperature distribution of each grid cell on the chip surface can be calculated. By solving this equation, the temperature data of each point on the chip surface is obtained, and then an initial heat distribution map is generated. In finite element analysis, the calculation of the temperature distribution begins with dividing the chip surface into a dense grid network, and each grid node carries spatial coordinate and material property data. Based on the three-dimensional unsteady heat conduction equation, first, the partial differential equation is spatially discretized by the Galerkin weighted residual method, and the continuous temperature field is transformed into a linear system of equations of nodal temperature values. In this process, the time-varying boundary conditions driven by the dynamic frequency parameter are embedded in the global stiffness matrix and the heat load vector, where the heat flux density of the boundary nodes is dynamically corrected according to the real-time power consumption change. Subsequently, the implicit Euler method is used for time discretization, a transient solution model containing the heat capacity matrix and the thermal conductivity matrix is constructed, and the large-scale sparse linear system of equations is iteratively solved by the preconditioned conjugate gradient algorithm. When the maximum relative error of the nodal temperature between two adjacent iterations is less than one ten-thousandth, it is determined to converge. Finally, the discrete temperature data of hundreds of thousands of grid nodes are bilinearly interpolated to generate a continuous heat distribution map with sub-micron spatial resolution.

[0036] In a specific embodiment, based on the calculation results of the heat conduction equation, an initial heat distribution map of the chip surface is generated. Assume that at a certain node ( ), the temperature is , then the initial heat distribution map can be represented as a two-dimensional temperature matrix: { , ,…, } where , ,…, , Respectively represent the temperatures of various regions on the chip surface. This temperature matrix can be presented as a temperature distribution map through graphical means, and the temperature values of each region are represented by different colors. For example, high-temperature regions can be represented by red or yellow, while low-temperature regions are represented by blue or green. Through these color differences, the temperature distribution of different regions on the chip surface can be intuitively reflected.

[0037] In a specific embodiment, after the initial thermal distribution map is generated, it is necessary to check whether the temperature of any region exceeds a preset temperature threshold. This threshold is set according to factors such as the material properties of the chip, the working environment, and the heat dissipation design. For example, if the temperature threshold is set at 85°C, when the temperature of a certain region in the initial thermal distribution map exceeds this threshold, it indicates that there is an overheating problem in this region. In order to better simulate the temperature changes under different workloads and frequencies, the frequency change parameters in the preset dynamic mode need to be adjusted.

[0038] When the temperature exceeds the threshold, by adjusting the frequency change parameters (such as adjusting the operating frequency f(t)), and recalculating the boundary conditions. The adjusted frequency and power consumption changes will affect the heat transfer path and heat distribution, thereby obtaining more accurate temperature data. For example, if the operating frequency of the chip is adjusted to 3.2 GHz when the load is high, and the power consumption at this frequency will cause the temperature of some regions to be too high, the system will adjust the frequency change parameters in the preset dynamic mode to lower the frequency, so that the heat distribution is more uniform and prevent the occurrence of overheating problems.

[0039] It should be noted that in the present invention, the preset implementation of the temperature threshold can be dynamically adjusted according to the different working states, material properties, environmental conditions, and aging process of the chip. First, set the temperature threshold based on the thermal design power (TDP) of the chip. For example, for a standard silicon chip with a TDP of 95 W, the temperature threshold can be set at 85°C; for a high-performance gallium nitride chip, the temperature threshold can be set at 120°C. Secondly, according to the operating frequency and load of the chip, the temperature threshold can also change dynamically. For example, when operating at a high frequency, the temperature threshold can be increased to 90°C, while it is 85°C at the standard frequency.

[0040] In another specific embodiment, the working environment and heat dissipation design of the chip will also affect the temperature threshold. If the chip operates in a high-temperature environment (such as 50°C), the temperature threshold can be set at 80°C, while it can be appropriately increased in a low-temperature environment. In addition, considering the aging effect of the chip, the temperature threshold can be appropriately reduced after 5 years of use, for example, adjusted to 80°C, to cope with the decline in the thermal performance of the chip.

[0041] In step S13, the initial thermal distribution map needs to be subjected to pixel-level denoising, and the resolution is enhanced by spatial interpolation and combined with a temperature gradient algorithm, and finally a temperature map of the chip surface is generated by color coding conversion, including: Using high-resolution thermal imaging technology to perform pixel-level processing on the initial thermal distribution map to obtain denoised temperature data; Performing spatial interpolation on the denoised temperature data using an interpolation algorithm to obtain interpolated temperature data; Calculate the temperature change at each point on the chip surface based on the interpolated temperature data and in combination with a temperature gradient algorithm; A temperature mapping algorithm is used to perform color coding conversion on the temperature variation to obtain a temperature mapping diagram of the chip surface.

[0042] First, based on the initial thermal distribution map obtained in step S12, a mapping operation is performed using high-resolution thermal imaging technology to obtain a temperature map of the chip surface. In specific implementation, the initial thermal distribution map of the chip surface is first processed at the pixel level using a high-resolution thermal imaging device (for example, an infrared thermal imager with a resolution of up to 25µm / pixel and an accuracy of 0.05°C). During this processing, the raw thermal imaging data contains noise (such as environmental interference and equipment errors), so it needs to be denoised. Common denoising methods include smoothing the image using a Gaussian filter-based smoothing algorithm to remove temperature data anomalies caused by equipment errors or external environmental factors, thereby obtaining more accurate temperature data.

[0043] In one specific embodiment, the denoised temperature data is further processed using a spatial interpolation algorithm. Specifically, bilinear interpolation or spline interpolation can be used to apply the denoised temperature data to a higher-resolution grid, generating denser temperature data. This process aims to increase the spatial resolution of the temperature data, making temperature variations more refined. For example, if the resolution of the original thermal image is 0.5 mm / pixel, interpolation can increase it to 0.25 mm / pixel, thereby enhancing the accuracy of the temperature map.

[0044] In a specific embodiment, the temperature data obtained by interpolation is combined with a temperature gradient algorithm to perform calculations to determine the temperature change at each point on the chip surface. In a specific implementation, a discrete numerical difference method can be used to calculate the temperature gradient around each point. The temperature gradient algorithm can identify areas with more drastic temperature changes, thereby revealing hot spots on the chip surface. For example, by calculating the temperature difference between adjacent points, temperature changes greater than a set threshold are identified, thereby helping to accurately locate key areas of temperature changes on the chip surface.

[0045] In a specific embodiment, a temperature mapping algorithm is used to perform color - coding conversion on the calculated temperature change amount to generate the final temperature mapping diagram. During this process, the temperature change amount can be color - mapped according to a preset color scale (for example, the area with lower temperature is represented by blue, and the area with higher temperature is represented by red), thereby forming an intuitive temperature distribution diagram. This diagram can clearly show the temperature change trend on the chip surface and help identify potential hot - spot areas. This temperature mapping diagram can provide an important basis for subsequent heat transfer path analysis and hot - spot area identification, and help optimize the chip design and heat dissipation system.

[0046] In step S14, based on the temperature mapping diagram, the Fourier heat conduction formula is applied to perform finite - element network division, and combined with the gradient - tracking algorithm to generate the heat transfer path diagram of the target chip layer, including: Extract discrete temperature data from the temperature mapping diagram; Extract the thermal conductivity of the target chip layer from the material property data; According to the discrete temperature data, calculate the temperature difference between adjacent regions to obtain the temperature gradient value; According to the material property data, perform coordinate - establishment operations to obtain a three - dimensional coordinate system reflecting the chip body structure; Based on the Fourier heat conduction formula, map the temperature gradient value to the three - dimensional coordinate system to obtain a heat transfer model; Set the heat - flow boundary condition in the heat transfer model, and based on the finite - element analysis method combined with the thermal conductivity, perform network - division operations on the heat transfer model to obtain a heat - division network; Use the heat conduction equation to calculate the heat transfer amount in the target chip layer in the heat - division network; According to the transfer amount, generate the temperature - field distribution diagram of the target chip layer; Based on the temperature - field distribution diagram, use the gradient - tracking algorithm to determine the heat diffusion path in the target chip layer; According to the diffusion path, perform path - drawing operations to obtain the heat transfer path diagram of the heat in the target chip layer.

[0047] First, extract discrete temperature data from the temperature mapping diagram. This step converts the temperature value of each pixel point in the mapping diagram into discrete data points. Specifically, image - processing software (such as MATLAB, the OpenCV library in Python) can be used to extract data at the pixel level of the temperature mapping diagram. By performing denoising processing on the image, the existing image noise is removed to ensure that the extracted temperature data is accurate and has high precision. For example, by performing smoothing processing on the preliminarily extracted data, using Gaussian filtering to remove random noise in the image, and then using interpolation methods to obtain higher - resolution temperature data.

[0048] In a specific embodiment, the thermal conductivity of the target chip layer is extracted from the material property data. Since the thermal conductivities of different materials are different, in the thermal conduction simulation of the chip, it is necessary to accurately select the thermal conductivity according to the specific material of the chip layer. For example, the thermal conductivity of silicon is approximately 150 W / m·K, while that of copper is as high as 400 W / m·K. In actual implementation, the thermal conductivities of the materials of different layers of the chip can be obtained by referring to the material property database or through experimental measurement. The material property data can also include physical properties such as the density and specific heat of each layer, and these factors are crucial for the accurate modeling of thermal conduction.

[0049] In a specific embodiment, according to the extracted discrete temperature data, the temperature difference between adjacent regions is calculated to obtain the temperature gradient value. The temperature gradient is the core driving force of heat conduction, so this step requires accurately calculating the temperature difference between each adjacent unit and obtaining the temperature gradient based on the temperature difference. Assume that the temperature of a certain grid unit is T1 and the temperature of the adjacent unit is T2, then the temperature gradient can be calculated by the following formula: where, is the temperature gradient, and are the temperatures of the adjacent units respectively, is the distance between the units. In this way, the temperature change rates of different regions on the surface and inside the chip can be obtained, providing the necessary boundary conditions for the subsequent heat transfer process.

[0050] In a specific embodiment, a coordinate establishment operation is performed to obtain a three-dimensional coordinate system reflecting the chip body structure. Since heat conduction is a three-dimensional process, it is necessary to map the three-dimensional structure of the chip into the coordinate system. In specific implementation, a corresponding three-dimensional model can be established according to the physical size and hierarchical structure of the chip (such as metal layer, silicon layer, insulating layer, etc.). For example, each layer of the chip can be represented by a three-dimensional grid, and each grid unit represents a volume element, which can more accurately simulate the propagation of heat.

[0051] Specifically, based on the Fourier heat conduction formula, the temperature gradient value is mapped into the three-dimensional coordinate system to obtain the heat transfer model. The Fourier heat conduction equation is: where, is the heat flux density, is the thermal conductivity of the material, is the temperature gradient. By substituting the temperature gradient value into this equation, the heat flux density inside the chip can be calculated. The establishment of the heat transfer model needs to combine the thermal conductivity and temperature gradient of each grid unit to ensure that the flow of heat inside the chip is accurately simulated.

[0052] In a specific embodiment, heat flux boundary conditions are set in the heat transfer model, and the heat transfer model is subjected to a mesh division operation based on the finite element analysis method to obtain a heat division network. This process divides the three-dimensional structure of the chip into multiple small grid cells, and the amount of heat transfer within each cell is calculated through the heat conduction equation. In specific implementation, finite element analysis software (such as ANSYS, COMSOL) can be used for mesh division, and heat flux boundary conditions (such as temperature boundary, heat flux boundary, etc.) are set on each grid cell. These boundary conditions will affect the heat distribution and determine the flow direction of heat from the high-temperature region to the low-temperature region.

[0053] In a specific embodiment, the heat conduction equation is used to calculate the amount of heat transfer in the heat division network and generate a temperature field distribution map of the target chip layer. In this process, first, through numerical solution methods (such as iterative methods or direct solution methods), the heat flow within each grid cell is calculated to further deduce the temperature changes on the surface and inside the chip. The iterative method calculates repeatedly until the temperature change amount is less than a predetermined threshold, while the direct solution method obtains the temperature distribution by solving a system of linear equations. Such numerical methods can accurately simulate the propagation of heat within the chip and reflect the temperature change trends in different regions. The generation of the temperature field distribution map is a crucial step in this process, which visualizes the heat distribution and represents the temperature of different regions through color gradients. For example, regions with higher temperatures are represented in red, and regions with lower temperatures are represented in blue. In this way, designers can intuitively see the heat distribution of the chip, thereby optimizing the heat dissipation scheme targeted and identifying hot spots to avoid failures caused by overheating or thermal stress of the chip.

[0054] In a specific embodiment, based on the temperature field distribution map, the gradient tracking algorithm is used to further determine the diffusion path of heat in the target chip layer. The core idea of the gradient tracking algorithm is to determine the diffusion direction of heat according to the regions with larger gradients in the temperature field. Because the larger the temperature gradient, the greater the heat flux density, and thus the main path of heat flow points to the region with a larger temperature difference. Through this algorithm, the propagation path of heat can be accurately tracked, and the process of heat flowing from the high-temperature region to the low-temperature region can be identified. In specific implementation, the temperature gradient of each region can be calculated, and the region with the largest gradient is selected as the preferred path of heat flow. On this basis, by gradually tracking and connecting the paths with larger temperature gradients, the main channel of heat diffusion can be formed, and through the accurate tracking of the path, it is ensured that the simulated heat transfer process is consistent with the actual situation.

[0055] In a specific embodiment, according to the heat diffusion path, a path drawing operation is performed to obtain a heat transfer path diagram of the target chip layer. The core of this step is to visualize the heat diffusion path determined by the gradient tracking algorithm, thereby forming a heat transfer path diagram. Through path drawing, a clear and intuitive graph is finally generated to show the specific route of heat flow inside the chip. In actual operation, computer graphics software (such as MATLAB, Python, etc.) can be used to perform the path drawing operation. Combining with the temperature field distribution diagram, the path of heat flow can be clearly marked. This diagram not only reveals the heat flow trajectory inside the chip, but also helps designers accurately identify potential hot spots. In the design, this graph is an important reference for optimizing the heat dissipation design. It can help engineers identify the areas where heat accumulates, and then adjust the chip layout, heat dissipation materials or install heat sinks, etc., to optimize the overall thermal management. Through such optimization, not only can the performance stability of the chip be improved, but also its service life can be effectively extended, and chip damage or performance degradation caused by overheating can be reduced.

[0056] In step S15, it is necessary to screen potential area grid points based on the heat transfer path diagram, and determine the spatial coordinates of hot spots through spatial clustering analysis to generate a potential heat distribution diagram of potential hot spots, including: Extract the temperature gradient values in the heat transfer path diagram; When the temperature gradient value is greater than the preset temperature threshold, mark the area corresponding to the temperature gradient value as a potential area; Perform spatial clustering analysis on the grid point coordinates corresponding to the potential area to obtain the spatial coordinates of the hot spot area; According to the spatial coordinates, perform a distribution diagram construction operation to obtain a potential heat distribution diagram of potential hot spots.

[0057] First, it is necessary to extract the temperature gradient value of each area from the heat transfer path diagram. The temperature gradient value can help identify the areas where the heat change is more obvious, and these areas are potential hot spots. The larger the temperature gradient, the greater the heat transfer speed and intensity in this area, which will cause local overheating. The extraction of the temperature gradient value can be obtained by calculating the temperature values of each grid cell in the heat transfer path diagram.

[0058] In a specific embodiment, during the implementation process, first perform a high-resolution grid division on the chip surface so that the temperature values in each grid cell can be clearly recorded. Through numerical calculation, the temperature difference between adjacent cells of each grid cell is the temperature gradient value. For example, the temperature in the central area of the chip is 90°C, and the temperature in the adjacent surrounding area is 80°C, then the temperature gradient value is 10°C. For such areas with large differences, special attention should be paid to determine whether they belong to potential hot spots.

[0059] In another specific embodiment, thermal imaging technology can be combined to obtain the temperature distribution map of the chip surface. In image processing, the temperature gradient can be directly extracted through color differences. For example, in the area where the color changes rapidly on the thermal imaging map, such as the transition area from red to blue, the temperature gradient value can be directly calculated through an algorithm, and the heat flow in these areas can be further analyzed.

[0060] Next, when the extracted temperature gradient value exceeds the preset temperature threshold, the corresponding area is marked as a potential hot spot area. The setting of the preset temperature threshold should consider factors such as the operating temperature of the chip and material properties. If the temperature threshold is too low, potential hot spots may be missed; if it is too high, irrelevant areas may be mislabeled. Therefore, it is crucial to set the temperature threshold reasonably. Under different application scenarios, the upper temperature limit of the chip is different, so it should be adjusted according to actual needs.

[0061] In a specific embodiment, if the upper limit of the chip's operating temperature is 85°C and the preset temperature threshold is 85°C. If the temperature gradient value of a certain grid unit is greater than this threshold, it is considered that there is a large heat flow in this area, which belongs to the potential hot spot area. For example, during high-speed operation, when the temperature gradient around the processor is greater than the preset value, the system automatically marks this area as a potential hot spot.

[0062] In another specific embodiment, the temperature threshold can be set dynamically. For example, when dealing with different power consumption working states of the chip, the set temperature threshold will change with the actual load. For example, the threshold in the idle mode can be set to 75°C, while in the high-load mode, the threshold can be increased to 95°C. In this way, the system can identify different potential hot spot areas according to different working states, avoiding omissions.

[0063] Specifically, through spatial clustering analysis, the areas marked as potential hot spots are clustered to identify the concentrated heat areas on the chip surface. Spatial clustering analysis can effectively identify multiple scattered hot spot areas on the chip surface and merge them into an overall heat area for subsequent heat dissipation design. Commonly used clustering algorithms include the K-means clustering algorithm and the DBSCAN density clustering algorithm, which can effectively process hot spot areas with different densities.

[0064] In a specific embodiment, the K-means algorithm is used to perform spatial clustering on the marked potential hot spots. The K-means algorithm will automatically identify the spatial coordinates of the hot spots on the chip surface according to the pre-set clustering centers, and multiple small hot spot regions will be merged into a larger hot spot region. Suppose on a certain high-performance processor chip, multiple small areas with relatively high temperatures gather near the central processing unit (CPU). The K-means algorithm will automatically identify these areas as a main hot spot area, facilitating subsequent analysis and optimization.

[0065] In another specific embodiment, in another implementation, the DBSCAN algorithm is used for clustering analysis, which is particularly suitable for dealing with the situation of uneven hot spot distribution. DBSCAN does not require setting the number of clusters in advance, but automatically determines the number and distribution of hot spot regions according to density. In some cases, the hot spot regions on the chip surface are relatively scattered, and DBSCAN can handle this situation more flexibly and accurately identify different heat source regions.

[0066] Specifically, according to the results of spatial clustering analysis and in combination with the spatial coordinates of the potential hot spot regions, a potential heat distribution map is constructed. The potential heat distribution map helps designers intuitively understand the heat conditions on and inside the chip surface by visualizing the hot spot regions. A common display method is through color coding, where regions with higher temperatures are displayed in red, colder regions are displayed in blue, and regions with medium temperatures can be displayed in yellow or green.

[0067] In a specific embodiment, assume that after spatial clustering, multiple regions with relatively high temperatures on the chip are marked as hot spot regions and displayed in the potential heat distribution map. The regions around the hot spot regions can be displayed in red, while the relatively colder regions are displayed in blue. Through the color difference, designers can intuitively identify the areas on the chip surface that most need optimization.

[0068] In another specific embodiment, in addition to the two-dimensional potential heat distribution map, a three-dimensional heat map is also an effective display method. The three-dimensional heat map can display the temperature gradient of each region on the chip surface. Through 3D visualization, designers can clearly understand the heat distribution of the chip at different levels, helping to identify the temperature concentration areas inside the chip. Especially for multi-layer chip structures or heterogeneous chip systems, the three-dimensional heat map can provide more intuitive thermal management information.

[0069] In step S16, it is necessary to analyze and locate the region with the highest temperature according to the potential heat distribution map, and perform microstructure feature analysis on the abnormal region to generate an abnormal analysis report including lattice defect parameters, including: According to the potential heat distribution map, perform a temperature extraction operation to obtain temperature spatial data; Performing gradient calculation based on the temperature spatial data to obtain a temperature gradient result, and extracting the highest temperature value from the temperature gradient result to obtain a maximum temperature value; Determine the area corresponding to the highest temperature value as an abnormal area, and extract characteristic numbers of the abnormal area; Processing the characteristic data using microscopic material analysis technology to obtain material characteristic data; determining the microstructural characteristics of the abnormal region based on the material characteristic data; Based on the lattice defect density and dislocation distribution parameters in the microstructure characteristics, an abnormality analysis report including the three-dimensional coordinates of the defects and the phase transition characteristics of the material is generated.

[0070] First, based on the underlying thermal map, specific temperature data must be extracted from the map to create a complete spatial temperature dataset. This spatial temperature dataset includes temperature values for various regions of the chip at different time points. To ensure data accuracy, temperature extraction should be performed using a high-precision algorithm, and the thermal map should be interpolated to obtain finer-grained temperature data. This dataset can be a two-dimensional or three-dimensional array containing the temperature value for each grid cell, depending on the complexity of the chip.

[0071] In a specific embodiment, assuming a two-dimensional heat transfer model is used for the chip, the temperature spatial data extracted from the potential thermal distribution map forms a two-dimensional matrix, where the value of each cell represents the temperature at that location. Numerical interpolation algorithms (such as bilinear interpolation or cubic spline interpolation) can be used to smoothly transition temperatures between grid cells, ensuring the accuracy of the temperature spatial data.

[0072] In another specific embodiment, if the chip is a three-dimensional structure, the temperature spatial data will include the temperature values of each chip layer and each surface unit. In this case, during the processing process, numerical calculation techniques based on the finite element method can be used to process the three-dimensional temperature spatial data to provide accurate temperature values within each small interval, ensuring data accuracy and integrity.

[0073] After obtaining the temperature spatial data, it is necessary to calculate the temperature gradient. The temperature gradient reflects the rate of temperature change and can help identify areas with the most dramatic temperature changes, which are hot spots where abnormalities occur. The temperature gradient can be calculated using the following formula: in, represents the temperature gradient, represents the temperature difference between adjacent areas, Represents the distance between these areas.

[0074] In one specific embodiment, the temperature difference between each grid cell and its adjacent cells on the chip surface can be calculated to generate a temperature gradient. Larger temperature gradients occur in the chip's central processing unit (CPU) or other high-power areas. For example, if the CPU area of the chip is hotter and the surrounding areas are cooler, the temperature gradient in that area will be larger.

[0075] In another specific embodiment, if localized heat concentrations occur on the chip surface, temperature gradient calculations can help identify these areas. For example, if the temperature gradient value at a certain location on the chip surface exceeds a certain threshold, it can be considered that the area has abnormal heat distribution and requires further analysis.

[0076] By calculating the temperature gradient, we can further extract the hottest areas within the temperature gradient results. This process first identifies the areas with the most dramatic temperature changes using the temperature gradient map. Based on this information, we then determine the areas with the highest temperature values. These highest temperature values represent the core locations of heat accumulation, and these areas are potential anomalies where heat concentration occurs due to design flaws, material inhomogeneities, or heat dissipation issues.

[0077] In a specific embodiment, suppose a grid cell in a temperature gradient map has a temperature gradient value as high as 20°C / mm. This high gradient value indicates that there is a large amount of heat accumulation in that area. In this case, the grid cell and its adjacent cells can be marked as an abnormal area. Further extracting the temperature value of this area, if the temperature reaches or exceeds 90°C, the area can be determined to be an abnormal area.

[0078] In another specific embodiment, a temperature threshold is set based on the thermal distribution characteristics of each region on the chip for screening. For example, the temperature threshold is set to 100°C. If the temperature value of a region in the calculated temperature gradient map is higher than this threshold, the region is marked as a potential abnormal region.

[0079] Once the potential abnormal area is identified, the next step is to further analyze the material properties of that area using microscopic material analysis techniques. Microscopic material analysis techniques include microscopy, scanning electron microscopy (SEM), and X-ray diffraction (XRD). These techniques can penetrate the microstructure of the chip and help identify material defects, changes in the lattice structure, or uneven thermal conductivity.

[0080] In one specific embodiment, during implementation, the portion marked as abnormal is observed using a scanning electron microscope to analyze the microscopic lattice structure of the region. If irregular lattice arrangement or material defects (such as cracks or voids) are found in the region, these can be further confirmed as the root cause of the heat accumulation.

[0081] In another specific embodiment, the crystalline structure of the chip material is analyzed by X-ray diffraction to check whether there is uneven crystallization in the material of this area, or whether there are material defects caused by process problems. These defects affect the heat conduction performance of the chip and lead to local overheating.

[0082] After obtaining the characteristic values of the abnormal area through micro-material analysis technology, further analyze the microscopic structure characteristics of this area based on the obtained material characteristic data. By comparing the microscopic structure differences between the normal area and the abnormal area, the specific reasons for heat accumulation can be inferred, and finally a detailed abnormal analysis report is generated. The report should include the temperature distribution of the abnormal area, the analysis results of material defects, and optimization suggestions.

[0083] In a specific embodiment, the analysis report will include the temperature data of each area of the chip, the spatial coordinates of the abnormal area, and the analysis results of material characteristics (such as crystal defects, uneven thermal conductivity, etc.). The report should also put forward improvement suggestions, such as increasing heat dissipation channels, optimizing material selection, etc. The abnormal analysis report can include a thermal management plan for a specific abnormal area. For example, for a certain high-temperature area found, the report can recommend adding a local radiator or using different heat dissipation materials to reduce the temperature of this area and prevent overheating from having an adverse effect on the chip performance.

[0084] In step S17, it is necessary to solve the high-temperature area distribution based on a preset material characteristic library according to the manufacturing process data and the abnormal analysis report, and conduct a correlation analysis by combining the regional clustering algorithm with process defects to generate a heat recognition report with visual mapping, including: According to the abnormal analysis report, judge whether the thermal conductivity of the chip material has changed; When the thermal conductivity changes, adjust the boundary conditions in combination with the preset material characteristic library to obtain an updated heat transfer equation; Solve the updated heat transfer equation to obtain updated temperature data; Extract the highest temperature value from the updated temperature data to obtain the highest updated temperature, and determine the area corresponding to the highest updated temperature as the high-temperature area; Use the regional clustering algorithm to group the high-temperature areas to obtain the boundary of the hot spot area; Based on the preset visualization library, perform a distribution map rendering output operation on the boundary of the hot spot area to obtain an updated distribution map; According to the manufacturing process data in combination with the updated distribution map, determine the correlation between the high-temperature area and process defects to obtain the regional abnormal characteristics; Classify the abnormal features of the said area, and generate a thermal identification report of the chip on the correlation between the hot spot area and process defects based on the distribution law of process defects.

[0085] First, based on the hot spot area extracted from the abnormal analysis report, determine whether there is a change in the thermal conductivity of the chip material. The thermal conductivity of the chip material directly affects the heat transfer efficiency. Therefore, a change in thermal conductivity means defects or changes during the manufacturing process. For example, certain materials undergo physical property changes due to uneven cooling or external forces applied. To determine the change in thermal conductivity, the system will extract the physical properties of the material and compare them with the standard data in the preset material property library. If the thermal conductivity changes, subsequent heat transfer path corrections are required.

[0086] In a specific embodiment, assume that during the manufacturing process, the thermal conduction material of the chip is subjected to external pressure, resulting in a slight structural change, which causes a decrease in the thermal conductivity of a local area. In this case, by comparing the thermal conductivity of this area with the standard value in the material library, the system confirms that the thermal conductivity of this area has decreased.

[0087] In another specific embodiment, if different batches of thermal conductive materials are used in the chip during the manufacturing process and there are differences in their thermal conductivities, the system will compare the thermal conductivity of the current material with the standard library. If areas with lower thermal conductivity are found, it means that the heat dissipation efficiency of these areas is poor and the heat transfer model needs to be further corrected.

[0088] After confirming that there is a change in the thermal conductivity of the chip material, the boundary conditions in the heat transfer model must be adjusted according to this change. Boundary conditions determine the path and efficiency of heat flow, so they play a crucial role in the heat conduction model. When updating the boundary conditions, the system will adjust the thermal conductivity value of the corresponding area according to the change in the material's thermal conductivity to ensure that the heat transfer equation can accurately reflect the heat flow situation within the chip.

[0089] In a specific embodiment, assume that the thermal conductivity of a certain area decreases, which means that the heat transfer efficiency of this area weakens. Therefore, the system needs to adjust the thermal conductivity coefficient of this area. The adjusted heat transfer equation will reflect the heat accumulation in this area, and during the heat propagation process, the temperature rise rate in this area will accelerate. The adjusted equation will provide a basis for subsequent temperature calculations.

[0090] In another specific embodiment, if a new thermal conductive layer is used at certain positions on the chip and the thermal conductivity of this layer is higher than that of other areas, the system will update the thermal conductivity of this layer in the heat transfer equation. Through this adjustment, more heat will be transferred through this thermal conductive layer, thus affecting the distribution of the overall temperature field.

[0091] After updating the heat transfer equation, the next step is to solve the updated equation to obtain the latest temperature data of the chip. This process requires the use of numerical calculation methods, such as finite element analysis (FEA) or finite difference method (FDM), to mesh the chip surface and its interior, and gradually calculate the temperature in each mesh cell. The updated temperature data will more accurately reflect the heat distribution of the chip during actual operation, especially the heat accumulation in high-temperature regions.

[0092] In a specific embodiment, after the thermal conductivity of a certain region is updated to be lower, when using the finite element method to solve the heat transfer equation, the temperature value of this region will be higher, indicating that heat accumulates here. Through the finite element method, the temperature distribution of this region can be accurately solved, and the temperature data of each mesh cell can be obtained, thereby obtaining the overall temperature field of the chip.

[0093] In another specific embodiment, if the change in the thermal conductivity of the chip causes the heat transfer efficiency of multiple regions to change, then when using the difference method to solve the updated heat transfer equation, more detailed temperature distribution data can be obtained. Through numerical solution methods, the system can accurately predict the temperature change trend of each region and provide data support for subsequent hot spot identification.

[0094] After obtaining the updated temperature data, the system needs to extract the highest temperature value from these data and determine the region corresponding to this highest temperature value. This step is crucial for judging potential hot spot regions. The region corresponding to the highest temperature value is the hot spot region of the chip. The system will determine the high-temperature regions based on these highest temperature values and use them as the key regions for subsequent heat conduction analysis.

[0095] In a specific embodiment, for example, in the updated temperature data, the temperature of a certain region reaches 180°C, while the temperature of other regions is only below 100°C. At this time, the region with a temperature of 180°C will be marked as a high-temperature region and used as the object for subsequent clustering analysis.

[0096] In another specific embodiment, if the temperature in some regions exceeds a preset high-temperature threshold (such as 150°C), the system will automatically mark these regions as high-temperature regions. These high-temperature regions will be further analyzed to determine whether they are associated with manufacturing process defects.

[0097] After determining the high-temperature regions, use the region clustering algorithm to group these high-temperature regions. Through the region clustering algorithm, the system can identify the spatial relationship between high-temperature regions and accurately mark the boundaries of the regions where heat is concentrated. This algorithm can effectively demarcate the regions where heat is concentrated as hot spot regions and provide data support for subsequent heat dissipation design and thermal management.

[0098] In a specific embodiment, in the heat data of the chip, it is found that the temperatures of multiple adjacent regions are relatively high. By using the K-means clustering algorithm, these regions can be clustered into a hot spot region, and the boundary of this region can be generated. This provides crucial thermal distribution information for subsequent designs.

[0099] In another specific embodiment, a density-based clustering algorithm (such as DBSCAN) is used. By analyzing the density distribution of the temperature data, the boundaries of the high-temperature regions are automatically identified. This method does not require pre-setting the number of clusters but adjusts automatically according to the data, thus providing a more flexible hot spot region identification scheme.

[0100] After clustering analysis, the system can generate an updated temperature distribution map, mark the regions with concentrated heat as high-temperature regions, and render the boundaries of these regions. This distribution map not only shows the temperature changes within the chip but also visually displays the positions of the high-temperature regions, providing crucial reference for the heat dissipation design of the chip. Through color coding, the regions with high temperature can be marked as red, and the low-temperature regions as blue. In this way, designers can quickly identify the regions that need to be optimized and formulate corresponding heat dissipation measures.

[0101] In a specific embodiment, through clustering analysis, multiple high-temperature regions in a certain area are identified as a hot spot region. In the updated distribution map generated by the system, the hot spot region is rendered as red and clearly marked in the map. This information will guide the heat dissipation designers to optimize the heat dissipation system in this region and avoid chip damage caused by overheating.

[0102] In another specific embodiment, the system identifies multiple local hot spot regions through an automatic clustering algorithm and generates an updated distribution map based on this information. This map uses color gradients to show different temperature regions, with the high-temperature areas represented by bright red. In this way, designers can effectively evaluate the effectiveness of the chip thermal management and adjust the heat dissipation system.

[0103] After generating the updated temperature distribution map and calibrating the hot spot regions, it is then necessary to analyze whether these hot spot regions are associated with manufacturing process defects of the chip. By combining the manufacturing process data with the updated temperature distribution map, the system can determine whether the generation of the high-temperature regions is related to process defects (such as welding problems, material non-uniformity, process deviations, etc.).

[0104] Specifically, based on the manufacturing process data of the chip, including material batches, processing parameters, temperature control processes, etc., the system can compare with the hot spots in the temperature distribution map. By analyzing the historical data of the hot spots, the system will identify whether these areas have been subjected to improper process treatment during the manufacturing process. For example, a local overheating occurs in a certain area due to inaccurate temperature control in the welding process, thus forming a hot spot. The system can also confirm whether these high-temperature areas are related to certain specific process steps through historical comparison with the process data.

[0105] In a specific embodiment, assume that a relatively high welding temperature is used during the production of a certain batch of chips, resulting in an increase in temperature in a local area. By combining the process data and the updated temperature distribution map, the system can analyze the direct correlation between these overheated areas and the temperature control error of the welding process. By further optimizing the welding process, the generation of such hot spots can be avoided.

[0106] In another specific embodiment, the temperature distribution map of the chip shows that there is abnormally high temperature at a certain position, while the process data indicates that different batches of thermal conductive materials are used at this position. After system analysis, it is determined that the thermal conductivity of this material is poor, resulting in heat accumulation in this area.

[0107] After completing the above steps, the system will generate a thermal identification report for the chip based on the correlation between the high-temperature areas and the process defects. The report not only details the hot spots existing in the chip but also points out the relationship between these hot spots and specific manufacturing process defects. This information will help engineers, designers, and manufacturers identify potential problems and optimize the heat dissipation system or process flow of the chip.

[0108] Specifically, the content of the report can include: Detailed description of the hot spots: including the location, temperature value, and temperature gradient of each hot spot area.

[0109] Correlation analysis between process defects and hot spots: Details the relationship between the hot spot areas and manufacturing processes (such as welding temperature, material selection, etc.).

[0110] Optimization suggestions: Based on the identified hot spot areas and process defects, give suggestions for improving the manufacturing process, materials, or heat dissipation design.

[0111] In another specific embodiment, assume that the system identifies heat accumulation at a certain position on the chip surface caused by the welding process. The report will detail the location of this hot spot area and its temperature data, compare it with the temperature control in the welding process, and finally put forward optimization suggestions, such as reducing the welding temperature or improving the thermal conductivity of the material.

[0112] In another specific embodiment, the system discovers that the high temperature in a certain area of the chip is related to the uneven distribution of the thermal conductive material. The report will point out the temperature distribution characteristics of this area and recommend using a more uniform thermal conductive material to solve this problem, ultimately improving the heat dissipation efficiency of the chip.

[0113] In summary, the present invention discloses a method for chip aging test based on thermal migration analysis. By comprehensively applying power consumption distribution data, high-resolution thermal imaging technology, microscopic material analysis technology, and heat conduction models, it accurately tracks the heat transfer path inside the chip and identifies potential hot spots. First, by obtaining the power consumption distribution data of the chip in the working state and combining with the dynamic mode to generate an initial thermal distribution map, the diffusion of heat on the chip surface is accurately simulated; then, high-resolution thermal imaging technology is used to generate a temperature mapping map, and combined with material property data, the heat transfer path is further determined. Subsequently, based on the transfer path map, potential hot spots are identified, and the structural characteristics of the abnormal area are further analyzed through microscopic material analysis technology to form a detailed abnormal analysis report. Finally, by combining manufacturing process data and material property libraries, the heat transfer path is corrected and process analysis is carried out, and finally a thermal identification report of the chip is generated.

[0114] Compared with the prior art, the present invention provides a non-destructive method for chip aging test, which can capture the details of heat transfer at the microscopic scale, overcoming the disadvantages of low resolution and difficulty in accurately identifying hot spots of traditional thermal imaging technology. By combining a variety of advanced technologies, the present invention can provide comprehensive heat analysis results, thereby effectively predicting potential problems during the chip aging process and improving the reliability and accuracy of chip testing.

[0115] The present invention can solve the problem of being unable to accurately capture the heat transfer path and identify hot spots under non-destructive testing.

[0116] Referring to Figure 2 , the second embodiment of the present invention provides a chip aging test system based on thermal migration analysis, including: A data acquisition module, configured to acquire the power consumption distribution data of the chip in the working state, the material property data of the chip layer structure, and the manufacturing process data of the chip; A power consumption analysis module, configured to discretely map the power consumption distribution data by using finite element network nodes, and based on a temperature threshold and combined with a preset dynamic mode, perform feedback iteration adjustment to obtain an initial thermal distribution map of the chip surface; A temperature mapping module, configured to perform pixel-level denoising processing on the initial thermal distribution map, enhance the resolution through spatial interpolation and combine with a temperature gradient algorithm, and finally generate a temperature mapping map of the chip surface through color coding conversion; A path determination module, configured to perform finite element network partitioning based on the temperature mapping diagram by applying Fourier's heat conduction formula, and generate a heat transfer path diagram of the target chip layer in combination with a gradient tracking algorithm; A potential identification module, configured to screen potential regional grid points based on the heat transfer path diagram through a preset temperature threshold, and determine the spatial coordinates of hot spots through spatial clustering analysis to generate a potential heat distribution diagram of potential hot spots; An anomaly analysis module, configured to analyze and locate the highest temperature region according to the potential heat distribution diagram, and perform microstructure feature analysis on the abnormal region to generate an anomaly analysis report including lattice defect parameters; A report generation module, configured to solve the high-temperature region distribution based on a preset material property library according to the manufacturing process data and the anomaly analysis report, and perform a correlation analysis on the regional clustering algorithm and process defects to generate a heat identification report with a visual mapping;

[0117] It should be noted that a chip aging test system based on heat migration analysis provided by an embodiment of the present invention is used to execute all process steps of a chip aging test method based on heat migration analysis in the above embodiment. The working principles and beneficial effects of the two correspond one by one, and thus will not be elaborated here.

[0118] An embodiment of the present invention further provides an electronic device. The electronic device includes: a processor, a memory, and a computer program stored in the memory and executable on the processor, such as a path determination program. When the processor executes the computer program, the steps in the above-mentioned embodiments of the chip aging test method based on heat migration analysis are implemented, such as Figure 1 Step S11 shown. Alternatively, when the processor executes the computer program, the functions of each module / unit in the above-mentioned device embodiments are implemented, such as the anomaly analysis module.

[0119] Exemplarily, the computer program can be divided into one or more modules / units. The one or more modules / units are stored in the memory and executed by the processor to complete the present invention. The one or more modules / units can be a series of computer program instruction segments capable of performing specific functions, and the instruction segments are used to describe the execution process of the computer program in the electronic device.

[0120] The electronic device can be a computing device such as a desktop computer, notebook, handheld computer, and smart tablet, etc. The electronic device may include, but is not limited to, a processor and a memory. Those skilled in the art can understand that the above components are only examples of the electronic device and do not constitute a limitation on the electronic device. It may include more or fewer components than the above, or combine some components, or different components. For example, the electronic device may also include input / output devices, network access devices, buses, etc.

[0121] The so-called processor can be a central processing unit (CPU), or can also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The processor is the control center of the electronic device and connects various parts of the entire electronic device through various interfaces and circuits.

[0122] The memory can be used to store the computer programs and / or modules. The processor realizes various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory, and by calling the data stored in the memory. The memory may mainly include a program storage area and a data storage area. Among them, the program storage area can store an operating system, application programs required for at least one function (such as a sound playback function, an image playback function, etc.); the data storage area can store data created according to the use of the mobile phone (such as audio data, phone book, etc.). In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as a hard disk, memory, plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, at least one magnetic disk storage device, flash device, or other volatile solid-state storage devices.

[0123] Among them, if the modules / units integrated in the electronic device are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, to implement all or part of the processes in the above-described embodiment methods of the present invention, it can also be completed by a computer program instructing relevant hardware. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps of the above-described various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file, or some intermediate form, etc. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice within the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0124] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in the attached drawings of the device embodiments provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, which can be specifically implemented as one or more communication buses or signal lines. Those of ordinary skill in the art can understand and implement it without creative efforts.

[0125] The above-described specific embodiments have further elaborated on the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only the specific embodiments of the present invention and is not used to limit the protection scope of the present invention. It is particularly pointed out that for those skilled in the art, any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A chip aging test method based on thermal migration analysis, characterized in that Including: Obtain the power consumption distribution data of the chip in the working state, the material property data of the chip layer structure, and the manufacturing process data of the chip; Discretely map the power consumption distribution data using finite element network nodes, and based on the temperature threshold, combine with the preset dynamic mode feedback iteration adjustment to obtain the initial thermal distribution map of the chip surface; Perform pixel-level denoising processing on the initial thermal distribution map, enhance the resolution through spatial interpolation, and combine with the temperature gradient algorithm to generate the temperature mapping map of the chip surface; Based on the temperature mapping map, apply the Fourier heat conduction formula for finite element network division, and combine with the gradient tracking algorithm to generate the heat transfer path map of the target chip layer; Based on the heat transfer path map, screen the potential area grid points through the preset temperature threshold, and determine the hot spot spatial coordinates through spatial clustering analysis to generate the potential thermal distribution map of the potential hot spots; According to the potential thermal distribution map, analyze and locate the highest temperature area, and perform microstructure feature analysis on the abnormal area to generate an abnormal analysis report; Based on the preset material property library, solve the high-temperature area distribution according to the manufacturing process data and the abnormal analysis report, and combine with the regional clustering algorithm and process defects for correlation analysis to generate a heat recognition report with visual mapping; 2. The chip aging test method based on thermal migration analysis according to claim 1, wherein The step of discretely mapping the power consumption distribution data using finite element network nodes, and based on the temperature threshold, combining with the preset dynamic mode feedback iteration adjustment to obtain the initial thermal distribution map of the chip surface includes: Using the finite element analysis method, map the power consumption distribution data to the chip surface network nodes to obtain discrete power consumption data; According to the discrete power consumption data, calculate the boundary conditions by combining the frequency change parameters in the preset dynamic mode to obtain the boundary conditions; Based on the heat conduction characteristics of the chip surface, combine the power consumption distribution data and the boundary conditions, and perform heat distribution calculation through the heat conduction equation to obtain the initial heat distribution result; According to the initial heat distribution result, perform a distribution map generation operation to obtain the initial thermal distribution map of the chip surface; When the initial heat distribution result is greater than the preset temperature threshold, adjust the frequency change parameters in the preset dynamic mode and recalculate the boundary conditions.

3. The chip aging test method based on thermal migration analysis according to claim 1, wherein The step of performing pixel-level denoising processing on the initial thermal distribution map, enhancing the resolution through spatial interpolation, and combining with the temperature gradient algorithm, and finally generating the temperature mapping map of the chip surface through color coding conversion includes: Using high-resolution thermal imaging technology to perform pixel-level processing on the initial thermal distribution map to obtain denoised temperature data; Using the interpolation algorithm to perform spatial interpolation on the denoised temperature data to obtain interpolated temperature data; According to the interpolated temperature data, combine with the temperature gradient algorithm to calculate the temperature change amount of each point on the chip surface; Using the temperature mapping algorithm to perform color coding conversion on the temperature change amount to obtain the temperature mapping map of the chip surface.

4. The chip aging test method based on thermal migration analysis according to claim 1, wherein The step of based on the temperature mapping map, applying the Fourier heat conduction formula for finite element network division, and combining with the gradient tracking algorithm to generate the heat transfer path map of the target chip layer includes: Extract discrete temperature data from the temperature mapping map; Extract the thermal conductivity of the target chip layer from the material property data; Calculate the temperature difference between adjacent regions based on the discrete temperature data to obtain a temperature gradient value; Perform a coordinate establishment operation based on the material property data to obtain a three-dimensional coordinate system reflecting the chip body structure; Map the temperature gradient value to the three-dimensional coordinate system based on the Fourier heat conduction formula to obtain a heat transfer model; Set a heat flux boundary condition in the heat transfer model, and perform a mesh division operation on the heat transfer model based on the finite element analysis method in combination with the thermal conductivity to obtain a heat division network; Calculate the amount of heat transfer in the target chip layer in the heat division network using the heat conduction equation; Generate a temperature field distribution map of the target chip layer according to the transfer amount; Based on the temperature field distribution map, use the gradient tracking algorithm to determine the diffusion path of heat in the target chip layer; Perform a path drawing operation according to the diffusion path to obtain a heat transfer path map of heat in the target chip layer.

5. The chip aging test method based on thermal migration analysis according to claim 1, wherein Based on the heat transfer path map, screen potential area grid points through a preset temperature threshold, and determine the spatial coordinates of hot spots through spatial clustering analysis to generate a potential heat distribution map of potential hot spots, including: Extract the temperature gradient value from the heat transfer path map; When the temperature gradient value is greater than the preset temperature threshold, mark the area corresponding to the temperature gradient value as a potential area; Perform spatial clustering analysis on the grid point coordinates corresponding to the potential area to obtain the spatial coordinates of the hot spot area; Perform a distribution map construction operation according to the spatial coordinates to obtain a potential heat distribution map of potential hot spots.

6. The chip aging test method based on thermal migration analysis according to claim 1, characterized in that According to the potential heat distribution map, analyze and locate the highest temperature area, and perform a microstructure feature analysis on the abnormal area to generate an abnormal analysis report including lattice defect parameters, including: Perform a temperature extraction operation according to the potential heat distribution map to obtain temperature spatial data; Perform a gradient calculation according to the temperature spatial data to obtain a temperature gradient result, and extract the highest temperature value from the temperature gradient result to obtain the highest temperature value; Determine the area corresponding to the highest temperature value as an abnormal area, and extract the characteristic numbers of the abnormal area; Process the characteristic numbers using a microscopic material analysis technique to obtain material characteristic data; Determine the microstructure characteristics of the abnormal area according to the material characteristic data; Generate an abnormal analysis report including the three-dimensional coordinates of defects and material phase change characteristics according to the lattice defect density and dislocation distribution parameters in the microstructure characteristics.

7. The chip aging test method based on thermal migration analysis according to claim 1, wherein Based on a preset material property library, solve the high-temperature area distribution according to the manufacturing process data and the abnormal analysis report, and perform a correlation analysis in combination with the region clustering algorithm and process defects to generate a heat recognition report with a visual mapping, including: Judge whether the thermal conductivity of the chip material has changed according to the abnormal analysis report; When the thermal conductivity changes, adjust the boundary conditions in combination with the preset material property library to obtain an updated heat transfer equation; Solve the updated heat transfer equation to obtain updated temperature data; Extract the highest temperature value from the updated temperature data to obtain the highest updated temperature, and determine the area corresponding to the highest updated temperature as the high-temperature area; The high-temperature region is grouped by using a regional clustering algorithm to obtain the boundary of the hot spot region; Based on a preset visualization library, a distribution map rendering output operation is performed on the boundary of the hot spot region to obtain an updated distribution map; According to the manufacturing process data and in combination with the updated distribution map, the correlation between the high-temperature region and process defects is determined to obtain regional anomaly features; The regional anomaly features are classified, and based on the distribution law of process defects, a thermal identification report of the chip with the correlation between the hot spot region and process defects is generated.

8. A chip aging test system based on thermal migration analysis, characterized in that, It includes: A data acquisition module for acquiring power consumption distribution data of the chip in the working state, material property data of the chip layer structure, and manufacturing process data of the chip; A power consumption analysis module for discretely mapping the power consumption distribution data by using finite element network nodes, and based on a temperature threshold and in combination with a preset dynamic mode feedback iteration adjustment, obtaining an initial thermal distribution map of the chip surface; A temperature mapping module for performing pixel-level denoising processing on the initial thermal distribution map, enhancing the resolution through spatial interpolation and in combination with a temperature gradient algorithm, and finally generating a temperature mapping map of the chip surface through color coding conversion; A path determination module for, based on the temperature mapping map, applying the Fourier heat conduction formula to perform finite element network division, and in combination with a gradient tracking algorithm to generate a heat transfer path map of the target chip layer; A potential identification module for, based on the heat transfer path map, screening potential region grid points through a preset temperature threshold, and determining the spatial coordinates of the hot spot through spatial clustering analysis to generate a potential thermal distribution map of the potential hot spot; An anomaly analysis module for, according to the potential thermal distribution map, analyzing and locating the region with the highest temperature, and performing microstructure feature analysis on the abnormal region to generate an anomaly analysis report including lattice defect parameters; A report generation module for, based on a preset material property library, solving the high-temperature region distribution according to the manufacturing process data and the anomaly analysis report, and performing correlation analysis in combination with the regional clustering algorithm and process defects to generate a thermal identification report with visual mapping.

9. An electronic device, characterized in that, It includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the chip aging test method based on thermal migration analysis according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored computer program, wherein when the computer program runs, it controls the device where the computer-readable storage medium is located to execute the chip aging test method based on thermal migration analysis according to any one of claims 1 to 7.

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