Silicon photonic chip, optical fiber array for chip-level testing, and testing method

Abstract

The present invention relates to a silicon photonic chip having a first input waveguide, multiple first output waveguides, and a loop on the same side; the loop has a second input waveguide and a second output waveguide, with the second input waveguide dividing 90% of its light into the MPD and 10% into the second output waveguide. A fiber array for chip-level testing comprises a first polarization-maintaining fiber, a third polarization-maintaining fiber, a multimode fiber, and four second polarization-maintaining fibers. The first polarization-maintaining fiber corresponds to the first input waveguide in the silicon photonic chip, the third polarization-maintaining fiber corresponds to the second input waveguide in the silicon photonic chip, the multimode fiber corresponds to the second output waveguide in the silicon photonic chip, and the four second polarization-maintaining fibers correspond to the four first output waveguides in the silicon photonic chip, respectively. The beneficial effect is that the chip testing speed can be significantly accelerated, and since the chip area and the number of MPDs do not increase, the chip cost does not increase.

Description

Technical Field

[0001] The present invention relates to the technical field of silicon photonic chips, and in particular to a silicon photonic chip, an optical fiber array for chip-level testing, and a testing method. Background Art

[0002] The structure of a traditional DR4 silicon photonic chip is as follows: it has an input waveguide and four output waveguides on the same side. The input waveguide is coupled to the input of a first 1×2 coupler, and the two outputs of the first 1×2 coupler are each coupled to the input of a second 1×2 coupler. The two outputs of each second 1×2 coupler are each coupled to an output waveguide via an MZM modulator. In order to couple the lens, a portion of the light from the input waveguide must be diverted to the MPD to monitor the optical power coupled into the input waveguide, and the rest of the light is diverted to the four output waveguides in equal proportions. Due to the large insertion loss of the DR4 silicon photonic chip, in order to ensure that sufficient optical power enters the MZM modulator, usually about 2% of the light is diverted to the MPD, and the remaining approximately 98% of the light is diverted to multiple output waveguides in equal proportions. In addition, the waveguide width on the silicon photonic chip is typically 6μm±0.5μm.

[0003] Due to the large insertion loss of DR4 silicon photonic chips and the unstable chip manufacturing process, in order to ensure the production yield of optical modules, it is usually necessary to test the optical performance parameters such as optical insertion loss of the chips 100%. The most commonly used supporting device in the testing process is the fiber array. When the fiber array is coupled with the DR4 silicon photonic chip, such as Figure 1 As shown, each polarization-maintaining fiber in the fiber array must be aligned with the input waveguide and output waveguide in the DR4 silicon photonic chip at the same time. The polarization-maintaining fiber used in common fiber arrays is single-mode fiber, and the single-mode fiber mode spot is about 9μm, while the waveguide width on the silicon photonic chip is usually 6μm±0.5μm. In addition, since the input waveguide only divides about 2% of the light into the MPD, the MPD photocurrent is very small, and coupling and light finding are difficult. As a result, it is difficult to align the polarization-maintaining fiber with the input waveguide and output waveguide during testing, resulting in low test efficiency. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a silicon photonic chip and an optical fiber array and a testing method for chip-level testing, so as to overcome the deficiencies in the above-mentioned prior art.

[0005] The technical solution of the present invention to solve the above technical problems is as follows:

[0006] A silicon photonic chip has a first input waveguide, multiple first output waveguides, and a loop on the same side. The first input waveguide distributes part of the light to the MPD, and the rest of the light is distributed in equal proportions to the multiple first output waveguides. The loop has a second input waveguide and a second output waveguide. The second input waveguide distributes 90% of the light to the MPD and 10% of the light to the second output waveguide. The width of the first input waveguide, first output waveguide, second input waveguide, and second output waveguide are all 6μm±0.5μm.

[0007] The beneficial effects of the present invention are:

[0008] A loop is designed in the silicon photonic chip. The loop has a second input waveguide and a second output waveguide, and the second input waveguide divides 90% of the light to the MPD. When an external light source provides high optical power to the second input waveguide in the silicon photonic chip through the polarization-maintaining fiber in the fiber array, since the MPD can monitor the photocurrent, and the photocurrent is very large, it makes coupling and finding light easy. Since only a single waveguide needs to be aligned, the difficulty is reduced. After the first input waveguide is aligned with the polarization-maintaining fiber in the fiber array for light input testing, it is also easy to align the polarization-maintaining fiber in the fiber array for light output testing with the second output waveguide. As a result, the present invention can greatly speed up the chip testing speed, and since the chip area and the number of MPDs do not increase, the chip cost will not be increased.

[0009] On the basis of the above technical solution, the present invention can also be improved as follows.

[0010] Furthermore, the first input waveguide, the first output waveguide, the second input waveguide and the second output waveguide are all distributed at an angle and are parallel to each other.

[0011] Further, the number of the first output waveguides is four.

[0012] Furthermore, the first input waveguide is coupled to the input of a first 1×2 coupler, the two outputs of the first 1×2 coupler are each coupled to the input of a second 1×2 coupler, and the two outputs of each second 1×2 coupler are each coupled to a first output waveguide via an MZM modulator.

[0013] Based on the above technical solution, the present invention also provides a chip-level test fiber array for testing the above-mentioned silicon photonic chip, which is equipped with a first polarization-maintaining fiber, a third polarization-maintaining fiber, a multimode fiber and four second polarization-maintaining fibers. The size of the third polarization-maintaining fiber is 3μm±0.3μm, and the size of the multimode fiber is 50μm±1μm. The position of the first polarization-maintaining fiber corresponds to the first input waveguide in the silicon photonic chip, the position of the third polarization-maintaining fiber corresponds to the second input waveguide in the silicon photonic chip, the position of the multimode fiber corresponds to the second output waveguide in the silicon photonic chip, and the positions of the four second polarization-maintaining fibers respectively correspond to the four first output waveguides in the silicon photonic chip.

[0014] The above further beneficial effects are:

[0015] When an external light source provides high optical power to the second input waveguide in the silicon photonic chip through the third polarization-maintaining fiber in the fiber array, the MPD photocurrent will be very large because the fiber array uses the third polarization-maintaining fiber to couple the second input waveguide in the silicon photonic chip, and the second input waveguide divides 90% of the light into the MPD, making it easy to couple the fiber array and the silicon photonic chip.

[0016] The fiber array uses multimode fiber to couple with the second output waveguide in the silicon photonic chip. When measuring with an external optical power meter using multimode fiber, due to the large mode spot of the 50μm±1μm multimode fiber, the optical power can still be effectively tested even if the fiber array and the silicon photonic chip are not aligned and the deviation is more than 10μm. The existing solution uses a single-mode fiber with a mode spot of about 9μm. If the deviation is more than 10μm, the optical power cannot be measured. In addition, when the fiber array is coupled with the silicon photonic chip, it is easy for the fiber array to have a very small angle with the silicon photonic chip. When the angle occurs, the spacing between the first polarization-maintaining fiber and the second polarization-maintaining fiber relative to the first input waveguide and the first output waveguide in the silicon photonic chip will be too small. In this way, the first polarization-maintaining fiber and the second polarization-maintaining fiber cannot be aligned with the first input waveguide and the first output waveguide of the silicon photonic chip at the same time. Since the chip performance can only be effectively measured when they are aligned at the same time, the test will fail if they cannot be aligned.

[0017] Furthermore, the inclination angle of the end face of the optical port is the same as the inclination angle of the first input waveguide, the first output waveguide, the second input waveguide or the second output waveguide.

[0018] Based on the above technical solution, the present invention also provides a silicon photonic chip testing method, which uses the above chip-level test fiber array to test the silicon photonic chip, including the following steps:

[0019] S1, the third polarization-maintaining optical fiber is connected to an external light source, which provides high optical power, and the multimode optical fiber is connected to an external optical power meter;

[0020] S2. Turn on the light source connected to the third polarization-maintaining fiber and the optical power meter connected to the multimode fiber, actively couple and align the third polarization-maintaining fiber in the fiber array with the second input waveguide in the silicon photonic chip, and actively couple and align the multimode fiber in the fiber array with the second output waveguide in the silicon photonic chip, until the photocurrent value measured by the MPD and the optical power measured by the optical power meter are maximum.

[0021] S3. Keep the positions of the silicon photonic chip and the fiber array unchanged, turn off the light source connected to the third polarization-maintaining fiber, connect the first polarization-maintaining fiber to an external light source, and connect the second polarization-maintaining fiber to an optical power meter.

[0022] S4. Turn on the light source connected to the first polarization-maintaining fiber and the optical power meter connected to the second polarization-maintaining fiber, and fine-tune the angle of the fiber array so that the fiber array is parallel to the silicon photonic chip. In the active coupling mode, align them until the light power measured by the optical power meter is maximum. This can test the performance of the silicon photonic chip.

[0023] The above method has the further beneficial effect of enabling accurate testing of chip performance, and the testing is convenient and quick.

[0024] Furthermore, the maximum optical power provided by the light source externally connected to the third polarization-maintaining optical fiber is greater than 20 dBm. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a diagram of the coupling test structure between the optical fiber array and the silicon photonic chip in the prior art;

[0026] Figure 2 This is a structural diagram of the silicon photonic chip in the present invention;

[0027] Figure 3 is a structural diagram of the optical fiber array in the present invention;

[0028] Figure 4 This is a diagram of the coupling test structure between the optical fiber array and the silicon photonic chip in the present invention.

[0029] In the accompanying drawings, the components represented by the reference numerals are as follows:

[0030] 1. Silicon photonic chip, 110. First input waveguide, 120. First output waveguide, 130. Second input waveguide, 140. Second output waveguide, 150. MPD, 160. First 1×2 coupler, 170. Second 1×2 coupler, 180. MZM modulator, 2. Fiber array, 210. First polarization-maintaining fiber, 220. Third polarization-maintaining fiber, 230. Multimode fiber, 240. Second polarization-maintaining fiber. DETAILED DESCRIPTION

[0031] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0032] Example 1

[0033] like Figure 2 As shown, a silicon photonic chip has a first input waveguide 110, multiple first output waveguides 120, and a loop on the same side. The first input waveguide 110 distributes part of the light to the MPD 150, and the rest of the light is distributed to the multiple first output waveguides 120 in a proportional manner, which is consistent with the existing technology. For example, the first input waveguide 110 distributes about 2% of the light to the MPD 150, and the remaining about 98% of the light is distributed to the multiple first output waveguides 120 in a proportional manner. Of course, this is only an illustrative example, and other proportions are not excluded in actual applications. The loop has a second input waveguide 130 and a first output waveguide 120. Two output waveguides 140, namely, a first input waveguide 110, a second input waveguide 130, a second output waveguide 140, and a plurality of first output waveguides 120 are located on the same side. The second input waveguide 130 distributes 90% of the light to the MPD 150 and 10% of the light to the second output waveguide 140. The width of the first input waveguide 110 is 6 μm ± 0.5 μm, and the width of the first output waveguide 120 is 6 μm ± 0.5 μm, which is consistent with the prior art. The width of the second input waveguide 130 is 6 μm ± 0.5 μm, and the width of the second output waveguide 140 is 6 μm ± 0.5 μm.

[0034] A loop is designed in the silicon photonic chip. The loop has a second input waveguide 130 and a second output waveguide 140, and the second input waveguide 130 distributes 90% of the light to the MPD 150. When an external light source provides high optical power to the second input waveguide 130 in the silicon photonic chip 1 through the polarization-maintaining fiber in the fiber array 2, the MPD 150 can monitor the photocurrent, and the photocurrent is very large, so coupling and finding the light are easy. Since only a single waveguide needs to be aligned, the difficulty is reduced. After the first input waveguide 110 is aligned with the polarization-maintaining fiber for light input testing in the fiber array 2, it is also easy to align the polarization-maintaining fiber for light output testing in the fiber array 2 with the second output waveguide 140. As a result, the present invention can significantly speed up chip testing. Since the chip area and the number of MPDs 150 do not increase, there is no additional increase in chip cost.

[0035] Example 2

[0036] like Figure 2 As shown, this embodiment is a further improvement on the basis of embodiment 1, specifically as follows:

[0037] The first input waveguide 110 , the first output waveguide 120 , the second input waveguide 130 , and the second output waveguide 140 are all tilted and parallel to each other, such as the common tilt of 8°. Of course, this is just an illustrative example, and other angles are not excluded in actual application.

[0038] Example 3

[0039] like Figure 2 As shown, this embodiment is a further improvement on the basis of embodiment 1 or 2, specifically as follows:

[0040] There are four first output waveguides 120. In this case, the silicon photonic chip is a DR4 silicon photonic chip. The first input waveguide 110 is coupled to the input of a first 1×2 coupler 160. The two outputs of the first 1×2 coupler 160 are each coupled to the input of a second 1×2 coupler 170, that is, there are two second 1×2 couplers 170. The two outputs of each second 1×2 coupler 170 are each coupled to a first output waveguide 120 via an MZM modulator 180, that is, there are four MZM modulators 180. The first 1×2 coupler 160 and the second 1×2 coupler 170 both split light in equal proportions, so that after the light output from the first output waveguide 120 is divided into parts toward the MPD 150, the remaining light can be split into the four first output waveguides 120 in equal proportions.

[0041] Example 4

[0042] like Figure 3 As shown, a chip-level test fiber array is used to test the silicon photonic chip 1 in any one of embodiments 1 to 3, which includes: a substrate, a cover plate, and a first polarization-maintaining fiber 210, a third polarization-maintaining fiber 220, a multimode fiber 230, and four second polarization-maintaining fibers 240 clamped by the substrate and the cover plate. The size of the third polarization-maintaining fiber 220 is 3μm±0.3μm, the size of the multimode fiber 230 is 50μm±1μm, and the position of the first polarization-maintaining fiber 210 corresponds to the first input in the silicon photonic chip 1. The positions of the waveguide 110 and the four second polarization-maintaining optical fibers 240 correspond to the four first output waveguides 120 in the silicon photonic chip 1, that is, this part of the content remains consistent with the existing technology; the position of the third polarization-maintaining optical fiber 220 corresponds to the second input waveguide 130 in the silicon photonic chip 1, and the position of the multimode optical fiber 230 corresponds to the second output waveguide 140 in the silicon photonic chip 1. The first polarization-maintaining optical fiber 210, the third polarization-maintaining optical fiber 220, the multimode optical fiber 230 and the four second polarization-maintaining optical fibers 240 are parallel to each other.

[0043] When an external light source provides high optical power to the second input waveguide 130 in the silicon photonic chip 1 through the third polarization-maintaining fiber 220 in the fiber array 2, since the fiber array 2 uses the third polarization-maintaining fiber 220 to couple the second input waveguide 130 in the silicon photonic chip 1, and the second input waveguide 130 distributes 90% of the light to the MPD 150, the photocurrent of the MPD 150 will be very large, making it easy to couple the fiber array 2 with the silicon photonic chip 1.

[0044] The optical fiber array 2 uses a multimode optical fiber 230 to couple with the second output waveguide 140 in the silicon photonic chip 1. When the multimode optical fiber 230 is measured with an external optical power meter, due to the large mode spot of the 50μm±1μm multimode optical fiber 230, the optical power can still be effectively tested even if the optical fiber array 2 and the silicon photonic chip 1 are not aligned and the deviation is more than 10μm. The existing solution uses a single-mode optical fiber with a mode spot of about 9μm. If the deviation is more than 10μm, the optical power cannot be measured. In addition, when the optical fiber array 2 is coupled with the silicon photonic chip 1, it is easy for the optical fiber array 2 to have a very small angle with the silicon photonic chip 1. When the angle occurs, the spacing between the first polarization-maintaining optical fiber 210 and the second polarization-maintaining optical fiber 240 relative to the first input waveguide 110 and the first output waveguide 120 in the silicon photonic chip 1 will be smaller (for example, the channel spacing of the optical fiber array 2 is 250μm, and it has 4 channels. The total spacing between channel 1 and channel 4 is 750μm, and the optical fiber array 2 has a small spacing of 250μm). When the array 2 is flush with the silicon photonic chip 1, the spacing between channel 1 and channel 4 is 750μm. When the fiber array 2 is not flush with the silicon photonic chip 1, an angle appears, such as 60° (the actual angle is generally less than 6°, and 60° is just used as an example for calculation). Then cos60°=0.5, 0.5×750=375μm. At this time, the spacing between channel 1 and channel 4 of the fiber array 2 relative to the silicon photonic chip 1 is only 375μm. In this way, after channel 1 is aligned with one first output waveguide 120 of the silicon photonic chip 1, channel 4 cannot be aligned with the other first output waveguide 120 of the silicon photonic chip 1). In this way, the first polarization-maintaining fiber 210 and the second polarization-maintaining fiber 240 cannot be simultaneously aligned with the first input waveguide 110 and the first output waveguide 120 of the silicon photonic chip 1. Since the chip performance can only be effectively measured when they are aligned at the same time, the test will fail if they cannot be aligned.

[0045] Example 5

[0046] like Figure 3 As shown, this embodiment is a further improvement on the basis of embodiment 4, specifically as follows:

[0047] The inclination angle of the end face of the optical port of the optical fiber array is the same as the inclination angle of the first input waveguide 110, the first output waveguide 120, the second input waveguide 130 or the second output waveguide 140 in the silicon photonic chip 1. For example, if the inclination angle of the first input waveguide 110, the first output waveguide 120, the second input waveguide 130 or the second output waveguide 140 is 8°, then the inclination angle of the end face of the optical port of the optical fiber array is also 8°. Of course, this is just an illustrative example, and other angles are not excluded in actual application.

[0048] Example 6

[0049] like Figure 4 As shown, a silicon photonic chip testing method uses the chip-level testing optical fiber array described in Example 4 or 5 to test the silicon photonic chip in any one of Examples 1 to 3, including the following steps:

[0050] S1. Connect the third polarization-maintaining optical fiber 220 in the optical fiber array 2 to an external light source, and have the light source provide high optical power. Also, connect the multimode optical fiber 230 in the optical fiber array 2 to an external optical power meter.

[0051] S2. Turn on the external light source connected to the third polarization-maintaining fiber 220 and the external optical power meter connected to the multimode fiber 230, so that the third polarization-maintaining fiber 220 in the fiber array 2 and the second input waveguide 130 in the silicon photonic chip 1 are actively coupled and aligned, and the multimode fiber 230 in the fiber array 2 and the second output waveguide 140 in the silicon photonic chip 1 are actively coupled and aligned, until the photocurrent value measured by the MPD 150 and the optical power measured by the optical power meter are maximized.

[0052] S3. Keep the positions of the silicon photonic chip 1 and the optical fiber array 2 unchanged, turn off the light source connected to the third polarization-maintaining fiber 220, connect the first polarization-maintaining fiber 210 to an external light source, and connect the second polarization-maintaining fibers 240 to an optical power meter.

[0053] S4. Turn on the light source connected to the first polarization-maintaining fiber 210 and the optical power meter connected to the second polarization-maintaining fiber 240, and fine-tune the angle of the fiber array 2 so that the fiber array 2 is parallel to the silicon photonic chip 1. In the active coupling mode, align them until the light power measured by the optical power meter is maximum, and then the performance of the silicon photonic chip 1 can be tested.

[0054] In this test solution, the maximum optical power provided by the light source externally connected to the third polarization-maintaining optical fiber 220 is greater than 20 dBm.

[0055] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A silicon photonic chip, characterized in that: The invention discloses a first input waveguide (110), a plurality of first output waveguides (120), and a loop circuit on the same side. The first input waveguide (110) distributes part of the light to the MPD (150), and the rest of the light is distributed to the plurality of first output waveguides (120) in equal proportion. The loop circuit has a second input waveguide (130) and a second output waveguide (140). The second input waveguide (130) distributes 90% of the light to the MPD (150) and 10% of the light to the second output waveguide (140). The width of the first input waveguide (110), the first output waveguide (120), the second input waveguide (130), and the second output waveguide (140) are all 6μm±0.5μm.

2. The silicon photonic chip according to claim 1, wherein: The first input waveguide (110), the first output waveguide (120), the second input waveguide (130) and the second output waveguide (140) are all distributed at an angle and are parallel to each other.

3. The silicon photonic chip according to claim 1, wherein: The number of the first output waveguides (120) is four.

4. The silicon photonic chip according to claim 3, wherein: The first input waveguide (110) is coupled to an input of a first 1×2 coupler (160), two outputs of the first 1×2 coupler (160) are each coupled to an input of a second 1×2 coupler (170), and two outputs of each second 1×2 coupler (170) are each coupled to a first output waveguide (120) via an MZM modulator (180).

5. A silicon photonic chip testing method, characterized in that: Used for testing the silicon photonic chip (1) as claimed in any one of claims 1 to 4, comprising: a chip-level test fiber array, the chip-level test fiber array having a first polarization-maintaining fiber (210), a third polarization-maintaining fiber (220), a multimode fiber (230) and four second polarization-maintaining fibers (240), the size of the third polarization-maintaining fiber (220) being 3 μm±0.3 μm, the size of the multimode fiber (230) being 50 μm±1 μm, the position of the first polarization-maintaining fiber (210) corresponding to the first input waveguide (110) in the silicon photonic chip (1), the position of the third polarization-maintaining fiber (220) corresponding to the second input waveguide (130) in the silicon photonic chip (1), the position of the multimode fiber (230) corresponding to the second output waveguide (140) in the silicon photonic chip (1), and the positions of the four second polarization-maintaining fibers (240) corresponding to the four first output waveguides (120) in the silicon photonic chip (1); The test steps are as follows: S1, the third polarization-maintaining optical fiber (220) is externally connected to a light source, and the light source provides high optical power, and the multimode optical fiber (230) is externally connected to an optical power meter; S2, turning on the light source externally connected to the third polarization-maintaining optical fiber (220), and turning on the optical power meter externally connected to the multimode optical fiber (230), so that the third polarization-maintaining optical fiber (220) in the optical fiber array (2) and the second input waveguide (130) in the silicon photonic chip (1) are actively coupled and aligned, and the multimode optical fiber (230) in the optical fiber array (2) and the second output waveguide (140) in the silicon photonic chip (1) are actively coupled and aligned, so that the photocurrent value measured by the MPD (150) is maximized and the optical power measured by the optical power meter is maximized; S3, keeping the positions of the silicon photonic chip (1) and the optical fiber array (2) unchanged, turning off the light source connected to the third polarization-maintaining optical fiber (220), connecting the first polarization-maintaining optical fiber (210) to an external light source, and connecting the second polarization-maintaining optical fiber (240) to an optical power meter; S4. Turn on the light source externally connected to the first polarization-maintaining optical fiber (210), and turn on the optical power meter externally connected to the second polarization-maintaining optical fiber (240), and fine-tune the angle of the optical fiber array (2) so that the optical fiber array (2) is parallel to the silicon photonic chip (1), and align them in an active coupling mode until the light power measured by the optical power meter is maximum, thereby testing the performance of the silicon photonic chip (1).

6. A silicon photonic chip testing method according to claim 5, characterized in that: The tilt angle of the end face of the optical port of the optical fiber array for chip-level testing is the same as the tilt angle of the first input waveguide (110), the first output waveguide (120), the second input waveguide (130) or the second output waveguide (140).

7. A silicon photonic chip testing method according to claim 5, characterized in that: The light source externally connected to the third polarization-maintaining optical fiber (220) provides a maximum optical power greater than 20 dBm.

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