A MEMS deformable mirror based on double silicon gold bonding and its preparation method

Abstract

The present invention provides a double silicon-gold bonded MEMS deformable mirror and its fabrication method. The MEMS deformable mirror comprises a silicon wafer substrate, a silicon nitride insulating layer, a lower polysilicon electrode, a first phosphosilicate glass sacrificial layer, an upper interdigitated electrode, a first bonding electrode layer, an SOI wafer structure, a second bonding electrode layer, and a gold-based reflective mirror surface. The fabrication method sequentially involves silicon wafer substrate pretreatment, silicon nitride insulating layer deposition, lower polysilicon electrode formation, first phosphosilicate glass sacrificial layer deposition and thinning, upper interdigitated electrode and related structure etching, first bonding electrode layer formation, SOI wafer pretreatment and solution channel formation, second phosphosilicate glass sacrificial layer filling, second bonding electrode layer formation, gold-to-gold hot-compression bonding, deep silicon etching, structural release and annealing, and gold-based reflective mirror surface fabrication and packaging. This invention can simplify the process flow, improve the correction performance of optical systems, and has broad market application prospects.

Description

Technical Field

[0001] The present invention relates to the technical field of micro-nano processing of deformable mirror structures, and in particular to a double silicon gold bonding MEMS deformable mirror and a preparation method thereof. Background Art

[0002] The manufacturing technology of microelectromechanical system (MEMS) deformable mirrors is a core challenge in the field of adaptive optics, and their performance directly affects the accuracy of beam wavefront correction. Traditional processes use a step-by-step deposition and etching method to prepare multilayer electrode structures. The main processes include substrate cleaning, insulating layer deposition, electrode photolithography, sacrificial layer release, and reflective mirror coating. However, this type of process has the following technical defects: traditional wet etching processes expose the reflective layer to the etching solution for a long time, resulting in an increase in surface defects, increased roughness, and irreversible degradation of optical reflective performance; the difference in thermal expansion coefficients between the electrode material and the reflective layer causes interfacial stress accumulation during annealing, increasing mirror deformation errors and affecting the accuracy and stability of the optical system; the single-channel backhole design restricts the diffusion of the etching solution, resulting in uneven release of the sacrificial layer, and the movable structure is prone to adhesion, reducing the device yield; the preparation of multilayer electrode structures requires multiple photolithography mask alignments, which is complex and has a low fault tolerance, restricting mass production efficiency and cost control.

[0003] Although existing improvement schemes can help alleviate structural adhesion problems or reduce the impact of thermal stress to a certain extent by optimizing the etching solution formula, introducing a porous backplane design, or adopting a low-temperature bonding process, they still have the following limitations: for example, although the porous backplane design can improve the diffusion efficiency of the etching solution, the complex micro-pore processing process greatly increases the manufacturing cost and easily leads to a decrease in mechanical strength; although low-temperature bonding technology can reduce the accumulation of thermal stress, its bonding strength is insufficient and it is difficult to meet the stringent requirements of high-precision devices for interface stability; in addition, the existing process's post-processing protection measures for the reflective mirror are still imperfect, and it is impossible to completely avoid secondary contamination of the mirror surface by etching residues. Summary of the Invention

[0004] Purpose of the invention: The technical problem to be solved by the present invention is to address the shortcomings of the existing technology and provide a MEMS deformable mirror based on double silicon-gold bonding and a preparation method thereof. Through gold-to-gold bonding technology, V-shaped solution channel and double-sided alignment mark collaborative design and mirror post-positioning process, efficient mass production of high-precision and high-stability devices can be achieved, thereby improving the correction performance of the optical system.

[0005] The present invention first provides a double silicon-gold bonded MEMS deformable mirror, comprising a silicon wafer substrate, a silicon nitride insulating layer, a lower polysilicon electrode, a first phosphosilicate glass sacrificial layer, an in-situ doped polysilicon layer, a first bonding electrode layer, an SOI wafer structure, a second bonding electrode layer and a gold-based reflective mirror surface;

[0006] On the silicon wafer substrate, a silicon nitride insulating layer, a lower polysilicon electrode, a first phosphosilicate glass sacrificial layer, and an in-situ doped polysilicon layer are sequentially arranged from near to far;

[0007] Etching the in-situ doped polysilicon layer to form upper interdigital electrodes, stress relief holes and solution diversion grooves;

[0008] The first bonding electrode layer is provided on the upper interdigital electrode;

[0009] The SOI sheet structure is arranged on the first bonding electrode layer;

[0010] The top silicon layer of the SOI wafer structure is etched and patterned to form a solution channel;

[0011] The second bonding electrode layer is provided on the top silicon layer of the SOI wafer structure;

[0012] The first bonding electrode layer and the second bonding electrode layer perform gold-to-gold bonding to complete double-sided silicon wafer connection;

[0013] After the SOI wafer structure is subjected to deep silicon etching and structure release, a mirror support layer is formed on the back side of the top silicon layer of the SOI wafer structure;

[0014] The gold-based reflecting mirror is arranged on a mirror support layer.

[0015] The trapezoidal alignment marks on the back of the silicon wafer substrate have a depth of 3 to 5 μm. This depth range ensures sufficient visibility of the alignment marks in subsequent process steps while avoiding excessive weakening of the silicon wafer's mechanical strength, ensuring the accuracy and reliability of subsequent bonding.

[0016] The thickness of the silicon nitride insulating layer is 500-600 nm. This thickness range ensures good insulation performance between the underlying polysilicon electrode and the silicon wafer substrate, while effectively buffering the stress caused by the difference in thermal expansion coefficient and reducing mirror deformation errors.

[0017] The thickness of the lower polysilicon electrode is 450-550nm, with a line width accuracy of ±0.1-0.2μm. This thickness range, combined with the line width accuracy requirements, can ensure the electrode's performance stability during high-frequency signal transmission while adapting to the precision limitations of micro-nano fabrication technology.

[0018] The thickness of the first phosphosilicate glass sacrificial layer is 2-3 μm. This thickness range balances the diffusion efficiency of the etching solution and the uniformity of the structure release while avoiding excessive increase in the vertical size of the device.

[0019] The in-situ doped polysilicon layer has a thickness of 2.5-3.5 μm. The stress relief holes are arranged in an array with a diameter of 1.5-2.5 μm and a spacing of 4-6 μm. The solution diversion grooves are 2-5 μm wide. The thickness of the polysilicon layer ensures the mechanical strength and conductivity of the electrode. The size and spacing of the stress relief holes are designed to optimize local stress distribution and reduce structural deformation. The width of the solution diversion grooves affects the flow efficiency and release uniformity of the etching solution.

[0020] The thickness of the first bonding electrode layer and the second bonding electrode layer is 500-600 nm. This thickness range ensures good conductivity and bonding strength while reducing the risk of interface defects caused by uneven thickness.

[0021] The solution channel has a V-shaped structure with an aspect ratio of 8:1 to 12:1 and a sidewall angle of 50° to 60°. This aspect ratio and sidewall angle design significantly improves the diffusion efficiency of the etching solution, reduces the release time, optimizes the freedom of the movable structure, and reduces the risk of adhesion.

[0022] The present invention also provides a method for preparing the double silicon gold bonded MEMS deformable mirror, comprising the following steps:

[0023] Step 1: Clean a 4-inch or 6-inch n-type double-sided polished silicon wafer substrate with a thickness of 675 μm using RCA standard cleaning solution, and etch alignment marks on the back side of the silicon wafer substrate using a deep reactive ion etching process;

[0024] Step 2: depositing a silicon nitride insulating layer on the front surface of the silicon wafer substrate using a low-pressure chemical vapor deposition process, and controlling the stress to be less than 100 MPa;

[0025] Step 3: depositing a polysilicon layer on the front surface of the silicon nitride insulating layer using a plasma enhanced chemical vapor deposition process, and patterning it after thinning and ion implantation to form a lower polysilicon electrode;

[0026] Step 4: depositing a first phosphosilicate glass sacrificial layer on the front surface of the lower polysilicon electrode by plasma enhanced chemical vapor deposition and performing a thinning process;

[0027] Step 5: depositing an in-situ doped polysilicon layer on the front surface of the first phosphosilicate glass sacrificial layer using a low-pressure chemical vapor deposition process, thinning it, and then simultaneously etching it to form upper interdigital electrodes, arrayed stress relief holes, and solution diversion grooves;

[0028] Step 6: magnetron sputtering a gold layer on the front surface of the upper interdigital electrode, aligning it with the alignment mark etched on the back surface of the silicon wafer substrate in step 1 and completing double-layer overlay to form a first bonding electrode layer;

[0029] Step 7: ultrasonically clean the SOI wafer structure, etch the back side of the bottom silicon of the SOI wafer structure using a deep reactive ion etching process to form alignment marks, and etch and pattern the top silicon surface of the SOI wafer structure to form a solution channel;

[0030] Step 8: Deposit a second sacrificial phosphosilicate glass layer on the top silicon front side of the SOI wafer structure using a plasma-enhanced chemical vapor deposition process, selectively remove excess phosphosilicate glass material (generally manually selected), and retain only the solution channel area for filling;

[0031] Step 9: magnetron sputtering a gold layer on the front surface of the top silicon of the SOI wafer structure, aligning it with the alignment mark etched on the back surface of the bottom silicon of the SOI wafer structure in step 7, and completing double-layer overlay to form a second bonding electrode layer;

[0032] Step 10: Performing gold-to-gold thermocompression bonding on the first bonding electrode layer and the second bonding electrode layer to complete the mechanical and electrical connection of the double-sided silicon wafer;

[0033] Step 11: Based on the alignment mark formed in step 7 on the back side of the bottom silicon of the SOI wafer structure, a deep silicon etching process is used to etch the bottom silicon of the SOI wafer structure down to its buried oxide layer (the "its" here refers to the SOI wafer structure, which has a three-layer structure, namely the bottom silicon, the buried oxide layer, and the top silicon layer);

[0034] Step 12: removing the first phosphosilicate glass sacrificial layer, the second phosphosilicate glass sacrificial layer, and the buried oxide layer of the SOI wafer structure to complete the structure release, and performing an annealing treatment in an inert gas environment to form an ohmic contact between the first bonding electrode layer and the second bonding electrode layer and the silicon;

[0035] Step 13, sputtering a gold layer on the back side of the top silicon of the SOI wafer structure and patterning it to form a gold-based reflective mirror, and then performing vacuum bonding packaging;

[0036] In step 8, the thickness of the second phosphosilicate glass sacrificial layer is 1-1.5 μm; a thinner second phosphosilicate glass sacrificial layer helps reduce etching time and chemical residue while maintaining sufficient structural support.

[0037] In step 11, deep silicon etching includes an etching stage and a passivation stage. In the etching stage, SF6 gas with a flow rate of 200 sccm and an RF power of 800 W is used. In the passivation stage, the gas is switched to C4F8 gas with a flow rate of 100 sccm and a power of 600 W. The Bosch process is implemented in a cyclic alternating manner, and the etching rate reaches 8 μm / min. During the deep silicon etching process, the thickness of the silicon layer is monitored in real time by a laser interferometer. When the buried oxide layer of the SOI wafer structure is etched, the reflectivity suddenly changes, and the etching is terminated.

[0038] The core innovation of this invention is mainly reflected in the systematic reconstruction of the traditional process flow by introducing the coordinated optimization of gold-to-gold bonding technology and the post-process of the reflector. Specifically, the coordinated design of the double-sided alignment mark and the V-shaped high aspect ratio solution channel significantly improves the diffusion uniformity of the etching solution and completely solves the problem of structural adhesion; the reflective mirror surface is prepared by a post-sputtering process, which avoids the direct damage of the etching solution to the mirror quality, reduces the surface roughness (Ra) to the sub-nanometer level, and significantly improves the optical performance. At the same time, the application of gold-to-gold bonding technology not only simplifies the overlay alignment steps of the multi-layer electrode, but its high-strength bonding interface also greatly enhances the mechanical stability of the device, effectively suppresses deformation and interface failure caused by thermal stress, and provides a reliable technical path for the efficient mass production of high-precision MEMS deformable mirrors.

[0039] Beneficial effects: 1. The post-sputtering process of the reflector avoids direct contact of the etching solution with the mirror surface, reducing the surface roughness Ra to sub-nanometer level, specifically less than 1nm, and increasing the optical reflectivity by more than 15%, significantly enhancing the accuracy of the beam wavefront correction;

[0040] 2. The high-strength bonding interface of gold-to-gold bonding technology has a shear strength of no less than 50Mpa. Combined with excellent thermal matching, it reduces the accumulation of interfacial stress caused by differences in thermal expansion coefficients during annealing. The mirror deformation error is controlled within plus or minus 0.1μm, improving the long-term stability of the optical system.

[0041] 3. The use of a V-shaped high-aspect-ratio solution channel with an aspect ratio of 8:1 to 12:1, combined with a double-sided alignment mark design, improves the etching solution diffusion efficiency by 40%, shortens the sacrificial layer release time to one-third of that of the traditional process, completely eliminates the adhesion problem of the movable structure, and improves the yield rate to over 95%;

[0042] 4. Gold-to-gold bonding achieves synchronous mechanical and electrical connection of double-sided silicon wafers, reducing the number of multi-layer electrode overlay alignments from the traditional five to two, reducing process steps by 20% and increasing mass production efficiency by more than 30%;

[0043] 5. By precisely controlling the thickness of the first phosphosilicate glass sacrificial layer to 2-3μm and the second layer to 1-1.5μm, and adopting a Bosch deep silicon etching process with an etching rate of 8μm / min and a termination accuracy of ±0.5μm, the integrity and uniformity of the micromirror support layer and electrode structure are ensured, and the device life is extended to more than 100,000 cycles. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 Schematic diagram of the structure of MEMS deformable mirror.

[0045] Figure 2 Schematic diagram of the silicon wafer substrate pretreatment structure in step 1.

[0046] Figure 3 Schematic diagram of the silicon nitride insulating layer structure in step 2.

[0047] Figure 4 Schematic diagram of the lower polysilicon electrode structure in step 3.

[0048] Figure 5 This is a schematic diagram of the processing structure of the first phosphosilicate glass sacrificial layer in step 4.

[0049] Figure 6 Schematic diagram of the upper interdigitated electrode structure in step 5.

[0050] Figure 7 Schematic diagram of the first bonding electrode layer structure in step 6.

[0051] Figure 8 Schematic diagram of the SOI wafer structure pretreatment and solution channel structure in step 7.

[0052] Figure 9 Schematic diagram of the second phosphosilicate glass sacrificial layer processing structure in step 8.

[0053] Figure 10 Schematic diagram of the second bonding electrode layer structure in step 9.

[0054] Figure 11 Schematic diagram of the gold-to-gold hot-compression bonding structure of double-sided silicon wafers in step 10.

[0055] Figure 12 Schematic diagram of the deep silicon etching process structure in step 11.

[0056] Figure 13 Schematic diagram of the structure release and annealing process in step 12.

[0057] Explanation of the accompanying figures: 1 is a silicon wafer substrate; 2 is a silicon nitride insulating layer; 3 is a lower polysilicon electrode; 4 is a first phosphosilicate glass sacrificial layer; 5 is an upper interdigitated electrode; 6 is a first bonding electrode layer; 7 is an SOI wafer structure; 8 is a second phosphosilicate glass sacrificial layer; 9 is a second bonding electrode layer; 10 is a gold-based reflective mirror. DETAILED DESCRIPTION

[0058] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more apparent.

[0059] Combine Figure 1 As shown, an embodiment of the present invention provides a MEMS deformable mirror based on double silicon gold bonding, comprising:

[0060] A silicon wafer substrate 1, a silicon nitride insulating layer 2 arranged on the silicon wafer substrate 1, a lower polysilicon electrode 3 arranged on the silicon nitride insulating layer 2, a first phosphosilicate glass sacrificial layer 4 arranged on the lower polysilicon electrode 3, an in-situ doped polysilicon layer arranged on the first phosphosilicate glass sacrificial layer 4, an upper interdigital electrode 5, stress relief holes and solution diversion grooves are etched on the in-situ doped polysilicon layer, a first bonding electrode layer 6 is arranged on the upper interdigital electrode 5, an SOI wafer structure 7 is arranged on the first bonding electrode layer, the top silicon of the SOI wafer structure 7 is etched and patterned to form a solution channel, a second bonding electrode layer 9 is arranged on the top silicon of the SOI wafer structure 7, the first bonding electrode layer 6 and the second bonding electrode layer 9 are bonded with gold to complete the double-sided silicon wafer connection, after deep silicon etching and structural release of the SOI wafer structure 7, a mirror support layer is formed on the back of the top silicon of the SOI wafer structure 7, and a gold-based reflective mirror 10 is arranged on the mirror support layer.

[0061] The depth of the trapezoidal alignment mark on the back of the silicon wafer substrate is 3~5μm.

[0062] The thickness of the silicon nitride insulating layer is 500~600nm.

[0063] The thickness of the lower polysilicon electrode is 450~550nm, and the line width accuracy is ±0.1~0.2μm.

[0064] Furthermore, the thickness of the first phosphosilicate glass sacrificial layer is 2-3 μm.

[0065] The thickness of the in-situ boron-doped polysilicon layer is 2.5~3.5μm, the aperture of the array stress relief holes is 1.5~2.5μm, the spacing is 4-6μm, and the width of the solution diversion groove is 2~5μm.

[0066] The thickness of the first bonding electrode layer and the second bonding electrode layer are both 500-600 nm.

[0067] The solution channel on the top silicon of the SOI wafer structure has a V-shaped structure with a depth-to-width ratio of 8:1~12:1 and a sidewall angle of 50~60°.

[0068] In a second embodiment of the present invention, a method for preparing a double silicon gold bonded MEMS deformable mirror is provided, comprising the following steps:

[0069] Combine Figure 2 In step 1, silicon wafer substrate 1 is cleaned using RCA standard cleaning, using SC-1 and SC-2 solutions to remove surface organic contaminants and metal ions. Subsequently, a deep reactive ion etch process is performed on the backside of silicon wafer substrate 1 using a mixture of SF6 and C4F8 at a flow ratio of 3:1. Trapezoidal alignment marks are etched to a depth of 3-5 μm, with an 80° sidewall angle and an etch rate of 3 μm / min.

[0070] Combine Figure 3 In step 2, a silicon nitride insulating layer 2 is deposited on the front surface of the silicon wafer substrate 1 using a low-pressure chemical vapor deposition process. The reactant gases are SiH2Cl2 and NH3, with a flow ratio of 1:2, a deposition temperature of 780°C, and a thickness of 500-600nm. The compressive stress of the silicon nitride layer is controlled at 80MPa by adjusting the gas flow ratio, and the stress distribution is monitored in real time using a laser interferometer.

[0071] Combine Figure 4 In step 3, a polysilicon layer is deposited on the silicon nitride insulating layer 2 using a plasma-enhanced chemical vapor deposition process to a thickness of 500-600 nm, and then thinned to 450-550 nm by chemical mechanical polishing. Boron ions are then implanted at a dose of 1×10¹ 5 cm⁻², with an energy of 30keV, and a lower polysilicon electrode layer 3 with a line width accuracy of ±0.1~0.2μm is formed by Cl2 and HBr dry etching.

[0072] Combine Figure 5 In step 4, a first sacrificial phosphosilicate glass layer 4 is deposited on the front surface of the lower polysilicon electrode layer 3 using plasma-enhanced chemical vapor deposition (PECVD). The thickness is 2-3 μm, and the gas composition is SiH₄, O₂, and PH₃ in a volume ratio of 1:3:0.1. Chemical mechanical polishing is performed to a surface roughness of less than 5 nm to ensure flatness between subsequent layers.

[0073] Combine Figure 6 In step 5, a low-pressure chemical vapor deposition process is used to deposit an in-situ boron-doped polysilicon layer on the front of the first phosphosilicate glass sacrificial layer 4, with a thickness of 2.5~3.5μm and a doping concentration of 1×10² 0 The etched surface is 1000 square centimeters thick and simultaneously forms the upper interdigitated electrodes 5, an array of stress relief holes with a diameter of 1.5-2.5 μm and a spacing of 4-6 μm, and solution diversion grooves with a width of 2-5 μm. Etching is performed using the Bosch process, with a sidewall verticality deviation of less than 1°.

[0074] Combine Figure 7 In step 6, a gold layer is deposited on the surface of the upper interdigital electrode 5 by magnetron sputtering. The sputtering parameters are an Ar gas flow rate of 20 sccm, a power of 300 W, and a substrate temperature of 200°C. The coating thickness is 500-600 nm. Double-sided alignment is achieved using an infrared aligner, with an overlay error of less than 0.4 μm, forming the first bonding electrode layer 6.

[0075] Combine Figure 8In step 7, the SOI wafer structure 7 is ultrasonically cleaned, and a mixed solvent of acetone and isopropyl alcohol is used to thoroughly remove surface particle contaminants. Subsequently, a deep reactive ion etching process is performed on the back side of the bottom silicon of the SOI wafer structure 7 to etch an alignment mark with a depth of 3 to 5 μm. A fluorine-based mixed gas is used as the etching gas, and the sidewall steepness is controlled at 88°±2°. Then, the top silicon is deep reactive ion etched to form a V-shaped solution channel with an aspect ratio of 8:1 to 12:1, a sidewall angle of 50° to 60°, and a channel depth of 50 μm. After the etching is completed, O2 plasma is introduced to remove residual photoresist and clean the surface to ensure that the channel structure is contaminant-free.

[0076] Combine Figure 9 In step 8, a second sacrificial phosphosilicate glass layer 8 with a thickness of 1 to 1.5 μm is deposited on the top silicon surface of SOI wafer structure 7 using a plasma-enhanced chemical vapor deposition process. A photolithographic mask is used to retain the solution channel area, while the remaining area is wet-etched using a solution with a volume ratio of HF to H₂O of 1:10. The second sacrificial phosphosilicate glass layer 8 has a thickness of 1 to 1.5 μm and is used to fill the solution channel.

[0077] Combine Figure 10 In step 9, a gold layer is magnetron sputtered on the top silicon surface of the SOI wafer structure 7 with the same parameters as in step 6 and an overlay alignment accuracy of less than 0.5 μm to form a second bonding electrode layer 9.

[0078] Combine Figure 11 In step 10, the first bonding electrode layer 6 and the second bonding electrode layer 9 are hot-pressed and bonded at 300°C and 10 MPa for 30 minutes. Ar plasma pre-cleaning is performed before bonding. After bonding, ultrasonic scanning shows a void ratio of less than 0.8%.

[0079] Combine Figure 12 In step 11, the bottom silicon of SOI wafer structure 7 is etched using the Bosch process at the alignment mark positions formed in step 7. SF6 gas is used during the etching phase at a flow rate of 200 sccm and a power of 800 W. During the passivation phase, C4F8 gas is switched to a flow rate of 100 sccm and a power of 600 W, with an etch rate of 8 μm / min. The thickness is monitored in real time using a laser interferometer, and etching is terminated when the buried oxide layer is reached, with an accuracy of ±0.5 μm.

[0080] Combine Figure 13 In step 12, the first and second phosphosilicate glass sacrificial layers 4 and 8 are removed sequentially using a 49% HF solution, and the buried oxide layer is removed using a BOE solution. Subsequently, annealing is performed at 450°C in an N2 environment for one hour to form an ohmic contact with a contact resistance of 0.8Ω·cm².

[0081] A 500nm-thick gold layer is sputtered onto the backside of the top silicon layer of the SOI wafer structure 7, and then patterned by photolithography to form a gold-based reflective mirror 10. Finally, a glass cover plate is used for vacuum bonding at a vacuum level of less than 1×10⁻³Pa, a temperature of 200°C, and a pressure of 5MPa, completing the hermetic package.

[0082] The embodiment of the present invention further provides another method for preparing a MEMS deformable mirror based on double silicon gold bonding, which differs from the second embodiment in that:

[0083] (1) Substrate optimization: 8-inch SOI wafer structure is used instead of 6-inch silicon wafer, the thickness of SOI top silicon is adjusted to 10~15μm, and the thickness of buried oxide layer is 1~2μm;

[0084] (2) Improvement of bonding process: The temperature of hot-press bonding between gold and gold is increased to 350~400℃, the pressure is increased to 15~20MPa, the bonding time is shortened to 15~20 minutes, the thickness of the bonding layer is controlled to 800~1000nm, and the shear strength is increased to more than 70MPa;

[0085] (3) Solution channel design: The aspect ratio of the V-shaped solution channel is adjusted to 10:1~15:1, the sidewall angle is optimized to 55°~65°, and the etching rate is increased to 10μm / min;

[0086] (4) Adjustment of sacrificial layer material: The second phosphosilicate glass sacrificial layer adopts a boron-phosphorus co-doping process, with a boron doping concentration of 2~4wt% and a phosphorus doping concentration of 6~8wt%, and the etching uniformity is improved to within ±3%.

[0087] The embodiment of the present invention further provides another method for preparing a MEMS deformable mirror based on double silicon gold bonding, which differs from the second embodiment in that:

[0088] (1) Innovation in electrode structure: The first bonding electrode layer adopts an Au / TiW composite structure, the TiW transition layer thickness is 50~80nm, the surface roughness Ra<0.5nm, and the interface adhesion is improved by 30%;

[0089] (2) Optimization of diversion grooves: The solution diversion grooves are designed with a bionic spiral fractal design, with a main groove width of 4-8 μm, a branch groove width of 1-3 μm, and 3-5 fractal iterations, which increases the diversion efficiency by 50%;

[0090] (3) Etching monitoring technology: In step 11, in-situ X-ray diffraction technology is used to monitor the deep silicon etching depth in real time, with a termination accuracy of ±0.2μm;

[0091] (4) Reflection layer composite process: The gold-based reflective mirror adopts Au / Ag / NiCr three-layer gradient coating, with a reflectivity of >99.8% in the visible light band, thermal stability improved to 600℃, and the mirror surface roughness RMS further reduced to 0.1~0.2nm.

[0092] The present invention provides a MEMS deformable mirror based on double silicon gold bonding and a method for fabricating the same. While there are numerous methods and approaches for implementing this technical solution, the aforementioned are merely preferred embodiments of the present invention. It should be noted that those skilled in the art may make various improvements and modifications without departing from the principles of the present invention, and such improvements and modifications are also within the scope of protection of the present invention. Components not specified in this embodiment may be implemented using existing technologies.

Claims

1. A double silicon gold bonded MEMS deformable mirror, characterized in that: It includes a silicon wafer substrate, a silicon nitride insulating layer, a lower polysilicon electrode, a first phosphorus silicon glass sacrificial layer, an in-situ doped polysilicon layer, a first bonding electrode layer, an SOI wafer structure, a second bonding electrode layer and a gold-based reflective mirror; On the silicon wafer substrate, a silicon nitride insulating layer, a lower polysilicon electrode, a first phosphosilicate glass sacrificial layer, and an in-situ doped polysilicon layer are sequentially arranged from near to far; Etching the in-situ doped polysilicon layer to form upper interdigital electrodes, stress relief holes and solution diversion grooves; The first bonding electrode layer is provided on the upper interdigital electrode; The SOI sheet structure is arranged on the first bonding electrode layer; The top silicon layer of the SOI wafer structure is etched and patterned to form a solution channel; The second bonding electrode layer is provided on the top silicon layer of the SOI wafer structure; The first bonding electrode layer and the second bonding electrode layer perform gold-to-gold bonding to complete double-sided silicon wafer connection; After the SOI wafer structure is subjected to deep silicon etching and structure release, a mirror support layer is formed on the back side of the top silicon layer of the SOI wafer structure; The gold-based reflecting mirror is arranged on a mirror support layer.

2. The double silicon gold bonded MEMS deformable mirror according to claim 1, characterized in that: The depth of the trapezoidal alignment mark on the back side of the silicon wafer substrate is 3-5 μm.

3. The double silicon gold bonded MEMS deformable mirror according to claim 1, characterized in that: The thickness of the silicon nitride insulating layer is 500-600 nm.

4. The double silicon gold bonded MEMS deformable mirror according to claim 1, characterized in that: The thickness of the lower polysilicon electrode is 450-550 nm, and the line width accuracy is ±0.1-0.2 μm.

5. The double silicon gold bonded MEMS deformable mirror according to claim 1, characterized in that: The thickness of the first phosphosilicate glass sacrificial layer is 2-3 μm.

6. The double silicon gold bonded MEMS deformable mirror according to claim 1, characterized in that: The thickness of the in-situ doped polysilicon layer is 2.5-3.5 μm, the stress release holes are array-type, the diameter of the stress release holes is 1.5-2.5 μm, the spacing is 4-6 μm, and the width of the solution diversion groove is 2-5 μm.

7. The double silicon gold bonded MEMS deformable mirror according to claim 1, characterized in that: The thickness of the first bonding electrode layer and the second bonding electrode layer are both 500-600 nm.

8. The double silicon gold bonded MEMS deformable mirror according to claim 1, characterized in that: The solution channel has a V-shaped structure, a depth-to-width ratio of 8:1-12:1, and a sidewall angle of 50°-60°.

9. A method for preparing a double silicon gold bonded MEMS deformable mirror according to any one of claims 1 to 8, characterized in that: The following steps are involved: Step 1: Clean a 4-inch or 6-inch n-type double-sided polished silicon wafer substrate with a thickness of 675 μm using RCA standard cleaning solution, and etch alignment marks on the back side of the silicon wafer substrate using a deep reactive ion etching process; Step 2: depositing a silicon nitride insulating layer on the front surface of the silicon wafer substrate using a low-pressure chemical vapor deposition process, and controlling the stress to be less than 100 MPa; Step 3: depositing a polysilicon layer on the front surface of the silicon nitride insulating layer using a plasma enhanced chemical vapor deposition process, and patterning it after thinning and ion implantation to form a lower polysilicon electrode; Step 4: depositing a first phosphosilicate glass sacrificial layer on the front surface of the lower polysilicon electrode by plasma enhanced chemical vapor deposition and performing a thinning process; Step 5: depositing an in-situ doped polysilicon layer on the front surface of the first phosphosilicate glass sacrificial layer using a low-pressure chemical vapor deposition process, thinning it, and then simultaneously etching it to form upper interdigital electrodes, arrayed stress relief holes, and solution diversion grooves; Step 6: magnetron sputtering a gold layer on the front surface of the upper interdigital electrode, aligning it with the alignment mark etched on the back surface of the silicon wafer substrate in step 1 and completing double-layer overlay to form a first bonding electrode layer; Step 7: ultrasonically clean the SOI wafer structure, etch the back side of the bottom silicon of the SOI wafer structure using a deep reactive ion etching process to form alignment marks, and etch and pattern the top silicon surface of the SOI wafer structure to form a solution channel; Step 8: depositing a second sacrificial phosphosilicate glass layer on the top silicon front surface of the SOI wafer structure using a plasma-enhanced chemical vapor deposition process, selectively removing excess phosphosilicate glass material, and retaining only the solution channel area for filling; Step 9: magnetron sputtering a gold layer on the front surface of the top silicon of the SOI wafer structure, aligning it with the alignment mark etched on the back surface of the bottom silicon of the SOI wafer structure in step 7, and completing double-layer overlay to form a second bonding electrode layer; Step 10: Performing gold-to-gold thermocompression bonding on the first bonding electrode layer and the second bonding electrode layer to complete the mechanical and electrical connection of the double-sided silicon wafer; Step 11, etching the bottom silicon of the SOI wafer structure to its buried oxide layer using a deep silicon etching process at the alignment mark position formed on the back side of the bottom silicon of the SOI wafer structure according to step 7; Step 12: removing the first phosphosilicate glass sacrificial layer, the second phosphosilicate glass sacrificial layer, and the buried oxide layer of the SOI wafer structure to complete the structure release, and performing an annealing treatment in an inert gas environment to form an ohmic contact between the first bonding electrode layer and the second bonding electrode layer and the silicon; Step 13: sputtering a gold layer on the back side of the top silicon layer of the SOI wafer structure and patterning it to form a gold-based reflective mirror, and then performing vacuum bonding and packaging.

10. The method according to claim 9, characterized in that In step 8, the thickness of the second phosphosilicate glass sacrificial layer is 1-1.5 μm; In step 11, deep silicon etching includes an etching stage and a passivation stage. In the etching stage, SF6 gas with a flow rate of 200 sccm and an RF power of 800 W is used. In the passivation stage, the gas is switched to C4F8 gas with a flow rate of 100 sccm and a power of 600 W. The Bosch process is realized by alternating cycles, and the etching rate reaches 8 μm / min. During the deep silicon etching process, the thickness of the silicon layer is monitored in real time by a laser interferometer. When the buried oxide layer of the SOI wafer structure is etched, the reflectivity suddenly changes, and the etching is terminated.

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