Method of measuring overlay error

Abstract

The present disclosure relates to the technical field of semiconductor, and provides a method for measuring overlay error, which is used to solve the technical problem of how to efficiently and accurately measure the overlay error between the current layer and the previous layer. The method comprises: obtaining a first scanning image of a first conductive pattern and a second conductive pattern in a semiconductor structure; determining a first overlay error between the second conductive pattern and the first conductive pattern according to the first scanning image; obtaining a second scanning image of a third conductive pattern and the first conductive pattern in the semiconductor structure; determining a second overlay error between the third conductive pattern and the first conductive pattern according to the second scanning image; and determining a third overlay error between the third conductive pattern and the second conductive pattern according to the second overlay error and the first overlay error. In this way, the overlay error between the current layer pattern and the previous layer pattern can be accurately and efficiently obtained, the product defects caused by the overlay error can be reduced, and the quality and yield of the product can be improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and particularly to a method for measuring overlay error. BACKGROUND

[0002] In a semiconductor manufacturing process, multiple photolithography processes are usually needed to transfer different layers of circuit patterns onto a wafer. By measuring the positional deviation between a current layer pattern and a previous layer pattern on the wafer, an overlay error (OVL) between the two layer patterns can be obtained. The overlay error is a key parameter for measuring the alignment accuracy of different layer patterns, and directly affects the yield and performance of a chip.

[0003] Therefore, how to efficiently and accurately measure the overlay error between a current layer pattern and a previous layer pattern becomes a technical problem to be solved. SUMMARY

[0004] Embodiments of the present disclosure provide a method for measuring overlay error, comprising: obtaining a first scanning image of a first conductive pattern and a second conductive pattern in a semiconductor structure, wherein the second conductive pattern is located above the first conductive pattern; determining a first overlay error between the second conductive pattern and the first conductive pattern according to the first scanning image; obtaining a second scanning image of a third conductive pattern and the first conductive pattern in the semiconductor structure, wherein the third conductive pattern is located above the second conductive pattern; determining a second overlay error between the third conductive pattern and the first conductive pattern according to the second scanning image; and determining a third overlay error between the third conductive pattern and the second conductive pattern according to the second overlay error and the first overlay error.

[0005] In some embodiments, the determining the third overlay error between the third conductive pattern and the second conductive pattern according to the second overlay error and the first overlay error comprises: calculating a difference value of the second overlay error and the first overlay error to obtain the third overlay error.

[0006] In some embodiments, the obtaining the first scanning image of the first conductive pattern and the second conductive pattern in the semiconductor structure comprises: performing first measurement on the semiconductor structure formed with the second conductive pattern in a first process station to generate the first scanning image.

[0007] In some embodiments, the obtaining the second scanning image of the third conductive pattern and the first conductive pattern in the semiconductor structure comprises: performing second measurement on the semiconductor structure formed with the third conductive pattern in a second process station after the first process station to generate the second scanning image.

[0008] In some embodiments, the first measurement and the second measurement comprise high voltage electron scanning electron microscope measurement.

[0009] In some embodiments, the measurement method further comprises: generating a first measurement result according to the third overlay error being less than or equal to a preset overlay error, wherein the first measurement result is used to indicate that the semiconductor structure is allowed to enter a next process station.

[0010] In some embodiments, the measurement method further comprises: generating a second measurement result according to the third overlay error being greater than the preset overlay error, wherein the second measurement result is used to indicate that the semiconductor structure is prohibited from entering the next process station.

[0011] In some embodiments, the preset overlay error is less than 14.5 nanometers.

[0012] In some embodiments, the first conductive pattern comprises a first contact structure, the second conductive pattern comprises a metal layer, and the third conductive pattern comprises a second contact structure, wherein the second contact structure, the metal layer, and the first contact structure are sequentially connected from top to bottom, and the first contact structure is connected to a peripheral circuit in the semiconductor structure.

[0013] In some embodiments, the second conductive pattern and the first conductive pattern are made of different materials; and the third conductive pattern and the first conductive pattern are made of different materials.

[0014] In the embodiments of the present disclosure, by respectively acquiring the first scanning image and the second scanning image, the first overlay error between the second conductive pattern and the first conductive pattern and the second overlay error between the third conductive pattern and the first conductive pattern can be measured step by step, and thus the third overlay error between the third conductive pattern and the second conductive pattern can be obtained. In this way, in the first aspect, the overlay error between the current layer pattern (i.e., the third conductive pattern) and the previous layer pattern (i.e., the second conductive pattern) can be accurately and efficiently obtained, product defects caused by the overlay error can be reduced, and the quality and yield of the product can be improved. In the second aspect, the technical problem that the station cannot directly measure the overlay error between the current layer pattern and the previous layer pattern in some processes is effectively solved, and an effective measurement means is provided for measuring the overlay error in the semiconductor manufacturing process. In the third aspect, the measurement process is compatible with the current measurement process, and no additional measurement process needs to be added, which is conducive to controlling the production cost. In the fourth aspect, the alignment accuracy between each layer can be effectively evaluated, and detailed and accurate data support is provided for process optimization. BRIEF DESCRIPTION OF DRAWINGS

[0015] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0016] Figure 1A is a schematic diagram of a semiconductor structure provided by an embodiment;

[0017] Figure 1B is a scanned image of a semiconductor structure provided by an embodiment;

[0018] Figure 2 is a flow chart of a method for measuring overlay error provided by an embodiment of the present disclosure;

[0019] Figure 3A is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure and having a second conductive pattern formed thereon;

[0020] Figure 3B is a schematic diagram of a first scanned image provided by an embodiment of the present disclosure;

[0021] Figure 4A is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure and having a third conductive pattern formed thereon;

[0022] Figure 4B is a schematic diagram of a second scanned image provided by an embodiment of the present disclosure;

[0023] Figure 5 The overlay error measurement results and physical failure analysis results provided by the embodiments of the present disclosure are as follows;

[0024] Figure 6 It is a fitting function of the measurement data and physical failure analysis data provided by the embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and examples. Although the accompanying drawings illustrate exemplary implementations of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0026] The following paragraphs describe the present disclosure in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present disclosure.

[0027] It is to be understood that the meaning of "on," "over," and "above" in the present disclosure should be interpreted in the broadest possible way, such that "on" not only means "on" something with no intervening intermediate characteristics or layers (i.e., directly on something), but also includes "on" something with intervening intermediate characteristics or layers.

[0028] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0029] In the embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of the underlying or overlying structure, or can have a scope that is less than the scope of the underlying or overlying structure. Further, the layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure, or the layer can be between any pair of horizontal planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include a plurality of sub-layers.

[0030] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0031] Overlay error after lithography and development is usually measured in the current process (also known as the current process site, referred to as the station). However, in some specific processes, due to the size and thickness limitations of some patterns, the overlay error between the current layer pattern and the previous layer pattern cannot be obtained after the station measurement, resulting in a lack of effective overlay error detection means on the production line (inline), affecting the quality and yield of the product. In the following, an exemplary description will be given in combination with Figure 1A and Figure 1B

[0032] Figure 1A is a schematic diagram of a semiconductor structure provided by an embodiment, Figure 1B is a scanning image of a semiconductor structure provided by an embodiment.

[0033] Referring to Figure 1A , the semiconductor structure includes a first contact structure 102, a metal layer 104, and a second contact structure 106. The first contact structure 102, the metal layer 104, and the second contact structure 106 can be formed in different process sites in sequence, respectively.

[0034] ​Generally, metrology is needed to obtain overlay error between the second contact structure 106 and the metal layer 104 in the process site of forming the second contact structure 106. However, due to the size and thickness limitation of the metal layer 104, for example, the thickness of the metal layer 104 is thin, not imaged under the scanning lens, resulting in that the overlay error between the second contact structure 106 and the metal layer 104 cannot be obtained in the process site of forming the second contact structure 106, and further resulting in that there is a lack of effective overlay error detection means on the production line, affecting the quality and yield of the product. Here, Figure 1B Only the second contact structure 106 and the first contact structure 102 can be seen in the scanning image.

[0035] Based on one or more of the above technical problems, the embodiments of the present disclosure provide a metrology method of overlay error.

[0036] Figure 2 is a flowchart of a metrology method of overlay error provided by the embodiments of the present disclosure. Referring to Figure 2 The metrology method comprises:

[0037] Step S210: obtaining a first scanning image of a first conductive pattern and a second conductive pattern in a semiconductor structure, wherein the second conductive pattern is located above the first conductive pattern;

[0038] Step S220: determining a first overlay error between the second conductive pattern and the first conductive pattern according to the first scanning image;

[0039] Step S230: obtaining a second scanning image of a third conductive pattern and the first conductive pattern in the semiconductor structure, wherein the third conductive pattern is located above the second conductive pattern;

[0040] Step S240: determining a second overlay error between the third conductive pattern and the first conductive pattern according to the second scanning image;

[0041] Step S250: determining a third overlay error between the third conductive pattern and the second conductive pattern according to the second overlay error and the first overlay error.

[0042] In the embodiment of the present disclosure, by respectively acquiring a first scan image and a second scan image, a first overlay error between the second conductive pattern and the first conductive pattern and a second overlay error between the third conductive pattern and the first conductive pattern can be measured step by step, thereby obtaining a third overlay error between the third conductive pattern and the second conductive pattern. Thus, firstly, the overlay error between the current layer pattern (i.e., the third conductive pattern) and the previous layer pattern (i.e., the second conductive pattern) can be accurately and efficiently obtained, reducing product defects caused by overlay error, which is beneficial to improving product quality and yield. Secondly, it effectively solves the technical problem that in certain processes, when a station cannot directly measure the overlay error between the current layer pattern and the previous layer pattern, it provides an effective measurement method for measuring overlay error in the semiconductor manufacturing process. Thirdly, it is compatible with the current measurement process and can be achieved without adding additional measurement processes, which is beneficial to controlling production costs. Fourthly, it can effectively evaluate the alignment accuracy between each layer, providing detailed and accurate data support for production process optimization.

[0043] Figure 3A is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure and having a second conductive pattern formed thereon. Figure 3B is a schematic diagram of a first scanned image provided by an embodiment of the present disclosure, Figure 4A is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure, in which a third conductive pattern is formed. Figure 4B This is a schematic diagram of a second scan image provided by an embodiment of the present disclosure. Figure 2 、 Figure 3A 、 Figure 3B 、 Figure 4A and Figure 4B The method for measuring the overlay error provided in the embodiment of the present disclosure is exemplarily described.

[0044] In step S210, refer to Figure 2 As shown, a first scanning image of a first conductive pattern and a second conductive pattern in a semiconductor structure is acquired, wherein the second conductive pattern is located above the first conductive pattern.

[0045] A semiconductor structure generally refers to a structure formed on a semiconductor substrate (eg, silicon, germanium, etc.) through various semiconductor manufacturing processes. The semiconductor structure may be an intermediate structure at any stage in the manufacturing process.

[0046] In some embodiments, the semiconductor structure may include a single-layer structure, for example, the substrate 300 , more specifically, a silicon (Si) substrate, a germanium (Ge) substrate, a gallium arsenide (GaAs) substrate, a gallium phosphide (GaP) substrate, a silicon carbide (SiC) substrate, or a gallium nitride (GaN) substrate.

[0047] In other embodiments, the semiconductor structure may include a multilayer structure, for example, a substrate 300 and a first conductive pattern and a second conductive pattern located on the substrate. The present disclosure does not specifically limit the specific structure and materials of the semiconductor structure; any structure formed by a semiconductor manufacturing process may be referred to as a semiconductor structure.

[0048] In practical applications, a substrate 300 may be provided, and patterns with specific shapes and sizes may be formed on the substrate through semiconductor manufacturing processes such as ion doping, thin film deposition, photolithography, and etching. These patterns may constitute various parts of a semiconductor structure, such as transistors, memory arrays, interconnects, and the like.

[0049] In some embodiments, reference Figure 3A As shown, the first conductive pattern includes a first contact structure 302 , and the second conductive pattern includes a metal layer 304 .

[0050] Reference Figure 3A As shown, a first contact structure 302 and a metal layer 304 can be sequentially formed on a substrate, with the first contact structure 302 connecting to an active region in the substrate, and the metal layer 304 connecting to the first contact structure 302. Here, the active region (e.g., a source or a drain) can be electrically led out through the first contact structure 302 and the metal layer 304.

[0051] It should be noted that the first conductive pattern and the second conductive pattern can be conductive patterns located at different levels in the semiconductor structure. The conductive patterns can include, for example, contact structures / contact plugs for connecting a metal layer and an active area, metal layers / interconnect layers, interconnect contacts (vias) for connecting two metal layers, and pads. This disclosure does not specifically limit the types and locations of the first conductive pattern and the second conductive pattern. Any pattern with conductive properties in a semiconductor structure can be referred to as a conductive pattern. For ease of understanding, the following description will take the first conductive pattern as the first contact structure 302 and the second conductive pattern as the metal layer 304 as an example.

[0052] The first scanning image refers to an image obtained using a scanning electron microscope (SEM), an optical microscope or other imaging device. By obtaining the first scanning image, the relative position of the first conductive pattern and the second conductive pattern and the respective contour shapes of the first conductive pattern and the second conductive pattern can be displayed.

[0053] In some embodiments, step S210 includes performing a first measurement on the semiconductor structure having the second conductive pattern formed thereon at a first process station to generate a first scan image. The first process station may be the current process station where the second conductive pattern is formed, and the first measurement includes high-voltage scanning electron microscopy (HSE) measurement.

[0054] Referring to Figure 3A After the metal layer 304 is formed, a high voltage scanning electron microscope (HV-SEM) measurement can be performed on the structure shown in FIG. 4A to generate a first scanning image 402 as shown in FIG. 4B. Figure 3A Figure 3B The first scanning image 402 shows two first contact structures, i.e., a first contact structure 302A and a first contact structure 302B, and two metal layers, i.e., a metal layer 304A and a metal layer 304B. Figure 3B Figure 3A Figure 3B

[0055] It is noted that the first measurement can also be other measurement techniques that can image the first conductive pattern and the second conductive pattern. The HV-SEM is often used to measure overlay error (OVL) of different materials due to the difference in absorption of secondary electrons and backscattered electrons by different materials, which results in different image contrasts.

[0056] In some embodiments, the material of the second conductive pattern is different from the material of the first conductive pattern. For example, the material of the first conductive pattern includes polysilicon or doped polysilicon, and the material of the second conductive pattern includes tungsten or the like.

[0057] In step S220, referring to Figure 2 According to the first scanning image 402, a first overlay error between the second conductive pattern and the first conductive pattern is determined. For example, the first overlay error between the second conductive pattern and the first conductive pattern can be calculated based on the relative positions or the respective contour shapes of the first conductive pattern and the second conductive pattern in the first scanning image 402.

[0058] Specifically, the center position of the first conductive pattern can be determined based on the imaging of the first conductive pattern in the first scanning image 402, and the center position of the second conductive pattern can be determined based on the imaging of the second conductive pattern in the first scanning image 402. The first overlay error can be calculated based on the position deviation between the center position of the second conductive pattern and the center position of the first conductive pattern.

[0059] Of course, in other embodiments, the first overlay error can also be calculated based on the respective reference points on the respective contour shapes of the first conductive pattern and the second conductive pattern in the first scanning image 402.

[0060] Referring to Figure 3B ​​​​As shown, the center position of the first contact structure 302A, the center position of the first contact structure 302B, the center position of the metal layer 304A, and the center position of the metal layer 304B can be determined respectively; the first position deviation between the center position of the metal layer 304A and the center position of the first contact structure 302A is calculated, and the second position deviation between the center position of the metal layer 304B and the center position of the first contact structure 302B is calculated; the average of the first position deviation and the second position deviation is calculated, and the average of the first position deviation and the second position deviation is taken as the first overlay error between the metal layer 304 and the first contact structure 302.

[0061] Here, in the case where the number of the first contact structure 302 and the number of the metal layer 304 are both plural, the position deviation between each metal layer 304 and the corresponding first contact structure 302 can be calculated to obtain a plurality of position deviations, and the first overlay error can be obtained by averaging the plurality of position deviations.

[0062] In practical applications, the overlay error between two conductive patterns can be determined by imaging the two conductive patterns in the scanning image, and the overlay error usually includes deviations in both horizontal (e.g., X-axis) and vertical (e.g., Y-axis) directions. The process of determining the overlay error usually involves image processing and analysis, which can include edge detection, feature matching, geometric measurement, etc. to ensure the accuracy of the measurement.

[0063] In step S230, referring to Figure 2 As shown, a second scanning image of the third conductive pattern and the first conductive pattern in the semiconductor structure is obtained, wherein the third conductive pattern is located on the second conductive pattern.

[0064] In some embodiments, referring to Figure 4A As shown, the third conductive pattern includes a second contact structure 306.

[0065] Referring to Figure 4A As shown, the second contact structure 306 can be formed on the metal layer 304, and the second contact structure 306 connects the metal layer 304. Here, the second contact structure 306, the metal layer 304, and the first contact structure 302 are connected in turn from top to bottom, and the first contact structure 302 can connect a peripheral circuit in the semiconductor structure, for example, the first contact structure 302 connects the active region of a transistor in the peripheral circuit.

[0066] Referring to Figure 4A As shown, the semiconductor structure can include a storage array and a peripheral circuit, wherein the storage array is located in an array region, and the peripheral circuit is located in a peripheral region. Here, the first contact structure 302, the metal layer 304, and the second contact structure 306 are all located in the peripheral region.

[0067] It should be noted that the first conductive pattern, the second conductive pattern and the third conductive pattern can be conductive patterns located at different levels in the semiconductor structure. For example, the first conductive pattern can be a contact structure for connecting the metal layer and the peripheral circuit (referred to as the peripheral contact structure (PC)), the second conductive pattern can be the first interconnected metal layer (M0), and the third conductive pattern can be a contact structure for connecting the metal layer and the pad (referred to as the interconnected contact structure (CT)). The present disclosure does not specifically limit the types and positions of the first conductive pattern, the second conductive pattern and the third conductive pattern. For the conductive patterns, please refer to the relevant description above.

[0068] The second scanned image refers to an image captured using a scanning electron microscope (SEM), optical microscope, or other imaging device. This second scanned image can display the relative positions of the first and third conductive patterns, as well as the outlines of each of the first and third conductive patterns. It should be noted that due to the thickness of the second conductive pattern, the second conductive pattern is not imaged by the scanning lens, meaning that the second conductive pattern is not visible in the second scanned image.

[0069] In some embodiments, step S230 includes performing a second measurement on the semiconductor structure having the third conductive pattern formed thereon at a second process station subsequent to the first process station to generate a second scan image. The second process station may be the current process station in which the third conductive pattern is formed, and the second measurement includes high-voltage electron scanning electron microscopy measurement.

[0070] Reference Figure 4A As shown, after forming the second contact structure 306, the second contact structure 306 may be formed in the current process station. Figure 4A The structure shown in the figure is measured by high voltage electron scanning electron microscope to generate the following Figure 4B A second scan image 404 is shown. Figure 4B Two first contact structures, namely first contact structure 302A and first contact structure 302B, and corresponding two second contact structures, namely second contact structure 306A and second contact structure 306B, are shown. However, the number of first contact structures 302 and the number of second contact structures 306 are not limited to Figure 4A and Figure 4B shown.

[0071] It should be noted that the second measurement can also be other measurement technologies that can obtain images of the first conductive pattern and the third conductive pattern. Among them, high-voltage electron scanning electron microscopy measurement is often used to measure the overlay error (OVL) of different materials because different materials have different absorption differences in secondary electrons and backscattered electrons, resulting in different image contrasts.

[0072] In some embodiments, the third conductive pattern and the first conductive pattern are made of different materials. For example, the first conductive pattern is made of polysilicon or doped polysilicon, and the third conductive pattern is made of metal tungsten.

[0073] In step S240, refer to Figure 2 As shown, a second overlay error between the third conductive pattern and the first conductive pattern is determined based on the second scanned image. For example, the second overlay error between the third conductive pattern and the first conductive pattern can be calculated based on the relative positions or respective contour shapes of the first conductive pattern and the third conductive pattern in the second scanned image.

[0074] Specifically, the center position of the first conductive pattern can be determined by imaging the first conductive pattern in the second scanned image; the center position of the third conductive pattern can be determined by imaging the third conductive pattern in the second scanned image; and the position deviation between the center position of the third conductive pattern and the center position of the first conductive pattern can be calculated to obtain the second overlay error.

[0075] Of course, in other embodiments, corresponding reference points on the contours of the first conductive pattern and the third conductive pattern in the second scanned image may be selected to calculate the second overlay error.

[0076] Reference Figure 4B As shown, the center position of the first contact structure 302A, the center position of the first contact structure 302B, the center position of the second contact structure 306A, and the center position of the second contact structure 306B can be determined respectively; the third position deviation between the center position of the second contact structure 306A and the center position of the first contact structure 302A is calculated, and the fourth position deviation between the center position of the second contact structure 306B and the center position of the first contact structure 302B is calculated; the average value of the third position deviation and the fourth position deviation is calculated, and the average value of the third position deviation and the fourth position deviation is used as the second overlay error between the second contact structure 306 and the first contact structure 302.

[0077] Here, when there are multiple first contact structures 302 and second contact structures 306, the position deviation between each second contact structure 306 and the corresponding first contact structure 302 can be calculated to obtain multiple position deviations. By averaging the multiple position deviations, a second overlay error can be obtained.

[0078] In step S250, a third overlay error between the third conductive pattern and the second conductive pattern is determined according to the second overlay error and the first overlay error. Here, the third overlay error between the third conductive pattern and the second conductive pattern can be indirectly measured through the second overlay error and the first overlay error, so as to realize accurate and efficient measurement of the overlay error between the third conductive pattern and the second conductive pattern.

[0079] In some embodiments, the step S250 includes: calculating a difference between the second overlay error and the first overlay error to obtain the third overlay error.

[0080] In the embodiment, the total position deviation of the third conductive pattern relative to the first conductive pattern can be the accumulation of the position deviation of the second conductive pattern relative to the first conductive pattern and the position deviation of the third conductive pattern relative to the second conductive pattern. By calculating the difference between the second overlay error and the first overlay error, the third overlay error between the third conductive pattern and the second conductive pattern can be accurately obtained. In addition, the measurement of the first overlay error and the second overlay error are both based on the first conductive pattern, that is, the same reference is used, which is conducive to improving the accuracy of the third overlay error.

[0081] In some embodiments, the measurement method further includes: generating a first measurement result according to that the third overlay error is less than or equal to a preset overlay error, wherein the first measurement result is used to indicate that the semiconductor structure is allowed to enter a next process site; and generating a second measurement result according to that the third overlay error is greater than the preset overlay error, wherein the second measurement result is used to indicate that the semiconductor structure is prohibited from entering the next process site.

[0082] In the embodiment, the corresponding measurement result is generated according to the comparison result of the third overlay error and the preset overlay error. Specifically, when the measured third overlay error is less than or equal to the preset overlay error, it indicates that the alignment accuracy of the current semiconductor structure meets the process requirements, so the first measurement result is generated, and the current semiconductor structure can enter the next process site for subsequent processes. Conversely, when the measured third overlay error is greater than the preset overlay error, it indicates that the alignment accuracy of the current semiconductor structure does not meet the process requirements, so the second measurement result is generated, and the current semiconductor structure needs to be reworked or even scrapped in serious cases, so the current semiconductor structure should be prohibited from entering the next process site to avoid waste of processes and raw materials.

[0083] It should be noted that the preset overlay error can be a predefined maximum deviation value for evaluating whether the alignment accuracy in the manufacturing process is within an acceptable range. In the embodiment, the preset overlay error is less than 14.2 nanometers. In actual applications, the preset overlay error can be reasonably set according to design requirements to ensure that the alignment accuracy between each layer of patterns is within an acceptable range, and the present disclosure does not have special limitations on this.

[0084] In the semiconductor manufacturing process, it is essential to ensure the accurate alignment between each layer of pattern, because it directly affects the performance and reliability of the final product. In the embodiment, by comparing the third overlay error and the preset overlay error, the corresponding measurement result is generated, which can ensure that only the semiconductor structure meeting the alignment accuracy requirement can enter the next process station, thereby reducing the defects caused by poor alignment and improving the overall production yield. In addition, when the third overlay error exceeds the preset overlay error, the second measurement result is generated in time and the semiconductor structure is prevented from entering the next station, which can avoid the subsequent process steps based on the error and reduce the waste of resources and time delay.

[0085] In order to verify the effectiveness of the measurement method provided in the above embodiment, physical failure analysis (PFA) can be used for verification, and the following will be further described in combination with Figure 5 and Figure 6 .

[0086] Figure 5 is a schematic diagram of the overlay error measurement result and the physical failure analysis result provided by the embodiment of the present disclosure, Figure 6 is a fitting function of the measurement data and the physical failure analysis data provided by the embodiment of the present disclosure. Wherein, Figure 5 CT_PC_Y in the above formula indicates that the measurement object is a mutual connection contact structure CT and a peripheral contact structure PC, SEM indicates the HV-SEM scanning image of CT and PC, PFA IMG indicates the PFA slice image of CT and PC, PV2E indicates the measurement data of the overlay error between CT and PC obtained according to the SEM scanning image, and PFA indicates the physical failure analysis data of the overlay error between CT and PC obtained according to the PFA slice image. In addition, in order to verify the effectiveness of the measurement method provided in the above embodiment, a plurality of positions can be selected, for example, Figure 5 five positions are provided in the above formula, and the five position numbers are (1) to (5).

[0087] Referring to Figure 5 , according to the SEM at positions (1) to (5), the corresponding measurement data of the overlay error between CT and PC are -11.517 nm, -9.293 nm, 9.672 nm, 10.632 nm and 0.509 nm respectively; according to the PFA IMG at positions (1) to (5), the corresponding physical failure analysis data of the overlay error between CT and PC are -16.4 nm, -17.37 nm, 6.4 nm, 13.25 nm and 0.6 nm respectively.

[0088] With the above measurement data as the horizontal axis (i.e., the x-axis) and the physical failure analysis data as the vertical axis (i.e., the y-axis), the following Figure 6 The coordinate axes are shown. Based on the measurement data and physical failure analysis data at the above positions (1) to (5), the following can be obtained: Figure 6 The five coordinate points shown (i.e. Figure 6 By fitting the five coordinate points, we can get the following: Figure 6 The fitting function shown is: y = 1.2995x - 2.7048, where the slope is 1.2995 and the R square (R 2 ) is 0.9576.

[0089] Here, R 2 The value range is from 0 to 1, R 2 The closer it is to 1, the higher the degree of agreement. Figure 6 It can be seen that by comparing the measurement results with the physical failure analysis results, the measurement data are highly consistent with the physical failure analysis data, that is, the measurement method provided by the above embodiment can effectively measure the overlay error between the current layer pattern and the previous layer pattern.

[0090] It should be noted that the overlay error between the interconnect contact structure CT and the first interconnect metal layer M0 is mainly contributed by the overlay error of CT_PC in the CT etch (CT Etch, CTEH) site. Therefore, Figure 5 The measurement objects in may be the interconnection contact structure CT and the peripheral contact structure PC.

[0091] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A method for measuring overlay error, characterized in that: include: Acquire a first scan image of a first conductive pattern and a second conductive pattern in a semiconductor structure, wherein the second conductive pattern is located above the first conductive pattern; determining a first overlay error between the second conductive pattern and the first conductive pattern based on images of the second conductive pattern and the first conductive pattern in the first scanned image; Acquire a second scan image of a third conductive pattern and the first conductive pattern in the semiconductor structure, wherein the third conductive pattern is located above the second conductive pattern; determining a second overlay error between the third conductive pattern and the first conductive pattern according to images of the third conductive pattern and the first conductive pattern in the second scanned image; A third overlay error between the third conductive pattern and the second conductive pattern is determined based on the second overlay error and the first overlay error.

2. The method for measuring overlay error according to claim 1, wherein: Determining a third overlay error between the third conductive pattern and the second conductive pattern according to the second overlay error and the first overlay error includes: The difference between the second overlay error and the first overlay error is calculated to obtain the third overlay error.

3. The method for measuring overlay error according to claim 1, wherein: The acquiring of a first scanning image of a first conductive pattern and a second conductive pattern in a semiconductor structure includes: In a first process station, a first measurement is performed on the semiconductor structure formed with the second conductive pattern to generate the first scan image.

4. The method for measuring overlay error according to claim 3, wherein: The acquiring of the second scanned image of the third conductive pattern and the first conductive pattern in the semiconductor structure includes: In a second process station subsequent to the first process station, a second measurement is performed on the semiconductor structure formed with the third conductive pattern to generate the second scan image.

5. The method for measuring overlay error according to claim 4, wherein: The first measurement and the second measurement include high voltage electron scanning electron microscope measurements.

6. The method for measuring overlay error according to any one of claims 1 to 5, characterized in that: The measuring method further comprises: A first measurement result is generated according to the third overlay error being less than or equal to a preset overlay error, wherein the first measurement result is used to indicate that the semiconductor structure is allowed to enter a next process station.

7. The method for measuring overlay error according to claim 6, wherein: The measuring method further comprises: A second measurement result is generated according to the third overlay error being greater than the preset overlay error, wherein the second measurement result is used to indicate prohibiting the semiconductor structure from entering the next process station.

8. The method for measuring overlay error according to claim 6, wherein: The preset overlay error is less than 14.5 nanometers.

9. The method for measuring overlay error according to claim 1, wherein: The first conductive pattern includes a first contact structure, the second conductive pattern includes a metal layer, and the third conductive pattern includes a second contact structure, wherein the second contact structure, the metal layer, and the first contact structure are connected in sequence from top to bottom, and the first contact structure is connected to the peripheral circuit in the semiconductor structure.

10. The method for measuring overlay error according to claim 1, wherein: The second conductive pattern and the first conductive pattern are made of different materials; the third conductive pattern and the first conductive pattern are made of different materials.

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