Motorcycle voltage regulator chip driving circuit with zero-cross detection function

Abstract

The invention belongs to the technical field of motorcycle voltage regulator chip circuits, and particularly relates to a motorcycle voltage regulator chip driving circuit with a zero-cross detection function. Comprising a zero-cross detection module which is used for inputting three-phase electric signals PH1-PH3, judging whether the three-phase electric signals PH1-PH3 cross zero positively and negatively, outputting low-level signals when the three-phase electric signals PH1-PH3 are larger than zero, and outputting high-level signals when the three-phase electric signals PH1-PH3 are smaller than zero; the digital signal processing module is used for processing the signals VOD1-VOD3 output by the zero cross detection module and then outputting signals DLA and DLB; and the driving module is used for inputting the signals DLA and DLB and outputting the signals DRV1-DRV3 to the off-chip switching tube. According to the invention, the problem of large thermal load during high-power output can be effectively solved, and the voltage regulation precision and stability are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of motorcycle voltage regulator chip circuits, and in particular relates to a motorcycle voltage regulator chip drive circuit with a zero-crossing detection function. Background Art

[0002] In a motorcycle's electrical system, the performance of the voltage regulator chip circuit plays a key role in the stable operation of the entire vehicle. With the continuous innovation of motorcycle technology, especially the development trend of intelligentization and high performance, the requirements for voltage regulator chip circuits are becoming increasingly stringent. Accurate zero-crossing detection has become a core element to improve system performance.

[0003] At present, the common motorcycle voltage regulators on the market have exposed a series of technical defects that need to be solved when dealing with complex working conditions. The traditional thyristor short-circuit voltage regulator adopts a parallel voltage regulation mode. When the motorcycle is running at high speed and the engine is running at high speed, causing the output power of the magneto to increase significantly, the thermal load of the voltage regulator will rise sharply. In order to prevent the voltage regulator from being damaged by overheating, the existing means have to increase a large amount of heat dissipation area. This not only makes the voltage regulator bulky and significantly increases the cost, but also severely limits its application in the compact space layout of motorcycles. In particular, its applicability in high-power voltage regulation scenarios is greatly reduced. The existing voltage regulator chip circuit lacks an effective zero-crossing detection method and cannot adjust the working state in a timely and accurate manner according to the phase change of voltage and current. This causes the chip to operate at high load for a long time, accelerating the aging process of the chip and greatly shortening its service life.

[0004] Existing technologies also have significant shortcomings in terms of the stability and accuracy of voltage regulation. For example, thyristor open-circuit voltage regulators use a series voltage regulation method. When the output end is under heavy load, the thermal load problem will be further exacerbated, making it only suitable for low-power voltage regulation scenarios. Furthermore, when the engine is running at high speeds, due to the constraints of the thyristor's dv / dt parameters, long conduction is very likely to occur, which can lead to loss of control of the voltage regulator. When the motorcycle is in a state of drastic changes in engine operating conditions, such as acceleration and climbing, voltage fluctuations become extremely obvious. At this time, the existing voltage regulator chip circuit cannot accurately capture the voltage zero crossing point, making it difficult to accurately regulate the voltage. For example, in the electronic control unit of a motorcycle's electronic fuel injection system, which requires extremely high voltage stability, voltage instability can cause deviations in fuel injection control, seriously affecting engine performance and even damaging the equipment.

[0005] In addition, when the load of the motorcycle changes, the response speed of the existing voltage regulator chip circuit is significantly lagged. When the load instantaneously switches from a low-power indicator light to a high-power headlight, or when an additional electronic device is connected, the load current will instantaneously change significantly. At this time, since the traditional voltage regulator chip circuit cannot quickly detect the zero-crossing moment of the voltage and adjust the output in a timely manner, it will cause a large fluctuation in the output voltage and cannot quickly stabilize within an appropriate range, thereby affecting the normal operation of the electrical equipment. In devices such as the anti-theft alarm system of the motorcycle that have strict requirements for real-time and stable power supply, such voltage fluctuations may cause adverse situations such as false alarms.

[0006] In summary, the existing motorcycle voltage regulator chip circuit has significant technical defects in multiple aspects such as thermal load management, voltage regulation accuracy, and load response. To a large extent, the root cause of these problems is the lack of an accurate and effective zero-crossing detection function. Therefore, researching and developing a motorcycle voltage regulator chip circuit with a zero-crossing detection function has extremely important practical significance for improving the overall performance, reliability, and stability of the motorcycle electrical system. Summary of the Invention

[0007] The purpose of the present invention is to provide a motorcycle voltage regulator circuit with a zero-crossing detection function. The present invention can effectively solve a series of key problems including eliminating the deficiency of the existing voltage regulator having a large thermal load during high-power output, improving the voltage regulation accuracy and stability, and accelerating the load change response speed.

[0008] To solve the above technical problems, the present invention provides a motorcycle voltage regulator chip driving circuit with a zero-crossing detection function, including: A zero-crossing detection module, which is used to input three-phase electrical signals PH1~PH3 and determine whether the three-phase electrical signals PH1~PH3 are positive zero-crossing and negative zero-crossing. When the three-phase electrical signals PH1~PH3 are greater than zero, a low-level signal is output. When the three-phase electrical signals PH1~PH3 are less than zero, a high-level signal is output; the zero-crossing detection module includes a zero-crossing comparison level generation circuit, a level detection circuit, and a comparison circuit; wherein the zero-crossing comparison level generation circuit is used to generate a low-level signal VCOMP by controlling a constant current source for resistor voltage division through a switching tube; the level detection circuit is used to detect whether the three-phase electrical signals PH1~PH3 are zero-crossing and respectively output signals VC1~VC3; the comparison circuit is used to compare the low-level signal VCOMP with the signals VC1~VC3 respectively and output signals VOD1~VOD3 respectively; A digital signal processing module, which processes the signals VOD1~VOD3 output by the zero-crossing detection module and outputs signals DL_A and DL_B; A driving module, which is used to input signals DL_A and DL_B and output signals DRV1~DRV3 to off-chip switching transistors to control the on and off of the off-chip switching transistors.

[0009] Preferably, the zero-crossing comparison level generation circuit includes: current sources Ia~Id, PMOS transistors P1~P4, resistors R1~R2, and control signals F1~F4; one ends of the current sources Ia~Id are connected to the power supply VCC1, and the other ends are respectively connected to the sources of the PMOS transistors P4~P1. The gates of the PMOS transistors P1~P4 are respectively connected to the control signals F1~F4. The drain of the PMOS transistor P1 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to one end of the resistor R2 and the drains of the PMOS transistors P2~P4 and outputs a low-level signal VCOMP. The other end of the resistor R2 is grounded.

[0010] Preferably, the relationship of the current sources Ia~Id is: current source Ia = I, current source Ib = 2I, current source Ic = Id = 4I.

[0011] Preferably, the level detection circuit includes: NMOS transistors N1~N4, resistors R3~R4, a capacitor C1, and a bias voltage VB1; the three-phase electrical signals PH1~PH3 are respectively connected to one ends of the resistors R3. The other ends of the resistors R3 are connected to the drains of the NMOS transistors N1. The gates of the NMOS transistors N1 are connected to the bias voltage VB1. The sources of the NMOS transistors N1 are connected to the drains and gates of the NMOS transistors N2 and one end of the resistor R4. The sources of the NMOS transistors N2 are connected to the drains and gates of the NMOS transistors N3. The sources of the NMOS transistors N3 are connected to the drains and gates of the NMOS transistors N4. The sources of the NMOS transistors N4 are grounded. The other end of the resistor R4 is connected to one end of the capacitor C1 and respectively outputs signals VC1~VC3. The other end of the capacitor C1 is grounded.

[0012] Preferably, the comparison circuit includes: PMOS transistors P5 to P10, NMOS transistors N5 to N6, resistor R5, current sources Ie to Ig, and bias voltages VB2 to VB5; the source of PMOS transistor P5 is connected to power supply VCC1, the drain of PMOS transistor P5 is connected to the source of PMOS transistor P6, the drain of PMOS transistor P6 is connected to the gate of PMOS transistor P5 and the drain of NMOS transistor N5 and is connected to bias voltage VB2, the gate of PMOS transistor P6 is connected to bias voltage VB3, the gate of NMOS transistor N5 is connected to bias voltage VB4, the source of NMOS transistor N5 is connected to the drain of PMOS transistor P9 and one end of current source If, the other end of current source If is grounded, the gate of PMOS transistor P9 is connected to low-level signal VCOMP, the source of PMOS transistor P9 is connected to resistor R5 and one end of current source Ie, the other end of current source Ie is connected to power supply VCC1, the other end of resistor R5 is connected to the source of PMOS transistor P10, the gate of PMOS transistor P10 is respectively connected to signals VC1 to VC3, the drain of PMOS transistor P10 is connected to the source of NMOS transistor N6 and one end of current source Ig, the other end of current source Ig is grounded, the gate of NMOS transistor N6 is connected to bias voltage VB5, the drain of NMOS transistor N6 is connected to the drain of PMOS transistor P8 and outputs signals VOD1 to VOD3, the gate of PMOS transistor P8 is connected to bias voltage VB3, the source of PMOS transistor P8 is connected to the drain of PMOS transistor P7, the gate of PMOS transistor P7 is connected to bias voltage VB2, and the source of PMOS transistor P7 is connected to power supply VCC1.

[0013] Preferably, the driving module includes: a digital logic circuit and a level conversion circuit; wherein the digital logic circuit is used for inputting signals DL_A and DL_B; wherein the signal DL_A indicates whether the three-phase electrical signals PH1 to PH3 cross zero, the signal DL_B indicates whether the digital signal processing module is working, the two signals DL_A and DL_B are processed by the digital logic circuit and then output signal DL_YN, and the signal DL_YN is processed by the level conversion circuit and then outputs signals DRV1 to DRV3 to drive the off-chip switching transistors.

[0014] Preferably, the level conversion circuit includes: PMOS transistors P11 to P18, NMOS transistors N7 to N11, resistors R6 to R11, capacitors C2 to C3, and diode D1; the sources of PMOS transistors P11, P14, and P17, and one ends of resistors R6 to R7 are connected to power supply VCC2, the gate and drain of PMOS transistor P11 are connected to the source of PMOS transistor P12, the gate and drain of PMOS transistor P12 are connected to the source of PMOS transistor P13, the gate and drain of PMOS transistor P13 are connected to the gate of PMOS transistor P18, the drains of NMOS transistors N7 to N8, and the other end of resistor R6, the sources of NMOS transistors N7 to N8 are interconnected, the drain of PMOS transistor P18 is connected to the drains of NMOS transistors N9 to N10, the gate and drain of PMOS transistor P16, the gate of PMOS transistor P17, and the other end of resistor R7, the gates of NMOS transistors N9 to N10 are interconnected, the sources of NMOS transistors N9 to N10 are interconnected, the drain of PMOS transistor P17 is connected to one end of diode D1, the other end of diode D1 is connected to one end of resistor R10 and the drain of NMOS transistor N11, the gate of NMOS transistor N11 is connected to signal DL_YN, the source of NMOS transistor N11 is connected to one end of resistor R11 and grounded, and the other end of resistor R11 is connected to the other end of resistor R10 and outputs signals DRV1 to DRV3.

[0015] Preferably, it further includes two filter circuits, one ends of the two filter circuits are respectively connected to the sources of NMOS transistors N7 to N8 and the sources of NMOS transistors N9 to N10, and the other ends are respectively grounded; wherein the two filter circuits are respectively composed of a parallel combination of capacitor C2 and resistor R8, and a parallel combination of capacitor C3 and resistor R9.

[0016] Preferably, it further includes a fuse trimming circuit one and a fuse trimming circuit two. The fuse trimming circuit one includes: PMOS transistors P20 to P21, NMOS transistors N13 to N14, resistor R13, and fuse FUSE1; the sources of PMOS transistors P20 to P21 are connected to power supply VCC1, the gate of PMOS transistor P20 is connected to bias voltage VB6, the drain of PMOS transistor P20 is connected to the gate of PMOS transistor P21 and the drain of NMOS transistor N13, the gate of NMOS transistor N13 is connected to bias voltage VB7, the source is connected to one end of resistor R13, the other end of resistor R13 is connected to one end of fuse FUSE1 and inputs the off-chip fuse writing signal FUSE_WR1, the other end of fuse FUSE1 is grounded, the drain of PMOS transistor P21 is connected to the drain of NMOS transistor N14 and outputs control signal F2, the gate of NMOS transistor N14 is connected to bias voltage VB8, and the source is grounded; The fuse trimming circuit 2 includes: PMOS transistor P19, NMOS transistor N12, resistor R12, and fuse FUSE2; the source of the PMOS transistor P19 is connected to the power supply VCC1, the gate is connected to the bias voltage VB6, and the drain is connected to the drain of the NMOS transistor N12 and outputs control signals F3~F4. The gate of the NMOS transistor N12 is connected to the bias voltage VB7, the source is connected to one end of the resistor R12, the other end of the resistor R12 is connected to one end of the fuse FUSE2 and inputs the off-chip fuse write signals FUSE_WR2~FUSE_WR3, and the other end of the fuse FUSE2 is grounded.

[0017] Preferably, when the voltages of the three-phase electrical signals PH1~PH3 are greater than 0V but less than 2.1V, the signals VC1~VC3 change following the three-phase electrical signals PH1~PH3; when the voltages of the three-phase electrical signals PH1~PH3 are greater than 2.1V, the three-phase electrical signals PH1~PH3 are clamped by three diode-connected NMOS transistors N2~N4, and the output signals VC1~VC3 are voltages of 2.1V; when the voltages of the three-phase electrical signals PH1~PH3 are lower than -0.8V, the diodes of the NMOS transistors N2~N4 that protect the three-phase electrical signals PH1~PH3 conduct, so that the output signals VC1~VC3 are voltages of -0.8V.

[0018] Compared with the prior art, the present invention has the following beneficial effects: 1. The present invention solves the problem of excessive heat load: In the prior art, the voltage regulator has a large heat load during high-power output, while the present invention can accurately grasp the zero-crossing moments of voltage and current through the zero-crossing detection function, and timely adjust the working state of the voltage regulator according to the working conditions of the motorcycle engine and the output changes of the magneto. This avoids the long-term high-load operation of the chip, reduces unnecessary power loss and heat generation, thereby reducing the heat load, extending the service life of the voltage regulator, and eliminating the need for additional large heat dissipation devices, saving space and cost.

[0019] 2. The present invention improves the voltage regulation accuracy and stability: The traditional voltage regulator has poor voltage regulation during working condition changes. The present invention uses zero-crossing detection to accurately capture the voltage zero-crossing point, and combines the real-time detected voltage and current signals to quickly and accurately adjust the output voltage.

[0020] 3. The present invention speeds up the response speed to load changes: In the face of sudden changes in the motorcycle load, the traditional voltage regulator responds slowly. The present invention enables the voltage regulator to quickly adjust the output by virtue of the drive circuit with zero-crossing detection function to meet the power consumption requirements of different loads. Description of the Drawings

[0021] Figure 1 It is the overall structural block diagram of the motorcycle voltage regulator chip drive circuit provided by the present invention.

[0022] Figure 2 This is the circuit diagram of the zero-crossing comparison level generation circuit provided by the present invention.

[0023] Figure 3 This is the circuit diagram of the level detection circuit provided by the present invention.

[0024] Figure 4 This is the circuit diagram of the comparison circuit provided by the present invention.

[0025] Figure 5 This is the schematic diagram of the digital signal processing module provided by the present invention.

[0026] Figure 6 This is the schematic diagram of the digital logic circuit provided by the present invention.

[0027] Figure 7 This is the circuit diagram of the level conversion circuit provided by the present invention.

[0028] Figure 8 This is the circuit diagram of the fuse trimming circuit provided by the present invention; where (a) is the circuit diagram of fuse trimming circuit one; (b) is the circuit diagram of fuse trimming circuit two. Detailed implementation manners

[0029] The following further describes the present invention in detail with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0030] As Figure 1 and Figure 5 shown, the embodiment of the present invention specifically provides a motorcycle regulator chip driving circuit with a zero-crossing detection function, including: A zero-crossing detection module, configured to input three-phase electrical signals PH1~PH3, and determine whether the three-phase electrical signals PH1~PH3 are positive zero-crossing and negative zero-crossing. When the three-phase electrical signals PH1~PH3 are greater than zero, a low-level signal is output, and when the three-phase electrical signals PH1~PH3 are less than zero, a high-level signal is output; the zero-crossing detection module includes a zero-crossing comparison level generation circuit, a level detection circuit, and a comparison circuit; wherein the zero-crossing comparison level generation circuit is configured to generate a low-level signal VCOMP through a switching tube to control a constant current source for resistor voltage division; the level detection circuit is configured to detect whether the three-phase electrical signals PH1~PH3 are zero-crossing, and respectively output signals VC1~VC3; the comparison circuit is configured to compare the low-level signal VCOMP with the signals VC1~VC3 respectively, and respectively output signals VOD1~VOD3; A digital signal processing module, which processes the signals VOD1~VOD3 output by the zero-crossing detection module and outputs signals DL_A and DL_B; A driving module is used to input signals DL_A and DL_B, and output signals DRV1~DRV3 to off-chip switching transistors, so as to control the on and off of the off-chip switching transistors, and realize the start and stop of charging the battery.

[0031] As Figure 2 shown, the zero-crossing comparison level generation circuit includes: current sources Ia~Id, PMOS transistors P1~P4, resistors R1~R2, and control signals F1~F4; one ends of the current sources Ia~Id are connected to the power supply VCC1, and the other ends are respectively connected to the sources of the PMOS transistors P4~P1. The gates of the PMOS transistors P1~P4 are respectively connected to the control signals F1~F4. The drain of the PMOS transistor P1 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to one end of the resistor R2 and the drains of the PMOS transistors P2~P4, and outputs a low-level signal VCOMP. The other end of the resistor R2 is grounded.

[0032] Preferably, the relationship of the current sources Ia~Id is: current source Ia = I, current source Ib = 2I, current source Ic = Id = 4I.

[0033] As Figure 8 shown, it also includes a fuse trimming circuit one and a fuse trimming circuit two. The fuse trimming circuit one includes: PMOS transistors P20~P21, NMOS transistors N13~N14, a resistor R13, and a fuse FUSE1; the sources of the PMOS transistors P20~P21 are connected to the power supply VCC1. The gate of the PMOS transistor P20 is connected to the bias voltage VB6. The drain of the PMOS transistor P20 is connected to the gate of the PMOS transistor P21 and the drain of the NMOS transistor N13. The gate of the NMOS transistor N13 is connected to the bias voltage VB7, and the source is connected to one end of the resistor R13. The other end of the resistor R13 is connected to one end of the fuse FUSE1 and inputs the off-chip fuse write signal FUSE_WR1 signal. The other end of the fuse FUSE1 is grounded. The drain of the PMOS transistor P21 is connected to the drain of the NMOS transistor N14 and outputs the control signal F2. The gate of the NMOS transistor N14 is connected to the bias voltage VB8, and the source is grounded; The fuse trimming circuit two includes: a PMOS transistor P19, an NMOS transistor N12, a resistor R12, and a fuse FUSE2; the source of the PMOS transistor P19 is connected to the power supply VCC1, the gate is connected to the bias voltage VB6, and the drain is connected to the drain of the NMOS transistor N12 and outputs the control signals F3~F4. The gate of the NMOS transistor N12 is connected to the bias voltage VB7, and the source is connected to one end of the resistor R12. The other end of the resistor R12 is connected to one end of the fuse FUSE2 and inputs the off-chip fuse write signals FUSE_WR2~FUSE_WR3. The other end of the fuse FUSE2 is grounded.

[0034] When the off-chip fuse write signals FUSE_WRn (n = 1, 2, 3) are input respectively, the corresponding outputs are Fi (i = 2, 3, 4) signals. For fuse FUSE1, when fuse FUSE1 is not blown, the output signal F2 is high level; when it is necessary to blow fuse FUSE1, the externally applied write signal FUSE_WR1 is high level, blowing FUSE1, and at this time the output signal F2 of this circuit is low level. For fuse FUSE2, when fuse FUSE2 is not blown, the output signals F3 and F4 are low level; when it is necessary to blow fuse FUSE2, the write signals FUSE_WR2 and FUSE_WR3 are high level, and at this time the corresponding output signals F3 and F4 of this circuit are high level respectively.

[0035] As Figure 3 shown, the level detection circuit includes: NMOS transistors N1 to N4, resistors R3 to R4, capacitor C1 and bias voltage VB1; the three-phase electrical signals PH1 to PH3 are respectively connected to one end of resistor R3, the other end of resistor R3 is connected to the drain of NMOS transistor N1, the gate of NMOS transistor N1 is connected to bias voltage VB1, the source of NMOS transistor N1 is connected to the drain and gate of NMOS transistor N2 and one end of resistor R4, the source of NMOS transistor N2 is connected to the drain and gate of NMOS transistor N3, the source of NMOS transistor N3 is connected to the drain and gate of NMOS transistor N4, the source of NMOS transistor N4 is grounded, the other end of resistor R4 is connected to one end of capacitor C1 and outputs signals VC1 to VC3 respectively, and the other end of capacitor C1 is grounded.

[0036] As Figure 4As shown, the comparison circuit includes: PMOS transistors P5 to P10, NMOS transistors N5 to N6, resistor R5, current sources Ie to Ig, and bias voltages VB2 to VB5; the source of PMOS transistor P5 is connected to power supply VCC1, the drain of PMOS transistor P5 is connected to the source of PMOS transistor P6, the drain of PMOS transistor P6 is connected to the gate of PMOS transistor P5 and the drain of NMOS transistor N5 and is connected to bias voltage VB2, the gate of PMOS transistor P6 is connected to bias voltage VB3, the gate of NMOS transistor N5 is connected to bias voltage VB4, the source of NMOS transistor N5 is connected to the drain of PMOS transistor P9 and one end of current source If, the other end of current source If is grounded, the gate of PMOS transistor P9 is connected to the low-level signal VCOMP, the source of PMOS transistor P9 is connected to one end of resistor R5 and current source Ie, the other end of current source Ie is connected to power supply VCC1, the other end of resistor R5 is connected to the source of PMOS transistor P10, the gate of PMOS transistor P10 is respectively connected to signals VC1 to VC3, the drain of PMOS transistor P10 is connected to the source of NMOS transistor N6 and one end of current source Ig, the other end of current source Ig is grounded, the gate of NMOS transistor N6 is connected to bias voltage VB5, the drain of NMOS transistor N6 is connected to the drain of PMOS transistor P8 and outputs signals VOD1 to VOD3, the gate of PMOS transistor P8 is connected to bias voltage VB3, the source of PMOS transistor P8 is connected to the drain of PMOS transistor P7, the gate of PMOS transistor P7 is connected to bias voltage VB2, and the source of PMOS transistor P7 is connected to power supply VCC1.

[0037] As Figure 6 and Figure 7 shown, the driving module includes: a digital logic circuit and a level conversion circuit; wherein the digital logic circuit is used to input signals DL_A and DL_B; wherein the signal DL_A represents whether the three-phase electrical signals PH1 to PH3 cross zero, and DL_B is the output signal of the digital signal processing module, representing whether the digital signal processing module is working. The two signals DL_A and DL_B are processed by the digital logic circuit and then output signal DL_YN. The signal DL_YN is processed by the level conversion circuit and then outputs signals DRV1 to DRV3 to drive the off-chip switching transistors. When X1_YN and X2_YN are constantly high levels, X1_YN and X2_YN are respectively the gate signals of transistors N7 and N8, and the gate signals of transistors N9 and N10, so that transistors P17 and P18 are in the conducting state when the level conversion circuit works.

[0038] As Figure 7As shown in the figure, the level conversion circuit includes: PMOS transistors P11 to P18, NMOS transistors N7 to N11, resistors R6 to R11, capacitors C2 to C3, and diode D1. The sources of PMOS transistor P11, PMOS transistor P14, and PMOS transistor P17, and one ends of resistors R6 to R7 are connected to power supply VCC2. The gate and drain of PMOS transistor P11 are connected to the source of PMOS transistor P12. The gate and drain of PMOS transistor P12 are connected to the source of PMOS transistor P13. The gate and drain of PMOS transistor P13 are connected to the gate of PMOS transistor P18, the drains of NMOS transistors N7 to N8, and the other end of resistor R6. The sources of NMOS transistors N7 to N8 are interconnected. The drain of PMOS transistor P18 is connected to the drains of NMOS transistors N9 to N10, the gate and drain of PMOS transistor P16, the gate of PMOS transistor P17, and the other end of resistor R7. The gates of NMOS transistors N9 to N10 are interconnected. The sources of NMOS transistors N9 to N10 are interconnected. The drain of PMOS transistor P17 is connected to one end of diode D1. The other end of diode D1 is connected to one end of resistor R10 and the drain of NMOS transistor N11. The gate of NMOS transistor N11 is connected to signal DL_YN. The source of NMOS transistor N11 is connected to one end of resistor R11 and grounded. The other end of resistor R11 is connected to the other end of resistor R10 and outputs signals DRV1 to DRV3.

[0039] When the level conversion circuit works, DL_YN is the output signal of signals DL_A and DL_B after passing through the digital logic circuit. Since X1_YN and X2_YN are always at high level, transistors N7, N8, N9, and N10 are always conducting, so the gate of transistor P17 is at low level. When the circuit DL_YN is at low level, transistor N11 is cut off, and the outputs DRV1 to DRV3 are at high level (the high level is the on-chip high-voltage working power supply VCC2); when DL_YN is at high level (the high level of this DL_YN is the on-chip low-voltage working power supply VCC1, that is, the voltage of VCC1 is less than the voltage of VCC2), transistor N11 is conducting, and the outputs DRV1 to DRV3 are at low level.

[0040] As Figure 7 shown, it further includes two filter circuits. One ends of the two filter circuits are respectively connected to the sources of NMOS transistors N7 to N8 and the sources of NMOS transistors N9 to N10, and the other ends are respectively grounded. Among them, the two filter circuits are respectively composed of a capacitor C2 and a resistor R8 connected in parallel, and a capacitor C3 and a resistor R9 connected in parallel.

[0041] When the zero-crossing detection module is working, its main function is to judge whether the voltages of the three-phase electrical signals PH1, PH2, and PH3 cross zero. When the three-phase electrical voltage is greater than zero, the circuit outputs a low-level signal to the subsequent digital signal processing module, notifying the digital signal processing module that this phase of electricity can be used to charge the battery. When the three-phase electrical voltage is less than zero, a high level is output, and the NMOS switch tube corresponding to this phase of electricity is turned off through the digital signal processing module to stop charging the battery. When the three-phase electrical voltage is greater than 0 but less than 2.1V, VC1, VC2, and VC3 follow the changes of PH1, PH2, and PH3. When the phase electrical voltage is greater than 2.1V, the three-phase electrical signal is clamped by three diode-connected MOS transistors, namely NMOS transistors N2 to N4, and a voltage of about 2.1V (i.e., about 3 threshold voltages VTH of N2 to N4) is output. When the phase electrical voltage is lower than -0.8V, due to the conduction of the diodes in the ESD circuit that protects the three-phase electricity PH1, PH2, and PH3, a voltage of about -0.8V, namely VC1, VC2, and VC3, is output to one end of the comparison circuit. F1, F2, F3, and F4 are constant current source control signals. A very low-level signal VCOMP is generated through a resistor, and this signal is compared with the generated VC1, VC2, and VC3 signals respectively to output VOD1, VOD2, and VOD3.

[0042] At the beginning, the constant current source control signal F1 is at a low level, while F2 is at a high level, and F3 and F4 are at low levels. VCOMP = 7IR (where R is the resistance value of resistor R2). When the digital signal processing module detects a zero-crossing level, F1 is flipped to a high level, and VCOMP becomes 4IR. This makes the function of this comparison circuit similar to that of a Schmitt trigger circuit. At the same time, due to the existence of resistor R5, it makes VC1, VC2, and VC3 require a lower level than VCOMP to make VOD1, VOD2, and VOD3 flip, thereby reducing the flip voltage downward from VCOMP by I×1 / 2R5. When it is necessary to adjust the positive and negative zero-crossing flip voltages, the VCOMP voltage value needs to be changed through a fuse, and the step size is IR. After the above-mentioned F1 is flipped, it remains at a high level, while F2 - F4 are adjusted through the off-chip fuse trimming circuit one and the fuse trimming circuit two. In order to overcome the zero-crossing error caused by process deviation, when it is necessary to adjust the positive and negative zero-crossing flip voltages, the fuse trimming circuit one and the fuse trimming circuit two are required to control the signals F2 to F4, change the VCOMP voltage value, and the adjustment step size is IR.

[0043] When the input phase voltage signal rises from a negative voltage to 5 mV, it is determined that the output current of the corresponding phase of the magneto passes through zero from negative to positive. The driving circuit of this phase outputs a low level, and the external NMOS switch tube is turned off, and the voltage regulator charges the battery. Similarly, when the input phase voltage signal drops from a positive voltage to -5 mV, it is determined that the output current of the corresponding phase of the magneto passes through zero from positive to negative. The driving circuit of this phase outputs a high level, and the external NMOS switch tube is turned on, and the voltage regulator stops charging the battery.

[0044] In summary, through the zero-crossing detection function, the present invention can accurately grasp the zero-crossing moment of voltage and current, adjust the working state of the voltage regulator in real time, and quickly and accurately adjust the output voltage in combination with the voltage and current signals detected in real time. The structure is simple and the cost is low. With the zero-crossing detection function, the driving module of the present invention can quickly sense and respond. It can timely adjust the driving signal at the moment of sudden change of the load, reduce the fluctuation of the output voltage, quickly stabilize the voltage within a suitable range, meet the power consumption requirements of different loads, avoid misoperation or damage of electrical equipment due to unstable voltage, and enhance the adaptability of the system to complex working conditions.

[0045] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the field of the present invention according to the above disclosure shall fall within the protection scope of the claims.

Claims

1. A driving circuit for a motorcycle voltage regulator chip with a zero-crossing detection function, characterized in that, Including: A zero-crossing detection module, which is used to input three-phase electrical signals PH1~PH3, and judge whether the three-phase electrical signals PH1~PH3 are positive zero-crossing and negative zero-crossing. When the three-phase electrical signals PH1~PH3 are greater than zero, a low-level signal is output. When the three-phase electrical signals PH1~PH3 are less than zero, a high-level signal is output; the zero-crossing detection module includes a zero-crossing comparison level generation circuit, a level detection circuit, and a comparison circuit; Among them, the zero-crossing comparison level generation circuit is used to generate a low-level signal VCOMP after resistor voltage division by controlling a constant current source through a switching tube; the level detection circuit is used to detect whether the three-phase electrical signals PH1~PH3 cross zero, and respectively output signals VC1~VC3; the comparison circuit is used to compare the low-level signal VCOMP with the signals VC1~VC3 respectively, and respectively output signals VOD1~VOD3; A digital signal processing module, which processes the signals VOD1~VOD3 output by the zero-crossing detection module and outputs signals DL_A and DL_B; A driving module, which is used to input signals DL_A and DL_B, and output signals DRV1~DRV3 to an off-chip switching tube to control the on and off of the off-chip switching tube.

2. The motorcycle regulator chip drive circuit with a zero-crossing detection function according to claim 1, characterized in that The zero-crossing comparison level generation circuit includes: current sources Ia~Id, PMOS transistors P1~P4, resistors R1~R2, and control signals F1~F4; one ends of the current sources Ia~Id are connected to the power supply VCC, and the other ends are respectively connected to the sources of the PMOS transistors P4~P1. The gates of the PMOS transistors P1~P4 are respectively connected to the control signals F1~F4. The drain of the PMOS transistor P1 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to one end of the resistor R2 and the drains of the PMOS transistors P2~P4 and outputs a low-level signal VCOMP. The other end of the resistor R2 is grounded.

3. The motorcycle regulator chip driving circuit with a zero-crossing detection function according to claim 2, characterized in that, The relationship of the current sources Ia~Id is: current source Ia = I, current source Ib = 2I, current source Ic = Id = 4I.

4. The driving circuit of a motorcycle voltage regulator chip with a zero-crossing detection function as described in claim 1, characterized in that The level detection circuit includes: NMOS transistors N1~N4, resistors R3~R4, a capacitor C1, and a bias voltage VB1; the three-phase electrical signals PH1~PH3 are respectively connected to one ends of the resistors R3. The other ends of the resistors R3 are connected to the drains of the NMOS transistors N1. The gates of the NMOS transistors N1 are connected to the bias voltage VB1. The sources of the NMOS transistors N1 are connected to the drains and gates of the NMOS transistors N2 and one end of the resistor R4. The sources of the NMOS transistors N2 are connected to the drains and gates of the NMOS transistors N3. The sources of the NMOS transistors N3 are connected to the drains and gates of the NMOS transistors N4. The sources of the NMOS transistors N4 are grounded. The other end of the resistor R4 is connected to one end of the capacitor C1 and respectively outputs signals VC1~VC3. The other end of the capacitor C1 is grounded.

5. The driving circuit of a motorcycle regulator chip with a zero-crossing detection function as described in claim 1, wherein The comparison circuit includes: PMOS transistors P5 to P10, NMOS transistors N5 to N6, resistor R5, current sources Ie to Ig, and bias voltages VB2 to VB5; the source of the PMOS transistor P5 is connected to the power supply VCC1, the drain of the PMOS transistor P5 is connected to the source of the PMOS transistor P6, the drain of the PMOS transistor P6 is connected to the gate of the PMOS transistor P5 and the drain of the NMOS transistor N5 and is connected to the bias voltage VB2, the gate of the PMOS transistor P6 is connected to the bias voltage VB3, the gate of the NMOS transistor N5 is connected to the bias voltage VB4, the source of the NMOS transistor N5 is connected to the drain of the PMOS transistor P9 and one end of the current source If, the other end of the current source If is grounded, the gate of the PMOS transistor P9 is connected to the low-level signal VCOMP, the source of the PMOS transistor P9 is connected to one end of the resistor R5 and the current source Ie, the other end of the current source Ie is connected to the power supply VCC1, the other end of the resistor R5 is connected to the source of the PMOS transistor P10, the gate of the PMOS transistor P10 is respectively connected to the signals VC1 to VC3, the drain of the PMOS transistor P10 is connected to the source of the NMOS transistor N6 and one end of the current source Ig, the other end of the current source Ig is grounded, the gate of the NMOS transistor N6 is connected to the bias voltage VB5, the drain of the NMOS transistor N6 is connected to the drain of the PMOS transistor P8 and outputs the signals VOD1 to VOD3, the gate of the PMOS transistor P8 is connected to the bias voltage VB3, the source of the PMOS transistor P8 is connected to the drain of the PMOS transistor P7, the gate of the PMOS transistor P7 is connected to the bias voltage VB2, and the source of the PMOS transistor P7 is connected to the power supply VCC1.

6. The motorcycle regulator chip drive circuit with a zero-crossing detection function as described in claim 1, characterized in that The driving module includes: a digital logic circuit and a level conversion circuit; wherein the digital logic circuit is used for inputting the signals DL_A and DL_B; wherein the signal DL_A represents whether the three-phase electrical signals PH1 to PH3 cross zero, the DL_B represents whether the digital signal processing module is working, the two signals DL_A and DL_B are processed by the digital logic circuit and then output the signal DL_YN, and the signal DL_YN is processed by the level conversion circuit and then outputs the signals DRV1 to DRV3 to drive the off-chip switching transistors.

7. The drive circuit for a motorcycle voltage regulator chip with a zero-crossing detection function according to claim 6, wherein The level conversion circuit includes: PMOS transistors P11 to P18, NMOS transistors N7 to N11, resistors R6 to R11, capacitors C2 to C3, and diode D1; the sources of PMOS transistor P11, PMOS transistor P14, and PMOS transistor P17, and one ends of resistors R6 to R7 are connected to power supply VCC2. The gate and drain of PMOS transistor P11 are connected to the source of PMOS transistor P12. The gate and drain of PMOS transistor P12 are connected to the source of PMOS transistor P13. The gate and drain of PMOS transistor P13 are connected to the gate of PMOS transistor P18, the drains of NMOS transistors N7 to N8, and the other end of resistor R6. The sources of NMOS transistors N7 to N8 are interconnected. The drain of PMOS transistor P18 is connected to the drains of NMOS transistors N9 to N10, the gate and drain of PMOS transistor P16, the gate of PMOS transistor P17, and the other end of resistor R7. The gates of NMOS transistors N9 to N10 are interconnected. The sources of NMOS transistors N9 to N10 are interconnected. The drain of PMOS transistor P17 is connected to one end of diode D1. The other end of diode D1 is connected to one end of resistor R10 and the drain of NMOS transistor N11. The gate of NMOS transistor N11 is connected to signal DL_YN. The source of NMOS transistor N11 is connected to one end of resistor R11 and grounded. The other end of resistor R11 is connected to the other end of resistor R10 and outputs signals DRV1 to DRV3.

8. The driving circuit of a motorcycle voltage regulator chip with a zero-crossing detection function as described in claim 7, wherein, It further includes two filter circuits. One ends of the two filter circuits are respectively connected to the sources of NMOS transistors N7 to N8 and the sources of NMOS transistors N9 to N10, and the other ends are respectively grounded; wherein the two filter circuits are respectively composed of a parallel combination of capacitor C2 and resistor R8, and a parallel combination of capacitor C3 and resistor R9.

9. The motorcycle regulator chip driving circuit with a zero-crossing detection function according to claim 2, wherein, It further includes a fuse trimming circuit one and a fuse trimming circuit two. The fuse trimming circuit one includes: PMOS transistors P20 to P21, NMOS transistors N13 to N14, resistor R13, and fuse FUSE1; the sources of PMOS transistors P20 to P21 are connected to power supply VCC1. The gate of PMOS transistor P20 is connected to bias voltage VB6. The drain of PMOS transistor P20 is connected to the gate of PMOS transistor P21 and the drain of NMOS transistor N13. The gate of NMOS transistor N13 is connected to bias voltage VB7, and the source is connected to one end of resistor R13. The other end of resistor R13 is connected to one end of fuse FUSE1 and inputs the off-chip fuse writing signal FUSE_WR1. The other end of fuse FUSE1 is grounded. The drain of PMOS transistor P21 is connected to the drain of NMOS transistor N14 and outputs control signal F2. The gate of NMOS transistor N14 is connected to bias voltage VB8, and the source is grounded; The second fuse trimming circuit includes: PMOS transistor P19, NMOS transistor N12, resistor R12 and fuse FUSE2; the source of the PMOS transistor P19 is connected to the power supply VCC1, the gate is connected to the bias voltage VB6, and the drain is connected to the drain of the NMOS transistor N12 and outputs the control signals F3~F4. The gate of the NMOS transistor N12 is connected to the bias voltage VB7, the source is connected to one end of the resistor R12, the other end of the resistor R12 is connected to one end of the fuse FUSE2 and inputs the off-chip fuse writing signals FUSE_WR2~FUSE_WR3, and the other end of the fuse FUSE2 is grounded.

10. A motorcycle regulator chip drive circuit with a zero-crossing detection function according to any one of claims 1 to 9, characterized in that, When the voltages of the three-phase electrical signals PH1~PH3 are greater than 0V but less than 2.1V, the signals VC1~VC3 change following the three-phase electrical signals PH1~PH3; when the voltages of the three-phase electrical signals PH1~PH3 are greater than 2.1V, the three-phase electrical signals PH1~PH3 are clamped by three diode-connected NMOS transistors N2~N4, and the output signals VC1~VC3 are voltages of 2.1V; when the voltages of the three-phase electrical signals PH1~PH3 are lower than -0.8V, the diodes of the NMOS transistors N2~N4 that protect the three-phase electrical signals PH1~PH3 conduct, so that the output signals VC1~VC3 are voltages of -0.8V.

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