Timer and controller

Abstract

According to the timer and the controller provided by the invention, under the conditions that other circuit structures in the timer are not changed and a DMA (Direct Memory Access) carrying mode is not adopted, a corresponding first-in first-out queue is added in at least one of a corresponding signal generation module and an automatic reloading register module in the timer; the first-in first-out queue is used for pre-loading at least two numerical values at one time for subsequently updating the corresponding registers, so that when different updating events arrive, the control unit can sequentially output the numerical values in the first-in first-out queue according to the different updating events so as to update the registers of the modules where the first-in first-out queue is located; therefore, the phase shift or waveform modification of the corresponding pulse signal output by the timer is realized so as to meet different requirements of corresponding application scenes, the scheme needs less chip resources and is mainly triggered and updated automatically by hardware, so that the complexity of software programming is simplified.

Description

Technical Field

[0001] The present invention relates to the technical field of pulse control, and particularly to a timer and a controller. Background Art

[0002] PWM (Pulse width modulation) technology is a technology that obtains the required waveform (including shape and amplitude) equivalently by modulating the widths of a series of pulses, and is widely used in power electronics technical fields including wind power generation, motor speed regulation, DC power supply, lighting dimming, etc.

[0003] In some application scenarios (such as motor vector control scenarios, etc.), a timer (TIMEER) is used to generate multiple PWM signals, and it is necessary to further perform phase shift processing on one or several of the multiple PWM signals to achieve corresponding control tasks or signal sampling tasks.

[0004] Currently, DMA (Direct Memory Access) is usually used to transfer different values to the comparison registers in the corresponding channels inside the timer, so that the phase of the PWM signal output on this channel changes with the change of the value in the comparison register (that is, the phase shift processing of the PWM signal is achieved). This method will cause the DMA transfer to be blocked in occasions where DMA is used more or when the bus is occupied, easily resulting in failure or error in numerical modification. Summary of the Invention

[0005] The purpose of the present invention is to provide a timer and a controller that can achieve phase shift or waveform modification of the corresponding pulse signal output by the timer without using DMA transfer.

[0006] To achieve the above purpose, the present invention provides a timer, which includes:

[0007] A counter for counting based on a clock signal;

[0008] An automatic reload register module including an automatic reload register coupled to the counter, and the automatic reload register is used to load the maximum count value that the counter can count;

[0009] At least one signal generation module, each signal generation module has a comparison register for loading a corresponding comparison value, and the signal generation module is used to compare the comparison value with the count value of the counter to output a corresponding pulse signal;

[0010] Among them, a first-in-first-out (FIFO) queue is provided in at least one of the automatic reload register module and all the signal generation modules, and at least two values are pre-loaded in the FIFO queue.

[0011] The timer further includes a control module, which is coupled to each of the FIFO queues and is configured to, according to corresponding update events, sequentially output corresponding values in the corresponding FIFO queues to update the corresponding automatic reload register or the comparison register, thereby performing phase shift or waveform modification on the corresponding pulse signal.

[0012] Optionally, among all the signal generation modules, at least one of the signal generation modules outputs a pulse signal including a PWM signal or including two complementary PWM signals, and / or

[0013] At least another signal generation module outputs a pulse signal including a trigger signal, and the trigger signal has at least two rising edges or falling edges during the first half cycle or the second half cycle of the counter, and the rising edge or the falling edge is used to trigger the corresponding module to be triggered to start.

[0014] Optionally, each of the signal generation modules further includes a comparison circuit, and an input end of the comparison circuit is coupled to the comparison register to compare the comparison value with the count value of the counter to generate the pulse signal.

[0015] Optionally, each of the signal generation modules that outputs two complementary PWM signals further includes an output circuit, and an input end of the output circuit is coupled to an output end of the comparison circuit. The output circuit is configured to generate two PWM signals according to the output of the comparison circuit, invert the two PWM signals, and then perform dead time compensation to output the two complementary PWM signals.

[0016] Optionally, the automatic reload register module and each of the signal generation modules are provided with corresponding FIFO queues, and the number of values loaded in the FIFO queues in the automatic reload register module and each of the signal generation modules is the same or different.

[0017] Optionally, the control module includes update control circuits provided in one-to-one correspondence with the FIFO queues, and each update control circuit further includes:

[0018] A software update bit, which is set to be valid when a corresponding software update event occurs;

[0019] A first update selector, which is configured to generate a valid hardware update signal when a corresponding comparison match event or a corresponding period event occurs;

[0020] A second update selector, one input terminal is coupled to the software update bit, and the other input terminal is coupled to the output terminal of the first update selector, and is configured to generate the valid update signal when the software update bit is set valid or when the first update selector outputs a valid hardware update signal.

[0021] Optionally, the update control circuit further includes a FIFO function enable bit, which is coupled to the corresponding first-in-first-out queue. The FIFO function enable bit is configured to enable the first-in-first-out queue, so that when the update signal is valid, the value in the first-in-first-out queue can be output to the auto-reload register or the comparison register coupled to the first-in-first-out queue to complete the update operation.

[0022] Optionally, the control module triggers the update operation of the auto-reload register or the comparison register according to the value in the first-in-first-out queue in response to a hardware update event, where the hardware update event includes a compare match event and / or a period event; and / or, the at least two values in the first-in-first-out queue are pre-loaded by software in the previous period for use in the update operation in the current period.

[0023] Optionally, when the count value of the counter is equal to the comparison value of the comparison register, a compare match event is generated to trigger the update operation; where the first-in-first-out queue sequentially outputs different values to complete the update operation.

[0024] Optionally, the counter counts in an up-counting manner. In the current period, when the count value increases from 0 to the value loaded by the auto-reload register in this period, a period event is generated to trigger the update operation; or, the counter counts in a down-counting manner. In the current period, when the count value decreases from the value loaded by the auto-reload register in this period to 0, a period event is generated to trigger the update operation; or, the counter counts in a center-aligned manner. In the first half of the current period, when the count value increases from 0 to the value loaded by the auto-reload register in this period, a period event is generated for the first time to trigger the update operation. In the second half of the current period, when the count value decreases from the value loaded by the auto-reload register in this period to 0, a period event is generated for the second time to trigger the update operation.

[0025] Based on the same inventive concept, the present invention further provides a controller, which includes a processor core and also includes the timer as described in the present invention. The processor core is configured to configure and control the timer.

[0026] Optionally, the controller further internally or externally provides a corresponding analog-to-digital converter (ADC). The trigger terminal of the ADC is coupled to an output terminal of the timer to be triggered by the timer for sampling. The output terminal of the ADC is coupled to the input terminal of the processor core, and the processor core is further configured to process the digital signal output by the ADC.

[0027] Optionally, other output terminals of the timer are further coupled to the control terminals of corresponding power converters to control the operation of the power converters by outputting corresponding PWM signals. The power converters are built into the controller or externally provided outside the controller; the power converters are further coupled to corresponding functional devices and coupled to the ADC through corresponding sampling resistors, and the power converters are configured to regulate the operating voltage and / or operating current of the functional devices.

[0028] Optionally, the power converter is a three-phase inverter, and the functional device is a three-phase motor. The timer outputs six complementary PWM signals to the control terminals of the upper and lower bridge arms of the three-phase inverter. The processor core further includes a vector control module. The vector control module is coupled to the output terminal of the ADC and is configured to obtain the rotor speed, position, and three-phase current of the three-phase motor according to the output of the ADC, and then through a series of mathematical operations, obtain a motor drive state feedback quantity, and then dynamically adjust according to the error between the motor drive state feedback quantity and the target value, so that the timer performs phase shift, frequency adjustment, or duty cycle adjustment on the PWM signal output by it; or, the power converter is a dimmer, and the functional device is a lighting lamp. The timer outputs one PWM signal or two PWM signals to the control terminal of the dimmer; or, the power converter is a photovoltaic inverter, and the functional device is a power grid. The timer outputs multiple PWM signals to the control terminal of the photovoltaic inverter.

[0029] Optionally, the number of the sampling resistors is one, and the timer triggers the ADC to sample multiple times by the trigger signal of one of the pulse signals within a single cycle.

[0030] Compared with the prior art, the technical solution of the present invention, without changing other internal structures of the timer, adds corresponding first-in-first-out queues in at least one of the corresponding signal generation module and the automatic reload register module inside the timer, for preloading at least two values at one time, for subsequent updating of the corresponding registers (i.e., the comparison register or the automatic reload register), so that when different update events arrive, the control unit can make the values in the first-in-first-out queue output in sequence according to different update events to update the corresponding registers, thereby realizing the phase shift or waveform modification of the corresponding pulse signal output by the timer to meet different requirements of corresponding application scenarios, such as meeting different requirements for triggering the analog-to-digital converter sampling multiple times. Since the present invention does not need to use the DMA transfer method to modify the value of the comparison register, it will not preempt the resources of the chip DMA and the bus, and because it is mainly triggered by hardware automatically for updating, the complexity of software programming is simplified. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0032] Figure 1 is a schematic diagram of the architecture of an existing timer applied to motor control and ADC triggering.

[0033] Figure 2 is Figure 1 a schematic diagram of the timer shown for generating multiple pulse signals and realizing the phase shift of the pulse signal.

[0034] Figure 3 is a schematic diagram of the architecture of the timer of a specific embodiment of the present invention.

[0035] Figure 4 is a schematic diagram of the architecture of the i-th update control circuit in the control module of a specific embodiment of the present invention.

[0036] Figure 5 is a schematic diagram of an architecture of the controller of a specific embodiment of the present invention.

[0037] Figure 6 is a timing diagram of the controller of a specific embodiment of the present invention applied to motor control.

[0038] Figure 7 is Figure 6 a schematic diagram of the architecture of FOC in the processor core of the controller shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0039] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without one or more of these details. In other instances, well-known features of the art are not described in order to avoid obscuring the present invention. It should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments presented herein. On the contrary, these embodiments are provided to make the disclosure thorough and complete, and to fully convey the scope of the present invention to those skilled in the art. Like reference numerals refer to like elements throughout. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element or there can be intervening elements. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0040] Please refer to Figure 1 , in the application of field-oriented control (FOC) of a motor, generally, the six-phase complementary PWM signals CH0~CH2, CH0N~CH2N output by the timer (TIMER) 10 are applied to the control terminals (such as the gates of MOS transistors) of the switching transistors (not shown) on the upper and lower arms of the three-phase inverter 40, so that the three-phase inverter 40 drives the three-phase motor M to rotate at a specified torque and speed. At the same time, an analog-to-digital converter (ADC) 30 is often used to sample the phase current or phase voltage of the three-phase motor M and convert the sampling result into a digital signal to meet the signal feedback requirements of motor vector control and direct torque control.

[0041] For cost considerations, generally, a sampling resistor R is coupled between the three-phase inverter 40 and the analog-to-digital converter (ADC) 30 to obtain the phase current or phase voltage of the three-phase motor M. According to the number of sampling resistors R used, it can be divided into single-resistor, double-resistor, and triple-resistor sampling methods. Among them, in the single-resistor sampling method, since there is only one sampling resistor R, to obtain the two-phase current of the three-phase motor M, the analog-to-digital converter (ADC) 30 must sample twice within one cycle, and each sampling samples the phase current that is out of phase with the other two-phase currents of the three-phase motor M.

[0042] Please refer to Figure 1 and Figure 2 , there are four channels set inside Timer 10, and comparison registers are correspondingly set on these four channels, storing comparison values CH0CV, CH1CV, CH2CV, and CH3CV respectively. Among them, comparing the comparison value CH0CV on the first channel with the count value CNT of counter 101 can generate two complementary PWM signals CH0 (not shown) and CH0N; comparing the comparison value CH1CV on the second channel with the count value CNT of counter 101 can generate two complementary PWM signals CH1 (not shown) and CH1N; comparing the comparison value CH2CV on the third channel with the count value CNT of counter 101 can generate two complementary PWM signals CH2 and CH2N; comparing the comparison value CH3CV on the fourth channel with the count value CNT of counter 101 can generate a trigger signal CH3. The PWM signals CH0 to CH2 can be applied to the control terminals of the switching tubes on the upper bridge arm of the three-phase inverter 40, and the PWM signals CH0N to CH2N can be applied to the control terminals of the switching tubes on the lower bridge arm of the three-phase inverter 40. The rising edge of the trigger signal CH3 is used to trigger the analog-to-digital converter (ADC) 30 to sample.

[0043] Among them, it is necessary for the trigger signal CH3 to provide two rising edges within one cycle (when counting up, for example, the first half cycle) to trigger the analog-to-digital converter (ADC) 30 to sample twice within a single cycle. One implementation method in the prior art is to modify the value stored in the comparison register CH3CV within one cycle through the DMA transfer method.

[0044] In addition, when the PWM signals CH2N and CH1N are relatively close, the sampling window time left for the analog-to-digital converter (ADC) 30 is short, which may lead to problems such as failure to sample the phase current or phase voltage or inaccurate sampling results. Therefore, it is necessary to perform phase shift processing on the PWM signal CH2N or CH1N. Figure 2 The shown solution is to perform phase shift on the PWM signal CH2N by modifying the comparison value CH2CV stored in the comparison register of the second channel within one cycle through the DMA transfer method. After CH2N is phase-shifted, the sampling window time left for the analog-to-digital converter (ADC) 30 increases.

[0045] As described in the background art, the method of modifying the comparison value stored in the corresponding comparison register through the DMA transfer method to achieve phase shift or waveform modification of the PWM signal is prone to problems such as failure or error in numerical modification due to DMA transfer blocking in occasions where DMA is used frequently or when the bus is occupied.

[0046] Based on this, the present invention provides a new timer and controller solution. Without changing other structures inside the timer and without adopting the DMA transfer method, by adding a corresponding First-In-First-Out (FIFO) queue in at least one of the automatic reload register module inside the timer and the signal generation module of the corresponding channel, it is used to pre-load at least two values at one time for subsequent updating of the corresponding registers (i.e., comparison registers or automatic reload registers). Thus, when different update events arrive, the control unit can make the values in the FIFO queue output sequentially according to different update events to update the corresponding registers, thereby realizing the phase shift or waveform modification of the corresponding pulse signal output by the timer to meet different requirements of corresponding application scenarios, such as meeting different requirements for triggering the analog-to-digital converter sampling multiple times. Since the present invention avoids using the DMA transfer method, it will not preempt the resources of the chip DMA and the bus, and because it is mainly triggered by hardware automatically for updating, the complexity of software programming is simplified.

[0047] The technical solution proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0048] Please refer to Figure 3 , an embodiment of the present invention provides a timer (TIMER) 10, which includes a counter 101, a control module 102, an automatic reload register module 103, and x + 1 signal generation modules 1040 to 104x respectively arranged on x + 1 channels, where x is an integer and x ≥ 0.

[0049] Among them, an automatic reload register 103a coupled to the counter 101 is provided in the automatic reload register module 103, and this automatic reload register 103a is used to load the maximum count value ARR that the counter 101 can count. The counter 101 counts the rising edge or falling edge of the clock signal clk after being enabled, and its count value is CNT. The counter 101 can support three counting modes: up counting, down counting, and central alignment counting (i.e., up and down bidirectional counting).

[0050] In the up - counting mode, the counter 101 starts counting from 0 within a single cycle, and the count value CNT increases until the count value CNT reaches the maximum count value ARR loaded in the automatic reload register 103a. Then, the counter 101 ends the counting of this cycle and generates a cycle event (which is also the counter up - overflow event). After that, the counter 101 enters the next cycle and starts counting from 0 again, and so on in a loop. That is to say, in this mode, the maximum value of the count value CNT of the counter 101 within a single cycle is the maximum count value ARR loaded in the automatic reload register 103a, i.e., CNT max = ARR. In one example, some or all of the cycle events generated in this up - counting mode can be used to trigger the corresponding update operations in the present invention. For example, the values in the first - in - first - out queue in a certain signal generation module are output in sequence to update the comparison register in the signal generation module (that is, each time a value is output from the first - in - first - out queue in sequence, it will overwrite the previously stored comparison value in the comparison register), and / or the values in the first - in - first - out queue FIFO_A are output in sequence to update the automatic reload register 103a (that is, each time a value is output from FIFO_A in sequence, it will overwrite the previously stored maximum count value ARR in the automatic reload register).

[0051] In the down - counting mode, the counter 101 starts counting from the maximum count value ARR loaded in the automatic reload register 103a within a single cycle, and the count value CNT decreases until the count value CNT decreases to 0. Then, the counter 101 ends the counting of this cycle and generates a cycle event (which is also the counter down - overflow event, and this cycle time is used to trigger the corresponding update operations in the present invention). After that, the counter 101 enters the next cycle and starts counting from the maximum count value ARR loaded in the automatic reload register 103a again, and so on in a loop. That is to say, in this mode, the maximum value of the count value CNT of the counter 101 within a single cycle is the maximum count value ARR loaded in the automatic reload register 103a, i.e., CNT max = ARR. In one example, some or all of the cycle events generated in this down - counting mode can be used to trigger the corresponding update operations in the present invention. For example, the values in the first - in - first - out queue in a certain signal generation module are output in sequence to update the comparison register in the signal generation module, and / or the values in the first - in - first - out queue FIFO_A are output in sequence to update the automatic reload register 103a.

[0052] The central alignment mode (bidirectional counting up and down) is that within the current cycle, the counter 101 first counts up from 0, the count value CNT increases, until the count value CNT reaches the maximum count value ARR loaded in the automatic reload register 103a minus 1, then the counter 101 generates the first periodic event (also the counter upward overflow event) for the first time. Then the counter 101 counts down from the maximum count value ARR minus 1, the count value CNT decreases, until the count value CNT decreases to 0, the counter 101 ends the counting of this cycle and generates the second periodic event (also the counter downward overflow event) for the second time. After that, the counter 101 enters the next cycle and starts counting from 0 again, and so on in a loop. That is to say, in this mode, the maximum value of the count value CNT of the counter 101 within a single cycle is the maximum count value ARR loaded in the automatic reload register 103a minus 1, that is, CNT max = ARR - 1. In one example, some or all of the periodic events generated in the central alignment mode (such as only the periodic event generated for the first time within a single cycle or only the periodic event generated for the second time within a single cycle or only the periodic events generated for the first time and the second time within only some cycles) can be used to trigger the corresponding update operations in the present invention, such as sequentially outputting the values in the first-in first-out queue in a certain signal generation module to update the comparison register in the signal generation module, and / or sequentially outputting the values in the first-in first-out queue FIFO_A to update the automatic reload register 103a.

[0053] Each of the signal generation modules 1040 to 104x is provided with a comparison register (such as shown by U0 to Ux in Figure 3 and a comparison circuit (such as shown by CMP0 to CMPx in Figure 3 ). Each comparison register is used to load the corresponding comparison value, and the comparison circuit is used to compare the comparison value loaded in the coupled comparison register with the current count value CNT of the counter 101 to output the corresponding pulse signal.

[0054] As an example, each comparison register (such as U0 to Ux in Figure 3 and the automatic reload register 103a are both 16-bit registers. In other embodiments, each comparison register and the automatic reload register 103a can also be 32-bit or 64-bit registers, which is specifically determined by the bit width of the timer.

[0055] In this embodiment, at least one of the automatic reload register module 103 and / or the signal generation modules 1040 to 104x is provided with a first-in-first-out queue FIFO (First In First Out), and at least two values are pre-loaded in the first-in-first-out queue FIFO. The timer 10 further includes a control module 102, and the control module 102 is coupled to each first-in-first-out queue FIFO and is configured to trigger a corresponding update operation according to a corresponding update event (which can be a hardware update event or a software update event), that is, to sequentially output the corresponding values in the corresponding first-in-first-out queue FIFO to update the register (i.e., the comparison register or the automatic reload register) coupled to the first-in-first-out queue FIFO, and further perform phase shift or waveform modification (including one or more modification methods such as duty cycle adjustment, edge increase, and period size adjustment) on the corresponding pulse signal.

[0056] As an example, the control module 102 triggers an update operation of the automatic reload register or the corresponding comparison register with the values in the corresponding first-in-first-out queue according to any one or more hardware update events such as a comparison match event and a period event. The corresponding first-in-first-out queue sequentially outputs different values to complete each update operation (that is, the values sequentially output by the first-in-first-out queue will overwrite the values previously stored in the automatic reload register or the comparison register). Among them, when the count value CNT of the counter 101 is equal to the comparison value of the corresponding comparison register, a corresponding comparison match event is generated to trigger an update operation of the automatic reload register or the corresponding comparison register.

[0057] As an example, the values in each of the first-in-first-out queues in any one or more of the automatic reload register module 103 and the signal generation modules 1040 to 104x are pre-loaded by software in the previous cycle for use in the update operation of the current cycle.

[0058] Among them, according to actual needs, before the corresponding value output by the first-in-first-out queue FIFO first updates the register of the module where the first-in-first-out queue FIFO is located, the register (i.e., the comparison register or the automatic reload register) of the module where the first-in-first-out queue FIFO is located can be non-empty (i.e., loaded with an initial value) or empty.

[0059] It should be understood that when the first-in-first-out queue FIFO_A is not set in the automatic reload register module 103, the maximum count value loaded in the automatic reload register remains unchanged. Thus, the period of the pulse signals output by each signal generation module 1040 to 104x (which is also the counting period of the counter, or the period length) is fixed and unchanged. In this case, when a first-in-first-out queue FIFO_B is set in any signal generation module and the first-in-first-out queue FIFO_B is non-empty, when a corresponding update event occurs (such as generating a comparison match event to trigger an update operation), the values in the first-in-first-out queue FIFO_B are sequentially output to update the comparison register of the signal generation module (that is, each time a value is output from the FIFO_B in sequence, it will overwrite the comparison value previously stored in the comparison register). Thus, the period of the pulse signal output by the signal generation module remains unchanged, but the phase or duty cycle or the number of waveform edges changes. When the first-in-first-out queue FIFO_A is set in the automatic reload register module 103 and the first-in-first-out queue FIFO_A is non-empty, when a corresponding update event occurs (such as generating a period event to trigger an update operation), the values in the first-in-first-out queue FIFO_A are sequentially output to update the automatic reload register (that is, each time a value is output from the FIFO_A in sequence, it will overwrite the maximum count value ARR previously stored in the automatic reload register). Thus, the period of the pulse signals output by each signal generation module 1040 to 104x (which is also the counting period of the counter, or the period length) will change. In this case, if a first-in-first-out queue FIFO_B is not set in any signal generation module, the period of the pulse signal output by the signal generation module changes (i.e., the frequency is adjusted), and the duty cycle of the pulse signal (i.e., the ratio of the value in the comparison register to the value in the automatic reload register) also changes, but parameters such as the number of edges within a single period remain unchanged. If a first-in-first-out queue FIFO_B is set in any signal generation module and the first-in-first-out queue FIFO_B is non-empty, when a corresponding update event occurs (such as generating a comparison match event to trigger an update operation), the values in the first-in-first-out queue FIFO_B are sequentially output to update the comparison register of the signal generation module. Thus, the pulse signal output by the signal generation module not only changes in period size, but also in phase or duty cycle or the number of edges within a single period.

[0060] Optionally, among the signal generation modules 1040 to 104x, at least one signal generation module (e.g., 1040 to 104x - 1) outputs a pulse signal that includes a PWM signal (e.g., CH0 to CHx - 1) or includes two complementary PWM signals (e.g., CH0 to CH1 and CH0N to CH1N). Further optionally, among the signal generation modules 1040 to 104x, at least another signal generation module (e.g., 104x) outputs a pulse signal that includes a trigger signal (e.g., CHx), and the trigger signal has at least two rising edges or falling edges during the first half - period or the second half - period of the counter 101, and the at least two rising edges or falling edges are both used to trigger the corresponding module to be triggered to start (e.g., trigger Figure 6 the ADC 30 sampling in

[0061] Optionally, at least one of the signal generation modules (e.g., 1040 to 104x) that output the PWM signal (e.g., CH0 to CH1 and CH0N to CH1N) and the trigger signal (e.g., CHx) is provided with a corresponding first - in - first - out queue FIFO.

[0062] As an example, please refer to Figure 3 , the automatic reload register module 103 is provided with an n - level first - in - first - out queue FIFO_A, and each of the signal generation modules 1040 to 104x is provided with a comparison register Ui, a comparison circuit CMPi, and an m i (i = 0 to x) - level first - in - first - out queue FIFO_B. The n - level first - in - first - out queue FIFO_A is used to pre - load (or write at one time, which can be executed by software) with n different values (for performing n update operations on the automatic reload register to change the period sizes of each pulse signal n times), and the m i - level first - in - first - out queue FIFO_B is used to pre - load (or write at one time, which can be executed by software) with m i different values (for performing m i update operations on the comparison register of this signal generation module to change the phase or duty cycle of the pulse signal output by this signal generation module m i times), where m i and n are both integers, and m i can be equal to n (in this case, the update operations of the automatic reload register and this comparison register have the same number of times, and their updates can be synchronized each time), or can be not equal to n (in this case, the update operations of the automatic reload register and this comparison register have different numbers of times, and their update operations can be asynchronous). m0 to m iAt least two of them can be equal (in this case, the number of update operations of the corresponding two comparison registers is the same, and each update operation of the two can be synchronized or not), or they can be unequal (in this case, the number of update operations of the corresponding two comparison registers is different, and their update operations can be asynchronous).

[0063] Among them, the n-level first-in-first-out queue FIFO_A is coupled to the automatic reload register 103a and the control module 102. In one example, during system initialization, n different values can be pre-written (i.e., pre-loaded) into the n-level first-in-first-out queue FIFO_A in sequence according to the counting method of the counter 101 by means of software or the like, and an initial value different from the n values in the n-level first-in-first-out queue FIFO_A can be pre-written (i.e., pre-loaded) into the automatic reload register 103a. During the actual operation of the timer, when the n-level first-in-first-out queue FIFO_A is empty, the automatic reload register 103a maintains its original value (the original value is the initial value during system initialization and is the last value output by the n-level first-in-first-out queue FIFO_A after the n-level first-in-first-out queue FIFO_A is updated) unchanged; when the n-level first-in-first-out queue FIFO_A is full or non-empty, the control module 102 generates corresponding update signals according to different update events, so that the corresponding values in the n-level first-in-first-out queue FIFO_A are output in sequence to update the automatic reload register 103a. In one example, the value of the automatic reload register 103a updated in the current cycle is used as the maximum count value ARR of the counter 101 in the next cycle. It should be understood that when the control module 102 generates n update signals to the n-level first-in-first-out queue FIFO_A, the n different values in the n-level first-in-first-out queue FIFO_A will be output in sequence to update the automatic reload register 103a n times. And after the last value in the n-level first-in-first-out queue FIFO_A is output and the automatic reload register 103a is updated, the n-level first-in-first-out queue FIFO_A becomes empty.

[0064] In one example, the counter 101 uses an upward counting method, and the n different values in the n-level first-in-first-out queue FIFO_A can be written and output in ascending order.

[0065] In another example, the counter 101 uses a downward counting method, and the n different values in the n-level first-in-first-out queue FIFO_A are written and output in descending order.

[0066] In yet another example, the counter 101 adopts a center-aligned counting method. Among the n (n is an even number) different values in the n-stage first-in-first-out queue FIFO_A, the first n / 2 values are sequentially written in ascending order and sequentially output in ascending order in the first half cycle, and the last n / 2 values are sequentially written in descending order and sequentially output in descending order in the second half cycle.

[0067] Please continue to refer to Figure 3, in the signal generation module 1040 provided on the first channel, there is a comparison circuit CMP0, an output circuit OUT_0, a comparison register U0, and an m0 (m0 is an integer greater than 0) - stage first - in - first - out queue FIFO_B0. The m0 - stage first - in - first - out queue FIFO_B0 is coupled to the control module 102 and the comparison register U0. The output terminal of the comparison register U0 is coupled to an input terminal of the comparison circuit CMP0 to receive the comparison value CH0CV in the comparison register U0. The other input terminal of the comparison circuit CMP0 is coupled to the output terminal of the counter 101 to receive the current count value of the counter 101. The output terminal of the comparison circuit CMP0 is coupled to the output circuit OUT_0. Among them, the comparison circuit CMP0 compares the count value CNT of the counter 101 in the current period with the comparison value CH0CV in the comparison register U0. The output circuit OUT_0 is used to generate two complementary PWM signals according to the output of the comparison register U0, and perform dead - zone compensation on the two complementary PWM signals to output two complementary PWM signals CH0 and CH0N with dead - zone compensation. Moreover, each time the comparison value CH0CV in the comparison register U0 is updated, the PWM signals CH0 and CH0N will have a corresponding phase shift. In an example, during system initialization, according to the counting method of the counter 101, m0 different values can be sequentially written (i.e., pre - loaded) into the m0 - stage first - in - first - out queue FIFO_B0 through software or other means, and an initial value different from the m0 values in the m0 - stage first - in - first - out queue FIFO_B0 is written (i.e., pre - loaded) into the comparison register U0. During the operation of the timer, when the m0 - stage first - in - first - out queue FIFO_B0 is empty, the comparison register U0 maintains its original value (the original value is the initial value during system initialization, and after being updated by the m0 - stage first - in - first - out queue FIFO_B0, it is the last value output by the m0 - stage first - in - first - out queue FIFO_B0) unchanged; when the m0 - stage first - in - first - out queue FIFO_B0 is full or non - empty, if the count value CNT of the counter 101 in the current period is equal to the comparison value in the comparison register U0, a corresponding comparison match event is generated, and the control module 102 generates a corresponding update signal according to this comparison match event to trigger the update operation of the comparison register U0, so that the corresponding value in the m0 - stage first - in - first - out queue FIFO_B0 is sequentially output to update the comparison register U0, thereby completing the update operation of the comparison register U0 this time. In an example, the comparison value updated by the comparison register U0 in the current period is used as the comparison value CH0CV for the next comparison between the comparison circuit CMP0 and the count value CNT of the counter (the next comparison of CMP0 can occur in the next period).It should be understood that when the control module 102 generates m0 update signals to the m0-level first-in-first-out queue FIFO_B0, the m0 different values in the m0-level first-in-first-out queue FIFO_B0 will be output in sequence to update the comparison register U0 m0 times. The writing and output orders of the m0 different values can refer to the writing and output orders of the n values in the above-mentioned n-level first-in-first-out queue FIFO_A, which will not be elaborated here. After the last value in the m0-level first-in-first-out queue FIFO_B0 is output and the comparison register U0 is updated, the m0-level first-in-first-out queue FIFO_B0 becomes empty. It should be noted that each update operation of the comparison register U0 means that the value output by the first-in-first-out queue FIFO_B0 each time overwrites the previously stored comparison value in the comparison register U0.

[0068] In the signal generation module 1041 provided on the second channel, there are a comparison circuit CMP1, an output circuit OUT_1, a comparison register U1, and an m1-level (where m1 is an integer greater than 0) first-in-first-out queue FIFO_B1. The m1-level first-in-first-out queue FIFO_B1 is coupled to the control module 102 and the comparison register U1. The output terminal of the comparison register U1 is coupled to an input terminal of the comparison circuit CMP1 to receive the comparison value CH1CV in the comparison register U1. The other input terminal of the comparison circuit CMP1 is coupled to the output terminal of the counter 101 to receive the current count value of the counter 101. The output terminal of the comparison circuit CMP1 is coupled to the output circuit OUT_1. Among them, the comparison circuit CMP1 compares the count value CNT of the counter 101 in the current period with the comparison value CH1CV in the comparison register U1. The output circuit OUT_1 is used to generate two complementary PWM signals according to the output of the comparison register U1, and perform dead-time compensation on the two complementary PWM signals to output two complementary PWM signals CH1 and CH1N with dead-time compensation. Moreover, each time the comparison value CH1CV in the comparison register U1 is updated, the PWM signals CH1 and CH1N will generate corresponding phase shifts. In an example, during system initialization, according to the counting method of the counter 101, m1 different values can be sequentially written (i.e., pre-loaded) into the m1-level first-in-first-out queue FIFO_B1 through software or other means, and an initial value different from the m1 values in the m1-level first-in-first-out queue FIFO_B1 is written (i.e., pre-loaded) into the comparison register U1. During the operation of the timer, when the m1-level first-in-first-out queue FIFO_B1 is empty, the comparison register U1 maintains its original value (the original value is the initial value during system initialization, and after being updated by the m1-level first-in-first-out queue FIFO_B1, it is the last value output by the m1-level first-in-first-out queue FIFO_B1) unchanged; when the m1-level first-in-first-out queue FIFO_B1 is full or non-empty, if the count value CNT of the counter 101 in the current period is equal to the comparison value in the comparison register U1, a corresponding comparison match event is generated, and the control module 102 generates a corresponding update signal according to the comparison match event to trigger the update operation of the comparison register U1, so that the corresponding values in the m1-level first-in-first-out queue FIFO_B1 are sequentially output to update the comparison register U1, thereby completing the update operation of the comparison register U1. As an example, the comparison value after the comparison register U1 is updated in the current period is used as the comparison value CH1CV for the comparison circuit CMP1 to compare with the count value CNT of the counter next time (the next comparison of CMP1 can occur in the next period).It should be understood that when the control module 102 generates m1 update signals to the m1-level first-in-first-out queue FIFO_B1, the m1 different values in the m1-level first-in-first-out queue FIFO_B1 will be output in sequence to update the comparison register U1 m1 times. The writing and output orders of the m1 different values can refer to the writing and output orders of the n values in the above-mentioned n-level first-in-first-out queue FIFO_A, which will not be elaborated here. After the last value in the m1-level first-in-first-out queue FIFO_B1 is output to update the comparison register U1, the m1-level first-in-first-out queue FIFO_B1 becomes empty. It should be noted that each update operation of the comparison register U1 means that the value output each time by FIFO_B1 overwrites the previously stored comparison value in the comparison register U1.

[0069] And so on, in the signal generation module 104i provided on the (i + 1)-th channel, there are a comparison circuit CMPi, an output circuit OUT_i, a comparison register Ui, and an m i (m i is an integer greater than 0)-level first-in-first-out queue FIFO_Bi. The m i -level first-in-first-out queue FIFO_Bi is coupled to the control module 102 and the comparison register Ui. The output end of the comparison register Ui is coupled to an input end of the comparison circuit CMPi to receive the comparison value in the comparison register Ui. The other input end of the comparison circuit CMPi is coupled to the output end of the counter 101 to receive the current count value of the counter 101. The output end of the comparison circuit CMPi is coupled to the output circuit OUT_i. Among them, the comparison circuit CMPi compares the count value CNT of the counter 101 in the current period with the comparison value CHiCV in the comparison register Ui. The output circuit OUT_i is used to generate two complementary PWM signals according to the output of the comparison register Ui and perform dead-time compensation on the two complementary PWM signals to output two complementary PWM signals CHi and CHiN with dead-time compensation. Moreover, each time the comparison value CHiCV in the comparison register Ui is updated, the PWM signals CHi and CHiN will generate corresponding phase shifts. In an example, during system initialization, according to the counting method of the counter 101, m i different values can be written (i.e., pre-loaded) into the m i -level first-in-first-out queue FIFO_Bi in sequence, and an initial value different from the m i values in the m i -level first-in-first-out queue FIFO_Bi can be written (i.e., pre-loaded) into the comparison register Ui. During the working process of the timer, when the m i -level first-in-first-out queue FIFO_Bi is empty, the comparison register U1 maintains its original value (this original value is the initial value during system initialization and becomes the value after m iAfter the m-level first-in-first-out queue FIFO_Bi is updated, it becomes m i (the last value output by the m-level first-in-first-out queue FIFO_Bi) remains unchanged; when m i the m-level first-in-first-out queue FIFO_Bi is full or non-empty, if the count value CNT of counter 101 in the current cycle is equal to the comparison value CHiCV in the comparison register Ui, a corresponding comparison match event is generated, and the control module 102 generates a corresponding update signal according to this comparison match event, so that m i the corresponding values in the m-level first-in-first-out queue FIFO_Bi are output in sequence to update the comparison register Ui, thereby completing the update operation of the comparison register Ui this time. As an example, the comparison value after the update of the comparison register Ui in the current cycle is used as the comparison value CHiCV for the next comparison between the comparison circuit CMPi and the count value CNT of the counter (the next comparison of CMPi can occur in the next cycle). It should be understood that when the control module 102 generates m i update signals to the m i level first-in-first-out queue FIFO_Bi, m i the m values in the m-level first-in-first-out queue FIFO_Bi i will be output in sequence to update the comparison register Ui m i times, and the writing and output order of the m i different values can refer to the writing and output order of the n values of the n-level first-in-first-out queue FIFO_A mentioned above, which will not be elaborated here. After the last value in the m i level first-in-first-out queue FIFO_Bi is output to update the comparison register Ui, m i the m-level first-in-first-out queue FIFO_Bi becomes empty. It should be noted that each update operation of the comparison register Ui means that the value output by FIFO_Bi each time overwrites the comparison value stored earlier in the comparison register Ui.

[0070] In this example, the signal generation module 104x set on the (x + 1)-th channel (i.e., the last channel) is used to generate the trigger signal CHx, which is provided with a comparison circuit CMPx, a comparison register Ux, and an m x (m x is an integer greater than 0) level first-in-first-out queue FIFO_Bx. m xThe level first-in-first-out queue FIFO_Bx is coupled to the control module 102 and the comparison register Ux. The output end of the comparison register Ui is coupled to an input end of the comparison circuit CMPx to receive the comparison value CHxCV in the comparison register Ux. The other input end of the comparison circuit CMPx is coupled to the output end of the counter 101 to receive the current count value CNT of the counter 101. The output end of the comparison circuit CMPx is used to output a trigger signal CHx according to the comparison result. In one example, during system initialization, according to the counting mode of the counter 101, m x different values are sequentially written (i.e., pre-loaded) into the level first-in-first-out queue FIFO_Bx in the m x level, and an initial value different from the m x values in the level first-in-first-out queue FIFO_Bx is written (i.e., pre-loaded) into the comparison register Ux. During the operation of the timer, when the m x level first-in-first-out queue FIFO_Bx is empty, the comparison register Ux maintains its original value (the original value is the initial value during system initialization and becomes the last value output by the m x level first-in-first-out queue FIFO_Bx after the m x level first-in-first-out queue FIFO_Bx is updated); when the m x level first-in-first-out queue FIFO_Bx is full or non-empty, if the count value CNT of the counter 101 in the current period is equal to the comparison value CHxCV in the comparison register Ux, a corresponding comparison match event is generated, and the control module 102 generates a corresponding update signal according to the comparison match event to trigger the update operation of the comparison register Ux, so as to sequentially output the corresponding values in the m x level first-in-first-out queue FIFO_Bx to update the comparison register Ux, thus completing the update operation of the comparison register Ux this time. In one example, the comparison value after the comparison register Ux is updated in the current period is used as the comparison value CHxCV for the next comparison between the comparison circuit CMPx and the count value CNT of the counter (the next comparison of CMPx can occur in the current period, for generating the second trigger edge of the trigger signal required for ADC sampling). It should be understood that when the control module 102 generates m x update signals to the m x level first-in-first-out queue FIFO_Bx, the m x different values in the m x level first-in-first-out queue FIFO_Bx will be sequentially output to update the comparison register Ux m x times, and m x times, and m xThe writing and output order of the different values can refer to the writing and output order of the n values in the above-mentioned n-level first-in-first-out queue FIFO_A, which will not be elaborated here. At m x After the last value in the m-level first-in-first-out queue FIFO_Bx is output to update the comparison register Ux, m x -level first-in-first-out queue FIFO_Bx becomes empty. Moreover, each time the comparison value CHxCV in the comparison register Ux is updated, the trigger signal CHx will generate corresponding waveform adjustments. For example, if the comparison value CHxCV is updated k times in the first half cycle, the trigger signal CHx has k + 1 rising edges in the first half cycle for triggering the corresponding modules to be triggered (such as Figure 5 and Figure 6 shown ADC).

[0071] In addition, it is worth noting that the control module 102 and each output circuit, etc. can all be implemented by any suitable circuit design, and the present invention does not make specific limitations thereto. For example, the control module 102 can be a circuit design that supports both software update and hardware update as two update sources, or it can be a circuit design that only supports one of the two update sources of software update and hardware update. The supported update method can be specifically selected according to the application. The hardware update source can include at least one comparison matching event and at least one periodic event, etc.

[0072] Optionally, the control module 102 includes update control circuits CTRL respectively corresponding to each first-in-first-out queue FIFO_A and FIFO_B. When each signal generation module 1040 to 104x has a first-in-first-out queue FIFO_B and the automatic reload register module 103 is provided with a first-in-first-out queue FIFO_A, there are x + 2 update control circuits CTRL0 to CTRLx+1 in the control module 102, and the structural designs of each update control circuit CTRL0 to CTRLx+1 can be basically the same. For example, the update control circuits CTRL0 to CTRLx (not shown) are respectively corresponding to the signal generation modules 1040 to 104x, and the update control circuit CTRLx+1 (not shown) is corresponding to the automatic reload register module 103.

[0073] As an example, taking any update control circuit CTRLi as an example, please refer to Figure 4, the i-th update control circuit CTRLi includes a software update bit Si, a first update selector OR1i, and a second update selector OR2i. Among them, the software update bit Si is used to be set valid each time a corresponding software update event occurs. The first update selector OR1i is used to generate a valid hardware update signal (not shown) each time a corresponding comparison match event or a corresponding periodic event occurs. One input terminal of the second update selector OR2i is coupled to the software update bit Si, and the other input terminal is coupled to the output terminal of the first update selector OR1i. The second update selector OR2i is used to generate a valid update signal Gi when the software update bit Si is set valid or when the first update selector OR1i outputs a valid hardware update signal.

[0074] In this example, any comparison register Ui supports two update methods:

[0075] (1) Software update method: The software update bit in the update control circuit CTRLi coupled to the comparison register Ui can be written by software. The update control circuit CTRLi outputs a valid update signal Gi, so that the corresponding values in the first-in, first-out queue FIFO_Bi coupled to the comparison register Ui are sequentially output to overwrite the previously stored comparison value in the comparison register Ui, as the new comparison value CHiCV, thus completing the update operation of the comparison register Ui.

[0076] (2) Hardware update method: a. When a comparison match event occurs (i.e., the count value CNT is equal to the comparison value CHiCV in the comparison register Ui), the update control circuit CTRLi coupled to the comparison register Ui outputs a valid update signal Gi, so that the corresponding values in the first-in, first-out queue FIFO_Bi coupled to the comparison register Ui are sequentially output to overwrite the previously stored comparison value in the comparison register Ui, as the new comparison value CHiCV, thus completing the update operation of the comparison register Ui; b. When a periodic event occurs (i.e., the count value CNT is equal to the maximum count value ARR in the auto-reload register 103a), the update control circuit CTRLi coupled to the comparison register Ui outputs a valid update signal Gi, so that the corresponding values in the first-in, first-out queue FIFO_B coupled to the comparison register Ui are sequentially output to overwrite the previously stored comparison value in the comparison register Ui, as the new comparison value CHiCV, thus completing the update operation of the comparison register Ui.

[0077] Meanwhile, in this example, the update methods of the auto-reload register 103a are:

[0078] (1) Software update method: It can be written by software to the update control circuit CTRLx+1 (not shown, for referenceFigure 4 ) The software update bit in, the update control circuit CTRLx+1 outputs a valid update signal Gx+1 (not shown, refer to Figure 4 ), so that the values in the first-in, first-out queue FIFO_A coupled to the automatic reload register 103a are output in sequence to overwrite the ARR previously stored in the automatic reload register 103a as the maximum count value ARR of the counter in the next cycle, thereby completing the update operation of the automatic reload register 103a.

[0079] (2) Hardware update method: a. When a comparison match event occurs (for example, the count value CNT is equal to the comparison value in the comparison register of any channel), the update control circuit CTRLx+1 outputs a valid update signal Gx+1, so that the values in the first-in, first-out queue FIFO_A coupled to the automatic reload register 103a are output in sequence to overwrite the ARR previously stored in the automatic reload register 103a as the new maximum count value ARR, thereby completing the update operation of the automatic reload register 103a; b. When a period event occurs (the count value CNT is equal to the maximum count value ARR currently loaded in the automatic reload register), the update control circuit CTRLx+1 outputs a valid update signal Gx+1, so that the values in the first-in, first-out queue FIFO_A coupled to the automatic reload register 103a are output in sequence to overwrite the ARR previously stored in the automatic reload register 103a as the maximum count value ARR of the counter in the next cycle, thereby completing the update operation of the automatic reload register 103a.

[0080] In another example, any update control circuit CTRLi, in addition to including a software update bit Si, a first update selector OR1i, and a second update selector OR2i, further includes a FIFO function enable bit Fi, and the FIFO function enable bit Fi is coupled to a corresponding first-in, first-out queue (i.e., one of FIFO_B0 to FIFO_Bx and FIFO_A). The FIFO function enable bit Fi is used to enable the first-in, first-out queue so that when the update signal Gi output by the second update selector OR2i is valid, the values in the first-in, first-out queue can be output in sequence to update the register (i.e., the corresponding one of FIFO_B0 to FIFO_Bx and FIFO_A) coupled to the first-in, first-out queue.

[0081] It should be understood that by updating the auto-reload register 103a through the FIFO_A (i.e., the value output by the FIFO_A overwrites the ARR previously stored in the auto-reload register 103a), the period of the pulse signals output by the signal generation modules 1040 to 104x of each channel can be adjusted. And by updating the comparison register coupled thereto through the FIFO_B on the corresponding channel (i.e., the value output by the FIFO_B overwrites the comparison value previously stored in the comparison register), the waveform or phase or duty cycle of the pulse signal output by this channel can be adjusted. Among them, when any comparison register compares the comparison value currently stored therein with the count value of the counter 101, when the count value is equal to the comparison value, the pulse signal output by the signal generation module where this comparison register is located undergoes a flip.

[0082] As can be seen from the above, the timer of this embodiment, compared with Figure 1 the existing timer shown, without changing other circuit structures inside the timer and without using the DMA transfer method, adds a corresponding FIFO to at least one of the auto-reload register module and the signal generation module for preloading at least two values at one time. At the same time, according to the corresponding update events (i.e., different update sources), the corresponding values in the FIFO are output in sequence to update the register coupled to this FIFO (i.e., the comparison register or the auto-reload register), so as to achieve different requirements such as phase shift or waveform modification of the corresponding pulse signals, and can be applicable to any application scenario that needs to generate trigger signals and PWM signals in pulse form. Since the present invention does not need to adopt the DMA transfer method, it will not occupy the resources of the chip DMA and the bus, and because it is mainly triggered by hardware automatically for update, the complexity of software programming is simplified.

[0083] Based on the same inventive concept, please combine Figure 3 and Figure 5 , an embodiment of the present invention further provides a controller MCU, which includes a processor core 20 and also includes the timer 10 as described in the present invention. The processor core 20 is used to configure and control the timer 10, such as configuring the initial values of the auto-reload register 103a and each comparison register and the values in each FIFO_A and FIFO_B, and controlling the control module of the timer 10 to generate valid update signals, etc.

[0084] Please refer to Figure 5, the controller MCU also internally or externally provides a corresponding analog-to-digital converter (ADC) 30. The trigger terminal of the analog-to-digital converter 30 is coupled to an output terminal of the timer 10 to be triggered for sampling by the timer 10. The output terminal of the analog-to-digital converter 30 is coupled to the input terminal of the processor core 20. The processor core 20 is further configured to process the digital signal DOUT output by the analog-to-digital converter 30, so as to control the timer according to the processing result, and make the values in the corresponding first-in-first-out queue be output in sequence, so as to update the corresponding register in the timer or load new values into the first-in-first-out queue of the timer, and further modify the phase of the PWM signal output by the timer or the waveform of the trigger signal, etc. As an example, the number of values loaded in the first-in-first-out queue in the signal generation module of the trigger signal (such as CH3) output by the timer 10 determines the number of edges (such as the rising edge) used to trigger the analog-to-digital converter 30 to sample in the first half cycle of a single period of the trigger signal, that is, it determines the number of times the analog-to-digital converter 30 is triggered for sampling in a single period.

[0085] Optionally, other output terminals of the timer 10 are also coupled to the control terminals of corresponding power converters (such as Figure 5 the three-phase inverter) 40 in the Figure 5 to output corresponding PWM signals to control the operation of the power converter 40. The power converter 40 is built into the controller MCU or externally provided outside the controller MCU; the power converter 40 is also coupled to a corresponding functional device (such as

[0086] the three-phase motor M) in the Figures 3 to 6, the power converter 40 is a three-phase inverter, the functional device is a three-phase motor M, and the timer 10 outputs six complementary PWM signals CH0 to CH2 and CH0N to CH2N to the control terminals of the upper and lower bridge arms of the three-phase inverter. In the variable frequency control of the three-phase motor M, the timer 10 can update the maximum count value ARR loaded in its automatic reload register 103a through the first-in-first-out queue FIFO_A in the automatic reload module 103 to adjust the period size of one or multiple PWM signals output by it. It can also update the comparison value loaded in its comparison register through the first-in-first-out queue FIFO_B in the signal generation module on the corresponding channel to adjust the duty cycle, phase, or waveform of one or multiple PWM signals output by it. The update of the maximum count value ARR and the update of the comparison value loaded in the comparison register can be selected one by one or both. For example, in the single-resistor sampling method, it is not necessary to modify the period size of each PWM signal. Therefore, the setting of the first-in-first-out queue FIFO_A in the automatic reload module 103 can be omitted, or the first-in-first-out queue FIFO_A in the automatic reload module 103 can be kept empty, or the first-in-first-out queue FIFO_A in the automatic reload module 103 can be disabled to avoid the update of the maximum count value ARR.

[0087] Combined Figures 3 to 6 As shown, in an example, the power converter 40 is a three-phase inverter, the functional device is a three-phase motor M, the counter 101 of the timer 10 uses the center-aligned counting method, and four channels are provided inside the timer 10. Signal generation modules 1040 to 1043 are correspondingly provided on these four channels, so that comparison registers U0 to U3 are correspondingly provided. The comparison registers U0 to U3 are respectively used to load comparison values CH0CV, CH1CV, CH2CV, and CH3CV. First-in-first-out queues FIFO_B2 to FIFO_B3 are respectively provided in the signal generation modules 1042 to 1043, and both are 2-level first-in-first-out queues FIFO, and both are loaded with 2 different values. And the three-phase inverter and the analog-to-digital converter 30 are coupled to the same sampling resistor R to implement the single-resistor sampling method. The working principle of this controller MCU is as follows:

[0088] During the current cycle, the comparison circuit CMP3 in the signal generation module 1043 on the fourth channel compares the comparison value CH3CV loaded in the comparison register U3 coupled thereto with the count value CNT of the counter 101, and can generate a trigger signal CH3. After the control module 102 of the timer 10 enables the FIFO function of the signal generation module 1043, both the software update event and the comparison match event of the update source are selected, and the update timing is selected to be updated only during the upward counting process, so that there are two rising edges of the trigger signal CH3 in the first half of the cycle, which are used to trigger the analog-to-digital converter (ADC) sampling twice. For example, during the downward counting process of the counter 101 in the previous cycle, two comparison values CH3CV for triggering the analog-to-digital converter (ADC) 30 sampling twice calculated during the motor control process can be written into the first-in-first-out queue FIFO_B3 of the signal generation module 1043 by software writing, and at the same time, the software update bit in the corresponding update control circuit of the software write control module 102 is set, so that the first comparison value in the first-in-first-out queue FIFO_B3 is output to update (or overwrite) the comparison value in the comparison register U3. Thus, during the upward counting process of the counter in the current cycle, when the count value CNT of the counter 101 is equal to the first comparison value, the first rising edge of the trigger signal CH3 in the first half of the cycle is generated, and at this time, it is considered that the comparison match event 1 occurs, and the current FIFO_B3 is not empty. Further, the second comparison value in the FIFO_B3 is output to update (or overwrite) the comparison value in the comparison register U3 again. When the count value CNT of the counter 101 is equal to the second comparison value, the second rising edge of the trigger signal CH3 in the first half of the cycle is generated, and at this time, it is considered that the comparison match event 2 occurs, and from this moment until the stage when two new comparison values are loaded into the FIFO_B3 again, the comparison value in the comparison register U3 is not updated (i.e., remains the second comparison value output by the FIFO_B3 before), thus realizing the operation of triggering the analog-to-digital converter (ADC) sampling twice in the current cycle (and in the first half of the cycle). During the downward counting process of the counter 101 in the current cycle, two new comparison values for triggering the analog-to-digital converter (ADC) sampling twice calculated during the motor control process are re-loaded into the FIFO_B3, and the operation of triggering the analog-to-digital converter (ADC) sampling twice in the next cycle can be realized.

[0089] When using a single sampling resistor for sampling, the comparison circuit CMP0 in the signal generation module 1040 on the first channel compares the comparison value CH0CV loaded in the comparison register U0 with the count value CNT of the counter 101 to generate two complementary PWM signals CH0 (not shown) and CH0N. The comparison circuit CMP1 in the signal generation module 1041 on the second channel compares the comparison value CH1CV loaded in the comparison register U1 with the count value CNT of the counter 101 to generate two complementary PWM signals CH1 and CH1N. The comparison circuit CMP2 in the signal generation module 1042 on the third channel compares the comparison value CH2CV loaded in the comparison register U2 with the count value CNT of the counter 101 to generate two complementary PWM signals CH2 and CH2N. Among them, the PWM signals CH0 to CH2 are applied to the control terminals of the switching tubes on the upper arm of the three-phase inverter, and the PWM signals CH0N to CH2N are applied to the control terminals of the switching tubes on the lower arm of the three-phase inverter. After the control module 102 of the timer 10 enables the FIFO function of the signal generation module 1042, the update sources both select the software update event and the comparison match event, and the update timing is selected to be updated only during the up-counting process. According to the logic control of the motor control algorithm, a phase shift operation is performed on the PWM signals CH2N and CH2. For example, during the down-counting process of the counter 101 in the previous cycle, the comparison value CH2CV obtained by shifting the PWM signal CH2 or CH2N twice calculated during the motor control process can be pre-loaded into the FIFO_B2 of the first-in-first-out queue of the signal generation module 1042 by software writing, and at this time, FIFO_B2 is full. When the counter 102 restarts from 0 and starts up-counting, it is considered that a cycle event 1 has occurred. At this time, FIFO_B2 is not empty, and the first comparison value in FIFO_B2 is output to update the comparison value in the comparison register U2. When the count value CNT of the counter 101 during up-counting is equal to this first comparison value, a falling edge of the PWM signal CH2N before phase shift will be generated. When the count value CNT of the counter 101 during up-counting is equal to the maximum count value ARR, it is considered that a cycle event 2 has occurred. At this time, FIFO_B2 is not empty, and the second comparison value in FIFO_B is output to update the comparison value in the comparison register U2 again, and from this moment until two new comparison values are loaded into FIFO_B2 again, the comparison value in the comparison register U2 is not updated (i.e., remains the second comparison value output by FIFO_B2 before). During this stage, when the count value CNT of the counter 101 during down-counting is equal to this second comparison value, a rising edge of the PWM signal CH2N before phase shift will be generated.During the down-counter operation of the counter 101 in the current cycle, two new comparison values for phase shift calculation in the motor control algorithm are further loaded into FIFO_B2, thus enabling the phase shift operation of PWM signals CH2N and CH2 in the next cycle.

[0090] As can be seen from Figure 6 before the phase shift of the PWM signal CH2N, on the one hand, the interval between the falling edge of the PWM signal CH2N and the first rising edge of the trigger signal CH3 is small, which easily causes the analog-to-digital converter 30 not to be ready when the trigger signal CH3 triggers the first sampling of the analog-to-digital converter 30, affecting the reliability of the sampling result; on the other hand, the distance between the falling edge of the PWM signal CH2N and the falling edge of the PWM signal CH1N is also too close, which also easily causes the switching tubes of the three-phase inverter to switch too fast, resulting in the analog-to-digital converter 30 being unable to sample the phase current change of the three-phase motor M. After the phase shift of the PWM signal CH2N, on the one hand, the interval between the falling edge of the PWM signal CH2N and the first rising edge of the trigger signal CH3 becomes larger, which can give the analog-to-digital converter 30 sufficient preparation time, so that the trigger signal CH3 can reliably trigger the first sampling of the analog-to-digital converter 30; on the other hand, the distance between the falling edge of the PWM signal CH2N and the falling edge of the PWM signal CH1N also becomes larger, which can also ensure the switching interval of the switching tubes of the three-phase inverter, thus ensuring that the analog-to-digital converter 30 can sample the phase current change of the three-phase motor M.

[0091] It should be understood that a control module for implementing any suitable motor control algorithm is provided in the processor core 20, and the present invention does not make specific limitations thereto. For example, please refer to Figure 7, the processor core 20 includes a vector control module FOC (field-oriented control, also known as magnetic field orientation control). The vector control module FOC is coupled to the output of the analog-to-digital converter 30 and is used to obtain information such as the rotor speed ω, position θ, and three-phase currents IA, IB of the three-phase motor M according to the output of the analog-to-digital converter 30. After a series of mathematical operations, a motor drive state feedback quantity is obtained, and then dynamic adjustment is performed according to the error between the motor drive state feedback quantity and the target value, so that the timer 10 performs phase shift or frequency adjustment on the PWM signal output by it. As an example, the vector control module FOC includes a Clark transformation module 201, a Park transformation module 202, a current regulation module 203, an inverse Park transformation module 204, an inverse Clark transformation module 205, and a position and speed estimator 206. Among them, the Clark transformation module 201 performs a Clark transformation on the digital signals output by the analog-to-digital converter 30 for reflecting the three-phase currents IA, IB to obtain the corresponding current α-axis component Iα and current β-axis component Iβ. The Park transformation module 202 performs a Park transformation on the current α-axis component Iα and current β-axis component Iβ to obtain the corresponding current d-axis component Id and current q-axis component Iq. The position and speed estimator 206 estimates the position θ and speed ω of the rotor of the three-phase motor M according to the current α-axis component Iα and current β-axis component Iβ. The current regulation module 203 performs superposition (∑) and integral regulation (PI) on the speed ω and the speed reference value ωref to obtain the current q-axis reference value Iqref, and further performs superposition (∑) and integral regulation (PI) on the current q-axis component Iq and the current q-axis reference value Iqref to obtain the voltage q-axis component Vq. At the same time, the current regulation module 203 also performs superposition (∑) and integral regulation (PI) on the current d-axis component Id and the current d-axis reference value Idref to obtain the voltage d-axis component Vd. The inverse Park transformation module 204 performs an inverse Park transformation on the voltage d-axis component Vd and the voltage q-axis component Vq to obtain the voltage α-axis component Vα and voltage β-axis component Vβ. The inverse Clark transformation module 205 performs an inverse Clark transformation on the voltage α-axis component Vα and voltage β-axis component Vβ to obtain the corresponding control signal to control the value in the timer update register or load a new value into the first-in-first-out queue of the timer, thereby modifying the waveform or performing phase shift on the trigger signal and / or PWM signal output by it.

[0092] In addition, it should also be noted that the above embodiments take the power converter as a three-phase inverter and the functional device as a three-phase motor as examples to illustrate the application and working principle of the controller of the present invention in detail. However, the technical solution of the present invention is not limited thereto.

[0093] For example, in another embodiment of the present invention, the power converter 40 can also be a dimmer, and the functional device coupled thereto can be a lighting lamp (such as an LED lamp, etc.). The timer 10 can output one or two PWM signals to the control terminal of the dimmer, so that the dimmer can adjust lighting parameters such as the brightness and / or color temperature of the lighting lamp.

[0094] For another example, in another embodiment of the present invention, the power converter 40 is a photovoltaic inverter, and the functional device is a power grid. The timer 10 outputs multiple PWM signals to the control terminal of the photovoltaic inverter, so that the photovoltaic inverter can adjust power parameters such as the power output to the power grid.

[0095] In summary, for the technical solution of the present invention, without changing other circuit structures inside the timer and without adopting the DMA transfer method, in at least one of the corresponding signal generation module and the automatic reload register module inside the timer, a corresponding first-in-first-out queue is added to preload multiple values at one time to update the corresponding register multiple times. Thus, when different update events arrive, the control unit can sequentially output the values in the first-in-first-out queue according to different update events to update the register of the module where the first-in-first-out queue is located, so as to realize the phase shift or waveform modification of the corresponding pulse signal output by the timer to meet the different requirements of corresponding application scenarios, such as meeting the different requirements of triggering the analog-to-digital converter sampling multiple times. Since the present invention does not need to adopt the DMA transfer method, it will not occupy the resources of the chip DMA and the bus, and because it is mainly triggered by hardware automatically for update, the complexity of software programming is simplified.

[0096] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure belong to the protection scope of the technical solution of the present invention.

Claims

1. A timer, characterized in that, Comprising: A counter for counting based on a clock signal; An auto-reload register module including an auto-reload register coupled to the counter, the auto-reload register being used to load the maximum count value that the counter can count; At least one signal generation module, each signal generation module having a comparison register for loading a corresponding comparison value, the signal generation module being used to compare the comparison value with the count value of the counter to output a corresponding pulse signal; Wherein, a first-in-first-out queue is provided in at least one of the auto-reload register module and / or all the signal generation modules, and at least two values are pre-loaded in the first-in-first-out queue; The timer further includes a control module, coupled to each of the first-in-first-out queues, and configured to, according to a corresponding update event, cause the corresponding value in the corresponding first-in-first-out queue to be sequentially output to update the corresponding auto-reload register or the comparison register, thereby performing phase shift or waveform modification on the corresponding pulse signal.

2. The timer according to claim 1, characterized in that Among all the signal generation modules, at least one of the signal generation modules outputs a pulse signal including a PWM signal or including two complementary PWM signals, and / or At least another signal generation module outputs a pulse signal including a trigger signal, the trigger signal having at least two rising edges or falling edges in the first half cycle or the second half cycle of the counter, and the rising edge or falling edge is used to trigger the corresponding module to be triggered to start.

3. The timer according to claim 2, characterized in that, Each of the signal generation modules further includes a comparison circuit, an input end of the comparison circuit is coupled to the comparison register, and is configured to compare the comparison value with the count value of the counter to generate the pulse signal.

4. The timer according to claim 3, characterized in that, Each of the signal generation modules that outputs two complementary PWM signals further includes an output circuit, an input end of the output circuit is coupled to an output end of the comparison circuit, and the output circuit is configured to generate two PWM signals according to the output of the comparison circuit, invert the two PWM signals, and then perform dead-time compensation to output the two complementary PWM signals.

5. The timer according to any one of claims 1-4, characterized in that, The auto-reload register module and each of the signal generation modules are provided with corresponding first-in-first-out queues, and the number of values loaded in the first-in-first-out queues in the auto-reload register module and each of the signal generation modules is the same or different.

6. The timer according to claim 1, characterized in that, The control module includes update control circuits provided in one-to-one correspondence with the first-in-first-out queues, and each update control circuit further includes: A software update bit, which is set to be valid when a corresponding software update event occurs; A first update selector for generating a valid hardware update signal when a corresponding comparison match event or a corresponding cycle event occurs; A second update selector, one input end of which is coupled to the software update bit, and the other input end is coupled to an output end of the first update selector, and is configured to generate a valid update signal when the software update bit is set to be valid or when the first update selector outputs a valid hardware update signal.

7. The timer according to claim 6, wherein The update control circuit further includes a FIFO function enable bit, which is coupled to the corresponding first-in-first-out queue. The FIFO function enable bit is used to enable the first-in-first-out queue, so that when the update signal is valid, the value in the first-in-first-out queue can be output to the automatic reload register or the comparison register coupled to the first-in-first-out queue to complete the update operation.

8. The timer according to claim 1, characterized in that, The control module triggers the update operation of the automatic reload register or the comparison register according to the value in the first-in-first-out queue by a hardware update event, where the hardware update event includes a comparison match event and / or a period event; and / or, at least two values in the first-in-first-out queue are pre-loaded by software in the previous period for use in the update operation in the current period.

9. The timer according to claim 8, wherein When the count value of the counter is equal to the comparison value of the comparison register, a comparison match event is generated to trigger the update operation; where the first-in-first-out queue sequentially outputs different values to complete the update operation.

10. The timer according to claim 8, wherein The counter counts in an up-counting manner. In the current period, when the count value increases from 0 to the value loaded by the automatic reload register in this period, a period event is generated to trigger the update operation; or, the counter counts in a down-counting manner. In the current period, when the count value decreases from the value loaded by the automatic reload register in this period to 0, a period event is generated to trigger the update operation; or, the counter counts in a center-aligned manner. In the first half of the current period, when the count value increases from 0 to the value loaded by the automatic reload register in this period, a period event is generated for the first time to trigger the update operation. In the second half of the current period, when the count value decreases from the value loaded by the automatic reload register in this period to 0, a period event is generated for the second time to trigger the update operation.

11. A controller, characterized in that, It includes a processor core and also includes the timer according to any one of claims 1-10. The processor core is used to configure and control the timer.

12. The controller according to claim 11, wherein The controller also internally or externally provides a corresponding analog-to-digital converter. The trigger terminal of the analog-to-digital converter is coupled to an output terminal of the timer to be triggered for sampling by the timer. The output terminal of the analog-to-digital converter is coupled to the input terminal of the processor core, and the processor core is also used to process the digital signal output by the analog-to-digital converter.

13. The controller according to claim 12, wherein Other output terminals of the timer are also coupled to the control terminals of corresponding power converters to control the operation of the power converters by outputting corresponding PWM signals. The power converters are built into the controller or externally provided outside the controller; the power converters are also coupled to corresponding functional devices and are coupled to the analog-to-digital converter through corresponding sampling resistors. The power converters are used to adjust the working voltage and / or working current of the functional devices.

14. The controller according to claim 13, characterized in that, The power converter is a three-phase inverter, the functional device is a three-phase motor, the timer outputs six complementary PWM signals to the control terminals of the upper and lower bridge arms of the three-phase inverter, the processor core further includes a vector control module, the vector control module is coupled to the output terminal of the analog-to-digital converter, and is used to obtain the rotor speed, position and three-phase current of the three-phase motor according to the output of the analog-to-digital converter, and then through a series of mathematical operations, obtain the motor drive state feedback quantity, and then dynamically adjust according to the error between the motor drive state feedback quantity and the target value, so that the timer performs phase shift or frequency adjustment or duty cycle adjustment on the PWM signal it outputs; or, the power converter is a dimmer, the functional device is a lighting lamp, the timer outputs one PWM signal or two PWM signals to the control terminal of the dimmer; or, the power converter is a photovoltaic inverter, the functional device is a power grid, and the timer outputs multiple PWM signals to the control terminal of the photovoltaic inverter.

15. The controller according to claim 13, wherein The number of the sampling resistors is one, and the timer triggers the analog-to-digital converter to sample multiple times by the trigger signal of one of the pulse signals within a single cycle.

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