A clock processing system, method, device, medium and program product

Abstract

The present application discloses a clock processing system, method, device, medium, and program product in the field of computer technology. In this application, each processor in each motherboard has a built-in first clock module. When providing a first clock signal, the downstream switching devices of these motherboards and at least two target devices connected to the switching devices all use the second clock signal provided by the second clock module in the switching device as a reference, thereby achieving homologous synchronization of the clock signals of the downstream switching devices and at least two target devices connected to the switching devices. Furthermore, this does not affect the first clock signals provided by the upstream motherboards, thus solving the problem of clock asynchrony in downstream devices in scenarios where multiple motherboards all provide clock signals.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a clock processing system, method, device, medium and program product. Background Art

[0002] In a multi-motherboard scenario, if processors on different motherboards all have built-in clock circuits and output clock signals, then multiple downstream devices connected to these motherboards can only use the clock signal output by a single motherboard, resulting in clock desynchronization of these downstream devices.

[0003] Therefore, how to solve the problem of clock asynchrony of downstream devices in a scenario where multiple mainboards provide clock signals is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a clock processing system, method, device, medium and program product to solve the problem of clock asynchrony of downstream devices in a scenario where multiple motherboards provide clock signals.

[0005] In the first aspect, the present application provides a clock processing system, comprising: at least two mainboards, a switching device and at least two target devices; wherein, the processor in each mainboard has a built-in first clock module; the first clock module is used to provide a first clock signal for the corresponding mainboard; the switching device comprises: a second clock module, a switching module, and a signal processing device respectively connected to each mainboard; the second clock module is respectively connected to the switching module, any signal processing device, and any two target devices; the second clock module is used to provide a second clock signal for any signal processing device, the switching module and any two target devices; the switching module is respectively connected to any signal processing device and any target device; the switching module is used to connect the data path between any signal processing device and any target device.

[0006] In the second aspect, the present application provides a clock processing method, which is applied to any signal processing device in a clock processing system, and the clock processing system includes: at least two mainboards, a switching device and at least two target devices; wherein the processor in each mainboard has a built-in first clock module; the first clock module is used to provide a first clock signal for the corresponding mainboard; the switching device includes: a second clock module, a switching module, and a signal processing device connected to each mainboard respectively; the second clock module is respectively connected to the switching module, any signal processing device, and any two target devices; the second clock module is used to provide a second clock signal for any signal processing device, the switching module and any two target devices; the switching module is respectively connected to any signal processing device and any target device; the switching module is used to connect the data path between any signal processing device and any target device; the clock processing method includes: referring to the second clock signal currently generated by the second clock module, performing clock recovery on the upstream data signal sent by the mainboard corresponding to the signal processing device to obtain a recovered clock signal; referring to the recovered clock signal, transmitting the current upstream data signal to the target device corresponding to the current upstream data signal; and / or, referring to the recovered clock signal, transmitting the received downstream data signal to the destination mainboard corresponding to the current downstream data signal.

[0007] In a third aspect, the present application provides an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the aforementioned disclosed clock processing method.

[0008] In a fourth aspect, the present application provides a non-volatile storage medium for storing a computer program, wherein the computer program implements the aforementioned disclosed clock processing method when executed by a processor.

[0009] In a fifth aspect, the present application provides a computer program product, comprising a computer program / instruction, which implements the steps of the aforementioned disclosed clock processing method when executed by a processor.

[0010] It can be seen from the above scheme that the present application provides a clock processing system, including: at least two mainboards, a switching device and at least two target devices; wherein, the processor in each mainboard has a built-in first clock module; the first clock module is used to provide a first clock signal for the corresponding mainboard; the switching device includes: a second clock module, a switching module, and a signal processing device connected to each mainboard respectively; the second clock module is respectively connected to the switching module, any signal processing device, and any two target devices; the second clock module is used to provide a second clock signal for any signal processing device, the switching module and any two target devices; the switching module is respectively connected to any signal processing device and any target device; the switching module is used to connect the data path between any signal processing device and any target device.

[0011] As can be seen, the beneficial effect of this application is that, when the processors in each motherboard have a built-in first clock module and provide a first clock signal, the downstream switching devices of these motherboards and at least two target devices connected to the switching devices all use the second clock signal provided by the second clock module in the switching device as a reference, thereby achieving the same-source synchronization of the clock signals of the downstream switching devices and the at least two target devices connected to the switching devices. Furthermore, this does not affect the first clock signals provided by the upstream motherboards, thus resolving the problem of clock asynchrony in downstream devices in scenarios where multiple motherboards all provide clock signals.

[0012] Correspondingly, the clock processing method, device, medium and program product provided by this application also have the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0014] Figure 1 A schematic diagram of a clock processing system disclosed in this application;

[0015] Figure 2 This is a schematic diagram of the second clock processing system disclosed in this application;

[0016] Figure 3 A schematic diagram of a mainboard structure disclosed in this application;

[0017] Figure 4 This is a schematic diagram of the structure of an FPGA accelerator card disclosed in this application;

[0018] Figure 5 This is a schematic diagram of data processing within an FPGA acceleration card disclosed in this application;

[0019] Figure 6 A schematic diagram of a clock recovery process disclosed in this application;

[0020] Figure 7 A server structure diagram provided for this application;

[0021] Figure 8 This is a terminal structure diagram provided for this application. DETAILED DESCRIPTION

[0022] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0023] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0024] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0025] Currently, in a multi-motherboard scenario, if processors on different motherboards all have built-in clock circuits and output clock signals, then multiple downstream devices connected to these motherboards can only use the clock signal output by a single motherboard, resulting in clock asynchrony among these downstream devices. To address this issue, the present application provides a clock processing solution that can achieve co-source synchronization of the clock signals of the downstream switching device of each motherboard and at least two target devices connected to the switching device, thereby resolving the problem of clock asynchrony among downstream devices in a scenario where multiple motherboards all provide clock signals.

[0026] See also Figure 1 As shown, an embodiment of the present application discloses a clock processing system, comprising: at least two mainboards, a switching device and at least two target devices; wherein, the processor in each mainboard has a built-in first clock module; the first clock module is used to provide a first clock signal for the corresponding mainboard; wherein, the second clock module includes: a clock generator and a clock buffer; the clock generator is used to generate a second clock signal; and the clock buffer is used to cache the second clock signal.

[0027] The switching device includes: a second clock module, a switching module, and a signal processing device connected to each mainboard respectively; the second clock module is connected to the switching module, any signal processing device, and any two target devices respectively; the second clock module is used to provide a second clock signal for any signal processing device, the switching module, and any two target devices; the switching module is connected to any signal processing device and any target device respectively; the switching module is used to connect the data path between any signal processing device and any target device.

[0028] In this embodiment, the target device may be a memory device or an accelerator card.

[0029] See Figure 1 , Figure 1 The bold lines are clock lines, and the non-bold lines are data lines. The specific transmission directions of these two lines can be found in Figure 2 Arrows shown. In one embodiment, the second clock module is respectively connected to the switching module, any signal processing device, and any target device with clock lines. Specifically, the second clock module and any signal processing device are connected via a slot that supports the high-speed serial computer expansion bus standard to achieve the clock line connection; the second clock module and any target device are connected via a slot that supports the high-speed serial computer expansion bus standard to achieve the clock line connection. In one embodiment, the switching module is respectively connected to any signal processing device and any two target devices with data lines. Specifically, the switching module and any signal processing device are connected via a slot that supports the high-speed serial computer expansion bus standard to achieve the data line connection; the switching module and any target device are connected via a slot that supports the high-speed serial computer expansion bus standard to achieve the data line connection.

[0030] Among them, the signal processing device is used to: refer to the second clock signal currently generated by the second clock module, perform clock recovery on the upstream data signal sent by the mainboard corresponding to the signal processing device, obtain a recovered clock signal, and refer to the recovered clock signal to transmit the current upstream data signal to the target device corresponding to the current upstream data signal, such as: it can be a certain acceleration card; and / or, refer to the recovered clock signal to transmit the received downstream data signal to the destination mainboard corresponding to the current downstream data signal.

[0031] In order to enable the signal processing device to have a clock recovery function, a clock recovery module is set up therein. The clock recovery module is a CDR (Clock and Data Recovery) module. The specific structure may include: a sampler, a detector, a filter and an oscillator; the sampler is used to: sample the received data signal; the detector is used to: detect the rising edge or falling edge of the sampled data signal, and compare the phase difference with the second clock signal currently generated by the second clock module, and output the phase error; the filter is used to: low-pass filter the phase error; the oscillator is used to: adjust the frequency and phase of the clock signal obtained by low-pass filtering to obtain a clock recovery signal, and use the clock recovery signal to sample the received data signal.

[0032] It should be noted that the second clock module and multiple signal processing devices are built into the switching device, and the multiple signal processing devices correspond one-to-one with each mainboard. Furthermore, since the switching device includes a switching module, the data transmission path from the mainboard to the downstream accelerator card is: mainboard → signal processing device → switching module → accelerator card. Correspondingly, the data transmission path from the downstream accelerator card to the mainboard is: accelerator card → switching module → signal processing device → mainboard.

[0033] The following describes the data transmission from the mainboard to the downstream acceleration card in combination with the various functional modules in the signal processing device. In one embodiment, the signal processing device includes: an upstream communication module, a clock recovery module, and a downstream communication module; the upstream communication module is used to: receive the upstream data signal sent by any mainboard; send the currently received downstream data signal to the destination mainboard corresponding to the current downstream data signal; the clock recovery module is used to: refer to the second clock signal currently generated by the second clock module, perform clock recovery on the upstream data signal sent by the mainboard corresponding to the signal processing device, and obtain a recovered clock signal; the downstream communication module is used to: receive the downstream data signal sent by any acceleration card; send the received upstream data signal to the destination acceleration card corresponding to the current upstream data signal. Among them, the upstream communication module is connected to the upstream connector, which is connected to the mainboard; the downstream communication module is connected to the gold finger, which is connected to the switching module (PCIe Switch or CXL Switch) in the switching device through PCIe Slots, and the downstream of the switching module is connected to numerous acceleration cards through numerous PCIe Slots.

[0034] More specifically, the signal processing device can also perform various processes on the data signal, such as decoding, frame parsing, and / or demultiplexing. In one embodiment, the signal processing device further includes: a first parsing unit, a cache unit, and a second parsing unit; the first parsing unit is configured to decode, frame parse, and / or demultiplex the upstream data signal sent by the upstream communication module with reference to the recovered clock signal; the cache unit is configured to cache the decoded, frame parsed, and / or demultiplexed upstream data signal with reference to the recovered clock signal; the second parsing unit is configured to read the upstream data signal from the cache unit; multiplex, frame parse, and / or encode the read upstream data signal with reference to the second clock signal currently generated by the second clock module, and transmit the multiplexed, frame parsed, and / or encoded upstream data signal to the downstream communication module.

[0035] It should also be noted that the data signal is a parallel signal inside the signal processing device and a serial signal outside the signal processing device. Therefore, in one embodiment, the signal processing device further includes: a first serial-to-parallel conversion unit and a first parallel-to-serial conversion unit; the first serial-to-parallel conversion unit is configured to perform serial-to-parallel conversion on the upstream data signal sent by the upstream communication module, and transmit the serial-to-parallel converted upstream data signal to the first parsing unit and the clock recovery module from top to bottom; the first parallel-to-serial conversion unit is configured to perform parallel-to-serial conversion on the multiplexed, frame parsed, and / or encoded upstream data signal, and transmit the parallel-to-serial converted upstream data signal to the downstream communication module.

[0036] The top-to-bottom cache unit includes a top-to-bottom random access memory area and a top-to-bottom double-rate synchronous dynamic random access memory area. Because the top-to-bottom random access memory area is limited in space, data from the top-to-bottom random access memory area is cached in the top-to-bottom double-rate synchronous dynamic random access memory area. Specifically, the top-to-bottom random access memory area is used to cache received upstream data signals with reference to the recovered clock signal and output upstream data signals with reference to the second clock signal currently generated by the second clock module. The top-to-bottom double-rate synchronous dynamic random access memory area is used to cache upstream data signals output by the random access memory area.

[0037] More specifically, the signal processing device can also encrypt or compress the data signal. In one embodiment, the signal processing device further includes: a top-down signal processing unit; the top-down signal processing unit is configured to compress and / or encrypt the upstream data signal output by the top-down first parsing unit.

[0038] The following describes the data transmission from the downstream accelerator card to the mainboard in conjunction with the various functional modules in the signal processing device. In one embodiment, the signal processing device further includes: a first parsing unit from bottom to top, a cache unit from bottom to top, and a second parsing unit from bottom to top; the first parsing unit from bottom to top is used to: decode, frame parse, and / or demultiplex the downstream data signal sent by the downstream communication module with reference to the second clock signal currently generated by the second clock module; the cache unit from bottom to top is used to: cache the decoded, frame parsed, and / or demultiplexed downstream data signal with reference to the second clock signal currently generated by the second clock module; the second parsing unit from bottom to top is used to: read the downstream data signal from the cache unit from bottom to top, multiplex, frame parse, and / or encode the read downstream data signal, and send the multiplexed, frame parsed, and / or encoded downstream data signal to the upstream communication module.

[0039] Since the data signal is a parallel signal inside the signal processing device and a serial signal outside the signal processing device, in one embodiment, the signal processing device further includes: a second serial-to-parallel conversion unit and a second parallel-to-serial conversion unit; the second serial-to-parallel conversion unit is configured to perform serial-to-parallel conversion on the downstream data signal sent by the downstream communication module, and transmit the serial-to-parallel converted downstream data signal to the first parsing unit from bottom to top; the second parallel-to-serial conversion unit is configured to perform parallel-to-serial conversion on the downstream data signal after multiplexing, frame parsing, and / or encoding, and transmit the parallel-to-serial converted downstream data signal to the upstream communication module.

[0040] Because the random access memory area is too small and limited, the data output from the random access memory area is cached in the double rate synchronous dynamic random access memory area. Specifically, in one embodiment, the bottom-to-top cache unit includes: a bottom-to-top random access memory area and a bottom-to-top double rate synchronous dynamic random access memory area; the bottom-to-top random access memory area is used to: cache the received downstream data signal with reference to the second clock signal currently generated by the second clock module; and output the downstream data signal with reference to the recovered clock signal; the bottom-to-top double rate synchronous dynamic random access memory area is used to: cache the downstream data signal output by the random access memory area.

[0041] Since the signal processing device can also encrypt or compress the data signal, in one embodiment, the signal processing device also includes: a bottom-to-top signal processing unit; the bottom-to-top signal processing unit is used to: compress and / or encrypt the downstream data signal output by the bottom-to-top first parsing unit.

[0042] It should also be noted that this embodiment allows different motherboard models to be different. In one embodiment, any motherboard includes: at least two processors; at least two processors have a built-in first clock module; at least two processors are used to generate corresponding upstream data signals using the first clock signal provided by their own built-in first clock module. That is, the same motherboard may include different processors that output different clock signals. To facilitate the interconnection between the motherboard and other devices, the motherboard can be in the form of a card that supports the high-speed serial computer expansion bus standard. In addition, the signal processing device can be an FPGA accelerator card. Accordingly, the FPGA accelerator card includes: an upstream connector and a gold finger; the upstream connector is connected to the corresponding motherboard; the gold finger is connected to the corresponding accelerator card through the switching module in the switching device.

[0043] As can be seen, in this embodiment, when each motherboard provides a clock signal, the downstream switching device of these motherboards and at least two target devices connected to the switching device all use the second clock signal provided by the second clock module in the switching device as a reference, thereby achieving the same-source synchronization of the clock signals of the downstream switching device and the at least two target devices connected to the switching device. Furthermore, this does not affect the clock signals provided by the upstream motherboards, thus resolving the problem of clock asynchrony in downstream devices when multiple motherboards provide clock signals.

[0044] In one example, the system architecture in a dual-motherboard scenario can be as follows: Figure 2 As shown. Figure 2 In this example, a motherboard includes a processor, a clock buffer, and an MCIO connector (MiniCoolEdge I / O, a high-speed I / O connector). These two motherboards are connected to two FPGA accelerator cards (signal processing devices) in the switch. The switch also includes a clock generator, clock buffer, switching modules, and multiple PCIe slots (slots supporting the high-speed serial computer expansion bus standard) required for connectivity. The three downstream PCIe slots each connect to three accelerator cards.

[0045] Specifically, the motherboard's MCIO connector is connected to the FPGA accelerator card's MCIO connector via a cable. The FPGA accelerator card's gold finger then connects to the switch chip (switching module) on the switch board (switching device). Furthermore, because the FPGA accelerator card uses the switch board's local clock (i.e., the secondary clock signal provided by the secondary clock module) rather than the motherboard's CPU clock, the FPGA accelerator card must perform clock recovery on the data signal received from the motherboard's CPU. This data signal is then input to the switch chip using the switch board's local clock, and then transmitted to the accelerator card. This allows the downstream accelerator card to also use the switch board's clock source. Consequently, the motherboard and switch board use asynchronous clocks. Furthermore, the FPGA accelerator card also acts as a switch device for the motherboard's CPU, meaning that the CPU data signal passes through two switches before reaching the downstream accelerator card.

[0046] See Figure 3The internal components of the motherboard may include CPU, BMC (Baseboard Management Controller), CPLD (Complex Programmable Logic Device), Flash, memory, hard disk, clock and VRM (Voltage Regulator Module) power module, etc. The CPU is primarily responsible for resource allocation and computing; the BMC is responsible for device information management, server status monitoring, server remote control, and VGA (Video Graphics Array) display. The CPLD is responsible for controlling power sequencing and GPIO (General-Purpose Input / Output) communication. The VRMs are different power modules that output different voltages for onboard components. DDR_CH1 through DDR_CH4 represent Rectangular Dimensional Memory (RDIMM) memory slots. The MCIO X8 connector connects to QSFP28, PCIe Gen4, and PCIe Gen5 signals, respectively. QSFP28 allows for optical communication with other devices, while PCIe Gen4 and PCIe Gen5 connect to NVMe SSDs or other PCIe devices. XDP and UART are standard CPU debugging interfaces. VGA connects to a monitor, and USB connects to a mouse and disk. This motherboard can be a pluggable PCIe micro motherboard.

[0047] See Figure 4 The FPGA accelerator card in the switch board can include an FPGA, CPLD, Flash, and a VRM power module. The FPGA is the main control chip, responsible for accelerating computing and communications; the CPLD is responsible for controlling power timing and GPIO communication; the VRM is a power module that outputs different voltages for the board components. DDR5_1 to DDR5_4 represent quad-channel memory slots, capable of accommodating four memory modules; QSFP28_1 and QSFP28_2 are the FPGA's optical connectors, enabling communication with other computing units or acceleration units; and the two MCIO X8 connectors are high-speed connectors, both supporting PCIe Gen5.0 and CXL protocols.

[0048] It should be noted that the CPU data from the CPU board enters the FPGA chip of the FPGA accelerator card. Because the clock of this data uses the clock output by the CPU itself, the FPGA accelerator card uses the local clock of the switch board. Both clocks are 100 MHz, but their phases are generally different, that is, they are asynchronous clocks.

[0049] See Figure 5, there are upstream ports and downstream ports inside the FPGA accelerator card, which can be understood as the FPGA accelerator card serving as the upstream port and downstream port of the Switch chip. The data signal of the motherboard CPU enters the physical high-speed transceiver IO (upstream communication module) of the FPGA accelerator card through the MCIO connector. The data signal then undergoes serial-to-parallel data conversion and then undergoes clock recovery. The clock recovery uses the CDR module inside the FPGA accelerator card to perform clock data recovery using the local clock as the reference clock. The recovered clock is then used to perform subsequent processing on the data signal, such as decoding, data frame parsing, and demultiplexer, and then output the processing layer data packet. At this time, the data packet can also perform some operations inside the FPGA accelerator card, such as compression, encryption, etc. Furthermore, the data packet is asynchronously cached through the RAM inside the FPGA accelerator card. The so-called asynchronous cache means that the input RAM uses the recovered clock mentioned above, and the RAM output uses the local clock. However, since the RAM space is too small, the data coming out of the RAM enters the DDR ( Figure 5 For DDR, the local clock is used to read the data signal. Then, a series of operations are performed at the processing layer, including packet packaging, multiplexing, data frame parsing, encoding, and parallel-to-serial conversion. The data packet is output through the physical high-speed transceiver I / O of the downstream port and then enters the corresponding PCIe slot through the Goldfinger.

[0050] On the downstream-to-upstream transmission path, the accelerator card's data signal enters the FPGA accelerator card's physical high-speed transceiver I / O through a gold finger. Using the local clock, the data signal undergoes a series of operations, including serial-to-parallel conversion, decoding, data frame parsing, demultiplexing, and packet processing. The packet processing can also undergo further operations within the FPGA accelerator card, such as compression and encryption. The data is then asynchronously cached in the FPGA accelerator card's internal RAM. Asynchronous caching means the RAM input uses the local clock, while the RAM output uses the recovered clock. However, due to RAM limitations, data exiting the RAM is cached in DDR. The DDR then uses the local clock to read the data signal. Processing layer packet packaging, multiplexing, data frame parsing, encoding, and serial-to-parallel conversion are then performed. The resulting data signal is then output through the upstream port's physical high-speed transceiver I / O and then fed into the motherboard CPU via the MCIO connector.

[0051] See Figure 6The data signal processing process of the CDR module within the FPGA accelerator card includes equalization preprocessing of the received serial data, multi-stage sampling, and then passing through a phase detector. Edge triggering is used to detect the phase difference between the rising / falling edge of the data and the local clock, outputting the phase error. The phase error signal then passes through a digital loop filter for low-pass filtering. Finally, a digitally controlled oscillator adjusts the frequency and phase of the output clock to restore the original CPU clock. The recovered clock is then used to sample the input data to restore the original data for output to the DDR cache. The core principle of CDR is to extract clock information from high-speed serial data through digital signal processing technology and generate a clock signal synchronized with the data.

[0052] It should be noted that it is also possible to customize the phase detector, digital loop filter, digitally controlled oscillator, etc. inside the FPGA accelerator card to implement the CDR function. This allows for self-adjustment of parameters such as filtering, making the solution more flexible.

[0053] This embodiment uses the FPGA accelerator card in the switch board to implement asynchronous clock communication between the mainboard CPU and the switch and its downstream accelerator card. Here, the FPGA accelerator card implements both the PCIe switch function and the clock recovery function of high-speed serial data.

[0054] A clock processing method provided in an embodiment of the present application is introduced below. The clock processing method described below can be referenced with other embodiments described in this document.

[0055] An embodiment of the present application discloses a clock processing method, which is applied to any signal processing device in a clock processing system, wherein the clock processing system includes: at least two mainboards, a switching device, and at least two target devices; wherein the processor in each mainboard has a built-in first clock module; the first clock module is used to provide a first clock signal for the corresponding mainboard; the switching device includes: a second clock module, a switching module, and a signal processing device connected to each mainboard respectively; the second clock module is respectively connected to the switching module, any signal processing device, and any two target devices; the second clock module is used to provide a second clock signal for any signal processing device, the switching module, and any two target devices; the switching module is respectively connected to any signal processing device and any target device; the switching module is used to connect the data path between any signal processing device and any target device.

[0056] The clock processing method provided in this embodiment includes: referring to the second clock signal currently generated by the second clock module, performing clock recovery on the upstream data signal sent by the mainboard corresponding to the signal processing device to obtain a recovered clock signal; referring to the recovered clock signal, transmitting the current upstream data signal to the target device corresponding to the current upstream data signal; and / or, referring to the recovered clock signal, transmitting the received downstream data signal to the destination mainboard corresponding to the current downstream data signal.

[0057] In order to enable the signal processing device to have a clock recovery function, a clock recovery module is set up therein. The clock recovery module is a CDR (Clock and Data Recovery) module. The specific structure may include: a sampler, a detector, a filter and an oscillator; the sampler is used to: sample the received data signal; the detector is used to: detect the rising edge or falling edge of the sampled data signal, and compare the phase difference with the second clock signal currently generated by the second clock module, and output the phase error; the filter is used to: low-pass filter the phase error; the oscillator is used to: adjust the frequency and phase of the clock signal obtained by low-pass filtering to obtain a clock recovery signal, and use the clock recovery signal to sample the received data signal.

[0058] In one embodiment, the signal processing device includes: an upstream communication module, a clock recovery module and a downstream communication module; the upstream communication module is used to: receive an upstream data signal sent by any mainboard; and send the currently received downstream data signal to the destination mainboard corresponding to the current downstream data signal; the clock recovery module is used to: refer to the second clock signal currently generated by the second clock module, perform clock recovery on the upstream data signal sent by the mainboard corresponding to the signal processing device, and obtain a recovered clock signal; the downstream communication module is used to: receive a downstream data signal sent by any acceleration card; and send the received upstream data signal to the destination acceleration card corresponding to the current upstream data signal.

[0059] In one embodiment, the signal processing device further includes: a first parsing unit from top to bottom, a cache unit from top to bottom, and a second parsing unit from top to bottom; the first parsing unit from top to bottom is used to: decode, frame parse and / or demultiplex the upstream data signal sent by the upstream communication module with reference to the recovered clock signal; the cache unit from top to bottom is used to: cache the decoded, frame parsed and / or demultiplexed upstream data signal with reference to the recovered clock signal; the second parsing unit from top to bottom is used to: read the upstream data signal from the cache unit from top to bottom; multiplex, frame parse and / or encode the read upstream data signal with reference to the second clock signal currently generated by the second clock module, and send the multiplexed, frame parsed and / or encoded upstream data signal to the downstream communication module.

[0060] In one embodiment, the signal processing device also includes: a first serial-to-parallel conversion unit and a first parallel-to-serial conversion unit; the first serial-to-parallel conversion unit is used to: perform serial-to-parallel conversion on the upstream data signal sent by the upstream communication module, and transmit the serial-to-parallel converted upstream data signal to the first parsing unit and the clock recovery module from top to bottom; the first parallel-to-serial conversion unit is used to: perform parallel-to-serial conversion on the upstream data signal after multiplexing, frame parsing and / or encoding, and transmit the parallel-to-serial converted upstream data signal to the downstream communication module.

[0061] In one embodiment, the top-to-bottom cache unit includes: a top-to-bottom random access storage area and a top-to-bottom double-rate synchronous dynamic random access storage area; the top-to-bottom random access storage area is used to: cache the received upstream data signal with reference to the recovered clock signal; output the upstream data signal with reference to the second clock signal currently generated by the second clock module; the top-to-bottom double-rate synchronous dynamic random access storage area is used to: cache the upstream data signal output by the random access storage area.

[0062] In one embodiment, the signal processing device further includes: a top-down signal processing unit; the top-down signal processing unit is used to: perform compression processing and / or encryption processing on the upstream data signal output by the top-down first parsing unit.

[0063] In one embodiment, the signal processing device further includes: a first parsing unit from bottom to top, a cache unit from bottom to top, and a second parsing unit from bottom to top; the first parsing unit from bottom to top is used to: decode, frame parse and / or demultiplex the downstream data signal sent by the downstream communication module with reference to the second clock signal currently generated by the second clock module; the cache unit from bottom to top is used to: cache the decoded, frame parsed and / or demultiplexed downstream data signal with reference to the second clock signal currently generated by the second clock module; the second parsing unit from bottom to top is used to: read the downstream data signal from the cache unit from bottom to top, multiplex, frame parse and / or encode the read downstream data signal, and send the multiplexed, frame parsed and / or encoded downstream data signal to the upstream communication module.

[0064] In one embodiment, the signal processing device further includes: a second serial-to-parallel conversion unit and a second parallel-to-serial conversion unit; the second serial-to-parallel conversion unit is used to: perform serial-to-parallel conversion on the downstream data signal sent by the downstream communication module, and transmit the serial-to-parallel converted downstream data signal to the first parsing unit from bottom to top; the second parallel-to-serial conversion unit is used to: perform parallel-to-serial conversion on the downstream data signal after multiplexing, frame parsing and / or encoding, and transmit the parallel-to-serial converted downstream data signal to the upstream communication module.

[0065] In one embodiment, the bottom-to-top cache unit includes: a bottom-to-top random access storage area and a bottom-to-top double-rate synchronous dynamic random access storage area; the bottom-to-top random access storage area is used to: cache the received downstream data signal with reference to the second clock signal currently generated by the second clock module; and output the downstream data signal with reference to the recovered clock signal; the bottom-to-top double-rate synchronous dynamic random access storage area is used to: cache the downstream data signal output by the random access storage area.

[0066] In one embodiment, the signal processing device further includes: a bottom-up signal processing unit; the bottom-up signal processing unit is used to: perform compression processing and / or encryption processing on the downstream data signal output by the bottom-up first parsing unit.

[0067] In one embodiment, different mainboards are of different models.

[0068] In one embodiment, the signal processing device is an FPGA accelerator card.

[0069] In one embodiment, the FPGA accelerator card includes: an upstream connector and a gold finger; the upstream connector is connected to the corresponding mainboard; the gold finger is connected to the corresponding accelerator card through a switching module in a switching device.

[0070] In one embodiment, any motherboard includes: at least two processors; at least two processors each have a built-in first clock module; at least two processors are configured to generate corresponding upstream data signals using a first clock signal provided by the built-in first clock module.

[0071] In one embodiment, any motherboard is in the form of a card that supports the high-speed serial computer expansion bus standard.

[0072] Among them, for more specific working processes of each module and unit in this embodiment, reference can be made to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.

[0073] In this embodiment, when each motherboard provides a clock signal, the downstream switching device of these motherboards and at least two target devices connected to the switching device all use the second clock signal provided by the second clock module in the switching device as a reference, thereby achieving co-source synchronization of the clock signals of the downstream switching device and the at least two target devices connected to the switching device. Furthermore, this does not affect the clock signals provided by the upstream motherboards, thus resolving the issue of clock asynchrony in downstream devices when multiple motherboards provide clock signals.

[0074] The following describes an electronic device provided in an embodiment of the present application. The electronic device described below can be cross-referenced with other embodiments described herein. The electronic device in this embodiment can be any device or functional module described in other embodiments, such as a motherboard, a switching device, an accelerator card, a first clock module, a switching device, a second clock module, and a signal processing device.

[0075] An embodiment of the present application discloses an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the method disclosed in any of the above embodiments.

[0076] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: providing a first clock signal to the corresponding mainboard.

[0077] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: generating a second clock signal.

[0078] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: referring to the second clock signal currently generated by the second clock module, performing clock recovery on the upstream data signal sent by the mainboard corresponding to the signal processing device to obtain a recovered clock signal, and referring to the recovered clock signal, transmitting the current upstream data signal to the destination accelerator card corresponding to the current upstream data signal; and / or, referring to the recovered clock signal, transmitting the received downstream data signal to the destination mainboard corresponding to the current downstream data signal.

[0079] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: sampling the received data signal.

[0080] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: detect the rising edge or falling edge of the sampled data signal, compare the phase difference with the second clock signal currently generated by the second clock module, and output the phase error.

[0081] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: performing low-pass filtering on the phase error.

[0082] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: adjust the frequency and phase of the clock signal obtained by low-pass filtering to obtain a clock recovery signal, and use the clock recovery signal to sample the received data signal.

[0083] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: receiving an upstream data signal sent by any motherboard; sending the currently received downstream data signal to the destination motherboard corresponding to the current downstream data signal.

[0084] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: referring to the second clock signal currently generated by the second clock module, performing clock recovery on the upstream data signal sent by the mainboard corresponding to the signal processing device to obtain a recovered clock signal.

[0085] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: receiving a downstream data signal sent by any accelerator card; and sending the received upstream data signal to the destination accelerator card corresponding to the current upstream data signal.

[0086] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: refer to the recovered clock signal, decode, frame parse and / or demultiplex the upstream data signal sent by the upstream communication module.

[0087] In this embodiment, when the processor executes the computer program stored in the memory, it may specifically implement the following steps: referring to the recovered clock signal, caching the upstream data signal after decoding, frame parsing and / or demultiplexing.

[0088] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: read the upstream data signal from the top-to-bottom cache unit; refer to the second clock signal currently generated by the second clock module, multiplex, frame parse and / or encode the read upstream data signal, and send the multiplexed, frame parsed and / or encoded upstream data signal to the downstream communication module.

[0089] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: perform serial-to-parallel conversion on the upstream data signal sent by the upstream communication module, and transmit the serial-to-parallel converted upstream data signal to the first analysis unit and clock recovery module from top to bottom.

[0090] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: convert the upstream data signal after multiplexing, frame parsing and / or encoding into parallel-to-serial mode, and transmit the upstream data signal after parallel-to-serial conversion to the downstream communication module.

[0091] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: cache the received upstream data signal with reference to the recovered clock signal; and output the upstream data signal with reference to the second clock signal currently generated by the second clock module.

[0092] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: caching the upstream data signal output by the random access memory area.

[0093] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: compressing and / or encrypting the upstream data signal output by the first parsing unit from top to bottom.

[0094] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: refer to the second clock signal currently generated by the second clock module, decode, frame parse and / or demultiplex the downstream data signal sent by the downstream communication module.

[0095] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: referring to the second clock signal currently generated by the second clock module, caching the downstream data signal after decoding, frame parsing and / or demultiplexing.

[0096] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: read the downstream data signal from the bottom-up cache unit, multiplex, frame parse and / or encode the read downstream data signal, and send the multiplexed, frame parsed and / or encoded downstream data signal to the upstream communication module.

[0097] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: perform serial-to-parallel conversion on the downstream data signal sent by the downstream communication module, and transmit the serial-to-parallel converted downstream data signal to the first parsing unit from bottom to top.

[0098] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: convert the downstream data signal after multiplexing, frame parsing and / or encoding into parallel-to-serial mode, and transmit the downstream data signal after parallel-to-serial conversion to the upstream communication module.

[0099] In this embodiment, when the processor executes the computer program stored in the memory, it can specifically implement the following steps: cache the received downstream data signal with reference to the second clock signal currently generated by the second clock module; and output the downstream data signal with reference to the recovered clock signal.

[0100] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: caching the downstream data signal output by the random access memory area.

[0101] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: compressing and / or encrypting the downstream data signal outputted by the first parsing unit from bottom to top.

[0102] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: using the first clock signal provided by the first clock module built into the processor to generate a corresponding upstream data signal.

[0103] Furthermore, the embodiment of the present application also provides an electronic device. The electronic device can be Figure 7 The server shown can also be Figure 8 Terminal shown. Figure 7 and Figure 8 Each of the diagrams is a structural diagram of an electronic device according to an exemplary embodiment, and the contents in the diagrams cannot be considered as any limitation on the scope of use of the present application.

[0104] Figure 7 This is a schematic diagram of the structure of a server provided in an embodiment of the present application. The server may include: at least one processor, at least one memory, a power supply, a communication interface, an input / output interface, and a communication bus. The memory is used to store a computer program, which is loaded and executed by the processor to implement the relevant steps of the clock processing disclosed in any of the aforementioned embodiments.

[0105] In this embodiment, the power supply is used to provide operating voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and external devices. The communication protocol it follows is any communication protocol that can be applied to the technical solution of this application and is not specifically limited here; the input and output interface is used to obtain external input data or output data to the outside world. The specific interface type can be selected according to specific application needs and is not specifically limited here.

[0106] In addition, the memory as a carrier for resource storage can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon include operating system, computer programs and data, etc. The storage method can be temporary storage or permanent storage.

[0107] The operating system is used to manage and control the hardware devices and computer programs on the server, enabling the processor to operate and process data in the memory. It can be Windows Server, NetWare, Unix, Linux, etc. In addition to computer programs capable of implementing the clock processing method disclosed in any of the aforementioned embodiments, computer programs can also include computer programs capable of performing other specific tasks. Data can include data such as application update information and information about the application developer.

[0108] Figure 8 This is a schematic diagram of the structure of a terminal provided in an embodiment of the present application. The terminal may specifically include but is not limited to a smartphone, tablet computer, laptop computer or desktop computer.

[0109] Generally, the terminal in this embodiment includes: a processor and a memory.

[0110] The processor may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor may be implemented in at least one of the following hardware forms: a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), or a PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is used to process data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing content required to be displayed on the display. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0111] The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory, and non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory is used to store at least the following computer program, wherein, after the computer program is loaded and executed by the processor, it can implement the relevant steps in the clock processing method performed by the terminal side disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory may also include an operating system and data, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include but is not limited to update information of the application.

[0112] In some embodiments, the terminal may further include a display screen, an input and output interface, a communication interface, a sensor, a power supply, and a communication bus.

[0113] Those skilled in the art will understand that Figure 8 The structure shown in the figure does not constitute a limitation to the terminal, and may include more or fewer components than shown in the figure.

[0114] A non-volatile storage medium provided in an embodiment of the present application is introduced below. The non-volatile storage medium described below can be referenced with other embodiments described herein.

[0115] A non-volatile storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the clock processing method disclosed in the aforementioned embodiment. The non-volatile storage medium is a computer-readable non-volatile storage medium that, as a carrier for resource storage, can be a read-only memory, random access memory, magnetic disk, or optical disk. The resources stored thereon include an operating system, computer program, and data, and the storage method can be either temporary or permanent.

[0116] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: providing a first clock signal to the corresponding mainboard.

[0117] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: generating a second clock signal.

[0118] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: referring to the second clock signal currently generated by the second clock module, performing clock recovery on the upstream data signal sent by the mainboard corresponding to the signal processing device to obtain a recovered clock signal, and referring to the recovered clock signal, transmitting the current upstream data signal to the destination accelerator card corresponding to the current upstream data signal; and / or, referring to the recovered clock signal, transmitting the received downstream data signal to the destination mainboard corresponding to the current downstream data signal.

[0119] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: sampling the received data signal.

[0120] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: detect the rising edge or falling edge of the sampled data signal, compare the phase difference with the second clock signal currently generated by the second clock module, and output the phase error.

[0121] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: performing low-pass filtering on the phase error.

[0122] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: adjust the frequency and phase of the clock signal obtained by low-pass filtering to obtain a clock recovery signal, and use the clock recovery signal to sample the received data signal.

[0123] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: receiving an upstream data signal sent by any motherboard; sending the currently received downstream data signal to the destination motherboard corresponding to the current downstream data signal.

[0124] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: referring to the second clock signal currently generated by the second clock module, performing clock recovery on the upstream data signal sent by the mainboard corresponding to the signal processing device to obtain a recovered clock signal.

[0125] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: receiving a downstream data signal sent by any accelerator card; and sending the received upstream data signal to the destination accelerator card corresponding to the current upstream data signal.

[0126] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: refer to the recovered clock signal, decode, frame parse and / or demultiplex the upstream data signal sent by the upstream communication module.

[0127] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: referring to the recovered clock signal, caching the upstream data signal after decoding, frame parsing and / or demultiplexing.

[0128] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: read the upstream data signal from the top-to-bottom cache unit; refer to the second clock signal currently generated by the second clock module, multiplex, frame parse and / or encode the read upstream data signal, and send the multiplexed, frame parsed and / or encoded upstream data signal to the downstream communication module.

[0129] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: perform serial-to-parallel conversion on the upstream data signal sent by the upstream communication module, and transmit the serial-to-parallel converted upstream data signal to the first analysis unit and clock recovery module from top to bottom.

[0130] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: convert the upstream data signal after multiplexing, frame parsing and / or encoding into parallel-to-serial, and transmit the upstream data signal after parallel-to-serial conversion to the downstream communication module.

[0131] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: cache the received upstream data signal with reference to the recovered clock signal; and output the upstream data signal with reference to the second clock signal currently generated by the second clock module.

[0132] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: caching the upstream data signal output by the random access memory area.

[0133] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: compressing and / or encrypting the upstream data signal output by the first parsing unit from top to bottom.

[0134] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: refer to the second clock signal currently generated by the second clock module, decode, frame parse and / or demultiplex the downstream data signal sent by the downstream communication module.

[0135] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: referring to the second clock signal currently generated by the second clock module, caching the downstream data signal after decoding, frame parsing and / or demultiplexing.

[0136] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: read the downstream data signal from the bottom-up cache unit, multiplex, frame parse and / or encode the read downstream data signal, and send the multiplexed, frame parsed and / or encoded downstream data signal to the upstream communication module.

[0137] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: perform serial-to-parallel conversion on the downstream data signal sent by the downstream communication module, and transmit the serial-to-parallel converted downstream data signal to the first parsing unit from bottom to top.

[0138] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: convert the downstream data signal after multiplexing, frame parsing and / or encoding into parallel-to-serial, and transmit the downstream data signal after parallel-to-serial conversion to the upstream communication module.

[0139] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, it can specifically implement the following steps: cache the received downstream data signal with reference to the second clock signal currently generated by the second clock module; and output the downstream data signal with reference to the recovered clock signal.

[0140] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: caching the downstream data signal output by the random access memory area.

[0141] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: compressing and / or encrypting the downstream data signal outputted by the first parsing unit from bottom to top.

[0142] In this embodiment, when the processor executes the computer program stored in the non-volatile storage medium, the following steps may be specifically implemented: using a first clock signal provided by a first clock module built into the processor to generate a corresponding upstream data signal.

[0143] A computer program product provided in an embodiment of the present application is introduced below. The computer program product described below can be referenced with other embodiments described herein.

[0144] A computer program product includes a computer program / instruction, which implements the steps of the aforementioned clock processing method when executed by a processor.

[0145] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium is used to store a computer program, and when the computer program is executed by a processor, the steps in any of the above embodiments are implemented.

[0146] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0147] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of non-volatile storage medium known in the art.

[0148] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A clock processing system, characterized in that: include: At least two motherboards, a switch device, and at least two target devices; The processor in each motherboard has a built-in first clock module; the first clock module is used to provide a first clock signal to the corresponding motherboard, so that each motherboard provides a clock signal; The switching device includes: a second clock module, a switching module, and a signal processing device connected to each mainboard respectively; The second clock module is connected to the switching module, any signal processing device, and any two target devices respectively; the second clock module is used to provide a second clock signal to any signal processing device, the switching module, and any two target devices, so as to achieve the same-source synchronization of the clock signals of the switching device and the at least two target devices; The switching module is connected to any signal processing device and any target device respectively; the switching module is used to connect the data path between any signal processing device and any target device, and realize asynchronous clock communication between the mainboard and the switching device and the target device.

2. The clock processing system according to claim 1, wherein: The second clock module is connected to the switching module, any signal processing device, and any target device through clock lines.

3. The clock processing system according to claim 2, wherein: The clock line connection between the second clock module and any signal processing device is achieved through a slot that supports the high-speed serial computer expansion bus standard; the clock line connection between the second clock module and any target device is achieved through a slot that supports the high-speed serial computer expansion bus standard.

4. The clock processing system according to claim 1, wherein: The switching module is respectively connected with any signal processing device and any two target devices via data lines.

5. The clock processing system according to claim 4, wherein: The data line connection between the switching module and any signal processing device is achieved through a slot that supports the high-speed serial computer expansion bus standard; the data line connection between the switching module and any target device is achieved through a slot that supports the high-speed serial computer expansion bus standard.

6. The clock processing system according to claim 1, wherein: The second clock module includes: a clock generator and a clock buffer; the clock generator is used to generate the second clock signal; the clock buffer is used to buffer the second clock signal.

7. The clock processing system according to claim 1, wherein: The signal processing device is configured to: perform clock recovery on the upstream data signal sent by the mainboard corresponding to the signal processing device with reference to the second clock signal currently generated by the second clock module to obtain a recovered clock signal; and transmit the current upstream data signal to a target device corresponding to the current upstream data signal with reference to the recovered clock signal; And / or, referring to the recovered clock signal, transmitting the received downstream data signal to the destination mainboard corresponding to the current downstream data signal.

8. The clock processing system according to claim 1, wherein: Any mainboard includes: at least two processors; the at least two processors both have the first clock module built in.

9. The clock processing system according to claim 1, wherein: Any motherboard is in the form of a card that supports the high-speed serial computer expansion bus standard.

10. The clock processing system according to claim 1, wherein: The signal processing device includes: an upstream communication module, a clock recovery module and a downstream communication module; The upstream communication module is used to: receive an upstream data signal sent by any motherboard; send the currently received downstream data signal to the destination motherboard corresponding to the current downstream data signal; The clock recovery module is configured to perform clock recovery on the upstream data signal sent by the mainboard corresponding to the signal processing device, with reference to the second clock signal currently generated by the second clock module, to obtain a recovered clock signal; The downstream communication module is used to: receive a downstream data signal sent by any target device; and send the received upstream data signal to the target device corresponding to the current upstream data signal.

11. The clock processing system according to claim 10, wherein: The signal processing device further comprises: a first parsing unit from top to bottom, a buffer unit from top to bottom, and a second parsing unit from top to bottom; The first parsing unit is configured to decode, parse frames and / or demultiplex the upstream data signal sent by the upstream communication module with reference to the recovered clock signal; The top-to-bottom buffer unit is used to: buffer the upstream data signal after decoding, frame parsing and / or demultiplexing with reference to the recovered clock signal; The second top-to-bottom parsing unit is configured to: read the upstream data signal from the top-to-bottom buffer unit; multiplex, frame parse, and / or encode the read upstream data signal with reference to the second clock signal currently generated by the second clock module; and send the multiplexed, frame parsed, and / or encoded upstream data signal to the downstream communication module; Accordingly, the signal processing device further comprises: a first serial-to-parallel conversion unit and a first parallel-to-serial conversion unit; The first serial-to-parallel conversion unit is used to perform serial-to-parallel conversion on the upstream data signal sent by the upstream communication module, and transmit the upstream data signal after the serial-to-parallel conversion to the first top-to-bottom parsing unit and the clock recovery module; The first parallel-to-serial conversion unit is configured to perform parallel-to-serial conversion on the multiplexed, frame parsed and / or encoded upstream data signal, and transmit the parallel-to-serial converted upstream data signal to the downstream communication module; Correspondingly, the top-to-bottom cache unit includes: a top-to-bottom random access memory area and a top-to-bottom double rate synchronous dynamic random access memory area; The top-to-bottom random access memory area is used to: buffer the received upstream data signal with reference to the recovered clock signal; and output the upstream data signal with reference to the second clock signal currently generated by the second clock module; The top-to-bottom double rate synchronous dynamic random access memory area is used to buffer the upstream data signal output by the random access memory area.

12. The clock processing system according to claim 11, wherein: The signal processing device further includes: a top-down signal processing unit; The top-to-bottom signal processing unit is used to perform compression processing and / or encryption processing on the upstream data signal output by the top-to-bottom first parsing unit.

13. The clock processing system according to claim 10, wherein: The signal processing device further comprises: a first parsing unit from bottom to top, a cache unit from bottom to top, and a second parsing unit from bottom to top; The first parsing unit is configured to decode, parse frames and / or demultiplex the downstream data signal sent by the downstream communication module with reference to the second clock signal currently generated by the second clock module; The bottom-up buffer unit is configured to: buffer the downstream data signal after decoding, frame parsing and / or demultiplexing, with reference to the second clock signal currently generated by the second clock module; The bottom-to-top second parsing unit is configured to: read the downstream data signal from the bottom-to-top buffer unit, multiplex, frame parse and / or encode the read downstream data signal, and send the multiplexed, frame parsed and / or encoded downstream data signal to the upstream communication module; Accordingly, the signal processing device further includes: a second serial-to-parallel conversion unit and a second parallel-to-serial conversion unit; The second serial-to-parallel conversion unit is used to perform serial-to-parallel conversion on the downstream data signal sent by the downstream communication module, and transmit the serial-to-parallel converted downstream data signal to the first bottom-to-top parsing unit; The second parallel-to-serial conversion unit is used to perform parallel-to-serial conversion on the downstream data signal after multiplexing, frame parsing and / or encoding, and transmit the downstream data signal after parallel-to-serial conversion to the upstream communication module; Accordingly, the bottom-to-top cache unit includes: a bottom-to-top random access memory area and a bottom-to-top double rate synchronous dynamic random access memory area; The bottom-to-top random access memory area is used to: buffer the received downstream data signal with reference to the second clock signal currently generated by the second clock module; and output the downstream data signal with reference to the recovered clock signal; The bottom-to-top double rate synchronous dynamic random access memory area is used to buffer the downstream data signal output by the random access memory area.

14. The clock processing system according to claim 13, wherein: The signal processing device further includes: a bottom-up signal processing unit; The bottom-to-top signal processing unit is used to perform compression processing and / or encryption processing on the downstream data signal output by the bottom-to-top first parsing unit.

15. The clock processing system according to any one of claims 10 to 14, characterized in that: The clock recovery module includes: a sampler, a detector, a filter and an oscillator; The sampler is used to: sample the received data signal; The detector is used to: detect the rising edge or falling edge of the sampled data signal, compare the phase difference with the second clock signal currently generated by the second clock module, and output a phase error; The filter is used to: perform low-pass filtering on the phase error; The oscillator is used to adjust the frequency and phase of the clock signal obtained by low-pass filtering to obtain the clock recovery signal, and use the clock recovery signal to sample the received data signal.

16. The clock processing system according to any one of claims 1 to 14, characterized in that: The signal processing device is an FPGA acceleration card, which includes: an upstream connector and a gold finger; the upstream connector is connected to the corresponding mainboard; the gold finger is connected to the corresponding target device through the switching module in the switching device.

17. A clock processing method, characterized in that: Any signal processing device used in a clock processing system, the clock processing system includes: at least two mainboards, a switching device and at least two target devices; wherein the processor in each mainboard has a built-in first clock module; the first clock module is used to provide a first clock signal to the corresponding mainboard, so that each mainboard provides a clock signal; the switching device includes: a second clock module, a switching module, and a signal processing device connected to each mainboard respectively; the second clock module is connected to the switching module, any signal processing device, and any two target devices respectively; the second clock module is used to provide a second clock signal to any signal processing device, the switching module and any two target devices, thereby realizing homologous synchronization of the clock signals of the switching device and the at least two target devices; the switching module is connected to any signal processing device and any target device respectively; the switching module is used to connect the data path between any signal processing device and any target device, thereby realizing asynchronous clock communication between the mainboard and the switching device and the target device; The clock processing method includes: performing clock recovery on an upstream data signal sent by the mainboard corresponding to the signal processing device, with reference to the second clock signal currently generated by the second clock module, to obtain a recovered clock signal; and transmitting the current upstream data signal to a target device corresponding to the current upstream data signal, with reference to the recovered clock signal; And / or, referring to the recovered clock signal, transmitting the received downstream data signal to the destination mainboard corresponding to the current downstream data signal.

18. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to execute the computer program to implement the method according to claim 17.

19. A non-volatile storage medium, characterized in that: Used to store a computer program, wherein the computer program implements the method according to claim 17 when executed by a processor.

20. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the method of claim 17 is implemented.

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