Server and server system

Abstract

The invention discloses a server and a server system, and relates to the technical field of communication, the server comprises at least one first board card, an exchange team group comprising a plurality of exchange boards, a second board card group comprising a plurality of second board cards and a middle backboard, the exchange boards are mutually orthogonal with any second board card and are in pluggable connection with any second board card, the at least one first board card is connected with at least part of the second board card through the middle backboard. Any two of the first board card, the switching board and the second board card are connected through the backboard in the related technology, wiring is very complex, direct interconnection of the switching board and the second board card is achieved through the orthogonal architecture of the switching board and the second board card, the maximum allowable wiring length is increased, and the problem that wiring is complex through backboard connection in the related technology is solved. The routing complexity of the first board card and the second board card is controllable through the middle backboard, the size of the case can be reduced to the maximum extent in space through connection of the middle backboard, and the size of the server case is compressed to the maximum extent while the routing complexity is reduced.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and particularly to a server and a server system. Background Art

[0002] With the continuous development of electronic technologies, signal rates have been continuously increasing. In high-speed network devices (such as data center switches and routers), the interconnection design of the switching board is the core foundation for achieving high-bandwidth and low-latency communication.

[0003] In the current switching board system design, in the interconnection design of the switching board, the second board card, and the first board card, most designs adopt a scheme of interconnection through a midplane. High-speed signals are fanned out from the switching board, pass through connectors, and are connected to the vertical midplane. Through the printed circuit board traces inside the midplane, they are connected to the connectors of the second board card, and then the interconnection with the second board card is achieved. Moreover, the interconnection between the switching board and the first board card is also realized through the midplane traces.

[0004] In this interconnection method, there are many traces on the midplane, the interconnection relationships are cross-complex, the probability of problems increases, and once a functional problem occurs, the subsequent problem location and maintenance are very difficult. Moreover, since the switching board, the second board card, and the first board card are all connected through the midplane, it will cause the overall volume of the server to be relatively large and the space occupancy rate to be relatively high. Summary of the Invention

[0005] This application provides a server and a server system to at least solve the problems in the related art that the switching board, the second board card, and the first board card are all connected through the midplane, the traces are complex and error-prone, and the overall volume of the server is relatively large.

[0006] This application provides a server, including: at least one first board card; a switching board group including a plurality of switching boards; a second board card group including a plurality of second board cards; and a midplane. Among them, the switching board and any one of the second board cards are orthogonal and pluggable, and at least one of the first board cards is connected to at least part of the second board cards through the midplane.

[0007] This application also provides a server system, including: the server according to any one of the above.

[0008] With this application, the orthogonal architecture of the switching board and the second board card enables their direct interconnection. The connection between the switching board and the second board card no longer requires routing through the midplane backplane, solving the problem of complex routing through the midplane backplane in the related art. Moreover, this orthogonal interconnection method increases the maximum allowable routing length on the switching board and the second board card. The routing complexity between the first board card and the second board card through the midplane backplane is controllable, and the connection through the midplane backplane can reduce the chassis volume in terms of space. Therefore, this solution reduces the routing complexity while also compressing the volume of the server chassis. Description of the Drawings

[0009] To more clearly illustrate the embodiments of this application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0010] Figure 1 Schematic diagram of the structure of a server provided by an embodiment of this application;

[0011] Figure 2 Schematic diagram of the connection between a second board card and a first board card through the midplane backplane provided by an embodiment of this application;

[0012] Figure 3 Schematic diagram of the position of the connectors of a second board card and a first board card on the midplane backplane provided by an embodiment of this application;

[0013] Figure 4 Another schematic diagram of the connection between a second board card and a first board card through the midplane backplane provided by an embodiment of this application;

[0014] Figure 5 Schematic diagram of the structure of a first housing including multiple second board cards provided by an embodiment of this application;

[0015] Figure 6 Schematic diagram of the structure of two second board cards included in a first housing provided by an embodiment of this application;

[0016] Figure 7 Another schematic diagram of the structure of a first housing including multiple second board cards provided by an embodiment of this application;

[0017] Figure 8 Schematic diagram of the structure of a second housing including multiple switching boards provided by an embodiment of this application;

[0018] Figure 9 Another schematic diagram of the structure of a second housing including multiple switching boards provided by an embodiment of this application;

[0019] Figure 10 A cross-sectional view of a plane where a connector provided by an embodiment of the present application contacts a printed circuit board;

[0020] Figure 11 A schematic diagram of the device layout design of an on-board solution switching board provided by an embodiment of the present application;

[0021] Figure 12 A schematic diagram of the trace connection of a switching board provided by an embodiment of the present application;

[0022] Figure 13 A high-speed signal link diagram constructed by a simulation software provided by an embodiment of the present application that only uses traces;

[0023] Figure 14 Based on the present application provided by an embodiment of the present application Figure 13 Schematic diagram of the simulation result;

[0024] Figure 15 A schematic diagram of the structure of a switching board provided by an embodiment of the present application;

[0025] Figure 16 A schematic diagram of the flying lead connection of a switching board provided by an embodiment of the present application;

[0026] Figure 17 A high-speed signal link diagram constructed by a simulation software provided by an embodiment of the present application that uses flying leads and traces;

[0027] Figure 18 Based on the present application provided by an embodiment of the present application Figure 17 Schematic diagram of the simulation result;

[0028] Figure 19 A fan-out schematic diagram of a flying lead connector provided by an embodiment of the present application;

[0029] Figure 20 A schematic diagram of the device layout of a flying lead connector solution switching board provided by an embodiment of the present application;

[0030] Figure 21 A schematic diagram of the pin correspondence of a connector between a second board and a switching board provided by an embodiment of the present application;

[0031] Figure 22 Another schematic diagram of the pin correspondence of a connector between a second board and a switching board provided by an embodiment of the present application;

[0032] Figure 23 A schematic diagram of the positive cross-connection relationship between a switching board and a second board provided by an embodiment of the present application;

[0033] Figure 24This is a schematic structural diagram of another server chassis provided by an embodiment of the present application.

[0034] 10. Switching board; 11. Switching chip; 12. First connector; 13. First relay chip; 14. First flying wire connector; 20. Second board; 21. Processor; 22. Second connector; 30. First board; 40. Middle backplane; 50. Bus bar; 60. First liquid cooling plate; 70. Second liquid cooling plate. Detailed implementation manners

[0035] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0036] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0037] To enable those skilled in the art of this technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0038] An embodiment of the present application provides a server, as Figure 1 shown, including: at least one first board; a switching board group including a plurality of switching boards 10; a second board group including a plurality of second boards 20; a middle backplane; wherein, the switching board 10 is orthogonal and pluggable to any second board 20, and at least one first board is connected to at least part of the second boards 20 through the middle backplane.

[0039] The above server can be applied to various types of communication devices. For example, the communication device can be an optical communication device, a router, a switch, etc. Of course, the server can also be applied to other types of communication devices, which is not limited herein. The first board is a control board including a controller (such as a CPU), and the second board is a device board including a processor (such as a GPU).

[0040] The switching board is one of the core components in network devices such as switches and routers, responsible for routing and forwarding data packets. It usually contains one or more switching chips (Switch Chip), which can identify, process, and redirect data packets to their destination addresses. The switching board also includes necessary peripheral circuits such as connectors, buffers, clock generators, etc., to transfer signals from the input ports to the switching chips, and then the switching chips output the signals to the correct destination ports.

[0041] In the field of network devices or servers, the second board card usually refers to the board card that carries terminal devices or loads. This includes but is not limited to storage devices, processor boards, I / O interface boards, etc. The second board card is orthogonally pluggable to the switching board through a connector, and through the switching board Ethernet, all device boards can achieve a full-interconnection topology to realize the exchange of data or instructions between the second board cards.

[0042] The first board card is the board card in the device used to monitor and control other hardware components. It is usually equipped with a microprocessor, a digital signal processor (DSP), a memory, and other control circuits. The function of the first board card is to execute the system management program, monitor the device status, and coordinate the communication and operation between various components. For example, the central processing unit (CPU) is a common type of first board card in a server, used to provide remote management functions and health monitoring.

[0043] The midplane is a key component in large network devices such as high-end routers and switches or server systems, used to connect multiple functional boards such as the second board card and the first board card. It provides the connection paths for signals and power between the boards. Its structure is complex and needs to support a large number of high-speed signal lines. The design of the midplane has a significant impact on signal integrity and system performance because it undertakes the task of carrying and routing a large number of high-speed and high-density signals, and at the same time, factors such as electromagnetic compatibility (EMC) and thermal management also need to be considered.

[0044] Since in the related technology, any two of the first board card, the switching board, and the second board card are connected through the midplane, the wiring is very complex. The above server realizes the direct interconnection between the switching board and the second board card through the orthogonal architecture of the switching board and the second board card. The connection between the switching board and the second board card no longer needs to pass through the midplane for wiring, solving the problem of complex wiring through the midplane in the related technology. And this orthogonal interconnection method increases the maximum allowable wiring length on the switching board and the second board card. The wiring complexity between the first board card and the second board card through the midplane is controllable, and through the connection of the midplane, the chassis volume can be reduced in space. Therefore, this solution reduces the wiring complexity while also compressing the volume of the server chassis.

[0045] Through the orthogonal architecture of the switching board and the second board, the direct interconnection of 112G high-speed links between two nodes is realized, the design of the mid-backplane is cancelled, and the maximum allowable routing length of the printed circuit boards of the switching board and the second board is increased, making the high-speed link design more simplified. The above cross-interconnection architecture can eliminate the optical backplane in the related technology, reduce the interconnection space between the switching board and the second board, facilitate the full utilization of the space within the subrack, and achieve the minimum design of the interconnection depth, increasing the available space between the switching board and the second board, enabling the switching board and the second board to integrate more functions. In addition, since the insertion loss of the optical cross-interconnection architecture is related to the number of nodes, the optical cross-interconnection architecture in the embodiments of the present application eliminates the optical backplane, and the switching board and the second board can be directly docked. Thus, the number of nodes is reduced, and the insertion loss of the optical cross-interconnection architecture in the embodiments of the present application is reduced. For example, the insertion loss can be reduced to about 1 dB.

[0046] Among them, the second board includes a processor, the first board includes a controller, the switching board includes a switching chip, the processor on the second board and the controller on at least one first board are communicatively connected through an interface communication protocol, the switching chip on the switching board and the processor on at least one second board are communicatively connected through an Ethernet protocol, and any two processors are communicatively connected through an Ethernet protocol.

[0047] That is, the processor on the second board and the controller on the connected first board communicate through the Peripheral Component Interconnect Express (PCIe) protocol, the switching chip on the switching board and the processor on the connected second board communicate through the Ethernet protocol and form a full-interconnection topology, and the full-interconnection topology is that any two processors communicate through the Ethernet protocol.

[0048] The controller can be a Central Processing Unit (CPU), and the processor can be a Graphics Processing Unit (GPU). In the above embodiments, the first board and the second board are connected through a backplane, so that the CPU on the first board and the GPU on the second board are communicatively connected through the Peripheral Component Interconnect Express (PCIe) protocol, and the switching chip on the switching board is connected to the OAM module in the second board through the Ethernet protocol, enabling the GPUs to form a full-interconnection topology to realize the interconnection networking among all GPUs.

[0049] A fully connected topology design can ensure the shortest communication path between any two processors, thereby reducing the latency of data transmission. In a fully connected architecture, there is no single bottleneck path, which means that data can be transmitted simultaneously in multiple directions, providing a higher total throughput. This is particularly important for GPU clusters that require a large amount of data exchange, as it can accelerate data processing and improve the performance of parallel computing. Since any two GPUs can communicate directly, resource scheduling becomes more flexible. In some deep learning scenarios, GPU resources can be dynamically allocated according to the needs of the algorithm, improving resource utilization efficiency. The direct communication between all GPUs allows for more efficient sharing of data and execution of collaborative tasks between parallel processing units, which is particularly beneficial for distributed computing and large-scale parallel computing tasks.

[0050] In addition, when the switching board and the second board cards are fully connected in the hardware design, the switching board can be controlled by software to only interconnect with a part of the second board cards, and the other part does not interconnect for communication. The software is controlled by the basic input / output system, and there is a BMC management module responsible for control on each switching board, and the switching board decides which part of the second board cards to interconnect with.

[0051] In some embodiments, such as Figure 2 , the first board card 30 is parallel to the extension direction of the second board card group, and at least one first board card 30 and the second board card group are arranged in sequence along the first direction ( Figure 2 the a direction in

[0052] ), and the first board card 30 and the second board card 20 are located on the same side of the switching board group. This way of placing both the first board card and the second board card on the same side of the switching board group can further save space and simplify the wiring on the midplane. If the first board card and the second board card are located on different sides of the switching board group, not only will more space be occupied, but also since the first board card and the second board card need to be connected through the midplane, the size of the midplane will increase accordingly, and the wiring on the midplane will be longer, which not only occupies the chassis space but also affects the integrity of signal transmission. Therefore, placing both the first board card and the second board card on the same side of the switching board group in the above embodiments can not only save the chassis space but also reduce the wiring length on the midplane, making the integrity of the transmitted signal higher.

[0053] Moreover, as Figure 2 shown, there is partial overlap between the orthographic projection of the midplane 40 and the switching board 10 on a preset plane, and the preset plane is a plane parallel to the extension direction of the switching board (such as Figure 2 the a direction in

[0054] ).Placing the midplane and switch board on the same side of the second card allows for more efficient use of space, further saving space. This structure eliminates the need for additional space, allowing the midplane to be placed directly within the original cubic structure without increasing the overall size of the chassis.

[0055] Further, such as Figure 2 As shown, the server further includes a bus bar 50, which is connected to the cooling device (not shown) on each second board 20. The mid-backplane 40 is located between the bus bar 50 and the switch board 10. The orthographic projections of the mid-backplane 40, the bus bar 50, and the switch board 10 on the preset plane partially overlap. The preset plane is parallel to the extension direction of the switch board (e.g., Figure 2 A plane parallel to the a direction in the middle.

[0056] The cooling device is a device on the second card that cools heat-generating components (such as GPUs). This device lowers the temperature of the heat-generating components through the flow of coolant. The busbar, on the other hand, collects the coolant from multiple second cards, allowing the coolant to flow through the busbar, cooling the coolant and circulating it around the heat-generating components on the second cards. Furthermore, placing the midplane in the gap between the busbar and the switch board optimizes space utilization without increasing the overall size of the chassis.

[0057] In some embodiments, such as Figure 2 As shown, all the first boards 30 are located on the first side or the second side of the second board group; or, a portion of the first boards 30 are located on the first side of the second board group, and another portion of the first boards 30 are located on the second side of the second board group, and the first side and the second side are opposite sides.

[0058] Among them, such as Figure 2 As shown, the server further includes a plurality of first shells ( Figure 2 (not shown), a first housing includes at least one second board 20.

[0059] Since the second boards need to be orthogonal to the switch board via connectors, arranging all the second boards closely together (i.e., forming a second board group) allows for a more compact arrangement of the connectors on the second boards, thus saving space for the connectors on the second boards. If a first board is installed between multiple second boards and is not connected to the switch board, the area on the switch board where the first board resides will need to be left empty. This will increase the spacing between the two connectors, making the second boards longer, which will take up unnecessary space and reduce space utilization. Therefore, the above embodiment, placing the second boards in the center and the first boards to the side, is the most space-efficient arrangement.

[0060] In some embodiments, such as Figure 2As shown, the number of the first boards 30 located on the first side of the second board group is equal to the number of the first boards 30 located on the second side of the second board group.

[0061] Among them, in the case where there are multiple first boards, splitting them into two parts and setting them on both sides of the second board respectively is also the most space-saving and routing-friendly setting. Splitting the first boards into two parts and setting them on both sides of the second board respectively can enable the first boards on both sides to be connected to the second boards closer to them respectively. In this way, the routing length on the midplane will be greatly reduced, simplifying the routing on the midplane and reducing the mutual interference between the routings.

[0062] Taking the example that there are four first boards and eight second boards, the positions of the connectors between the second boards and the first boards on the midplane are as Figure 3 shown. Among them, the first first board is connected to the first second board and the second second board through routing, the second first board is connected to the third second board and the fourth second board through routing, the third first board is connected to the fifth second board and the sixth second board through routing, and the fourth first board is connected to the seventh second board and the eighth second board through routing. In this way, the first boards are distributed on both sides, and the first boards control the second boards closer to them, which can make the wiring on the midplane more compact and orderly, increase the wiring density, reduce the wiring complexity, can reduce the occurrence of errors, and the routing lengths on the midplane are more balanced, without the situation that some routings are very short and some routings are very long. Each first board needs to be connected to 2 second boards. The first boards are evenly placed on both sides, which can not only make the PCB (printed circuit board) routings on the midplane symmetrically distributed, but also make the second boards gather together and orthogonally plug into the switching board.

[0063] Figure 3 In the embodiment shown, each first board has one connector interconnected with the midplane. Through the routings on the midplane, the connector can be divided into two parts of pins, that is, one part is connected to one second board and the other part is connected to another second board. In some embodiments, the first board can also be provided with 2 connectors, each first board has 2 connectors interconnected with the midplane, and each second board has 1 connector interconnected with the midplane.

[0064] In addition to the structure of the above embodiments, there is another positional relationship between the second board and the first board, as Figure 4 shown. The switching board 10 is located on the first side of the second board 20, and the first board 30 is located on the second side of the second board 20, and the first side and the second side are opposite sides.

[0065] As Figure 4 shown, a first housing ( Figure 4not shown) includes a first board 30, a mid-backplane 40, and at least one second board 20. The first board 30 in a first housing is connected to all the second boards 20 in the first housing through the mid-backplane 40.

[0066] In the above embodiment, the first board and the second boards it controls are integrated in a first housing, and then the first housing is used as a whole to achieve the plug-in connection with the switching board.

[0067] One first housing can be installed with one first board and one or more second boards, or one first housing can also be installed with multiple first boards and multiple second boards, that is, one first board is connected to multiple second boards, or one first board is only connected to one second board. Among them, the CPU in the first board is responsible for coordinating and allocating tasks to the GPUs in the second boards in the same first housing. The number of the first board and the second boards in the same first housing is related to their respective performances. The CPU communicates with the GPU through the PCI Express (PCIe) bus. Therefore, the number of PCIe slots on the motherboard directly determines the number of GPUs that the CPU can directly control. However, in some high-end servers or workstations, a bridge chip or a PCIe switch can be used to increase the number of GPU connections. The performance of the CPU (such as the number of cores, cache size, bus bandwidth, etc.) will also affect how many GPUs it can effectively control. A more powerful CPU can manage more concurrent tasks, thus supporting the simultaneous processing of more GPUs. For example: If there are two second boards in a first housing and the CPU has good performance, then only one first board is needed to control these two second boards. If the CPU has poor performance, then two first boards need to be installed in this first housing to control these two second boards respectively. Connecting one first board to multiple second boards through the backplane can make the wiring more flexible.

[0068] Inside the same first housing, the communication between the CPU and the GPU can be achieved through a shorter distance, thereby significantly reducing the latency of data transmission and improving the response time and processing speed of the system. The CPU and the GPU integrated in a first housing can communicate directly through a high-speed connection (such as PCIe Gen4 or Gen5), providing higher data bandwidth. Integrating the CPU and the GPU into a first housing can simplify the system architecture and wiring, reduce the number of required cables and connectors, thereby reducing the system complexity and improving the reliability and maintainability.

[0069] In some embodiments, such as Figure 5 shown, multiple second boards 20 are located in the same first housing, and the multiple second boards 20 in the same first housing are arranged along the first direction (such as Figure 2arranged in the a direction), and there is a first liquid cooling plate between two second board cards 20 in the same first housing ( Figure 5 not shown in the figure), and the first direction is the same as the arrangement direction of the connectors of an exchange board.

[0070] Setting multiple second board cards in one first housing can increase the device compactness of the overall system and reduce space occupation. If multiple second board cards are respectively arranged in multiple first housings, more space will be occupied. However, setting multiple second board cards in one first housing reduces the number of first housings, saves costs, and further saves space and improves device density.

[0071] Figure 5 It is an example diagram of a first housing including two second board cards. As Figure 5 shown, two second board cards 20 are included in the same first housing. The processor of one second board card 20 is the first processor, and the processor of the other second board card 20 is the second processor. The first liquid cooling plate is located between the first processor and the second processor.

[0072] Since there are two second board cards 20 in one first housing and the two second board cards 20 are relatively close in the same first housing, resulting in poor heat dissipation, a first liquid cooling plate is added between the two second board cards 20 for simultaneously dissipating heat from the two second board cards. And the two second board cards 20 in the same first housing are arranged oppositely, that is, the sides of the two second board cards 20 where the GPUs are installed are in contact with the first liquid cooling plate, which can better cool the heat-generating component GPU.

[0073] Figure 6 It is a cross-sectional view of two second board cards in one first housing. As Figure 6 shown, the first second board card and the second second board card in one first housing are arranged oppositely, and a first liquid cooling plate 60 is arranged in the middle. In the figure, J1, J2, J3, J4, J5, and J6 are respectively the connectors on the second board cards for positive interconnection with the exchange board. The first liquid cooling plate 60 is arranged in the middle of the two second board cards to dissipate heat from the GPUs, power modules, heat sources such as logic management control chips, etc. on the second board cards. There are 6 orthogonal high-density connectors from left to right on each second board card. It can be seen from the figure that the two second board cards are arranged oppositely and in reverse. Since the second board cards need to be positively interconnected with the exchange board, the connectors of the two second board cards need to be on the same side. And in order to achieve better heat dissipation effect, the sides of the two second board cards where the GPUs are installed need to face the liquid cooling plate. Therefore, the installation positions as Figure 6 shown are designed. If there are multiple second board cards in one first housing, liquid cooling plates are installed between adjacent two second board cards.

[0074] If a first housing includes multiple second daughter cards, there can be other installation positions, such as Figure 7 As shown, multiple second daughter cards 20 are located in the same first housing, and the multiple second daughter cards 20 in the same first housing are arranged in parallel along the second direction ( Figure 7 direction b in the figure), and the second direction is the same as the arrangement direction of the connectors of one second daughter card.

[0075] This can be applied to some scenarios where the second daughter cards do not need to be connected to all switching boards. In a large system, if each GPU is interconnected with all switching boards, the communication network will become extremely complex, resulting in increased difficulty in management and maintenance, as well as increased communication latency and potential bit error rate. And this installation method of the second daughter cards can reduce the interconnection range, simplify the architecture of the communication network, reduce the complexity of the communication links, thereby reducing latency and improving the reliability of communication. The full-interconnection architecture requires a large number of high-speed connectors, cables, and complex backplane designs, all of which will increase the hardware cost of the device. Under the condition of meeting the application requirements, adopting Figure 7 this structure, some of the second daughter cards are only interconnected with some of the switching boards, which can significantly reduce the required high-speed interconnection components and reduce the hardware cost. In the case where full interconnection is not required, the installation structure of Figure 7 can be adopted. Limiting the interconnection range of the GPUs can avoid unnecessary data transmission, reduce communication overhead, and thus improve the overall efficiency and performance of the system.

[0076] Based on the structure of the second daughter cards in the first housing in the above embodiments, by the same principle, the switching boards can also have various installation methods, such as Figure 8 As shown, the server includes multiple second housings, one second housing includes multiple switching boards 10, and the multiple switching boards 10 are stacked along the second direction ( Figure 8 direction b in the figure), a second liquid cooling plate 70 is arranged between two adjacent switching boards 10, and the arrangement order of the connectors of two adjacent switching boards 10 is opposite.

[0077] Figure 8FIG. 0 is an exemplary diagram of a second housing including two switching boards 10. Since two switching boards 10 are included in one second housing, the two switching boards 10 will face the problem of poor heat dissipation due to the close distance in the same second housing. Therefore, a second liquid cooling plate 70 is added between the two switching boards 10 for simultaneously dissipating heat from the two switches. And the two switching boards 10 in the same second housing are arranged oppositely, that is, the sides of the two switching boards 10 where the switching chips are installed are in contact with the second liquid cooling plate 70, which can better cool the heat-generating component, the switching chip. Moreover, arranging the two switching boards 10 in one second housing can increase the overall device compactness of the system and reduce the space occupation. If the two switching boards 10 are respectively arranged in two second housings, the two switching boards 10 need to be located in two second housings respectively, which will occupy more space. While arranging the two switching boards 10 in one second housing saves the space of one second housing, further saving space and increasing the device density.

[0078] If a second housing includes multiple switching boards 10, there can be other installation positions, such as Figure 9 As shown, a second housing includes multiple switching boards 10, and the multiple switching boards 10 are arranged in parallel along the first direction ( Figure 9 direction a in FIG.).

[0079] This can be applicable to scenarios where some switching boards do not need to be connected to all second boards. In a large system, if each GPU is interconnected with all switching boards, the communication network will become extremely complex, resulting in increased difficulty in management and maintenance, as well as increased communication latency and potential bit error rate. And this installation method of the switching board can reduce the interconnection range, simplify the architecture of the communication network, reduce the complexity of the communication link, thereby reducing latency and improving the reliability of communication. The full-interconnection architecture requires a large number of high-speed connectors, cables, and complex backplane designs, all of which will increase the hardware cost of the device. Under the condition of meeting the application requirements, adopting Figure 9 such a structure, where some switching boards are only interconnected with some second boards, can significantly reduce the required high-speed interconnection components and reduce the hardware cost. In the case where full interconnection is not required, the Figure 9 installation structure can be adopted to avoid unnecessary data transmission, reduce communication overhead, and thus improve the overall efficiency and performance of the system.

[0080] In some embodiments, the switching board has a first connector, and the number of rows of the pins of the first connector is greater than the number of layers of the traces on the switching board.

[0081] Generally, one pin of the first connector leads out a pair of differential signals. If the first connector has M rows, then a column of pins of the first connector will lead out M pairs of differential signals, and each pair of differential signals is distributed on different layers of the switching board.

[0082] In the above embodiments, the number of rows of pins of the first connector is greater than the number of layers of traces on the switching board, which greatly reduces the number of layers of traces on the switching board, reduces the thickness of the switching board, further saves space, and reduces the chassis size.

[0083] The number of rows of pins of the first connector exceeding the number of layers of traces on the switching board means that more signal fan-outs can be achieved on fewer PCB layers. This increases the signal transmission density, enabling the switching board to handle a larger amount of data flow within a limited physical space, which is crucial for high-bandwidth communication. When the number of rows of pins of the first connector is greater than the number of layers of traces, the signals can be more efficiently distributed onto fewer layers, reducing the signal traces for inter-layer conversion, thereby reducing signal insertion loss and improving signal quality.

[0084] In some embodiments, the number of rows of pins of the first connector is an integer multiple of the number of layers of traces on the switching board.

[0085] Setting the number of rows of pins of the first connector as an integer multiple of the number of layers of traces can ensure that the signals are evenly distributed on each layer. This helps to optimize the signal layout, reduce the mutual interference between signal lines, and improve signal integrity. With an integer multiple of the number of rows of pins, efficient signal fan-out can be achieved, meeting the requirements of high-density signal transmission even within the limited area of the switching board, thereby increasing the overall communication bandwidth and data processing capacity. This design allows for more orderly and simplified signal routing on the PCB layer, reducing complex corners and inter-layer traces, which helps to reduce signal delay and loss and improve signal quality.

[0086] Specifically, the switching board has a first connector. There is a gap between any two adjacent rows of solder joints on the switching board that are soldered to the first connector. There are traces in at least one of the gaps. One end of the trace is connected to the pin of the first connector, and the other end of the trace is connected to the switching chip on the switching board.

[0087] Among them, the second board also has a second connector, and the first connector and the second connector are the same connector. Figure 10 is a top view of a printed circuit board, that is Figure 10 shown is a cross-sectional view of the plane where the connector contacts the printed circuit board, as Figure 10 shown, the switching board and the second board are connected through the connector. For the switching board, Figure 10 A in is the solder joint on the switching board that is soldered to the first connector, and B1, B2, B3, and B4 are the traces on the switching board respectively; for the second board, Figure 10 A in is the solder joint on the second board that is soldered to the second connector, and B1, B2, B3, and B4 are the traces on the second board respectively.

[0088] Among them, the above connector is an orthogonal high-density connector. For the signal fan-out routing at the orthogonal high-density connector, 16 pairs of differential signals are routed out on each layer, and a total of 4 signal layers are required. There are two rows of signals distributed on each layer. Compared with the traditional high-density connector where only one pair of differential lines can be routed out in one column per layer, the pin layout of this high-density connector has upper and lower parts, and the empty area in the middle enables two pairs of differential lines to be routed out in one column per layer. The routing layer occupied by the connector routing is reduced by half, which can greatly improve the routing density. Figure 10 The signal lines of the same color are on one layer, and the signal lines of different colors are represented by different grayscales.

[0089] For example, if the second circuit board is Figure 6 the structure in (i.e., two second circuit boards are included in one first housing), to install two second circuit boards in one first housing, it is necessary that the second circuit board is as thin as possible in design. At this time, the pin layout and solder joint layout of the orthogonal high-density connector shown in Figure 10 can be adopted. This pin layout will reduce the number of routing layers on the circuit board, so the thickness of the circuit board will be reduced, that is, the thickness of the second circuit board will be reduced. Similarly, when the switching board adopts Figure 8 the structure in (i.e., two switching boards are included in one second housing), the pin layout of the orthogonal high-density connector shown in Figure 10 can also be adopted to reduce the thickness of the switching board.

[0090] Preferably, there are N rows of solder joints on the switching board, and there is routing between the N / 2-th row of solder joints and the N / 2 + 1-th row of solder joints. That is, the two parts of the solder joints with intervals on the switching board are evenly distributed. The pins of the first connector have the same layout as the solder joints on the switching board. In addition, the solder joints of the second circuit board and the pins of the second connector can also be as shown above.

[0091] This evenly distributed solder joint distribution on the circuit board leaves an empty area in the middle, enabling two pairs of differential lines to be routed on each layer instead of the traditional one pair. This directly reduces the requirement for the number of layers of the PCB (printed circuit board), thereby reducing the complexity and cost of the circuit board. At the same time, reducing the routing layer also means reducing potential routing errors and improving the production yield. The pin layout with upper and lower equal division and an empty area in the middle can reduce the influence of electromagnetic interference and improve the electromagnetic compatibility of the system by reasonably arranging the positions of signal lines and ground lines.

[0092] Differential signals are a commonly used signal transmission method, especially in the fields of high-speed data transmission and precision electronic communication. A differential signal pair consists of two traces (or pins) that transmit the positive and inverted signals respectively. This signal transmission method can effectively reduce electromagnetic interference (EMI), improve signal integrity, and noise immunity. Pin equalization helps to ensure the symmetry of the differential pair. In connector design, the trace lengths, characteristic impedances, and routing paths of the differential pair should be as consistent as possible to ensure signal integrity and reduce signal distortion. A pair of traces of the differential signal need to be close to each other to maintain the differential characteristics of the signal, but at the same time, they are also vulnerable to interference from adjacent signal traces. The up-and-down equalized pin layout effectively isolates adjacent differential pairs through the vacant area in the middle, reduces crosstalk between signals, and improves signal quality.

[0093] Moreover, without increasing the number of connector layers, the equalized pin distribution can achieve double differential pair routing. This not only reduces the required number of PCB layers, but also optimizes the routing path, improves the routing density, and the space utilization rate of the circuit board.

[0094] In some embodiments, the connector of the switching board is the first connector, and the connector of the second board is the second connector. The switching board further includes a switching chip, and the second board further includes a processor. The switching chip is electrically connected to the first connector by means of traces, or the switching chip is first connected to the first flying wire connector by means of traces and then connected to the first connector by means of flying wires. The processor is electrically connected to the second connector by means of traces, or the processor is first connected to the second flying wire connector by means of traces and then connected to the second connector by means of flying wires. Among them, the channel operating margin for the high-speed signal to be transmitted from the switching chip to the processor is greater than a preset margin, and the preset margin is the minimum margin when the integrity of the high-speed signal transmitted from the switching chip to the processor is greater than or equal to a preset integrity.

[0095] The first connector (or the second connector) can be: various types of connectors such as an MT fiber optic connector, a multi-core multi-channel pluggable (MPO) fiber optic connector, or an LC type fiber optic connector. In practical applications, the first connector (or the second connector) can be fastened to the printed circuit board (PCB) or the optical component of the switching board (or the second board) by screws. Alternatively, other methods can also be used to fix the first connector or the second connector, which is not limited herein.

[0096] The Channel Operating Margin (COM) is a metric used to evaluate the performance of a signal link in the field of high-speed digital signal transmission. It reflects the reliability and stability of signal transmission in the signal link, especially in terms of signal integrity. The definition of COM is based on the transmission characteristics of the signal link, usually including factors such as signal attenuation, reflection, crosstalk, and noise. It represents the difference between the actual performance of the signal in the signal link and the minimum performance requirements of the link, or the additional margin that the signal link has under the premise of ensuring signal integrity. The higher the COM value, the more reliable the performance of the signal link, the better the stability of signal transmission, and the higher the tolerance to various environmental changes and signal interferences. When designing a high-speed signal link, engineers usually set a minimum COM value to ensure that the signal link can still meet the performance requirements under the worst conditions. When the COM value is lower than this threshold, the performance of the signal link may become unreliable, and even transmission errors may occur.

[0097] By controlling the trace lengths on the switching board and the second board card, the signal consumption can be reduced, ensuring that the channel operating margin of the high-speed signal is greater than the preset margin and guaranteeing signal integrity. In cases where the trace lengths cannot ensure that the channel operating margin of the signal is greater than the preset margin, a flying lead connector can be considered and the signal can be transmitted in the form of a flying lead.

[0098] By controlling the length of the signal path, using flying lead connectors, and optimizing the trace design, signal attenuation and distortion can be reduced, thereby improving signal integrity. Improving signal integrity means fewer bit error rates and higher data transmission quality, which is crucial for high-speed data transmission applications. The use of flying lead connectors can reduce the trace length of the signal on the PCB, thereby reducing the signal transmission delay. In scenarios such as high-performance computing and network communication, reducing the delay can significantly improve the system's response speed and processing efficiency. Optimizing the signal transmission path helps reduce the energy loss during signal transmission, thereby reducing the overall power consumption of the system. This is particularly important for scenarios such as data centers and cloud computing that require high performance and low power consumption. Ensuring that the channel operating margin of high-speed signal transmission is greater than the preset margin means that the system has a greater tolerance to various interferences and noises, improving the stability and reliability of the system. By using the first flying lead connector and the second flying lead connector, system designers can flexibly select the signal transmission path according to actual needs, either directly connected or connected through a flying lead, which increases the flexibility and scalability of the system architecture. Reducing the trace length and optimizing the signal path helps simplify the circuit board design, reduce the complexity of the PCB layer, reduce potential wiring conflicts, make the design process more efficient, and at the same time reduce the production cost.

[0099] Figure 11Schematic diagram of the device layout of the on-board solution for the switch board, as Figure 11 shown. The switch board 10 includes a first connector 12, a switch chip 11, a power input connector, a Serial Gigabit Media Independent Interface network management signal input connector (referred to as SGMII network management signal input connector), a chip power supply, a Baseboard Management Controller (referred to as BMC management module), and a Complex Programmable Logic Device (referred to as CPLD). All the orthogonal high-density connectors (the first connector) of the switch board adopt the on-board solution. One switch chip corresponds to 8 orthogonal high-density connectors. Each orthogonal high-density connector can transmit 2 groups of 112G high-speed signals of X16 Lane. The signal connection between the switch chip and the orthogonal high-density connector is realized through PCB copper traces. The signal path is as shown by the lines in the appendix Figure 11 .

[0100] The SGMII signal input connector is interconnected with the network management board inside the all-in-one machine to provide an out-of-band management network signal. The power input connector provides 12V power supply for the whole board. The CPLD is used for the hardware control, management, and coordination of the SW chip, monitors the status of the switch chip, and controls the power-on and power-off sequence of the switch chip. The BMC management module provides in-node management signals and status detection, is mainly used for remote access management and maintenance, and records system logs for engineers to analyze.

[0101] In some embodiments, as Figure 12 shown, the switch board 10 has a switch chip 11 and a first connector 12. The second board 20 includes a processor 21 and a second connector 22. The switch chip 11 and the first connector 12 are connected through a first trace. The processor 21 and the second connector 22 are connected through a second trace. The sum of the lengths of the first trace and the second trace is less than or equal to a first preset length. The first preset length is the minimum trace length that enables the channel operation margin of the high-speed signal transmitted from the switch chip 11 to the processor 21 to be greater than the preset margin. Among them, the preset margin is the minimum margin when the integrity of the high-speed signal transmitted from the switch chip 11 to the processor 21 is greater than or equal to the preset integrity.

[0102] By controlling the length of the first trace between the switching chip and the first connector, and the length of the second trace between the processor and the second connector, ensure that the sum of the lengths of these two traces is less than or equal to a preset maximum length (the first preset length). Limiting the sum of the trace lengths can reduce the attenuation and distortion of the signal during transmission, thereby ensuring signal integrity. Longer traces will increase the insertion loss of the signal, resulting in a smaller eye diagram and affecting the signal's recognizability and signal-to-noise ratio. By controlling the trace length, the margin of the signal at the receiving end can be maintained, ensuring the stability and reliability of the signal. The Channel Operating Margin (COM) is a key indicator for measuring the performance of the signal link, which reflects the margin of the signal link under the condition of ensuring the minimum received level. The above solution ensures that the sum of the trace lengths does not exceed the first preset length, making the COM of the high-speed signal transmitted from the switching chip to the processor greater than the preset margin, which guarantees the stable operation of the signal link under various working conditions and meets the design and specification requirements. The trace length directly affects the signal transmission delay. Shorter trace lengths help reduce the signal transmission time, which is crucial for applications that require low latency characteristics (such as high-performance computing and real-time data processing). The signal transmission on the trace will be accompanied by a certain amount of energy loss, and longer traces will increase the power consumption. By controlling the trace length, the energy loss during signal transmission can be reduced, which helps to lower the overall power consumption of the system. Limiting the trace length helps to simplify the circuit board layout design, reduce the complexity of the interlayer traces, and improve the design efficiency and manufacturability. Reducing the trace length can reduce the failure rate of the signal link and improve the overall reliability of the system. Shorter traces are less affected by external interference and crosstalk within the circuit board, which helps to ensure stable signal transmission. Shorter traces help to reduce electromagnetic radiation and lower the electromagnetic interference inside and outside the system, which is very important for meeting electromagnetic compatibility standards and reducing interference between systems.

[0103] For the 112G high-speed signal, the interconnection scheme design of the signal link is as shown in the appendix Figure 12 as follows. The signal sending end is the switching chip 11. After passing through the PCB trace with a length of 10 inches on the switching board 10, it enters the pin of the first connector 12 located at the edge of the switching board. After the orthogonal plug-in interconnection of two high-density connectors (the first connector 12 and the second connector 22), it enters the PCB trace on the second board 20 with a length of 19 inches, and finally enters the processor 21.

[0104] For the above 112G high-speed signal, build a link in the simulation software and perform COM simulation. The built simulation link is as shown in the appendix Figure 13 as follows. The simulation results are as shown in the appendix Figure 1\4As shown. The simulation results show that when the trace length on the switching board is 10 inches and the trace length on the second board is 19 inches, the channel operating margin value is 3.388 dB, which is already close to the critical value of 3 dB. Therefore, through simulation experiments, it can be obtained that when the trace length on the switching board is 10 inches and the trace length on the second board is 19 inches, it is the maximum trace length. Therefore, the first preset length can be set to 29 inches, and the preset margin is 3 dB.

[0105] In some embodiments, such as Figure 15 As shown, the switching board 10 has a switching chip 11, a first connector 12, and a first relay chip 13. The switching chip 11 is connected to the first relay chip 13 through a first sub-trace, and the first relay chip 13 is connected to the first connector 12 through a second sub-trace. The first relay chip 13 is used to enhance the signal strength of the high-speed signal. Among them, the sum of the length of the first sub-trace and the length of the second sub-trace is greater than the second preset length, and the first preset length is greater than the second preset length.

[0106] When the high-speed signal is transmitted from the switching chip to the connector, if the total trace length of the signal link exceeds a certain limit (the first preset length), so that the channel operating margin (COM) of the signal cannot meet the requirements of the preset margin, it is particularly important to introduce the first relay chip as a signal enhancement link. When the high-speed signal is transmitted from the switching chip to the connector, if the total trace length of the signal link exceeds a certain limit (the first preset length), so that the channel operating margin (COM) of the signal cannot meet the requirements of the preset margin, it is particularly important to introduce the first relay chip as a signal enhancement link. Through the relay chip, signal distortion and eye diagram closure can be reduced, and the control accuracy of the signal rise time and fall time can be improved, thereby improving signal integrity and ensuring high-quality transmission of the signal under high-speed transmission conditions. The use of the relay chip overcomes the signal attenuation problem caused by the trace length limit (the second preset length), enabling the signal to maintain good performance over a longer distance, providing greater flexibility and a wider application range for system design. In Figure 15 In the embodiment shown, the sum of the lengths of the first sub-trace and the second sub-trace is greater than the second preset length, which means that even if the total trace length exceeds the limit without using the relay chip, the signal can still maintain the required COM because the role of the relay chip compensates for signal attenuation, enabling the link to meet the signal integrity requirements over a longer distance. The relay chip can re-time the signal, reduce delay fluctuations, and ensure the transmission stability of the signal under different temperature and voltage conditions, which is particularly important for applications that require precise timing control. Through signal enhancement and delay adjustment, the relay chip improves the robustness of the system and reduces the impact of the signal link's sensitivity to environmental conditions, enabling stable performance even in harsh working environments.

[0107] Based on the simulation results, when the PCB traces on the switching board exceed 10 inches, or when the PCB traces on the second board exceed 19 inches, the operating margin of the channel is insufficient, and there is a risk of link signal transmission errors. At this time, a first relay chip needs to be added between the switching chip and the first connector to ensure the integrity of high-speed signals. Therefore, the second preset length is 10 inches.

[0108] In some embodiments, the second board further includes a second relay chip. The processor is connected to the second relay chip through a third sub-trace, and the second relay chip is connected to the second connector through a fourth sub-trace. The second relay chip is used to enhance the signal strength of the high-speed signal. Among them, the sum of the lengths of the third sub-trace and the fourth sub-trace is greater than a third preset length, and the first preset length is greater than the third preset length.

[0109] In the above embodiments, the second board introduces a second relay chip, which is connected to the processor through a third sub-trace and then to the second connector through a fourth sub-trace. This design adds a link for signal enhancement and processing to the signal transmission path. Especially when the sum of the lengths of the third sub-trace and the fourth sub-trace exceeds the third preset length, and the first preset length is greater than the third preset length, it means that the direct connection path length (the first preset length) from the switching chip to the first connector can be longer. However, at the second board end, the signal needs additional signal processing after a longer distance of transmission (the third preset length).

[0110] The main function of the second relay chip is to enhance the signal strength. In high-speed signal transmission, the signal gradually attenuates as the transmission distance increases. The relay chip can compensate for this attenuation to ensure that the signal has sufficient strength when it reaches the processor to meet the requirements of the receiving sensitivity. The relay chip not only enhances the signal but also improves the signal integrity. It can re-time the signal, reduce the delay and delay variation caused by the trace length, and reduce signal distortion such as eye diagram closure and signal reflection, thereby improving the signal quality. When the total length of the third sub-trace and the fourth sub-trace exceeds the third preset length, it means that the transmission distance of the signal inside the second board is relatively long, which is particularly important in a system with limited physical size. The use of the relay chip ensures that even in long-distance transmission, the signal can still meet specific performance standards. The presence of the relay chip allows designers to have greater freedom in the wiring design. Especially in the case of limited PCB layout, longer trace paths can be used without worrying about the degradation of signal quality. The relay chip can reduce the impact of electromagnetic interference (EMI) on the signal, especially in the case of longer traces and higher environmental noise. Through signal shaping and re-timing, the radiation of the signal and the interference to adjacent signals can be reduced. The enhancement of signal strength and the improvement of signal integrity directly improve the reliability of the system in high-speed data transmission, reduce the bit error rate, and ensure the accurate transmission of data.

[0111] According to the simulation results, when the PCB traces on the switching board exceed 10 inches, or the PCB traces on the second board exceed 19 inches, the operating margin of the channel is insufficient, and there is a risk of link signal transmission errors. At this time, a second relay chip needs to be added between the processor chip and the second connector to ensure the integrity of the high-speed signal. Therefore, the third preset length can be set to 19 inches.

[0112] Similarly, in addition to adding the first relay chip between the switching chip and the first connector to ensure the integrity of the high-speed signal, a second relay chip can also be added between the second board and the second connector to ensure the integrity of the high-speed signal. In some embodiments, if the traces are too long and the signal is prone to transmission errors, it can be considered to add both the first relay chip between the switching chip and the first connector and the second relay chip between the second board and the second connector to ensure the integrity of the high-speed signal, or multiple first relay chips can be added between the switching chip and the first connector, and multiple second relay chips can be added between the second board and the second connector, which are all optional settings.

[0113] In addition, if the solution of using on-board orthogonal high-density connectors is adopted for the entire switching board, problems such as too long PCB traces, excessive link loss, and reduced eye diagram will occur. Adding a relay chip requires additional space. Therefore, another solution is to use in-board wire jumpers. Fly-line connectors are arranged around the switching chip, so that the traces inside the PCB board can be controlled within 3 inches. The fly-line connectors are interconnected with the orthogonal high-density connectors (the first connectors) on the board-edge structure parts through cables. In this way, the loss of the entire link can meet the specification requirements, and there is no need to add relay chips anymore.

[0114] In some embodiments, as Figure 16 shown, the switching board 10 has a switching chip 11, a first fly-line connector 14, and a first connector 12. The switching chip 11 is connected to the first fly-line connector 14 through a third trace, and the first fly-line connector 14 is connected to the first connector 12 through a first cable.

[0115] The first fly-line connector 14 is introduced into the switching board 10 and is connected to the switching chip 11 through a third trace and then to the first connector 12 through a first cable. By using fly-line connectors and cables, the signal path can directly skip the long PCB traces from the switching chip and directly reach the connector. This reduces the trace length of the signal on the PCB board, helps reduce the insertion loss and reflection of the signal, thereby improving signal integrity. The insertion loss of the cable is usually lower than that of the PCB trace, especially in high-speed signal transmission. Therefore, using cables instead of some PCB traces can reduce signal attenuation and ensure that the signal still maintains sufficient strength during long-distance transmission. The use of fly-line connectors can reduce the propagation of signals between complex PCB layers, thereby reducing the time delay and improving signal transmission efficiency, which is crucial for real-time and high-bandwidth applications. The introduction of fly-line connectors simplifies the routing design of the circuit board, reduces the complexity of inter-layer traces, reduces the design difficulty and production cost, and at the same time improves the yield and reliability of the circuit board. The use of cables provides additional flexibility for the signal link, allowing designers to connect different devices through cables under the condition of limited physical space to achieve a more optimized layout. Reducing the PCB trace length helps reduce the heat source around the signal line, improves the thermal management of the switching board, and reduces the demand for complex heat dissipation systems. Fly-lines and cables usually have better shielding performance, can reduce electromagnetic radiation during signal transmission, reduce EMI, and improve the signal purity within the system.

[0116] The design of the 112G high-speed signal link is as shown in the appendix Figure 16As shown in the figure. The signal transmitting end is the switching chip 11. After passing through the 2.5-inch PCB trace on the switching board 10, it enters the first flying lead connector 14 around the switching chip 11. From the first flying lead connector 14, it passes through a first cable with a length of 0.54 m and a wire diameter of 32 AWG, and is connected to the first connector 12 on the side node chassis structure of the switching board 10. After the first connector 12 and the second connector 22 are orthogonally inserted and interconnected, it enters the PCB trace on the second board 20 with a length of 19 inches, and finally enters the processor 21.

[0117] Build a link in the simulation software and perform simulation evaluation on this 112G high-speed signal link. The link construction of the second embodiment is as shown in the appendix Figure 17 As shown. The COM simulation results are as shown in the appendix Figure 18 As shown. The simulation results show that when the length of the PCB trace on the switching board is 2.5 inches, the length of the first cable of the first flying lead connector is 0.54 m, and the length of the PCB trace on the second board is 19 inches, the channel operating margin value of the link is 3.024 dB, meeting the design requirements.

[0118] Among them, the fan-out example of the flying lead connector is as shown in the appendix Figure 19 As shown. Each layer of the flying lead connector outputs 4 pairs of differential lines, and a total of 4 signal layers are required. Among them, RX is the received signal, and TX is the transmitted signal, that is, RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8 are the first received signal, the second received signal, the third received signal, the fourth received signal, the fifth received signal, the sixth received signal, the seventh received signal, and the eighth received signal respectively; TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8 are the first transmitted signal, the second transmitted signal, the third transmitted signal, the fourth transmitted signal, the fifth transmitted signal, the sixth transmitted signal, the seventh transmitted signal, and the eighth transmitted signal respectively.

[0119] The schematic diagram of the layout scheme of the flying lead connector on the switching board is as shown in the appendix Figure 20 As shown, 16 orthogonal high-density connectors are fixed on the structural member on the left side of the switching board, and there are 32 flying lead connectors around each switching chip in the board, that is, the cables of 4 flying lead connectors are connected to 1 orthogonal high-density connector (the first connector). As Figure 20 As shown, there are 16 orthogonal high-density connectors (the first connectors), chip power supplies and motherboard management controllers (referred to as BMC management modules), central processors and memory module controllers (referred to as CPU + memory module controllers), power supply modules of switching chips, power conversion modules, and 32 flying lead connectors around each switching chip on the switching board.

[0120] In some embodiments, a switching chip is connected to a first number of first flying lead connectors, and a first connector is connected to a second number of first flying lead connectors, where the first number is greater than the second number.

[0121] This configuration allows the switching chip to fan out high-speed signals in multiple directions simultaneously, increasing the signal transmission paths and capacity. The first connector, as the signal concentration point, receives signals from multiple flying lead connectors. This design helps to achieve efficient signal distribution and collection, especially suitable for scenarios requiring high-density signal transmission. Since a switching chip is connected to multiple flying lead connectors, even if one flying lead connector or line fails, other lines can still transmit signals, improving the overall redundancy and reliability of the signal link. By connecting the first connector to a smaller number of flying lead connectors, the time difference of signals arriving at the first connector can be reduced, ensuring signal synchronization, which is particularly important for communication systems requiring precise clock synchronization. The routing length between each flying lead connector and the switching chip can be shorter, helping to reduce signal reflection and insertion loss, thus improving signal integrity. At the same time, the connection of a smaller number of first connectors to flying lead connectors can reduce crosstalk on the signal path, further optimizing signal quality.

[0122] The bandwidth and rate requirements of high-speed signals determine the necessity of signal fanning out and concentration. At data rates of 112 Gbps or higher, in order to maintain signal integrity and reduce crosstalk and reflection in the link, multiple flying lead connectors may be required to disperse the signal path, while reducing the amount of signals that each first connector needs to process, thus achieving more efficient and reliable signal transmission. The physical space limitations of the circuit board and the overall system will affect the number configuration of the connectors. In a compact space, more flying lead connectors may be required to achieve flexible signal routing, so as to maximize the signal transmission density within a limited area. To improve the reliability and fault tolerance of the system, redundant connections may be set on the signal path. For example, starting from a switching chip, it is connected to a first connector through multiple flying lead connectors respectively. Even if a certain path fails, the signal can still be transmitted through other paths, which usually means that the number of flying lead connectors on the switching chip side is more than that on the first connector side. The design architecture and topology of the system will also affect the quantity relationship of these components. For example, if the switching chip communicates directly with multiple devices, then more flying lead connectors may be required to achieve this goal. If the first connector is used as a hub, then the number of flying lead connectors connected to it may be relatively small. The more complex the signal link is, the more connection points may be required to optimize signal transmission, reduce signal loss and improve signal quality. This may require setting multiple flying lead connectors between the switching chip and the first connector to ensure effective signal transmission.

[0123] In some embodiments, the second board card further includes a second flying lead connector. The processor is connected to the second flying lead connector through a fourth trace, and the second flying lead connector is connected to the second connector through a second cable.

[0124] The use of flying lead connectors and cables shortens the signal path between the processor and the connector, reduces the trace length of the signal on the circuit board, thereby reducing signal insertion loss and reflection, and optimizing signal integrity. The introduction of the second flying lead connector provides greater flexibility in physical layout. They are not restricted by the planar geometry of the circuit board and can connect components at a distance more freely, which is beneficial for dense component layout and heat dissipation management. Since the trace length near the processor is reduced, the potential heat source is reduced, which helps to improve the thermal management of the second board card and reduces the need for complex heat dissipation solutions. Flying lead connectors and cables usually have better shielding characteristics, which can reduce electromagnetic radiation and the impact of electromagnetic interference on other signal lines, improve signal purity, and ensure the stable operation of the system. Flying lead connectors occupy less space on the circuit board, which helps designers to arrange more components within a limited board area and achieve higher integration. The use of cables and flying lead connectors can reduce the dependence of the link on the manufacturing tolerance of the circuit board, improve the robustness of the signal link, and reduce the risk of functional failure caused by PCB manufacturing defects.

[0125] Similarly, in addition to adding a first flying lead connector between the switching chip and the first connector to increase the trace length, a second flying lead connector can also be added between the second board card and the second connector to increase the trace length and ensure the integrity of high-speed signals. In some embodiments, if the trace is too long and the signal is easily transmitted incorrectly, it can be considered to add both a first flying lead connector between the switching chip and the first connector and a second flying lead connector between the second board card and the second connector to increase the trace length and ensure the integrity of high-speed signals.

[0126] Among them, the materials of the traces and the flying leads are both copper.

[0127] In some embodiments, the switching board has a first connector, and the second board card has a second connector. The first surface of the first connector includes a plurality of first pins arranged in a matrix, and each first pin corresponds to an element in the first pin matrix. The first surface of the second connector includes a plurality of second pins arranged in a matrix, and each second pin corresponds to an element in the second pin matrix. The first pin matrix and the second pin matrix are transposed matrices. The first surface of the first connector is the surface connected to the corresponding second connector, and the first surface of the second connector is the surface connected to the corresponding first connector.

[0128] When two connectors are mated in a transposed matrix manner, the corresponding relationship of signals becomes intuitive and easy to manage. The transposed property of the matrix ensures that signals can seamlessly transition from one connector to the corresponding pins on the other connector without complex cross-wiring. The mated design of the transposed matrix reduces the likelihood of signal errors and signal loss. Due to the clear pin correspondence, signals can avoid signal chaos caused by wiring errors during the transmission from the first connector to the second connector, improving the reliability and stability of the overall system. Through matrix transposition, designers can utilize space more efficiently and simplify internal wiring. This design allows signals to be transmitted between the two connectors along the shortest and most direct path, reducing the complexity of signal traces, helping to reduce signal latency, and improving signal integrity. The design of matrix transposition ensures the alignment of signals between the two connectors, helping to reduce crosstalk between signals and improve the clarity and quality of signals. Especially in high-speed signal transmission, the optimization of signal integrity is crucial for ensuring the accuracy and efficiency of data transmission.

[0129] As Figure 21 shown, for the pin correspondence order of the orthogonal high-density connectors of the switching board and the second board, due to the orthogonal relationship between the two boards, the differential signals in the row where the A1 pin is located on the switching board correspond to the differential signals in the column where the A8 pin is located on the second board. If the corresponding relationship of the differential pair order is represented by a matrix, the pin order on the switching board is defined as matrix T02, and the pin order on the second board is defined as matrix T05, then matrix T02 and matrix T05 form a transposed matrix relationship. T01 shows the top view of the switching board, which is the top view of the distribution position of the pins of the first connector on the PCB board. T02 shows the pin distribution order of the interconnected end of the orthogonal high-density connector (i.e., the pin distribution on the side where the first connector is interconnected with the second connector), on the orthogonal plane of the two nodes, as shown in P02. T03 shows the top view of the second connector of the second board, which is the top view of the distribution position of the pins of the second connector on the PCB board. T04 shows the pin distribution order of the interconnected end of the orthogonal high-density connector (i.e., the pin distribution on the side where the second connector is interconnected with the first connector), on the orthogonal plane of the two nodes, as shown in P04. T05 shows the pin distribution order on the basis of the pin distribution order of T04, with the board and the connector as a whole, rotated counterclockwise by 90 degrees to achieve an orthogonal positional relationship, on the orthogonal plane of the two nodes, and the position of the pins is as shown in P05. The orthogonal architecture in the scheme, that is, the boards shown in P02 and P05 present an orthogonal relationship.

[0130] In some embodiments, a first housing includes two second circuit boards, namely the first second circuit board and the second second circuit board. The first surface of the first connector includes a plurality of first pins arranged in a matrix, and each first pin corresponds to an element in the first pin matrix. The first surface of the second connector of the first second circuit board includes a plurality of second pins arranged in a matrix, and each second pin corresponds to an element in the second pin matrix. The first surface of the second connector of the second second circuit board includes a plurality of third pins arranged in a matrix, and each third pin corresponds to an element in the third pin matrix. The first pin matrix and the second pin matrix are transposed matrices, and the positions of the second pins and the third pins are centrosymmetric. The first surface of the first connector is the surface connected to the corresponding second connector, and the first surfaces of the second connectors of the first second circuit board and the second second circuit board are both surfaces connected to the corresponding first connectors.

[0131] Since the first pin matrix and the second pin matrix form a transposed matrix, this means that the signal correspondence between the second connector of the first second circuit board and the first connector is intuitive and clear, without the need for complex signal line design, ensuring accurate signal docking and transmission. The centrosymmetric design of the third pin matrix ensures that even when the second connector on the second second circuit board is inserted into the first connector, the signals can correspond accurately, enhancing the overall stability and reliability of the signal link. The precise pairing of the pin matrices helps to reduce crosstalk and reflection between signals, optimize signal integrity, and ensure that the quality and clarity of the signals are maintained in a high-speed signal environment, such as a 112 Gbps transmission rate. Through the matrix transposition and centrosymmetric pin design, the layout design of the circuit board can be greatly simplified, the complexity of the traces can be reduced, the signal delay can be decreased, and the signal transmission efficiency can be improved. During equipment maintenance and fault diagnosis, this matrix pairing design enables technicians to quickly locate problems, simplify the maintenance process, and improve the maintainability of the system.

[0132] The wire sequence relationship of the orthogonal high-density connector is as shown in the appendix Figure 22 shown. For the pin correspondence order of the orthogonal high-density connectors of the switching board and the second circuit board, in addition to the same parts in the above embodiments (i.e., Figure 21 ), since a first housing includes two second circuit boards, namely the first second circuit board and the second second circuit board, the pin distributions of the orthogonal high-density connectors corresponding to the first second circuit board and the second second circuit board are centrosymmetric, that is, they can overlap after rotating 180 degrees, which means that the pin sequences shown in T051 and T052 present a centrosymmetric relationship. The parts shown in T01~T04 are the same as Figure 21It is exactly the same in [the figure]. T051 shows that, based on the pin distribution order of T04, with the board and the connector regarded as a whole, it is rotated counterclockwise by 90 degrees to achieve an orthogonal positional relationship. On the orthogonal plane of the two nodes, the pin distribution order and positions are as shown in P051. T052 shows that, based on the pin distribution order of T04, with the board and the connector regarded as a whole, it is rotated clockwise by 90 degrees to achieve an orthogonal positional relationship. On the orthogonal plane of the two nodes, the pin distribution order and positions are as shown in P052. The orthogonal architecture in the solution, that is, P02 presents an orthogonal relationship with the boards shown in P051 and P052. For the orthogonal relationship between the two boards, the differential signals in the row where the A1 pin of the high-density connector on the switching board is located correspond to the differential signals in the column where the A8 pin of the high-density connector on the first and second boards of the second board is located, that is, the corresponding relationship between T02 and T051. The differential signals in the row where the A1 pin of the high-density connector on the switching board is located correspond to the differential signals in the column where the A1 pin of the high-density connector on the second board of the second board is located, that is, the corresponding relationship between T02 and T052. This requires that when the signals in the column where the A1 pin of the high-density connector on the device are connected to send signals, the signals in the column where the A8 pin is located also need to be connected to send signals. If the signals in the column where the A1 pin is located are connected to receive signals, the signals in the column where the A8 pin is located also need to be connected to receive signals. And so on, the signals in the column where the A2 pin of the high-density connector on the device needs to be the same as the signals in the column where the A7 pin is located, the signals in the column where the A3 pin is located need to be the same as the signals in the column where the A6 pin is located, and the signals in the column where the A4 pin is located need to be the same as the signals in the column where the A5 pin is located.

[0133] Similarly, for the high-density connector on the switching board, the signals in the row where the A1 pin is located need to be the same as the signals in the row where the A8 pin is located, the signals in the row where the A2 pin is located need to be the same as the signals in the row where the A7 pin is located, the signals in the row where the A3 pin is located need to be the same as the signals in the row where the A6 pin is located, and the signals in the row where the A4 pin is located need to be the same as the signals in the row where the A5 pin is located.

[0134] In some embodiments, a first housing includes a second board, a second housing includes a third number of switching boards, the third number of switching boards are arranged side by side in the second housing along a first direction, a switching board includes a fourth number of first connectors, the number of second boards is the product of the third number and the fourth number, and the number of second connectors on a second board is the number of second housings.

[0135] In some embodiments, a first housing includes a second board, a second housing includes a fifth number of switching boards, the fifth number of switching boards are arranged in a stacked manner in the second housing along a second direction, a switching board includes a sixth number of first connectors, the number of second boards is the sixth number, and the number of second connectors on a second board is the sum of the numbers of all the switching boards.

[0136] In some embodiments, a second housing includes a switching board, and a first housing includes a seventh number of second daughter cards. The seventh number of second daughter cards are stacked in a first direction in the first housing. An eighth number of second connectors are included on one second daughter card, and the number of first connectors on a switching board is the sum of the numbers of all the second daughter cards.

[0137] In some embodiments, a second housing includes a ninth number of switching boards, and the ninth number of switching boards are stacked in a second direction in the second housing. A first housing includes a tenth number of second daughter cards. The tenth number of second daughter cards are stacked in a first direction in the first housing. An eleventh number of second connectors are included on one second daughter card, and the number of first connectors on a switching board is the sum of the numbers of all the second daughter cards. The eleventh number is the number of all the switching boards.

[0138] In some embodiments, a second housing includes a twelfth number of switching boards, and the twelfth number of switching boards are arranged side by side in a first direction in the second housing. A first housing includes a thirteenth number of second daughter cards. The thirteenth number of second daughter cards are stacked in a first direction in the first housing. A fourteenth number of second connectors are included on one second daughter card, and the number of first connectors on a switching board is half of the sum of the numbers of all the second daughter cards. The fourteenth number is the number of second housings.

[0139] Figure 23 The figure is a schematic diagram of the orthogonal connection relationship between a switching board and a second daughter card provided by an embodiment of the present application. As Figure 23 shown, 8 first housings are vertically inserted into a server chassis, 12 second housings are horizontally inserted into the server chassis, and the first housing and the second housing are orthogonally plugged.

[0140] Figure 24 The figure is a schematic diagram of the structure of another server chassis provided by an embodiment of the present application. As Figure 24 shown, the first housing is horizontally inserted into the server chassis, the second housing is vertically inserted into the server chassis, and the first housing and the second housing are orthogonally plugged.

[0141] This embodiment further provides a server system, including any one of the above servers.

[0142] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation manner.

[0143] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered as exceeding the scope of this application.

[0144] The above has introduced in detail a server and a server system provided by this application. Specific examples are used herein to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A server, characterized in that, Comprising: At least one first board card; A switching board group including a plurality of switching boards; A second board card group including a plurality of second board cards; A midplane; Wherein, the switching board is orthogonally and pluggably connected to any one of the second board cards, and at least one of the first board cards is connected to at least a part of the second board cards through the midplane.

2. The server according to claim 1, wherein The first board card is parallel to the extending direction of the second board card group, at least one of the first board cards and the second board card group are arranged in sequence along a first direction, and the first board card and the second board card are located on the same side of the switching board group.

3. The server according to claim 1, characterized in that, The switching board is located on a first side of the second board card, the first board card is located on a second side of the second board card, and the first side and the second side are opposite sides.

4. The server according to claim 2, wherein All of the first board cards are located on a first side or a second side of the second board card group; Or, a part of the first board cards are located on a first side of the second board card group, and another part of the first board cards are located on a second side of the second board card group, and the first side and the second side are opposite sides.

5. The server according to claim 4, characterized in that The number of the first board cards located on the first side of the second board card group is equal to the number of the first board cards located on the second side of the second board card group.

6. The server according to claim 2, wherein A part of the orthographic projection of the midplane and the switching board on a preset plane overlaps, and the preset plane is a plane parallel to the extending direction of the switching board.

7. The server according to claim 2, wherein The server further includes a bus bar, the bus bar is connected to the cooling devices on each of the second board cards, the midplane is located between the bus bar and the switching board, and a part of the orthographic projection of the midplane, the bus bar and the switching board on a preset plane overlaps.

8. The server according to claim 2 or 3, characterized in that, A plurality of the second board cards are located in the same first housing, the plurality of the second board cards in the same first housing are arranged along a first direction, and a first liquid cooling plate is provided between two of the second board cards in the same first housing, and the first direction is the same as the arrangement direction of the connectors of one of the switching boards.

9. The server according to claim 8, characterized in that, Two of the second board cards are included in the same first housing, the processor of one of the second board cards is a first processor, the processor of the other second board card is a second processor, and the first liquid cooling plate is located between the first processor and the second processor.

10. The server according to claim 2 or 3, characterized in that, A plurality of the second board cards are located in the same first housing, the plurality of the second board cards in the same first housing are arranged in parallel along a second direction, and the second direction is the same as the arrangement direction of the connectors of one of the second board cards.

11. The server according to claim 1, wherein The switching board has a first connector, and the number of rows of the pins of the first connector is greater than the number of layers of the traces on the switching board.

12. The server according to claim 11, wherein The number of rows of the pins of the first connector is an integer multiple of the number of layers of the traces on the switching board.

13. The server according to claim 1, wherein The switching board has a first connector, there is a gap between any two adjacent rows of solder joints welded to the first connector on the switching board, and at least one of the gaps has a trace, one end of the trace is connected to the pin of the first connector, and the other end of the trace is connected to the switching chip on the switching board.

14. The server according to claim 13, wherein There are N rows of the solder joints on the switching board, and there are the traces between the solder joints in the N / 2-th row and the solder joints in the (N / 2 + 1)-th row.

15. The server according to claim 1, characterized in that, The second board card includes a processor, the first board card includes a controller, the switching board includes a switching chip, the processor on the second board card and the controller on at least one of the first board cards are communicatively connected through an interface communication protocol, the switching chip on the switching board and the processor on at least one of the second board cards are communicatively connected through an Ethernet protocol, and any two of the processors are communicatively connected through the Ethernet protocol.

16. The server according to claim 1, characterized in that, The switching board has a switching chip and a first connector, the second board card includes a processor and a second connector, the switching chip is connected to the first connector through a first trace, the processor is connected to the second connector through a second trace, and the sum of the length of the first trace and the length of the second trace is less than or equal to a first preset length, where the first preset length is the minimum trace length for enabling the channel operating margin of the high-speed signal transmitted from the switching chip to the processor to be greater than a preset margin, and the preset margin is the minimum margin when the integrity of the high-speed signal transmitted from the switching chip to the processor is greater than or equal to a preset integrity.

17. The server according to claim 1, wherein The switching board has a switching chip, a first connector, and a first relay chip, the switching chip is connected to the first relay chip through a first sub-trace, the first relay chip is connected to the first connector through a second sub-trace, and the first relay chip is used to enhance the signal strength of the high-speed signal, where the sum of the length of the first sub-trace and the length of the second sub-trace is greater than a second preset length, and the first preset length is greater than the second preset length.

18. The server according to claim 1, wherein The switching board has a switching chip, a first flying wire connector, and a first connector, the switching chip is connected to the first flying wire connector through a third trace, and the first flying wire connector is connected to the first connector through a first cable.

19. The server according to claim 1, characterized in that, The switching board has a first connector, the second board card has a second connector, the first surface of the first connector includes a plurality of first pins arranged in a matrix, each of the first pins corresponds to each element in the first pin matrix, the first surface of the second connector includes a plurality of second pins arranged in a matrix, each of the second pins corresponds to each element in the second pin matrix, the first pin matrix and the second pin matrix are transposed matrices, the first surface of the first connector is the surface connected to the corresponding second connector, and the first surface of the second connector is the surface connected to the corresponding first connector.

20. A server system, characterized in that, Including the server according to any one of claims 1 to 19.

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