Power management method and storage device

Abstract

The invention provides a power management method and a storage device. The method comprises the following steps: obtaining a first configuration instruction from a host system; responding to the first configuration instruction, controlling the storage device to be in an operable power supply state, and setting a power supply mode of the storage device to be a first low-power-consumption power supply mode; and adjusting the clock frequency of the storage device according to the flow information in the first low-power-consumption power mode, the flow information reflecting the total number of at least one to-be-processed instruction in the storage device, and the adjusted clock frequency being positively correlated to the total number. Therefore, the energy-saving performance of the storage device can be improved under the condition that the working performance of the storage device is not influenced as far as possible.

Description

Technical Field

[0001] The present invention relates to the field of storage technologies, and more particularly, to a power management method and a storage device. Background Art

[0002] Low power consumption is one of the most important evaluation criteria for consumer storage devices. For example, for an electronic device (such as a notebook computer) equipped with a consumer storage device, low power consumption means that its battery has a longer service life, the power consumption speed is lower, and the heat generation of the electronic device will also be improved. Therefore, how to balance the working efficiency and energy-saving performance of the storage device is one of the problems that need to be solved urgently at present. Summary of the Invention

[0003] The present invention provides a power management method and a storage device, which can effectively improve the energy-saving performance of the storage device without affecting the working efficiency of the storage device as much as possible.

[0004] An embodiment of the present invention provides a power management method for a storage device. The power management method includes: obtaining a first configuration instruction from a host system; in response to the first configuration instruction, controlling the storage device to be in an operable power state and setting the power mode of the storage device to a first low-power consumption power mode; and in the first low-power consumption power mode, adjusting the clock frequency of the storage device according to traffic information, where the traffic information reflects the total number of at least one to-be-processed instruction in the storage device, and the adjusted clock frequency is positively correlated with the total number.

[0005] Another embodiment of the present invention provides a storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is used to: obtain a first configuration instruction from the host system; in response to the first configuration instruction, control the storage device to be in an operable power state and set the power mode of the storage device to a first low-power consumption power mode; and in the first low-power consumption power mode, adjust the clock frequency of the storage device according to traffic information, where the traffic information reflects the total number of at least one to-be-processed instruction in the storage device, and the adjusted clock frequency is positively correlated with the total number. Brief Description of the Drawings

[0006] Figure 1 is a schematic diagram of a data storage system shown according to an embodiment of the present invention;

[0007] Figure 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention;

[0008] Figure 3 is a schematic diagram of managing a memory module shown according to an embodiment of the present invention;

[0009] Figure 4 is a schematic diagram of a management strategy for power states and power modes shown according to an embodiment of the present invention;

[0010] Figure 5 is a schematic diagram of the relative relationship of power consumption per unit time corresponding to different power modes shown according to an embodiment of the present invention;

[0011] Figure 6 is a schematic diagram of adjusting the clock frequency and / or internal power distribution of a storage device according to the power mode of the storage device shown according to an embodiment of the present invention;

[0012] Figure 7 is a flowchart of a power management method shown according to an embodiment of the present invention. Detailed Embodiment

[0013] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0014] Figure 1 is a schematic diagram of a data storage system shown according to an embodiment of the present invention. Refer to Figure 1 , the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 can include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0015] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 may support an embedded Multi-Media Card (eMMC), Universal Flash Storage (UFS), Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVM express), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 via the connection interface 121 (such as exchanging signals, instructions, and / or data).

[0016] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more arrays of memory cells. The memory cells in the memory cell array store data in the form of a voltage (also known as a threshold voltage). For example, the memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0017] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the overall or partial operation of the storage device 12. For example, the memory controller 123 may include a Central Processing Unit (CPU), or other programmable general-purpose or special-purpose microprocessors, Digital Signal Processors (DSPs), programmable controllers, Application-Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs), or other similar devices, or a combination of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0018] The memory controller 123 can send an instruction sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited in the present invention. The memory module 122 can receive the instruction sequence from the memory controller 123 and access the storage units inside the memory module 122 according to this instruction sequence.

[0019] Figure 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention. Please refer to Figure 1 and Figure 2 , the memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0020] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage the overall or partial operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 can include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is the same as the description of the memory controller 123.

[0021] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and is used to cache data. For example, the buffer memory 24 can be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0022] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on the data to ensure the correctness of the data. For example, the decoding circuit 25 can support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may further include various other types of circuit modules (such as a power management circuit, etc.), which are not limited in the present invention.

[0023] Figure 3 is a schematic diagram of managing a memory module shown according to an embodiment of the present invention. Please refer to Figures 1 to 3 , the memory module 122 includes a plurality of physical units 301(1) to 301(B). Each physical unit includes a plurality of memory cells and is used to store data non-volatilely.

[0024] In one embodiment, a physical unit may include one or more physical erasure units. In addition, a physical unit may include a plurality of sub-physical units. For example, a sub-physical unit may include one or more physical programming units.

[0025] In one embodiment, an entity programming unit may include a plurality of entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, both the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit may be adjusted according to practical requirements, and the present invention is not limited thereto. In one embodiment, an entity programming unit may be regarded as an entity page. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and the present invention is not limited to this.

[0026] In one embodiment, an entity programming unit is the minimum unit for synchronously writing data in the memory module 122. For example, when performing a programming operation (also referred to as a write operation) on an entity programming unit to write data into this entity programming unit, multiple storage units in this entity programming unit may be synchronously programmed to store the corresponding data. For example, when programming an entity programming unit, a write voltage may be applied to this entity programming unit to change the threshold voltage of at least some of the storage units in this entity programming unit. For example, the threshold voltage of a storage unit may reflect the bit data stored in this storage unit.

[0027] In one embodiment, an entity erasure unit may contain a plurality of entity programming units. The plurality of entity programming units in an entity erasure unit may be synchronously erased. For example, when performing an erase operation on an entity erasure unit, an erase voltage may be applied to the plurality of entity programming units in this entity erasure unit to change the threshold voltage of at least some of the storage units in these entity programming units. By performing an erase operation on an entity erasure unit, the data stored in this entity erasure unit can be cleared. In one embodiment, an entity erasure unit may be regarded as an entity block.

[0028] In one embodiment, the memory control circuit 23 may logically associate the entity units 301(1) to 301(A) and 301(A + 1) to 301(B) with the data area 31 and the idle area 32, respectively. The entity units 301(1) to 301(A) in the data area 31 all store data (also referred to as user data) from the host system 11. For example, any one of the entity units in the data area 31 may store valid data and / or invalid data. In addition, the entity units 301(A + 1) - 301(B) in the idle area 32 do not store data (such as valid data).

[0029] In one embodiment, if a certain physical unit does not store valid data, this physical unit can be associated with the idle area 32. In addition, the physical units in the idle area 32 can be erased to clear the data in these physical units. In one embodiment, the physical units in the idle area 32 are also referred to as idle physical units. In one embodiment, the idle area 32 is also referred to as a free pool.

[0030] In one embodiment, when data is to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data in the selected physical units. After the data is stored in this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be alternately used between the data area 31 and the idle area 32.

[0031] In one embodiment, the memory control circuit 23 can configure a plurality of logical units 302(1) to 302(C) to map the physical units (i.e., physical units 301(1) to 301(A)) in the data area 31. For example, one logical unit can correspond to one logical block address (Logical Block Address, LBA) or other logical management units. One logical unit can be mapped to one or more physical units.

[0032] In one embodiment, if a certain physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. On the contrary, if a certain physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0033] In one embodiment, the memory control circuit 23 can record the mapping relationship between the logical units and the physical units in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 can, according to the information in this management table (i.e., the logical-to-physical mapping table), instruct the memory module 122 to perform operations such as data reading, writing, or erasing.

[0034] In one embodiment, the storage device 12 can operate in an operational power state or a no - operational power state. For example, at a certain point in time (also referred to as the first time point), the storage device 12 can operate in an operational power state. However, at another point in time (also referred to as the second time point), the storage device 12 can operate in a no - operational power state. Alternatively, at yet another point in time (also referred to as the third time point), the storage device 12 can switch from a no - operational power state to an operational power state, or from an operational power state to a no - operational power state.

[0035] In one embodiment, if the storage device 12 operates in an operational power state, then in the operational power state, the memory control circuit 23 can process operation instructions from the storage device 12. For example, the operation instructions may include read instructions, write instructions, and / or delete instructions. The read instructions are used to read data from the storage device 11. The write instructions are used to store data in the storage device 11. The delete instructions are used to delete the data stored in the storage device 11. For example, in the operational power state, the memory control circuit 23 can control the memory module 122 to perform corresponding read operations, write operations, or erase operations respectively according to the read instructions, write instructions, or delete instructions from the storage device 12. However, if the storage device 12 operates in a no - operational power state, then in the no - operational power state, the memory control circuit 23 cannot process operation instructions from the storage device 12. In addition, the operation instructions may also include other types of instructions, which are not limited in the present invention.

[0036] In one embodiment, the power consumption per unit time corresponding to the no - operational power state can be lower than the power consumption per unit time corresponding to the operational power state. On the other hand, the performance (or performance upper limit) corresponding to the operational power state can be higher than the performance (or performance upper limit) corresponding to the no - operational power state. For example, when the storage device 12 operates in an operational power state, although the storage device 12 can process operation instructions from the host system 11 in real time based on relatively high performance, the power consumption per unit time of the storage device 12 is also relatively high. Or, when the storage device 12 operates in a no - operational power state, although the power consumption per unit time of the storage device 12 is relatively low, however, the storage device 12 still needs to spend extra time and / or energy consumption to switch to the operational power state to facilitate processing subsequent operation instructions from the host system 11. Therefore, how to balance the working performance and energy - saving performance of the storage device 12 is actually one of the problems that need to be solved urgently at present.

[0037] In one embodiment, after the storage device 12 is powered on, the storage device 12 may be in a preset power state (also referred to as the normal power state). The normal power state belongs to an operable power state. Therefore, if the storage device 12 is in the normal power state, the memory control circuit 23 can process operation instructions from the storage device 12 in the normal power state. In addition, in response to the storage device 12 being in the normal power state, the memory control circuit 23 can automatically set the power mode of the storage device 12 to a preset power mode (also referred to as the normal power mode).

[0038] In one embodiment, the memory control circuit 23 can obtain a configuration instruction (also referred to as the first configuration instruction) from the host system 11. For example, the first configuration instruction may include a set feature instruction or a similar instruction. The first configuration instruction can be used to indicate or control the storage device 12 to operate in a power state (also referred to as the first target power state). In response to the first configuration instruction, the memory control circuit 23 can automatically control the storage device 12 to be in the first target power state. It should be noted that similar to the normal power state, the first target power state also belongs to an operable power state. However, the first target power state is different from the aforementioned normal power state.

[0039] In one embodiment, in response to the first configuration instruction (or the storage device 12 being in the first target power state), the memory control circuit 23 can automatically set the power mode of the storage device 12 to a specific power mode (also referred to as the first low-power consumption power mode). It should be noted that the power consumption per unit time corresponding to the first low-power consumption power mode (also referred to as the first power consumption per unit time) must be lower than (or not higher than) the power consumption per unit time corresponding to the normal power mode (also referred to as the preset power consumption per unit time). For example, the first power consumption per unit time can be 60% - 80% of the preset power consumption per unit time or other ratios. That is, when the storage device 12 is in the first low-power consumption power mode, the power consumption per unit time of the storage device 12 may be 60% - 80% of the power consumption per unit time of the storage device 12 when the storage device 12 is in the normal power mode or other ratios. Thus, the power consumption per unit time of the storage device 12 can be appropriately reduced when the storage device 12 is not in a busy state.

[0040] In one embodiment, in the first low-power consumption power mode, the memory control circuit 23 can obtain traffic information. The traffic information can reflect the total number of at least one pending instruction in the storage device 12. Or, in one embodiment, the traffic information can reflect the current information pressure level or busy level of the storage device 12. For example, the information pressure level or busy level can be positively correlated with the total number of pending instructions.

[0041] In one embodiment, after obtaining an operation instruction from the host system 11, the operation instruction can be cached in the buffer memory 24 to await processing. Therefore, each operation instruction currently cached in the buffer memory 24 and awaiting processing can be regarded as a to-be-processed instruction. In one embodiment, the memory control circuit 23 can obtain the traffic information by monitoring the total number of operation instructions awaiting processing in the buffer memory 24 (i.e., the total number of to-be-processed instructions).

[0042] In one embodiment, in the first low-power power mode, the memory control circuit 23 can adjust the clock frequency of the storage device 12 according to the traffic information. In particular, the adjusted clock frequency can be positively correlated with the total number of to-be-processed instructions. That is, if the traffic information reflects that the total number of to-be-processed instructions is relatively large (for example, relatively many operation instructions awaiting processing are currently cached in the buffer memory 24), the memory control circuit 23 can appropriately increase the clock frequency of the storage device 12 to improve or maintain the working efficiency of the storage device 12. However, if the traffic information reflects that the total number of to-be-processed instructions is relatively small (i.e., relatively few operation instructions awaiting processing are currently cached in the buffer memory 24), the memory control circuit 23 can appropriately reduce the clock frequency of the storage device 12 to reduce the power consumption per unit time of the storage device 12. Thus, the energy-saving performance of the storage device 12 can be effectively improved without significantly affecting the working performance of the storage device 12 and the user experience.

[0043] In one embodiment, in the first low-power power mode, the memory control circuit 23 can compare the total number of to-be-processed instructions with a standard quantity to obtain evaluation data (also referred to as traffic evaluation data). The traffic evaluation data can reflect the numerical relative relationship between the total number of to-be-processed instructions and the standard quantity. For example, in one embodiment, the traffic evaluation data can reflect that the total number of to-be-processed instructions is greater than, less than, or equal to the standard quantity. Or, in one embodiment, the traffic evaluation data can reflect the ratio of the total number of to-be-processed instructions to the standard quantity. For example, assuming that the total number of to-be-processed instructions is X and the standard quantity is Y, the ratio can be expressed as X / Y. For example, assuming that the total number of to-be-processed instructions is 80 and the standard quantity is 100, the ratio can be expressed as 0.8 (i.e., X / Y = 0.8).

[0044] In one embodiment, in the first low-power power mode, after obtaining the traffic evaluation data, the memory control circuit 23 may adjust the clock frequency of the storage device 12 according to the traffic evaluation data. For example, the memory control circuit 23 may query a management table according to the traffic evaluation data to determine a clock frequency (also referred to as the target clock frequency). Then, the memory control circuit 23 may set or adjust the clock frequency of the storage device 12 according to the target clock frequency. For example, the memory control circuit 23 may adjust the clock frequency of the storage device 12 to be the same as (e.g., identical to) the target clock frequency.

[0045] In one embodiment, the management table may record multiple candidate values or multiple candidate value ranges respectively corresponding to multiple candidate clock frequencies. If the currently detected traffic evaluation data is the same as a certain value (also referred to as the first value) among the multiple candidate values or falls within a certain value range (also referred to as the first value range) among the multiple candidate value ranges, the memory control circuit 23 may determine the clock frequency corresponding to the first value or the first value range (also referred to as the first clock frequency) among the multiple candidate clock frequencies as the target clock frequency. Or, if the currently detected traffic evaluation data is the same as another value (also referred to as the second value) among the multiple candidate values or falls within another value range (also referred to as the second value range) among the multiple candidate value ranges, the memory control circuit 23 may determine the clock frequency corresponding to the second value or the second value range (also referred to as the second clock frequency) among the multiple candidate clock frequencies as the target clock frequency. The first clock frequency may be the same as or different from the second clock frequency. Thereafter, the memory control circuit 23 may set or adjust the clock frequency of the storage device 12 according to the target clock frequency.

[0046] In one embodiment, in the first low-power power mode, assuming that the currently detected traffic evaluation data reflects that the ratio of the total number of pending instructions to the standard quantity is greater than 80%, the target clock frequency set by the memory control circuit 23 may be the same as the normal clock frequency (also referred to as the preset clock frequency). However, as the currently detected traffic evaluation data reflects that the ratio of the total number of pending instructions to the standard quantity gradually decreases (e.g., less than 80% or even less than 60%, etc.), the target clock frequency set by the memory control circuit 23 may gradually decrease. As the set target clock frequency decreases, the frequency difference between the target clock frequency and the normal clock frequency (i.e., the preset clock frequency) will increase. This frequency difference may be positively correlated with the energy-saving performance of the storage device 12.

[0047] In one embodiment, the memory control circuit 23 may preset a threshold value of a target clock frequency. In one embodiment, even if the currently detected traffic evaluation data reflects that the ratio of the total number of the to-be-processed instructions to the standard quantity is further reduced, the target clock frequency will not be set to be less than this threshold value. Thereby, problems in the operation of the storage device 12 can be avoided due to excessive reduction of the clock frequency of the storage device 12.

[0048] In one embodiment, in the first low-power power mode, the memory control circuit 23 may detect a trigger event (also referred to as the first trigger event). The first trigger event can be used to moderately reduce the power consumption per unit time of the storage device 12 without changing the power state of the storage device 12.

[0049] In one embodiment, the first trigger event includes that the time length of the storage device 12 in the idle state reaches a preset time length. For example, in the first low-power power mode, when the storage device 12 is in the idle state (i.e., non-busy state), the memory control circuit 23 may start a counter (also referred to as a timer). The output value (also referred to as the count value) of this counter may continuously increase as time passes. If the storage device 12 leaves the idle state (i.e., enters the busy state), the memory control circuit 23 may stop and reset this counter. In one embodiment, the memory control circuit 23 may determine the time length of the storage device 12 in the idle state according to the current count value of this counter.

[0050] In one embodiment, if the time length of the storage device 12 in the idle state is greater than or equal to the preset time length (for example, the aforementioned count value is greater than the preset value), the memory control circuit 23 may determine that the first trigger event is detected. However, if the time length of the storage device 12 in the idle state is less than this preset time length (for example, the aforementioned count value is less than the preset value), the memory control circuit 23 may determine that the first trigger event is not detected. For example, the preset time length can be set according to practical requirements, such as 5 minutes, 10 minutes or other time lengths, and the present invention is not limited thereto.

[0051] In one embodiment, in response to a first trigger event, while the storage device 12 remains in an operable power state (i.e., without changing the power state of the storage device 12), the memory control circuit 23 can automatically switch the power mode of the storage device 12 from a first low-power mode to another low-power mode (also referred to as a second low-power mode). The second low-power mode is different from the first low-power mode. It should be noted that the power consumption per unit time corresponding to the second low-power mode (also referred to as the second unit time power consumption) must be lower than the power consumption per unit time corresponding to the first low-power mode (i.e., the first unit time power consumption). For example, the second unit time power consumption can be 60% - 80% of the first unit time power consumption or other ratios.

[0052] In other words, in response to the power mode of the storage device 12 being switched from the first low-power mode to the second low-power mode, even if the power state of the storage device 12 remains unchanged (i.e., the storage device 12 maintains an operable power state), the memory control circuit 23 can appropriately reduce the performance and power consumption per unit time of the storage device 12. Thus, the energy-saving effect of the storage device 12 can be effectively improved without significantly affecting the working performance of the storage device 12.

[0053] In one embodiment, in the second low-power mode, the memory control circuit 23 can detect another trigger event (also referred to as a second trigger event). The second trigger event can be used to improve the working performance of the storage device 12 without changing the power state of the storage device 12.

[0054] In one embodiment, the second trigger event can include a wake-up event for the storage device 12. For example, the wake-up event can include detecting an operation instruction from the host system 11, detecting an interrupt event for a specific program, or detecting a link reset between the host system 11 and the storage device 12, etc. In addition, the wake-up event can also include any system event that requires immediately enhancing the working performance of the storage device 12, which will not be elaborated one by one here.

[0055] In one embodiment, in response to the second trigger event, the memory control circuit 23 can automatically restore the power mode of the storage device 12 from the second low-power mode to the first low-power mode. After restoring to the first low-power mode, the memory control circuit 23 can process corresponding system events (such as operation instructions from the host system 11) through the higher performance of the storage device 12.

[0056] In other words, in response to the power mode of the storage device 12 reverting from the second low-power mode to the first low-power mode, even if the power state of the storage device 12 remains unchanged (i.e., the storage device 12 maintains an operable power state), the memory control circuit 23 can actively increase the partial performance and power consumption per unit time of the storage device 12. In this case, although the power consumption per unit time of the storage device 12 will increase slightly, it can effectively prevent the user from feeling the operation delay of the storage device 12. Thus, a better balance can be achieved between the working performance and energy-saving performance of the storage device 12.

[0057] In one embodiment, the memory control circuit 23 can also obtain another configuration instruction (also referred to as the second configuration instruction) from the host system 11. For example, the second configuration instruction can include a setting feature instruction or a similar instruction. The second configuration instruction can be used to indicate or control the storage device 12 to operate in another power state (also referred to as the second target power state). In response to the second configuration instruction, the memory control circuit 23 can automatically control the storage device 12 to be in the second target power state. The second target power state is different from the first target power state. It should be noted that the second target power state belongs to an inoperable power state.

[0058] In one embodiment, in response to the second configuration instruction (or the storage device 12 being in the second target power state), the memory control circuit 23 can automatically set the power mode of the storage device 12 to a specific power mode (also referred to as the third low-power mode). It should be noted that the power consumption per unit time (also referred to as the third power consumption per unit time) corresponding to the third low-power mode must be lower than (or not higher than) the power consumption per unit time (i.e., the second power consumption per unit time) (or the first power consumption per unit time) corresponding to the second low-power mode. For example, the third power consumption per unit time can be 60% - 80% of the second power consumption per unit time or other ratios.

[0059] In one embodiment, the third low-power mode includes multiple sub-low-power modes. The multiple sub-low-power modes respectively correspond to different power consumptions per unit time. It should be noted that the power consumption per unit time corresponding to each sub-low-power mode is lower than (or not higher than) the power consumption per unit time (i.e., the second power consumption per unit time) corresponding to the second low-power mode.

[0060] In one embodiment, in the inoperable power state, the memory control circuit 23 can set the power mode of the storage device 12 to one of the multiple sub-low-power modes in the third low-power mode according to the length of time the storage device 12 is in the idle state. For example, the length of time the storage device 12 is in the idle state can be obtained according to the aforementioned count value, which will not be repeated here.

[0061] In one embodiment, if the length of time that the storage device 12 is in the idle state is a certain length of time (also referred to as the first length of time), the memory control circuit 23 may set the power mode of the storage device 12 to a certain power mode among the multiple sub-low-power consumption power modes (also referred to as the first sub-low-power consumption power mode). Alternatively, if the length of time that the storage device 12 is in the idle state is another length of time (also referred to as the second length of time), then the memory control circuit 23 may set the power mode of the storage device 12 to another power mode among the multiple sub-low-power consumption power modes (also referred to as the second sub-low-power consumption power mode). The second length of time is different from the first length of time. The power consumption per unit time corresponding to the second sub-low-power consumption power mode (also referred to as the second sub-unit time power consumption) is different from the power consumption per unit time corresponding to the first sub-low-power consumption power mode (also referred to as the first sub-unit time power consumption).

[0062] In one embodiment, it is assumed that the second length of time is longer than the first length of time, and the second sub-unit time power consumption is lower than the first sub-unit time power consumption. In the non-operable power state, as the length of time that the storage device 12 is in the idle state increases (for example, from the first length of time to the second length of time), the memory control circuit 23 may switch the power mode of the storage device 12 from the first sub-low-power consumption power mode to the second sub-low-power consumption power mode. Thus, the power consumption per unit time of the storage device 12 can be effectively reduced without affecting the working efficiency of the storage device 12.[[ID=]}]

[0063] Figure 4 It is a schematic diagram of the management strategy for the power state and power mode shown according to the embodiments of the present invention. Please refer to Figure 4 In one embodiment, the operable power states include power state 0 (PS0) and power state 1 (PS1). Power state 0 and power state 1 correspond to the normal power mode and the low-power consumption power mode A respectively.

[0064] In one embodiment, the aforementioned normal power state may be power state 0, the first target power state may be power state 1, and the first low-power consumption power mode may be the low-power consumption power mode A. In addition, the second low-power consumption power mode may be the low-power consumption power mode B.

[0065] In one embodiment, when the storage device 12 is in power state 1, the power mode of the storage device 12 can be switched between the low-power consumption power modes A and B to attempt to achieve a better balance between the working efficiency and energy-saving performance of the storage device 12. The relevant operation details have been described in detail above and will not be repeated here.

[0066] In one embodiment, the non-operational power state includes Power State 2 (PS2). Power State 2 corresponds to Low Power Mode C, Low Power Mode D, and Low Power Mode E. Low Power Mode C, Low Power Mode D, and Low Power Mode E are all sub-low power modes of the third low power mode.

[0067] Figure 5 It is a schematic diagram showing the relative relationship of the power consumption per unit time corresponding to different power modes shown in the embodiments of the present invention. Please refer to Figure 5 , following the Figure 4 embodiment, if the power consumption per unit time is sorted from high to low, the power consumption per unit time corresponding to the normal power mode is the highest, followed by Low Power Mode A to D in sequence, and the power consumption per unit time corresponding to Low Power Mode E is the lowest. It should be noted that the power consumption per unit time corresponding to each power mode can be set according to actual needs as long as the above order is not violated.

[0068] In one embodiment, the memory control circuit 23 can dynamically adjust at least one of the clock frequency of the storage device 12 and the internal power distribution of the storage device 12 according to the current power mode of the storage device 12, so as to change the power consumption per unit time of the storage device 12. For example, for Figure 4 and Figure 5 the different power modes in, the memory control circuit 23 can control the storage device 12 to adopt different clock frequencies and / or change the internal power distribution of the storage device 12. Thus, the required power consumption per unit time can be achieved.

[0069] In one embodiment, the storage device 12 includes a plurality of circuit modules. For example, each circuit module may include at least one electronic circuit configured at any position, presented in any form, and / or used to provide any function in the storage device 12.

[0070] In one embodiment, the dynamic adjustment of the clock frequency of the storage device 12 and / or the internal power distribution of the storage device 12 by the memory control circuit 23 may include at least one of the following operations: adjusting the clock frequency of at least one circuit module (also referred to as the first circuit module) among the plurality of circuit modules; stopping the operation of at least one circuit module (also referred to as the second circuit module) among the plurality of circuit modules; and stopping the power supply to at least one circuit module (also referred to as the third circuit module) among the plurality of circuit modules. The first circuit module, the second circuit module, and the third circuit module may include the same circuit module or different circuit modules.

[0071] Figure 6It is a schematic diagram for adjusting the clock frequency and / or internal power distribution of a storage device according to the power mode of the storage device shown in the embodiments of the present invention. Please refer to Figure 6 , assuming that the storage device 12 includes a clock circuit module 61, a functional hardware module 62, a buffer module 63, and a memory module 64. The number of each of the clock circuit module 61, the functional hardware module 62, the buffer module 63, and the memory module 64 can be one or more, and the present invention is not limited thereto.

[0072] The clock circuit module 61 is used to provide a clock signal inside the storage device 12 and / or control the frequency of the clock signal (i.e., the clock frequency). The functional hardware module 62 may include at least one integrated circuit module. Each integrated circuit module can be responsible for the corresponding function. For example, the functional hardware module 62 may include a processor module, an interface module, a memory module, and / or other types of functional hardware modules. The buffer module 63 may include a random access memory (RAM) and / or other types of buffer modules. The memory module 64 may include a rewritable non-volatile memory module (such as a flash memory module) or other types of memory modules.

[0073] In one embodiment, for different power modes, the memory control circuit 23 can dynamically perform functional control on at least one of the clock circuit module 61, the functional hardware module 62, the buffer module 63, and the memory module 64, so as to achieve the technical effect of adjusting the clock frequency of the storage device 12 and / or the internal power distribution of the storage device 12.

[0074] For example, in the normal power mode, the memory control circuit 23 can control all of the clock circuit module 61, the functional hardware module 62, the buffer module 63, and the memory module 64 to operate normally (including normal power supply).

[0075] In the low-power supply mode A, the memory control circuit 23 can control the clock circuit module 61 to reduce the frequency (for example, reduce the frequency of the clock signal output by the clock circuit module 61), and control the functional hardware module 62, the buffer module 63, and the memory module 64 to operate normally. In the low-power supply modes B to E, the memory control circuit 23 can further stop the operation of a part of the clock circuits in the clock circuit module 61 (i.e., partial failure) to further save energy. In addition, in the low-power supply modes C to E, the memory control circuit 23 can, according to requirements, further stop the operation of some modules in the functional hardware module 62, the buffer module 63, and the memory module 64 and / or stop the power supply to some modules in the functional hardware module 62, the buffer module 63, and the memory module 64 (i.e., partial failure or total failure). Thus, the required power consumption per unit time can be achieved or satisfied for different power supply modes of the storage device 12. It should be noted that Figure 6 the adjustments or settings made for each type of circuit module can be adjusted according to actual requirements.

[0076] In one embodiment, when the storage device 12 is in an inoperable power state (such as Figure 4 the power state 2), the memory control circuit 23 can continuously detect wake-up events. For example, the wake-up event can include detecting an operation instruction from the host system 11, detecting an interrupt event for a specific program, or detecting a connection reset between the host system 11 and the storage device 12, etc. When a wake-up event is detected, the memory control circuit 23 can restore the storage device 12 from the inoperable power state to an operable power state (such as Figure 4 the power state 0 or 1).

[0077] Figure 7 is a flowchart of the power management method shown in an embodiment of the present invention. Please refer to Figure 7 , in step S701, a first configuration instruction is obtained from the host system. In step S702, in response to the first configuration instruction, the storage device is controlled to be in an operable power state, and the power supply mode of the storage device is set to the first low-power supply mode.

[0078] In step S703, in the first low-power supply mode, according to the traffic information, the clock frequency of the storage device is adjusted, where the traffic information reflects the total number of at least one pending instruction in the storage device, and the adjusted clock frequency is positively correlated with the total number.

[0079] However, Figure 7 each step has been described in detail above and will not be elaborated here. It should be noted that Figure 7 each step can be implemented as multiple pieces of program code or circuits, and the present invention does not limit this. In addition, Figure 7The method can be used in conjunction with the above exemplary embodiments or alone, and the present invention does not impose any restrictions.

[0080] In summary, the power management method and storage device proposed in the embodiments of the present invention can automatically match and / or switch the power mode of the storage device according to the current power state of the storage device. In addition, by dynamically adjusting the clock frequency and / or internal power distribution of the storage device, the power consumption per unit time corresponding to multiple power modes can be satisfied. Thus, the energy-saving performance of the storage device can be effectively improved without significantly affecting the working efficiency of the storage device.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A power management method, characterized in that, For a storage device, the power management method includes: Obtaining a first configuration instruction from a host system; In response to the first configuration instruction, controlling the storage device to be in an operable power state and setting the power mode of the storage device to a first low-power consumption power mode; and In the first low-power consumption power mode, adjusting the clock frequency of the storage device according to traffic information, where the traffic information reflects the total number of at least one pending instruction in the storage device, and the adjusted clock frequency is positively correlated with the total number.

2. The power management method according to claim 1, wherein in the first low-power consumption power mode, the step of adjusting the clock frequency of the storage device according to the traffic information includes: In the first low-power consumption power mode, comparing the total number with a standard number to obtain traffic evaluation data, where the traffic evaluation data reflects the numerical relative relationship between the total number and the standard number; And Adjusting the clock frequency of the storage device according to the traffic evaluation data.

3. The power management method according to claim 1, further includes: Detecting a first trigger event; And In response to the first trigger event, automatically switching the power mode of the storage device to a second low-power consumption power mode while the storage device is still in the operable power state, where the second unit time power consumption corresponding to the second low-power consumption power mode is lower than the first unit time power consumption corresponding to the first low-power consumption power mode.

4. The power management method according to claim 3, further includes: In the second low-power consumption power mode, detecting a second trigger event; And In response to the second trigger event, automatically restoring the power mode of the storage device to the first low-power consumption power mode.

5. The power management method according to claim 1, further includes: Obtaining a second configuration instruction from the host system; And In response to the second configuration instruction, controlling the storage device to be in an inoperable power state and setting the power mode of the storage device to a third low-power consumption power mode, where the third unit time power consumption corresponding to the third low-power consumption power mode is lower than the first unit time power consumption corresponding to the first low-power consumption power mode.

6. The power management method according to claim 5, further includes: In the inoperable power state, setting the power mode of the storage device to one of a plurality of sub-low-power consumption power modes in the third low-power consumption power mode according to the length of time the storage device is in an idle state, where the plurality of sub-low-power consumption power modes respectively correspond to different unit time power consumptions.

7. The power management method according to claim 6, wherein the multiple sub-low-power supply modes include a first sub-low-power supply mode and a second sub-low-power supply mode, and the step of setting the power mode of the storage device to one of the multiple sub-low-power supply modes in the third low-power supply mode according to the length of time the storage device is in the idle state includes: If the length of time the storage device is in the idle state is a first length of time, setting the power mode of the storage device to the first sub-low-power supply mode; And If the length of time the storage device is in the idle state is a second length of time, setting the power mode of the storage device to the second sub-low-power supply mode, wherein the second length of time is different from the first length of time, and the second sub-unit power consumption per unit time corresponding to the second sub-low-power supply mode is different from the first sub-unit power consumption per unit time corresponding to the first sub-low-power supply mode.

8. The power management method according to claim 1, further comprising: Dynamically adjusting at least one of the clock frequency and the internal power distribution of the storage device according to the current power mode of the storage device to change the power consumption per unit time of the storage device.

9. The power management method according to claim 8, wherein the storage device includes a plurality of circuit modules, and the step of dynamically adjusting at least one of the clock frequency and the internal power distribution of the storage device includes at least one of the following multiple operations: Adjusting the clock frequency of at least one first circuit module among the plurality of circuit modules; Stopping the operation of at least one second circuit module among the plurality of circuit modules; Stopping the power supply to at least one third circuit module among the plurality of circuit modules.

10. The power management method according to claim 9, wherein the plurality of circuit modules include at least two of a clock circuit module, a functional hardware module, a buffer module, and a memory module.

11. A storage device, characterized in that, Comprising: A connection interface for connecting to a host system; A memory module; And A memory controller connected to the connection interface and the memory module, wherein the memory controller is configured to: Obtain a first configuration instruction from the host system; In response to the first configuration instruction, control the storage device to be in an operable power state and set the power mode of the storage device to a first low-power supply mode; And In the first low-power supply mode, adjust the clock frequency of the storage device according to traffic information, wherein the traffic information reflects the total number of at least one pending instruction in the storage device, and the adjusted clock frequency is positively correlated with the total number.

12. The storage device according to claim 11, wherein the operation of the memory controller adjusting the clock frequency of the storage device according to the traffic information in the first low-power supply mode includes: In the first low-power supply mode, compare the total number with a standard number to obtain flow evaluation data, where the flow evaluation data reflects the numerical relative relationship between the total number and the standard number; and Adjust the clock frequency of the storage device according to the flow evaluation data.

13. The storage device according to claim 11, wherein the memory controller is further configured to: Detect a first trigger event; and In response to the first trigger event, automatically switch the power supply mode of the storage device to a second low-power supply mode while the storage device remains in the operable power state, wherein the second unit time power consumption corresponding to the second low-power supply mode is lower than the first unit time power consumption corresponding to the first low-power supply mode.

14. The storage device according to claim 13, wherein the memory controller is further configured to: In the second low-power supply mode, detect a second trigger event; and In response to the second trigger event, automatically restore the power supply mode of the storage device to the first low-power supply mode.

15. The storage device according to claim 11, wherein the memory controller is further configured to: Obtain a second configuration instruction from the host system; and In response to the second configuration instruction, control the storage device to be in an inoperable power state and set the power supply mode of the storage device to a third low-power supply mode, wherein the third unit time power consumption corresponding to the third low-power supply mode is lower than the first unit time power consumption corresponding to the first low-power supply mode.

16. The storage device according to claim 15, wherein the memory controller is further configured to: In the inoperable power state, set the power supply mode of the storage device to one of a plurality of sub-low-power supply modes in the third low-power supply mode according to the length of time the storage device is in an idle state, where the plurality of sub-low-power supply modes respectively correspond to different unit time power consumptions.

17. The storage device according to claim 16, wherein the plurality of sub-low-power supply modes include a first sub-low-power supply mode and a second sub-low-power supply mode, and the operation of the memory controller setting the power supply mode of the storage device to one of the plurality of sub-low-power supply modes in the third low-power supply mode according to the length of time the storage device is in the idle state includes: If the length of time the storage device is in the idle state is a first length of time, set the power supply mode of the storage device to the first sub-low-power supply mode; and If the length of time the storage device is in the idle state is a second length of time, set the power supply mode of the storage device to the second sub-low-power supply mode. The second time length is different from the first time length, and the power consumption per second sub-unit time corresponding to the second sub-low power consumption power mode is different from the power consumption per first sub-unit time corresponding to the first sub-low power consumption power mode.

18. The storage device according to claim 11, wherein the memory controller is further configured to: dynamically adjust at least one of the clock frequency and the internal power distribution of the storage device according to the current power mode of the storage device, so as to change the power consumption per unit time of the storage device.

19. The storage device according to claim 18, wherein the storage device includes a plurality of circuit modules, and the operation of the memory controller dynamically adjusting at least one of the clock frequency and the internal power distribution of the storage device includes at least one of the following operations: adjust the clock frequency of at least a first circuit module among the plurality of circuit modules; stop the operation of at least a second circuit module among the plurality of circuit modules; stop supplying power to at least a third circuit module among the plurality of circuit modules.

20. The storage device according to claim 19, wherein the plurality of circuit modules include at least two of a clock circuit module, a functional hardware module, a buffer module, and a memory module.

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