Sequencing circuit, sequencing control method, chip and terminal

Abstract

The invention discloses a sorting circuit, a sorting control method, a chip and a terminal, and belongs to the field of chips. The sorting circuit comprises a main selection unit, an auxiliary selection unit, a sorting unit and a data selection unit, and based on different selection signals received by the main selection unit, the auxiliary selection unit and the data selection unit, the sorting unit performs sorting according to a main sorting sequence selected by the main selection unit and an auxiliary sorting sequence selected by the auxiliary selection unit. Therefore, an ordered main sorting sequence and a sorted auxiliary sorting sequence are obtained, and at least one of the ordered main sorting sequence and the sorted auxiliary sorting sequence is output. The sequencing circuit can support sequencing of different functions, multiple sets of different sequencing circuits do not need to be used for achieving different sequencing functions, the sequencing circuit is applied to a chip, the area of the chip can be effectively reduced, and the winding complexity of the chip can be reduced.

Description

Technical Field

[0001] This application relates to the field of chips, and particularly to a sorting circuit, a sorting control method, a chip, and a terminal. Background Art

[0002] In the vector processing unit of a chip, stable sorting and vector compression are two very important functions. Stable sorting refers to the sorting function that does not change the relative positions of elements with equal keys in the sequence to be sorted. The elements in the sequence to be sorted include at least one sub-element, and the key is the sub-element used for sorting. Vector compression is a way to compress the valid data of vector data to the lowest consecutive several bits.

[0003] In the related art, a separate set of hardware implementation circuits is designed for each function respectively to achieve the purpose of providing the above two functions for the chip.

[0004] Although the above method can implement the above two functions for the chip, it will also increase the area of the chip. Therefore, how to design the implementation circuits of the above two functions so as to provide the functions of stable sorting and vector compression for the chip while not occupying too much chip area is a problem that needs to be solved currently. Summary of the Invention

[0005] This application provides a sorting circuit, a sorting control method, a chip, and a terminal. The technical solutions are as follows:

[0006] According to one aspect of this application, a sorting circuit is provided. The sorting circuit includes a main selection unit, an auxiliary selection unit, a sorting unit, and a data selection unit. The sorting unit includes a main sorting input end, an auxiliary sorting input end, a main sorting output end, and an auxiliary sorting output end. The main selection unit includes a first input end, a second input end, a first selection end, and a first output end. The first output end is connected to the main sorting input end. The auxiliary selection unit includes a third input end, a fourth input end, a second selection end, and a second output end. The second output end is connected to the auxiliary sorting input end. The data selection unit includes a fifth input end, a sixth input end, a third selection end, and a data output end. The main sorting output end is connected to the fifth input end. The auxiliary sorting output end is connected to the sixth input end.

[0007] The main selection unit is configured to output the main sorting sequence input from the first input end when the first selection signal is received at the first selection end, and output the main sorting sequence input from the second input end when the second selection signal is received at the first selection end.

[0008] The auxiliary selection unit is configured to output an auxiliary sorting sequence input from the third input terminal when the first selection signal is received at the second selection terminal; and output an auxiliary sorting sequence input from the fourth input terminal when the second selection signal is received at the second selection terminal.

[0009] The sorting unit is configured to receive the main sorting sequence and the auxiliary sorting sequence. The main sorting sequence includes at least two main sorting elements, and the auxiliary sorting sequence includes at least two auxiliary sorting elements. The auxiliary sorting elements and the main sorting elements correspond one by one according to their positions in the sequences. Based on the at least two main sorting elements, sort the at least two main sorting elements to obtain ordered at least two main sorting elements and sort the at least two auxiliary sorting elements to obtain sorted at least two auxiliary sorting elements. Based on the ordered at least two main sorting elements, obtain an ordered main sorting sequence, and based on the sorted at least two auxiliary sorting elements, obtain a sorted auxiliary sorting sequence.

[0010] The data selection unit is configured to output the ordered main sorting sequence input from the fifth input terminal when the first selection signal is received at the third selection terminal; and output the sorted auxiliary sorting sequence input from the sixth input terminal when the second selection signal is received at the third selection terminal.

[0011] According to one aspect of the present application, there is provided a sorting control method applied to the above sorting circuit. The method includes:

[0012] The main selection unit outputs the main sorting sequence input from the first input terminal when the first selection signal is received at the first selection terminal; and outputs the main sorting sequence input from the second input terminal when the second selection signal is received at the first selection terminal.

[0013] The auxiliary selection unit outputs the auxiliary sorting sequence input from the third input terminal when the first selection signal is received at the second selection terminal; and outputs the auxiliary sorting sequence input from the fourth input terminal when the second selection signal is received at the second selection terminal.

[0014] The sorting unit receives the main sorting sequence and the secondary sorting sequence. The main sorting sequence includes at least two main sorting elements, and the secondary sorting sequence includes at least two secondary sorting elements. The secondary sorting elements and the main sorting elements correspond one by one according to their positions in the sequences. Based on the at least two main sorting elements, the at least two main sorting elements are sorted to obtain at least two ordered main sorting elements, and the at least two secondary sorting elements are sorted to obtain at least two sorted secondary sorting elements. An ordered main sorting sequence is obtained based on the at least two ordered main sorting elements, and a sorted secondary sorting sequence is obtained based on the at least two sorted secondary sorting elements.

[0015] When the data selection unit receives the first selection signal at the third selection terminal, it outputs the ordered main sorting sequence input from the fifth input terminal. When the data selection unit receives the second selection signal at the third selection terminal, it outputs the sorted secondary sorting sequence input from the sixth input terminal.

[0016] According to one aspect of the present application, a chip is provided, and the chip includes the above sorting circuit.

[0017] According to one aspect of the present application, a terminal is provided, and the terminal includes the above chip.

[0018] The beneficial effects brought by the technical solution provided by the present application at least include:

[0019] A sorting circuit is designed. The sorting circuit can sort the main sorting sequence and the secondary sorting sequence according to the main sorting sequence. The elements in the main sorting sequence and the elements in the secondary sorting sequence correspond one by one. The input main sorting sequence and secondary sorting sequence are selected through the selection signals received at the first selection terminal and the second selection terminal, so that the sorting circuit can realize different sorting functions without using multiple different sorting circuits to realize different sorting functions. Applying this sorting circuit in a chip can effectively reduce the area of the chip and also reduce the wiring complexity of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0021] Figure 1 Shows a schematic diagram of a stable sorting method in the related art;

[0022] Figure 2Shows a schematic diagram of a vector compression method in the related art;

[0023] Figure 3 Shows a schematic structural diagram of a sorting circuit provided by an exemplary embodiment of the present application;

[0024] Figure 4 Shows a schematic structural diagram of a comparison unit provided by an exemplary embodiment of the present application;

[0025] Figure 5 Shows a schematic diagram of a position information number provided by an exemplary embodiment of the present application;

[0026] Figure 6 Shows a schematic diagram of a sorting network provided by an exemplary embodiment of the present application;

[0027] Figure 7 Shows a schematic diagram of a sorting control method provided by an exemplary embodiment of the present application;

[0028] Figure 8 Shows a schematic diagram of a sorting control method provided by an exemplary embodiment of the present application;

[0029] Figure 9 Shows a schematic diagram of a sorting control method provided by an exemplary embodiment of the present application;

[0030] Figure 10 Shows a schematic diagram of a sorting network provided by an exemplary embodiment of the present application;

[0031] Figure 11 Shows a schematic diagram of a sorting network provided by an exemplary embodiment of the present application;

[0032] Figure 12 Shows a schematic diagram of a sorting network provided by an exemplary embodiment of the present application;

[0033] Figure 13 Shows a schematic structural diagram of a terminal provided by an exemplary embodiment of the present application. Detailed implementation manners

[0034] To make the objectives, technical solutions and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

[0035] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0036] The terms used in this disclosure are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. The singular forms "a", "the", and "that" used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0037] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use, and processing of relevant data need to comply with the relevant laws, regulations, and standards of relevant countries and regions. For example, the information such as setting operations involved in this application is obtained under full authorization.

[0038] It should be understood that although the terms first, second, etc. may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this disclosure, the first parameter may also be referred to as the second parameter, and similarly, the second parameter may also be referred to as the first parameter. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining".

[0039] First, introduce the relevant terms involved in this application:

[0040] Stable sorting function: It refers to the sorting function that does not change the relative positions of elements with equal keys in the sequence to be sorted. The elements in the sequence to be sorted include at least one sub-element, and the key is the sub-element used for sorting. That is, there may be two or more elements with equal keys in the sequence to be sorted. In the sequence before sorting, if the first element is before the second element before sorting, then the first element should still be before the second element after sorting, that is, the relative positions of elements with equal keys remain unchanged after sorting. Among them, the first element and the second element are elements with equal keys. Stable sorting is a classification method of sorting algorithms. Corresponding to it is unstable sorting. Common stable sorting algorithms include bubble sort, insertion sort, merge sort, etc. Unstable sorting algorithms include selection sort, quick sort, shell sort, heap sort, etc.

[0041] The stable sorting function is as follows Figure 1 shown. The elements in the sequence to be sorted are vectors, and each vector includes two sub-elements, namely vector data and vector index. Among them, the vector data sequence before sorting is {5.0, 2.0, 1.0, 1.0, 4.0, 1.0, 3.0, 2.0}, and the vector index sequence before sorting is {1, 0, 2, 5, 3, 4, 6, 7}. In the stable sorting function of this scenario, the key used for sorting is the vector data. To better display the result of stable sorting, permutation information is introduced to identify the position information in the initial situation, that is, the position information of each element in the sequence to be sorted, and this position information is arranged in ascending order from right to left. Using the stable sorting function on this vector, where the result of this stable sorting function is in ascending order from right to left. It can be seen that in the stable sorting result, the relative positions of vectors with the same vector data do not change. That is, in the permutation information corresponding to the vector with vector data 2.0, it is still arranged in ascending order from right to left. It can be understood that the vector with permutation information 6 is still on the left of the vector with permutation information 0. In the permutation information corresponding to the vector with vector data 1.0, it is still arranged in ascending order from right to left. It can be understood that the vector with permutation information 5 is on the left of the vector with permutation information 4, and the vector with permutation information 4 is on the left of the vector with permutation information 2.

[0042] Vector compression function: It refers to the method of compressing the valid data of vector data to the lowest consecutive several bits. The source data of the vector compression function is usually a vector, and the vector includes two sub-elements, namely vector data and vector mask. The vector mask is used to indicate whether the vector data is valid data or invalid data. A mask of 1 indicates that the corresponding vector data is valid data; a mask of 0 indicates that the corresponding vector data is invalid data.

[0043] The vector compression function is as Figure 2 shown. In the chip, the bit representation of vector data is as Figure 2As shown, from right to left, they are from the low bit to the high bit in sequence. If the bit width of an element in the vector data sequence is 32, that is, the bit width of a vector data is 32, then the vector data d0 is in the 0 - 31st bits of the vector data sequence. Thus, the positions of d0 to d7 in the vector data can be deduced in turn. The vector compression function is to compress the valid data to the lowest consecutive several bits of the vector data sequence, that is, to compress the vector data d7, d5, d2, and d0 with the vector mask being 1 to the lowest consecutive several bits of the vector data sequence.

[0044] In the vector processing unit of the chip, the above two functions are called by means of instructions.

[0045] The instruction for the stable sorting function is: vsort vd1, vd2, vs1, vs2

[0046] Among them, vs1 is the input 256 - bit source vector data to be sorted, that is, the above - mentioned vector data sequence to be sorted, vs2 is the index information corresponding to the vs1 source vector data, that is, the above - mentioned vector index sequence to be sorted. The elements of the vs1 and vs2 source vectors are both 32 - bit, that is, one vector data is 32 - bit and one vector index is also 32 - bit. Therefore, there are a total of 8 elements; vd1 is the output 256 - bit sorted result vector data, that is, the sorted vector data sequence, and vd2 is the index information corresponding to the sorted result vd2, that is, the sorted vector index sequence.

[0047] The instruction for the vector compression function is: vsqz vd, vs, pn

[0048] Among them, vs is the input 256 - bit source vector data, that is, the vector data sequence, pn is the 8 - bit mask source data corresponding to the source vector elements (each mask represents whether the corresponding data element is valid), that is, the vector mask sequence, and vd is the output 256 - bit result vector data, that is, the compressed vector data sequence.

[0049] Artificial Intelligence (AI): It is the theory, method, technology, and application system that uses digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use knowledge to obtain the best results. In other words, artificial intelligence is a comprehensive technology in computer science that attempts to understand the essence of intelligence and produce a new intelligent machine that can react in a way similar to human intelligence. Artificial intelligence also studies the design principles and implementation methods of various intelligent machines to enable machines to have the functions of perception, reasoning, and decision-making. Artificial intelligence technology is an interdisciplinary subject with a wide range of fields, including both hardware-level and software-level technologies. The basic technologies of artificial intelligence generally include sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technology, pre-trained model technology, operation / interaction systems, mechatronics, etc. Among them, the pre-trained model, also known as the large model or the foundation model, can be widely applied to downstream tasks in various directions of artificial intelligence after fine-tuning. The software technologies of artificial intelligence mainly include several major directions such as computer vision technology, speech processing technology, natural language processing technology, and machine learning / deep learning. With the research and progress of artificial intelligence technology, artificial intelligence technology has been studied and applied in multiple fields. For example, common ones include smart homes, smart wearable devices, virtual assistants, smart speakers, smart marketing, driverless, autonomous driving, drones, digital twins, virtual humans, robots, Artificial Intelligence Generated Content (AIGC), conversational interaction, intelligent healthcare, intelligent customer service, game AI, etc. It is believed that with the development of technology, artificial intelligence technology will be applied in more fields and play an increasingly important role.

[0050] Figure 3 FIG. shows a schematic structural diagram of a sorting circuit 100 provided by an exemplary embodiment of the present application. The sorting circuit 100 includes: a main selection unit 10, an auxiliary selection unit 20, a sorting unit 30, and a data selection unit 40; the sorting unit 30 includes a main sorting input terminal 31, an auxiliary sorting input terminal 32, a main sorting output terminal 33, and an auxiliary sorting output terminal 34; the main selection unit 10 includes a first input terminal 11, a second input terminal 12, a first selection terminal 13, and a first output terminal 14; the first output terminal 14 is connected to the main sorting input terminal 31; the auxiliary selection unit 20 includes a third input terminal 21, a fourth input terminal 22, a second selection terminal 23, and a second output terminal 24; the second output terminal 24 is connected to the auxiliary sorting input terminal 32; the data selection unit 40 includes a fifth input terminal 41, a sixth input terminal 42, a third selection terminal 43, and a data output terminal 44; the main sorting output terminal 33 is connected to the fifth input terminal 41; the auxiliary sorting output terminal 34 is connected to the sixth input terminal 42.

[0051] The main selection unit 10 is configured to output the main sorting sequence input from the first input terminal 11 when the first selection signal is received at the first selection terminal 14; and output the main sorting sequence input from the second input terminal 12 when the second selection signal is received at the first selection terminal 14;

[0052] In some embodiments, the selection signals that the first selection terminal can receive include a first selection signal and a second selection signal. For example, the selection signal is a 1-bit binary number; the first selection signal is 0 and the second selection signal is 1; or, the first selection signal is 1 and the second selection signal is 0. The selection signal is a 2-bit binary number, and the selection signal includes at least a first selection signal and a second selection signal; the first selection signal is 00, the second selection signal is 11; or, the first selection signal is 11, the second selection signal is 00; or, the first selection signal is 00, the second selection signal is 10; or, the first selection signal is 00, the second selection signal is 01. Regarding the number of bits of the selection signal and the values of the first selection signal and the second selection signal, the embodiments of the present application will not be listed one by one, but the protection scope of the embodiments of the present application is not limited thereto.

[0053] The auxiliary selection unit 20 is configured to output the auxiliary sorting sequence input from the third input terminal 21 when the first selection signal is received at the second selection terminal 23; and output the auxiliary sorting sequence input from the fourth input terminal 22 when the second selection signal is received at the second selection terminal 23;

[0054] In some embodiments, the function of the auxiliary selection unit 20 is similar to that of the main selection unit 10, and will not be elaborated here.

[0055] In some embodiments, the sorting circuit can be understood to have four input terminals, namely the first input terminal and the second input terminal of the main selection unit, and the third input terminal and the fourth input terminal of the auxiliary selection unit. The main sorting sequence to be sorted is received according to the selection signal received at the first selection terminal, and the auxiliary sorting sequence to be sorted is received according to the selection signal received at the second selection terminal.

[0056] The sorting unit 30 is configured to receive the main sorting sequence and the auxiliary sorting sequence. The main sorting sequence includes at least two main sorting elements, and the auxiliary sorting sequence includes at least two auxiliary sorting elements. The auxiliary sorting elements and the main sorting elements correspond one by one according to the positions of the elements in the sequence; based on at least two main sorting elements, at least two main sorting elements are sorted to obtain at least two ordered main sorting elements and at least two auxiliary sorting elements are sorted to obtain at least two sorted auxiliary sorting elements; an ordered main sorting sequence is obtained based on the at least two ordered main sorting elements, and a sorted auxiliary sorting sequence is obtained based on the at least two sorted auxiliary sorting elements;

[0057] Exemplarily, the main sorting sequence is a 256-bit binary sequence. The bit width of each main sorting element in the main sorting sequence is 32 bits, so the main sorting sequence includes 8 main sorting elements.

[0058] In some embodiments, the secondary sorting elements and the main sorting elements correspond one by one according to their positions in the sequence, that is, the i-th main sorting element in the main sorting sequence corresponds to the i-th secondary sorting element in the secondary sorting sequence. Exemplarily, the main sorting sequence is an 8-bit binary sequence, and the bit width of each main sorting element in the main sorting sequence is 1; the secondary sorting sequence is a 256-bit binary sequence, and the bit width of each secondary sorting element in the secondary sorting sequence is 32; or, the main sorting sequence is a 256-bit binary sequence, the bit width of each main sorting element in the main sorting sequence is 32; the secondary sorting sequence is a 256-bit binary sequence, and the bit width of each secondary sorting element in the secondary sorting sequence is 32; that is, both the main sorting sequence and the secondary sorting sequence include 8 elements.

[0059] When the main sorting sequence is an 8-bit binary sequence, the bit width of each main sorting element in the main sorting sequence is 1, and the secondary sorting sequence is a 256-bit binary sequence, and the bit width of each secondary sorting element in the secondary sorting sequence is 32, the 1st main sorting element in the main sorting sequence corresponds to the 1st secondary sorting element in the secondary sorting sequence, that is, the main sorting element at the 0th bit in the main sorting sequence corresponds to the secondary sorting elements at the 0-31st bits in the secondary sorting sequence; the 2nd main sorting element in the main sorting sequence corresponds to the 2nd secondary sorting element in the secondary sorting sequence, that is, the main sorting element at the 1st bit in the main sorting sequence corresponds to the secondary sorting elements at the 32-63rd bits in the secondary sorting sequence; and so on, the 8th main sorting element in the main sorting sequence corresponds to the 8th secondary sorting element in the secondary sorting sequence, that is, the main sorting element at the 8th bit in the main sorting sequence corresponds to the secondary sorting elements at the 223(7*32 - 1)-255(8*32 - 1)th bits in the secondary sorting sequence.

[0060] In some embodiments, based on at least two main sorting elements, sorting at least two main sorting elements to obtain at least two ordered main sorting elements and sorting at least two secondary sorting elements to obtain at least two sorted secondary sorting elements can be understood as sorting at least two main sorting elements to obtain at least two ordered main sorting elements. During the sorting process, when the main sorting elements change positions, their corresponding secondary sorting elements will also change positions accordingly. Among them, the at least two ordered main sorting elements and the at least two sorted secondary sorting elements still correspond one by one.

[0061] Exemplarily, the main sorting sequence is a 256-bit binary sequence, and the bit width of each main sorting element in the main sorting sequence is 32; the secondary sorting sequence is a 256-bit binary sequence, and the bit width of each secondary sorting element in the secondary sorting sequence is 32; both the main sorting sequence and the secondary sorting sequence include 8 elements. Both the main sorting elements and the secondary sorting elements are represented in decimal numerical form. It is known that there are 8 main sorting elements which are {10, 45, 26, 42, 8, 63, 56, 71} respectively, and there are 8 secondary sorting elements which are {1, 0, 2, 5, 3, 4, 6, 7} respectively. The 8 main sorting sequences and the 8 secondary sorting sequences correspond one by one. For example, the main sorting element 10 corresponds to the secondary sorting element 1; the main sorting element 45 corresponds to the secondary sorting element 0; the main sorting element 26 corresponds to the secondary sorting element 2; the main sorting element 26 corresponds to the secondary sorting element 5, etc.; the sorting rule is to sort the main sorting elements in ascending order from left to right. Then the 8 sorted main sorting elements can be obtained as {8, 10, 26, 42, 45, 56, 63, 71} respectively, and the 8 sorted secondary sorting elements can be obtained as {3, 1, 2, 5, 0, 6, 4, 7} respectively. During the sorting process, when the position of the main sorting element changes, the position of its corresponding secondary sorting element will also change accordingly.

[0062] Optionally, the main sorting output terminal 33 of the sorting unit 30 is used to output the ordered main sorting sequence; the secondary sorting output terminal 34 of the sorting unit 30 is used to output the sorted secondary sorting sequence.

[0063] The data selection unit 40 is configured to output the ordered main sorting sequence input from the fifth input terminal 41 when the first selection signal is received at the third selection terminal 43; and output the sorted secondary sorting sequence input from the sixth input terminal 42 when the second selection signal is received at the third selection terminal 43.

[0064] In some embodiments, the selection signals received by the first selection terminal 13, the second selection terminal 23, and the third selection terminal 43 are the same selection signal. One selection signal is used to indicate the function of a sorting circuit. For example, the first selection terminal 13, the second selection terminal 23, and the third selection terminal 43 all receive the first selection signal; or, the first selection terminal 13, the second selection terminal 23, and the third selection terminal 43 all receive the second selection signal.

[0065] In some embodiments, the selection signals received by the first selection terminal 13, the second selection terminal 23, and the third selection terminal 43 are different selection signals, and the combination of the selection signals received by the first selection terminal 13, the second selection terminal 23, and the third selection terminal 43 is used to indicate the function of a sorting circuit. For example, the selection signal is a 1-bit binary number, and the correspondence between the combination of the selection signals received by the first selection terminal 13, the second selection terminal 23, and the third selection terminal 43 and the function of the sorting circuit is shown in Table 1. At this time, up to 8 selection signals can be combined, that is, up to 8 functions of the sorting circuit can be indicated. For example, the sorting circuit can implement 3 functions, and the combination of the selection signals received by the first selection terminal 13, the second selection terminal 23, and the third selection terminal 43 is any three of the 8 combinations shown in Table 1.

[0066] Optionally, the number of bits of the selection signals received by the first selection terminal 13, the second selection terminal 23, and the third selection terminal 43 is different. For example, the selection signals received by the first selection terminal 13 and the second selection terminal 23 are 1-bit, and the selection signal received by the third selection terminal 43 is 2-bit.

[0067] It should be noted that the embodiments of the present application do not list one by one the number of bits of the selection signal, the number of functions that the sorting circuit can implement, and the correspondence between the selection signal and the function of the sorting circuit, but the protection scope of the embodiments of the present application is not limited thereto.

[0068] Table 1 Correspondence table between the combination of selection signals and the functions of the sorting circuit

[0069]

[0070] Optionally, the functions of the sorting circuit at least include a stable sorting function and a vector compression function. The selection signals at least include a first selection signal and a second selection signal.

[0071] In some embodiments, the first selection signal is used to indicate the stable sorting function. When the first selection signal is received by the first selection terminal 13, the first input terminal 11 of the main selection unit 10 is used to receive the vector data sequence; when the first selection signal is received by the second selection terminal 23, the third input terminal 21 of the auxiliary selection unit 20 is used to receive the vector index sequence; when the first selection signal is received by the third selection terminal 43, the data output terminal 44 of the data selection unit 40 is used to output the ordered vector data sequence output by the main sorting output terminal 33 of the sorting unit 30.

[0072] In some embodiments, the second selection signal is used to indicate the vector compression function. When the first selection terminal 13 receives the second selection signal, the second input terminal 12 of the main selection unit 10 is used to receive the vector mask sequence; when the second selection terminal 23 receives the second selection signal, the fourth input terminal 22 of the auxiliary selection unit 20 is used to receive the vector data sequence; when the third selection terminal 43 receives the second selection signal, the data output terminal of the data selection unit 40 is used to output the sorted vector data sequence output from the auxiliary sorting output terminal 34 of the sorting unit 30. The elements in the vector mask sequence are used to indicate whether the elements in the vector data sequence are valid data or invalid data. For example, a vector mask element of 1 indicates that the corresponding vector data element is valid data, and a vector mask element of 0 indicates that the corresponding vector data element is invalid data; or, a vector mask element of 1 indicates that the corresponding vector data element is invalid data, and a vector mask element of 0 indicates that the corresponding vector data element is valid data. In this application, it is exemplified that a vector mask element of 1 indicates that the corresponding vector data element is valid data, and a vector mask element of 0 indicates that the corresponding vector data element is invalid data, but this is not limited thereto.

[0073] In some embodiments, the sorting circuit further includes an index output terminal 50, and the index output terminal 50 is connected to the auxiliary sorting output terminal of the sorting unit 30. The index output terminal 50 is used to output the sorted auxiliary sorting sequence. The first selection signal is used to indicate the stable sorting function. When the second selection terminal 23 receives the first selection signal, the fourth input terminal 22 of the auxiliary selection unit 20 is used to receive the vector data sequence, and the index output terminal 50 is used to output the sorted vector data sequence; the second selection signal is used to indicate the vector compression function. When the second selection terminal 23 receives the second selection signal, the fourth input terminal 22 of the auxiliary selection unit 20 is used to receive the vector data sequence, and the index output terminal 50 is used to output the sorted vector data sequence.

[0074] In some embodiments, the sorting circuit can be understood as including two output terminals, one is the data output terminal 44 of the data selection unit 40, and the other is the index output terminal 50. The index output terminal 50 is connected to the auxiliary sorting output terminal 34 of the sorting unit 30 and is used to output the sorted auxiliary sorting sequence; the data selection unit 40 outputs the sorting sequence according to the selection signal received by the third selection terminal 43. When the third selection terminal 43 receives the first selection signal, it outputs the ordered main sorting sequence input from the fifth input terminal 41; when the third selection terminal 43 receives the second selection signal, it outputs the sorted auxiliary sorting sequence input from the sixth input terminal 42. It can be understood that the sorting circuit outputs the sorted auxiliary sorting sequence at both output terminals based on the selection signal; or, outputs the ordered main sorting sequence and the sorted auxiliary sorting sequence at the two output terminals respectively.

[0075] In summary, the sorting circuit provided by the embodiment of the present application can sort the main sorting sequence and the secondary sorting sequence according to the main sorting sequence. The elements in the main sorting sequence correspond one by one to the elements in the secondary sorting sequence. The input main sorting sequence and secondary sorting sequence are selected through the selection signals received by the first selection end and the second selection end, so that the sorting circuit can implement different sorting functions without using multiple different sorting circuits to implement different sorting functions. Applying this sorting circuit in a chip can effectively reduce the area of the chip and also reduce the wiring complexity of the chip. Since the sorting circuit realizes the multifunctional multiplexing sorting unit by adding a selection unit, the selection unit is simple to implement and can reduce the overhead and complexity of sorting unit multiplexing. At the same time, the first selection signal indicates the stable sorting function, the second selection signal indicates the vector compression function, and the sequences output by the main selection unit and the secondary selection unit are different for different functions, so that the stable sorting function and the vector compression function can share a sorting circuit well. And the above sorting function can also be a non-sorting function similar to the vector compression function that can be implemented by a sorting method.

[0076] In some embodiments, the sorting unit 30 includes at least one comparison unit 60. Each comparison unit 60 includes a first main sorting input end 611, a first secondary sorting input end 612, a first position input end 613, a second main sorting input end 621, a second secondary sorting input end 622, a second position input end 623, a first main sorting output end 631, a first secondary sorting output end 632, a first position output end 633, a second main sorting output end 641, a second secondary sorting output end 642, and a second position output end 643; the first main sorting input end 611 and the second main sorting input end 621 are used for inputting two main sorting elements to be compared; the first secondary sorting input end 612 and the second secondary sorting input end 622 are used for inputting two secondary sorting elements to be compared; the first position input end 613 and the second position input end 623 are used for inputting the position information of the two main sorting elements to be compared and the two secondary sorting elements to be compared in the sequence.

[0077] The comparison unit 60 is configured to receive two main sorting elements to be compared and two secondary sorting elements to be compared, and receive the position information of the two main sorting elements to be compared and the two secondary sorting elements to be compared in the sequence. The secondary sorting elements and the main sorting elements correspond one by one according to the position of the elements in the sequence; perform stable sorting on the elements to be sorted according to the main sorting elements and the corresponding position information of the main sorting elements. The elements to be sorted include the main sorting elements and the secondary sorting elements corresponding to the main sorting elements. The stable sorting is performed with the main sorting elements as the main key and the position information as the secondary key. The main key is used to indicate the main key for performing stable sorting, and the secondary key is used to indicate the secondary key for sorting when the main keys are equal.

[0078] In some embodiments, the sorting unit 30 obtains the position information of at least two primary sorting elements in the primary sorting sequence before sorting, and obtains the position information of at least two secondary sorting elements in the secondary sorting sequence before sorting. Optionally, the above position information is numbered from right to left, or numbered from left to right. Since the secondary sorting elements and the primary sorting elements correspond one by one according to the positions of the elements in the sequence, the position information of the corresponding two secondary sorting elements and the primary sorting elements is the same. As Figure 5 shown, the primary sorting sequence is split into at least two primary sorting elements, and the secondary sorting sequence is split into at least two secondary sorting elements. According to the one-to-one correspondence of the primary sorting elements and the secondary sorting elements in the sequence, Figure 5 the at least two primary sorting elements and secondary sorting elements in part (1) as shown are obtained. The primary sorting elements and the secondary sorting elements are numbered to obtain position information, as Figure 5 the position information numbered from left to right shown in part (2) of Figure 5 is shown. The position information numbered from right to left is shown in part (3) of

[0079] In some embodiments, the comparison unit 60 is used to perform stable sorting on two elements to be sorted, and the elements to be sorted include a primary sorting element and its corresponding secondary sorting element. As Figure 5 shown in part (1) of

[0080] the elements to be sorted can be any one of {5.0, 1}, {2.0, 0}, {1.0, 2}, {1.0, 5}, {4.0, 3}, {1.0, 4}, {3.0, 6}, {2.0, 7}. When the comparison unit 60 performs sorting, it is stable sorting. And during stable sorting, the primary sorting element is used as the main key word, and the position information is used as the secondary key word for sorting. That is, when comparing, first compare the sizes of the primary sorting elements. If the sizes of the primary sorting elements of two elements to be sorted are different, then sort according to the sizes of the primary sorting elements; if the sizes of the primary sorting elements of two elements to be sorted are the same, then sort according to the secondary key word, that is, the size of the position information. Since the position information of each element to be sorted is different, and the position information can represent the position of the element to be sorted in the initial situation, sorting according to the position information when the main key word, that is, the primary sorting element, is equal, can ensure that the finally obtained sorting result meets the requirements of stable sorting, that is, the relative positions of the elements with equal key words in the sequence to be sorted will not be changed during sorting.

[0081] For example, Figure 5 The position information and elements to be sorted shown in part (2) are given as examples. The comparison target of the comparison unit 60 is to output the smaller element from the first main sort output terminal 631, the first auxiliary sort output terminal 632, and the first position output terminal 633, and output the larger element from the second main sort output terminal 641, the second auxiliary sort output terminal 642, and the second position output terminal 643; the two elements to be sorted received by the input terminal of the first comparison unit 60 are {5.0, 1} and {4.0, 3}, that is, the main sort element received by the first main sort input terminal 611 is 5.0, the auxiliary sort element received by the first auxiliary sort input terminal 612 is 1, the position information received by the first position input terminal 613 is 0, the main sort element received by the second main sort input terminal 621 is 4.0, the auxiliary sort element received by the second auxiliary sort input terminal 622 is 3, and the position information received by the second position input terminal 623 is 4. First, based on the primary key, a comparison is performed, and 5.0>4.0 is found. Therefore, the elements to be sorted are {5.0, 1}>{4.0, 3}. The first primary sort output terminal 631 outputs 4.0, the first auxiliary sort output terminal 632 outputs 3, and the first position output terminal 633 outputs 4. The second primary sort output terminal 641 outputs 5.0, the second auxiliary sort output terminal 642 outputs 1, and the second position output terminal 643 outputs 0. Alternatively, the two elements to be sorted received at the input terminals of the first comparison unit 60 are {1.0, 4} and {1.0, 5}, respectively. That is, the primary sort element received by the first primary sort input terminal 611 is 1.0, the auxiliary sort element received by the first auxiliary sort input terminal 612 is 4, the position information received by the first position input terminal 613 is 5, the primary sort element received by the second primary sort input terminal 621 is 1.0, the auxiliary sort element received by the second auxiliary sort input terminal 622 is 5, and the position information received by the second position input terminal 623 is 3. First, compare the primary keyword 1.0=1.0, and compare the secondary keywords, 5>3, that is, the elements to be sorted are {1.0, 4}>{1.0, 5}, the first primary sorting output terminal 631 outputs 1.0, the first secondary sorting output terminal 632 outputs 5, and the first position output terminal 633 outputs 3, the second primary sorting output terminal 641 outputs 1.0, the second secondary sorting output terminal 642 outputs 4, and the second position output terminal 643 outputs 5.

[0082] Taking ascending order sorting as an example, there are the following two cases where the comparison unit 60 needs to perform data exchange. Ascending order sorting can be understood as outputting smaller elements from the first main sorting output terminal 631, the first auxiliary sorting output terminal 632, and the first position output terminal 633, and outputting larger elements from the second main sorting output terminal 641, the second auxiliary sorting output terminal 642, and the second position output terminal 643. Data exchange can be understood as the element input from the first main sorting input terminal 611 is not output from the first main sorting output terminal 631 but from the second main sorting output terminal 641, the element input from the first auxiliary sorting input terminal 612 is not output from the first auxiliary sorting output terminal 632 but from the second auxiliary sorting output terminal 642, and the element input from the first position input terminal 613 is not output from the first position output terminal 633 but from the second position output terminal 643.

[0083] · The element input from the second main sorting input terminal 621 (din_b) < the element input from the first main sorting input terminal 611 (din_a).

[0084] · The element input from the second main sorting input terminal 621 (din_b) is equal to the element input from the first main sorting input terminal 611 (din_a), and the element input from the second position input terminal 623 (loc_b_i) < the element input from the first position input terminal 613 (loc_a_i).

[0085] If the comparison unit 60 performs exchange according to the exchange signal swap_en, when swap_en = 1, it indicates that an exchange is required, and when swap_en = 0, it indicates that no exchange is required. The logical expression of swap_en at this time is as follows.

[0086] swap_en = (din_b < din_a) | (din_b == din_a) & (loc_b_i < loc_a_i)

[0087] In the formula, "|" represents the OR operation, "&" represents the AND operation, and "==" represents the judgment formula for two elements to be equal.

[0088] The comparison unit sets the output value according to the exchange signal swap_en, and the corresponding output judgment logical expression is as follows.

[0089] dout_a = swap_en? din_b : din_a;

[0090] idx_a_o = swap_en? idx_b_i : idx_a_i;

[0091] loc_a_o = swap_en? loc_b_i : loc_a_i;

[0092] dout_b = swap_en? din_a : din_b;

[0093] idx_b_o = swap_en? idx_a_i : idx_b_i;

[0094] loc_b_o = swap_en? loc_a_i : loc_b_i.

[0095] Among them, s? a : b is a ternary operation expression. When the value of s is true (usually represented as 1 or true), the result of s? a : b is a; when the value of s is false (usually represented as 0 or false), the result of s? a : b is b.

[0096] In summary, the sorting circuit provided by the embodiments of the present application designs the structure and comparison logic of the comparison unit that constitutes the sorting unit, so as to enable the comparison unit to perform stable sorting. On the basis that the comparison unit can perform stable sorting, it provides a certain guarantee for the sorting unit to achieve stable sorting.

[0097] In some embodiments, the sorting unit 30 includes at least one comparison unit 60, that is, the sorting unit realizes the sorting function through at least one comparison unit 60. Optionally, the sorting method used by the sorting unit 30 is a sorting network, and the sorting network is at least one of a bitonic sorting network and a parity sorting network. The sorting network is a sorting method suitable for hardware circuit implementation. The sorting process of the sorting network can be split into multiple comparison processes. The execution of each comparison process has a fixed order, and when there are no common elements to be compared between different comparison processes, these comparison processes can be parallel, thereby improving the sorting speed. Next, an example is given using an eight-input parity sorting network for the sorting unit 30. The sorting logic diagram of the eight-input parity sorting network is as Figure 6As shown in the figure. Among them, din0-din7 on the far left represent the 8 elements to be sorted in the input sorting network, and dout0-dout7 represent the 8 ordered elements output by the sorting network; each vertical solid line corresponds to a comparison and exchange process, and whether to perform an exchange is determined according to the sorting target of the odd-even sorting network. For example, when the sorting target is ascending from bottom to top, the end pointed by the arrow is the position where the smaller element is located after each comparison and exchange process, and the end without an arrow represents the position where the larger element is located after each comparison and exchange process; or, when the sorting target is descending from bottom to top, the end pointed by the arrow is the position where the larger element is located after each comparison and exchange process, and the end without an arrow represents the position where the smaller element is located after each comparison and exchange process. The sorting of eight elements requires six stages of comparison and exchange processes, and the comparison and exchange processes in each stage can be executed simultaneously because there will be no data conflicts. In addition to the above eight-input odd-even sorting network, according to the specific design of the sorting unit 30, the sorting network can also be at least one of a two-input sorting network, a four-input sorting network, and a sixteen-input sorting network.

[0098] Among them, each comparison and exchange process in the sorting network is executed by the above-mentioned comparison unit 60, that is, each vertical solid line in the sorting network represents a comparison unit 60, and the elements at both ends of the vertical solid line are the two elements to be sorted and their position information in the comparison unit 60. It can also be said that the sorting process in the sorting network is executed by at least one comparison unit.

[0099] Figure 7 The figure shows a schematic diagram of a sorting control method provided by an exemplary embodiment of the present application. This method is applied to a sorting circuit as shown in Figures 3 to 6 any one of them, and the method includes:

[0100] Step 1, when the main selection unit 10 receives the first selection signal at the first selection terminal 13, it outputs the main sorting sequence 1 input from the first input terminal 11; when the main selection unit 10 receives the second selection signal at the first selection terminal 13, it outputs the main sorting sequence 2 input from the second input terminal 12.

[0101] In some embodiments, step 1 performs the functions executed by the above-mentioned main selection unit 10, which will not be elaborated here.

[0102] Step 2, when the auxiliary selection unit 20 receives the first selection signal at the second selection terminal 23, it outputs the auxiliary sorting sequence 1 input from the third input terminal 21; when the auxiliary selection unit 20 receives the second selection signal at the second selection terminal 23, it outputs the auxiliary sorting sequence input from the fourth input terminal 22.

[0103] In some embodiments, step 2 performs the functions executed by the above-mentioned auxiliary selection unit, which will not be elaborated here.

[0104] Step 3: The sorting unit 30 receives a primary sorting sequence and a secondary sorting sequence. The primary sorting sequence includes at least two primary sorting elements, and the secondary sorting sequence includes at least two secondary sorting elements. The secondary sorting elements and the primary sorting elements correspond to each other one by one according to their positions in the sequence. Based on the at least two primary sorting elements, the at least two primary sorting elements are sorted to obtain the ordered at least two primary sorting elements, and the at least two secondary sorting elements are sorted to obtain the sorted at least two secondary sorting elements. An ordered primary sorting sequence is obtained based on the ordered at least two primary sorting elements, and a sorted secondary sorting sequence is obtained based on the sorted at least two secondary sorting elements.

[0105] In some embodiments, step 3 performs the functions executed by the above-mentioned sorting unit, which will not be elaborated here.

[0106] Optionally, after sorting, the sorting unit 30 outputs the ordered primary sorting sequence through the primary sorting output terminal and outputs the sorted secondary sorting sequence through the secondary sorting output terminal.

[0107] Optionally, the sorting unit 30 includes at least one comparison unit 60.

[0108] In some embodiments, the comparison unit 60 receives two primary sorting elements to be compared and two secondary sorting elements to be compared, and also receives the position information of the two primary sorting elements to be compared and the two secondary sorting elements to be compared in the sequence. The secondary sorting elements and the primary sorting elements correspond to each other one by one according to their positions in the sequence. According to the primary sorting elements and the corresponding position information, stable sorting is performed on the elements to be sorted. The elements to be sorted include the primary sorting elements and the secondary sorting elements corresponding to the primary sorting elements. The stable sorting is performed with the primary sorting elements as the main key and the position information as the secondary key. The main key is used to indicate the main key for performing stable sorting, and the secondary key is used to indicate the secondary key for sorting when the main keys are equal. This step is similar to the functions executed by the above-mentioned sorting unit and will not be elaborated here.

[0109] Step 4: When the data selection unit 40 receives a first selection signal at the third selection terminal 43, it outputs the ordered primary sorting sequence input from the fifth input terminal 41; when it receives a second selection signal at the third selection terminal 43, it outputs the sorted secondary sorting sequence input from the sixth input terminal 42.

[0110] In some embodiments, step 4 performs the functions executed by the above-mentioned data selection unit 40, which will not be elaborated here.

[0111] In some embodiments, such as Figure 8As shown, the first selection signal is used to indicate the stable sorting function. When the main selection unit 10 receives the first selection signal at the first selection terminal 13, it outputs the vector data sequence input from the first input terminal 11. When the auxiliary selection unit 20 receives the first selection signal at the second selection terminal 23, it outputs the vector index sequence input from the third input terminal 21. When the data selection unit 40 receives the first selection signal at the third selection terminal 43, it outputs the ordered vector data sequence input from the fifth input terminal 41.

[0112] In some embodiments, as Figure 9 As shown, the second selection signal is used to indicate the vector compression function. When the main selection unit 10 receives the second selection signal at the first selection terminal 13, it outputs the vector mask sequence input from the second input terminal 12. When the auxiliary selection unit 20 receives the second selection signal at the second selection terminal 23, it outputs the vector data sequence input from the fourth input terminal 22. When the data selection unit 40 receives the second selection signal at the third selection terminal 43, it outputs the sorted vector data sequence input from the sixth input terminal 42.

[0113] In summary, the method provided by the embodiments of the present application selects the main sorting sequence, the auxiliary sorting sequence to be sorted, and the finally output sequence according to the selection signal. Through different combinations of the selection signals, multiple sorting functions can share the sorting circuit shown in the embodiments of the present application. There is no need to use multiple different sorting circuits to implement different sorting functions. Applying this sorting circuit in a chip can effectively reduce the area of the chip and also reduce the wiring complexity of the chip. And by distinguishing functions through the selection signal, the control logic is simple and easy to implement, and it will not add too much burden to the overall operation of the chip, resulting in a reduction in the operating efficiency of the chip. At the same time, the stable sorting function is indicated by the first selection signal, the vector compression function is indicated by the second selection signal, and the sequences output by the main selection unit and the auxiliary selection unit are different for different functions, so that the stable sorting function and the vector compression function can share a sorting circuit well. And the above sorting function can also be a non-sorting function similar to the vector compression function that can be achieved by a sorting method. In addition, the comparison unit can perform stable sorting, providing a basic guarantee for the sorting unit to achieve stable sorting.

[0114] The above sorting unit includes at least one comparison unit, that is, the sorting unit 30 realizes the sorting function through at least one comparison unit 60. Optionally, the sorting method used by the sorting unit 30 is a sorting network, and the sorting network is at least one of a bitonic sorting network and a parity sorting network. A sorting network is a sorting method suitable for hardware circuit implementation. The sorting process of the sorting network can be split into multiple comparison processes. The execution of each comparison process has a fixed order, and when there are no common elements to be compared between different comparison processes, these comparison processes can be parallelized, thereby improving the sorting speed. Next, an example will be given using an eight-input parity sorting network for the sorting unit 30. The sorting logic diagram of the eight-input parity sorting network is as shown in Figure 6 shown. Among them, din0-din7 on the leftmost side represent the 8 elements to be sorted in the input sorting network, and dout0-dout7 represent the 8 ordered elements output by the sorting network; each vertical solid line corresponds to a comparison and exchange process, and whether to exchange is determined according to the sorting target of the parity sorting network; for example, when the sorting target is ascending from bottom to top, the end pointed by the arrow is the position where the smaller element is located after each comparison and exchange process, and the end without an arrow represents the position where the larger element is located after each comparison and exchange process; or, when the sorting target is descending from bottom to top, the end pointed by the arrow is the position where the larger element is located after each comparison and exchange process, and the end without an arrow represents the position where the smaller element is located after each comparison and exchange process. The sorting of eight elements requires six stages of comparison and exchange processes, and the comparison and exchange processes in each stage can be executed simultaneously because there will be no data conflicts. In addition to the above eight-input parity sorting network, according to the specific design of the sorting unit, the sorting network can also be at least one of a two-input sorting network, a four-input sorting network, and a sixteen-input sorting network.

[0115] Among them, each comparison and exchange process in the sorting network is executed by the above comparison unit 60, that is, each vertical solid line in the sorting network represents a comparison unit, and the elements at both ends of the vertical solid line are the two elements to be sorted and their position information in the comparison unit. It can also be said that the sorting process in the sorting network is executed by at least one comparison unit.

[0116] First, the sorting of four data, which is easier to understand, will be described. Figure 10 is the schematic diagram of a four-input parity sorting network. Figure 10 In it, din0 to din3 on the left side of the sorting network represent the four data before sorting, that is, the four input data, and dout0 to dout3 on the right side of the sorting network represent the four data after sorting, that is, the four output data.

[0117] Next, taking the sorting target as ascending order from din0 to din3, and the four input data being {1, 4, 2, 3} as an example, the sorting process is as follows Figure 11 shown. In stage 1, compare the data at the din2 and din3 positions. Since 4 > 1, swap the data at the din2 and din3 positions; compare the data at the din0 and din1 positions. Since 3 > 2, swap the data at the din0 and din1 positions; after stage 1, the sorted data is {4, 1, 3, 2}; in stage 1, the data at the din2 position is the smaller data between din2 and din3, the data at the din3 position is the larger data between din2 and din3, the data at the din0 position is the smaller data between din0 and din1, and the data at the din1 position is the larger data between din0 and din1. In stage 2, compare the data at the din1 and din3 positions. Since 3 < 4, no swap; compare the data at the din0 and din2 positions. Since 2 > 1, swap the data at the din0 and din2 positions; after stage 2, the sorted data is {4, 2, 3, 1}; in stage 2, compare the larger data (the data at the din1 and din3 positions) in group 1 (din0 and din1) and group 2 (din2 and din3) to get the largest data among the four data, and swap it to the din3 position; compare the smaller data (the data at the din0 and din2 positions) in group 1 (din0 and din1) and group 2 (din2 and din3) to get the smallest data among the four data, and swap it to the din0 position. After stage 2, the data at the din0 and din3 positions has been confirmed. Therefore, in stage 3, only compare the data at the din1 and din2 positions. Since 3 > 2, swap the data at the din1 and din2 positions, and after stage 3, the sorted data is {4, 3, 2, 1}. The sorting of the four data is completed.

[0118] Next, the eight-input odd-even sorting network will be described. The sorting process is as follows Figure 12As shown. When sorting eight data, first divide the eight data into two groups (Group 1: din0 to din3, Group 2: din4 to din7), with four elements in each group. Sort the four elements in each group. This will not be elaborated here. After Stage 3, two groups of ordered data are obtained. The data sorting after Stage 3 is {7, 5, 2, 1, 8, 6, 4, 3}. In Stage 4, compare the data in Group 1 (din0 to din3) and Group 2 (din4 to din7) one by one. That is, compare the first data in Group 1 (the data corresponding to din0) with the first data in Group 2 (the data corresponding to din4). Since 3 > 1, exchange the data at the positions of din0 and din4. Since din0 and din4 respectively correspond to the smallest data in Group 1 and Group 2, the smaller data among din0 and din4 is the smallest data among the eight data, and exchange it to the din0 position; compare the second data in Group 1 (the data corresponding to din1) with the second data in Group 2 (the data corresponding to din5). Since 4 > 2, exchange the data at the positions of din1 and din5; compare the third data in Group 1 (the data corresponding to din2) with the third data in Group 2 (the data corresponding to din6). Since 6 > 5, exchange the data at the positions of din2 and din6; compare the fourth data in Group 1 (the data corresponding to din3) with the fourth data in Group 2 (the data corresponding to din7). Since 8 > 7, exchange the data at the positions of din3 and din7. Since din3 and din7 respectively correspond to the largest data in Group 1 and Group 2, the larger data among din3 and din7 is the largest data among the eight data, and exchange it to the din7 position; the data sorting after Stage 4 is obtained as {1, 2, 5, 7, 3, 4, 6, 8}; in Stage 4, the largest and smallest data among the eight data are determined, that is, the data at the din0 and din7 positions; in Stage 5, compare the data at the din3 and din5 positions. Since 7 > 4, exchange the data at the positions of din3 and din5; compare the data at the din2 and din4 positions. Since 5 > 3, exchange the data at the positions of din2 and din4; the data sorting after Stage 5 is obtained as {1, 2, 3, 4, 5, 7, 6, 8}; in Stage 6, compare the data at the din1 and din2 positions. Since 2 < 3, do not exchange; compare the data at the din3 and din4 positions. Since 4 < 5, do not exchange; compare the data at the din5 and din6 positions. Since 7 > 6, exchange the data at the positions of din5 and din6; the data sorting after Stage 6 is obtained as {1, 2, 3, 4, 5, 6, 7, 8}. The sorting of the eight data ends.

[0119] Next, it is proved how to sort two ordered groups into one ordered group after the end of Phase 4 to Phase 6. Among them, d0 to d7 represent the data at the positions of din0 to din7 after the end of Phase 3, where d0 to d3 is an ascending sequence and d4 to d7 is an ascending sequence; min(d0, d1) represents the smaller data at the positions of din0 and din7; max(d0, d1) represents the larger data at the positions of din0 and din7.

[0120] The sorted sequence after the end of Phase 4 can be expressed as:

[0121] max(d3, d7)

[0122] max(d2, d6)

[0123] max(d1, d5)

[0124] max(d0, d4)

[0125] min(d3, d7)

[0126] min(d2, d6)

[0127] min(d1, d5)

[0128] min(d0, d4)

[0129] Among them, the sequence after the end of Phase 4 satisfies the rules of min(d0, d4) < min(d1, d5) < min(d2, d6) < min(d3, d7) and max(d0, d4) < max(d1, d5) < max(d2, d6) < max(d3, d7).

[0130] The proof is as follows. For min(d0, d4) and min(d1, d5), there is an inference table as shown in Table 2.

[0131] Table 2 Inference Table

[0132] min(d0, d4) min(d1, d5) Known conditions Conclusion d0 d1 d0 < d1 min(d0, d4) < min(d1, d5) d0 d5 d0 < d4 < d5 < d1 min(d0, d4) < min(d1, d5) d4 d1 d4 < d0 < d1 min(d0, d4) < min(d1, d5) d4 d5 d4 < d5 min(d0, d4) < min(d1, d5) [[ID=4o]]

[0133] According to the above method, similarly, it can be deduced that the sequence rules after the end of Phase 4 are min(d0, d4) < min(d1, d5) < min(d2, d6) < min(d3, d7) and max(d0, d4) < max(d1, d5) < max(d2, d6) < max(d3, d7).

[0134] The sorted sequence after the end of Phase 5 can be expressed as:

[0135] max(d3, d7)

[0136] max(d2, d6)

[0137] max(max(d1, d5), min(d3, d7))

[0138] max(max(d0, d4), min(d2, d6))

[0139] min(max(d1, d5), min(d3, d7))

[0140] min(max(d0, d4), min(d2, d6))

[0141] min(d1, d5)

[0142] min(d0, d4)

[0143] It can be obtained by comparing and swapping the following three groups of data respectively in Phase 6.

[0144] Conclusion: The entire sequence is ordered after Phase 6.

[0145] Premise: The three groups of data compared in Phase 6 need to satisfy that all data in the first group are less than all data in the second group, and all data in the second group are less than all data in the third group.

[0146] The first group of data:

[0147] min(max(d0, d4), min(d2, d6))

[0148] min(d1, d5)

[0149] The second group of data:

[0150] max(max(d0, d4), min(d2, d6))

[0151] min(max(d1, d5), min(d3, d7))

[0152] The third group of data:

[0153] max(d2, d6)

[0154] max(max(d1, d5), min(d3, d7))

[0155] Next, prove the correctness of the above premise.

[0156] First, prove that all the data in the first group are less than all the data in the second group. The proof for this premise can be transformed into "the larger data in the first group is less than all the data in the second group", so there are the following two cases for this premise.

[0157] Case 1, the larger data in the first group is min(d1, d5), that is, min(d1, d5) > min(max(d0, d4), min(d2, d6)).

[0158] The problem is transformed into proving min(d1, d5) < max(max(d0, d4), min(d2, d6)) and min(d1, d5) < min(max(d1, d5), min(d3, d7)).

[0159] If min(d1, d5) < max(max(d0, d4), min(d2, d6)) holds, then there are the following two cases.

[0160] Equation 1, min(d1, d5) < max(d0, d4);

[0161] Equation 2, min(d1, d5) < min(d2, d6).

[0162] In the scenario corresponding to Equation 1, max(max(d0, d4), min(d2, d6)) = max(d0, d4), then there is max(d0, d4) > min(d2, d6). Since the sequence rule is min(d1, d5) < min(d2, d6), it can be deduced that min(d1, d5) < max(d0, d4).

[0163] In the scenario corresponding to Equation 2, according to the sequence rule min(d1, d5) < min(d2, d6), it can be deduced that Equation 2 holds.

[0164] If min(d1, d5) < min(max(d1, d5), min(d3, d7)) holds, then there are the following two cases.

[0165] Equation 3, min(d1, d5) < max(d1, d5);

[0166] Equation 4, min(d1, d5) < min(d3, d7).

[0167] In the scenario corresponding to Equation 3, min(d1, d5) < max(d1, d5) always holds.

[0168] In the scenario corresponding to Equation 4, according to the sequence rule min(d1, d5) < min(d2, d6) < min(d3, d7), it can be deduced that Equation 2 holds.

[0169] Therefore, Case 1 holds.

[0170] Case 2, the larger data in the first group is min(max(d0, d4), min(d2, d6)), that is, min(max(d0, d4), min(d2, d6)) > min(d1, d5).

[0171] The problem is transformed into proving min(max(d0, d4), min(d2, d6)) < max(max(d0, d4), min(d2, d6)) and min(max(d0, d4), min(d2, d6)) < min(max(d1, d5), min(d3, d7)).

[0172] If min(max(d0, d4), min(d2, d6)) = max(d0, d4), then max(d0, d4) < min(d2, d6); min(max(d0, d4), min(d2, d6)) < max(max(d0, d4), min(d2, d6)) can be divided into the following two cases.

[0173] Equation 5, max(d0, d4) < max(d0, d4);

[0174] Equation 6, max(d0, d4) < min(d2, d6).

[0175] In the scenario corresponding to Equation 5, due to the premise min(max(d0, d4), min(d2, d6)) = max(d0, d4), the situation where max(max(d0, d4), min(d2, d6)) = max(d0, d4) cannot occur.

[0176] In the scenario corresponding to Equation 6, since max(max(d0, d4), min(d2, d6)) = min(d2, d6), then max(d0, d4) < min(d2, d6) always holds.

[0177] min(max(d0, d4), min(d2, d6)) < min(max(d, d5), min(d3, d7)) can be divided into the following two cases.

[0178] Equation 7, max(d0, d4) < max(d1, d5);

[0179] Equation 8, max(d0, d4) < min(d3, d7).

[0180] In the scenario corresponding to Equation 7, according to the sequence rule max(d0, d4) < max(d1, d5), it can be deduced that Equation 7 holds.

[0181] In the scenario corresponding to Equation 8, since min(max(d0, d4), min(d2, d6)) = max(d0, d4), then max(d0, d4) < min(d2, d6); and according to the sequence rule min(d2, d6) < min(d3, d7), it can be deduced that max(d0, d4) < min(d3, d7).

[0182] If min(max(d0, d4), min(d2, d6)) = min(d2, d6), then min(d2, d6) < max(d0, d4); min(max(d0, d4), min(d2, d6)) < max(max(d0, d4), min(d2, d6)) can be divided into the following two cases.

[0183] Equation 9, min(d2, d6) < max(d0, d4);

[0184] Equation 10, min(d2, d6) < min(d2, d6).

[0185] In the scenario corresponding to Equation 9, since max(max(d0, d4), min(d2, d6)) = max(d0, d4), then min(d2, d6) < max(d0, d4) always holds.

[0186] In the scenario corresponding to Equation 10, due to the premise min(max(d0, d4), min(d2, d6)) = min(d2, d6), the situation of max(max(d0, d4), min(d2, d6)) = min(d2, d6) cannot occur.

[0187] min(max(d0, d4), min(d2, d6)) < min(max(d1, d5), min(d3, d7)) can be divided into the following two cases.

[0188] Equation 11, min(d2, d6) < max(d1, d5);

[0189] Equation 12, min(d2, d6) < min(d3, d7).

[0190] In the scenario corresponding to Equation 11, since min(max(d0, d4), min(d2, d6)) = min(d2, d6), then min(d2, d6) < max(d0, d4); according to the sequence rule max(d0, d4) < max(d1, d5), it can be deduced that min(d2, d6) < max(d1, d5).

[0191] In the scenario corresponding to Equation 12, according to the sequence rule min(d2, d6) < min(d3, d7), it can be deduced that Equation 12 holds.

[0192] Therefore, Case 2 holds.

[0193] From this, it can be deduced that all the data in the first data set are less than all the data in the second data set. Similarly, it can be deduced that all the data in the second data set are less than all the data in the third data set.

[0194] Under the premise that the above conditions are established, the conclusion also holds.

[0195] It should be noted that when performing a four-input odd-even sorting network and an eight-input odd-even sorting network, for the sake of easy understanding, the input of the sorting network is a single value. In actual execution, the input of the sorting network can be a group of three elements shown by the above comparison unit, or a group of n elements, where n is a positive integer. The comparison logic between the element groups can be the same as the comparison logic of the comparison unit. The comparison logic of the comparison unit is to perform stable sorting with the main sorting element as the main keyword and the position information as the secondary keyword. The comparison logic between the element groups can include multiple keywords, and there are different priorities between the keywords. For example, in the embodiments of the present application, the priority of the main keyword is higher than that of the secondary keyword. Only when the main keywords are equal, will the sorting be performed according to the secondary keyword. The embodiments of the present application do not limit the design of the basic structure of the above comparison unit and the design of the comparison logic, but the protection scope of the present application is not limited thereto.

[0196] Figure 13 FIG. shows a schematic structural diagram of a terminal 300 provided by an embodiment of the present application. The terminal 300 may include: a chip 310 including a sorting circuit.

[0197] The chip 310 including a sorting circuit can execute the above sorting control method; or, the terminal 300 can execute the above sorting control method according to the chip 310 including a sorting circuit.

[0198] Optionally, the chip 310 including the sorting circuit is the central processing unit (CPU) of the terminal 300; or, the chip 310 including the sorting circuit is the processor of the terminal 300 for executing the sorting control method; or, the chip 310 including the sorting circuit is the chip of the terminal 300 for making a logical judgment on the sorting control method.

[0199] An exemplary embodiment of the present application further provides a chip, which includes the above-mentioned sorting circuit. Optionally, the chip is the chip 310 including the sorting circuit in the above-mentioned terminal device.

[0200] It should be understood that "a plurality of" mentioned herein refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after. In addition, the step numbers described in this article only exemplarily show a possible execution sequence between steps. In some other embodiments, the above steps may not be executed in the order of the numbers. For example, two steps with different numbers are executed simultaneously, or two steps with different numbers are executed in the reverse order of the illustration. The embodiments of the present application do not limit this.

[0201] The above are only optional embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A sorting circuit, characterized in that, The sorting circuit includes a main selection unit, an auxiliary selection unit, a sorting unit, and a data selection unit; the sorting unit includes a main sorting input terminal, an auxiliary sorting input terminal, a main sorting output terminal, and an auxiliary sorting output terminal; the main selection unit includes a first input terminal, a second input terminal, a first selection terminal, and a first output terminal; the first output terminal is connected to the main sorting input terminal; the auxiliary selection unit includes a third input terminal, a fourth input terminal, a second selection terminal, and a second output terminal; the second output terminal is connected to the auxiliary sorting input terminal; the data selection unit includes a fifth input terminal, a sixth input terminal, a third selection terminal, and a data output terminal; the main sorting output terminal is connected to the fifth input terminal; the auxiliary sorting output terminal is connected to the sixth input terminal; The main selection unit is configured to output the main sorting sequence input from the first input terminal when the first selection signal is received at the first selection terminal; When the second selection signal is received at the first selection terminal, output the main sorting sequence input from the second input terminal; The auxiliary selection unit is configured to output the auxiliary sorting sequence input from the third input terminal when the first selection signal is received at the second selection terminal; When the second selection signal is received at the second selection terminal, output the auxiliary sorting sequence input from the fourth input terminal; The sorting unit is configured to receive the main sorting sequence and the auxiliary sorting sequence, the main sorting sequence includes at least two main sorting elements, the auxiliary sorting sequence includes at least two auxiliary sorting elements, and the auxiliary sorting elements and the main sorting elements are in one-to-one correspondence according to the positions of the elements in the sequence; based on the at least two main sorting elements, sort the at least two main sorting elements to obtain at least two ordered main sorting elements and sort the at least two auxiliary sorting elements to obtain at least two sorted auxiliary sorting elements; Obtain an ordered main sorting sequence based on the at least two ordered main sorting elements, and obtain a sorted auxiliary sorting sequence based on the at least two sorted auxiliary sorting elements; The data selection unit is configured to output the ordered main sorting sequence input from the fifth input terminal when the first selection signal is received at the third selection terminal; when the second selection signal is received at the third selection terminal, output the sorted auxiliary sorting sequence input from the sixth input terminal.

2. The sorting circuit according to claim 1, wherein The first selection signal is used to indicate the stable sorting function; When the first selection signal is received at the first selection terminal, the first input terminal of the main selection unit is used to receive vector data; When the first selection signal is received at the second selection terminal, the third input terminal of the auxiliary selection unit is used to receive vector indices; When the first selection signal is received at the third selection terminal, the data output terminal of the data selection unit is used to output the vector data output from the main sorting output terminal of the sorting unit.

3. The sorting circuit according to claim 1, wherein The second selection signal is used to indicate the vector compression function; When the second selection signal is received at the first selection terminal, the second input terminal of the main selection unit is used to receive a vector mask; When the second selection signal is received at the second selection terminal, the fourth input terminal of the auxiliary selection unit is used to receive vector data; When the second selection signal is received at the third selection terminal, the data output terminal of the data selection unit is used to output the vector data output from the auxiliary sorting output terminal of the sorting unit.

4. The sorting circuit according to any one of claims 1 to 3, characterized in that, The sorting unit includes at least one comparison unit; each comparison unit includes a first main sorting input terminal, a first auxiliary sorting input terminal, a first position input terminal, a second main sorting input terminal, a second auxiliary sorting input terminal, a second position input terminal, a first main sorting output terminal, a first auxiliary sorting output terminal, a first position output terminal, a second main sorting output terminal, a second auxiliary sorting output terminal, and a second position output terminal; The first main sorting input terminal and the second main sorting input terminal are used to input two main sorting elements to be compared; The first auxiliary sorting input terminal and the second auxiliary sorting input terminal are used to input two auxiliary sorting elements to be compared; the first position input terminal and the second position input terminal are used to input the position information of the two main sorting elements to be compared and the two auxiliary sorting elements to be compared in the sequence; Each comparison unit in the at least one comparison unit is used to receive the two main sorting elements to be compared and the two auxiliary sorting elements to be compared, and receive the position information of the two main sorting elements to be compared and the two auxiliary sorting elements to be compared in the sequence, and the auxiliary sorting elements and the main sorting elements correspond one by one according to the position of the elements in the sequence; according to the main sorting elements and the corresponding position information of the main sorting elements, perform a stable sorting on the main sorting elements and the auxiliary sorting elements corresponding to the main sorting elements, and the stable sorting is a sorting with the main sorting elements as the main key and the position information as the secondary key, the main key is used to indicate the main key for performing the stable sorting, and the secondary key is used to indicate the auxiliary key for sorting when the main keys are equal.

5. The sorting circuit according to claim 4, characterized in that, The sorting method used by the sorting unit is a sorting network, the sorting network is at least one of a parity sorting network and a bitonic sorting network, and the sorting process in the sorting network is executed by the at least one comparison unit.

6. A sorting control method, characterized in that, Applied to the sorting circuit according to any one of claims 1 to 5, the method includes: When the first selection signal is received at the first selection terminal, the main selection unit outputs the main sorting sequence input from the first input terminal; when the second selection signal is received at the first selection terminal, the main selection unit outputs the main sorting sequence input from the second input terminal; When the first selection signal is received at the second selection terminal, the auxiliary selection unit outputs the auxiliary sorting sequence input from the third input terminal; when the second selection signal is received at the second selection terminal, the auxiliary selection unit outputs the auxiliary sorting sequence input from the fourth input terminal; The sorting unit receives the main sorting sequence and the secondary sorting sequence. The main sorting sequence includes at least two main sorting elements, and the secondary sorting sequence includes at least two secondary sorting elements. The secondary sorting elements and the main sorting elements correspond one by one according to their positions in the sequence. Based on the at least two main sorting elements, the at least two main sorting elements are sorted to obtain at least two ordered main sorting elements, and the at least two secondary sorting elements are sorted to obtain at least two sorted secondary sorting elements. An ordered main sorting sequence is obtained based on the at least two ordered main sorting elements, and a sorted secondary sorting sequence is obtained based on the at least two sorted secondary sorting elements. When the data selection unit receives the first selection signal at the third selection terminal, it outputs the ordered main sorting sequence input from the fifth input terminal. When the data selection unit receives the second selection signal at the third selection terminal, it outputs the sorted secondary sorting sequence input from the sixth input terminal.

7. The method according to claim 6, wherein The first selection signal is used to indicate the stable sorting function. When the main selection unit receives the first selection signal at the first selection terminal, it outputs the main sorting sequence input from the first input terminal, including: When the main selection unit receives the first selection signal at the first selection terminal, it outputs the vector data sequence input from the first input terminal. When the secondary selection unit receives the first selection signal at the second selection terminal, it outputs the secondary sorting sequence input from the third input terminal, including: When the secondary selection unit receives the first selection signal at the second selection terminal, it outputs the vector index sequence input from the third input terminal. When the data selection unit receives the first selection signal at the third selection terminal, it outputs the ordered main sorting sequence input from the fifth input terminal, including: When the data selection unit receives the first selection signal at the third selection terminal, it outputs the ordered vector data sequence input from the fifth input terminal.

8. The method according to claim 6, wherein The second selection signal is used to indicate the vector compression function. When the main selection unit receives the second selection signal at the first selection terminal, it outputs the main sorting sequence input from the second input terminal, including: When the main selection unit receives the second selection signal at the first selection terminal, it outputs the vector mask sequence input from the second input terminal. When the secondary selection unit receives the second selection signal at the second selection terminal, it outputs the secondary sorting sequence input from the fourth input terminal, including: When the secondary selection unit receives the second selection signal at the second selection terminal, it outputs the vector data sequence input from the fourth input terminal. When the data selection unit receives the second selection signal at the third selection terminal, it outputs the sorted secondary sorting sequence input from the sixth input terminal, including: When the data selection unit receives the second selection signal at the third selection terminal, it outputs the sorted vector data sequence input from the sixth input terminal.

9. The method according to any one of claims 6 to 8, characterized in that, The sorting unit includes at least one comparison unit; Based on the at least two main sorting elements, the sorting unit sorts the at least two main sorting elements to obtain the ordered at least two main sorting elements and sorts the at least two secondary sorting elements to obtain the sorted at least two secondary sorting elements, including: Each comparison unit in the at least one comparison unit receives two main sorting elements to be compared and two secondary sorting elements to be compared, and receives the position information of the two main sorting elements to be compared and the two secondary sorting elements to be compared in the sequence. The secondary sorting elements and the main sorting elements correspond one by one according to the position of the elements in the sequence; according to the main sorting elements and the corresponding position information of the main sorting elements, a stable sorting is performed on the main sorting elements and the secondary sorting elements corresponding to the main sorting elements. The stable sorting is a sorting with the main sorting elements as the main key and the position information as the secondary key. The main key is used to indicate the main key for performing stable sorting, and the secondary key is used to indicate the auxiliary key for sorting when the main keys are equal.

10. The sorting circuit according to claim 9, characterized in that The sorting method used by the sorting unit is a sorting network, and the sorting network is at least one of a parity sorting network and a bitonic sorting network. The sorting process in the sorting network is executed by the at least one comparison unit.

11. A chip, characterized in that, The chip includes the sorting circuit according to any one of claims 1 to 5.

12. A terminal, characterized in that, The terminal includes a chip with the sorting circuit according to any one of claims 1 to 5.

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