Calculation method and system based on two-stage assembly line, chip and storage medium

Abstract

The invention provides a calculation method and system based on a two-stage pipeline, a chip and a storage medium. The method comprises the steps of obtaining data bits, flag bit setting and performance requirement parameters of a target calculation task; determining a configuration mode of a target register according to the data bits, and loading operands participating in calculation into the target register from a memory; and according to the performance demand parameters, determining a calculation mode for executing the basic calculation task and the advanced calculation task to obtain a second-level calculation result. According to the calculation method and system based on the two-stage assembly line, the chip and the storage medium provided by the embodiment of the invention, the two-stage assembly line design capable of adapting to complex calculation tasks with different data bits and different performance requirements is provided, and resource shortage caused by processing a large amount of data at a time is avoided; reasonable allocation of computing resources at the first level and smooth execution of high-level computing tasks at the second level are ensured, and the resource bottleneck of the system is avoided.

Description

Technical Field

[0001] The present application relates to the field of computer systems, and in particular to a computing method, system, chip and storage medium based on a two-stage pipeline. Background Art

[0002] In modern computer systems, data computing efficiency and computing energy management are two major challenges. Traditional single-stage pipeline architectures waste resources and create performance bottlenecks when processing multi-precision data. Furthermore, application scenarios with high real-time requirements and strict security requirements, such as power monitoring and industrial automation, place even higher demands on computing systems.

[0003] Computational pipelining is a technique that breaks down complex batch computing tasks into multiple simpler subtasks and allows these subtasks to overlap in time, thereby improving the computer's overall computational efficiency. Traditional single-stage pipelines suffer from resource waste and performance bottlenecks when processing complex tasks. Lack of optimization in stages such as data prefetching, instruction decoding, execution, and storage leads to overall low efficiency. Furthermore, existing technologies often focus on a single data precision (such as 32-bit or 64-bit), making it difficult to meet the diverse data precision requirements of different scenarios. Furthermore, the lack of task-specific hardware optimization during data processing and storage results in significant energy waste, leading to low energy efficiency. Existing instruction sets have also made some optimizations to traditional single-machine pipelines. For example, the x86 architecture relies on memory, core timers, and data interfaces to implement a multi-stage computational pipeline, offering strong versatility. However, due to its complex instruction set, multi-stage pipeline design, backward compatibility requirements, complex memory model, and multi-core design, the x86 architecture suffers from resource waste and performance bottlenecks. These issues stem primarily from its design goals of versatility and compatibility, which lead to excessive use of hardware resources and increased complexity. Other architectures such as ARM and RISC-V lack sufficient optimization when facing complex batch computing tasks, resulting in low computing efficiency and energy consumption. As a result, the computing pipeline in the existing architecture is unable to meet the needs of application scenarios with high real-time requirements and strict security requirements, such as power monitoring and industrial automation. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a dynamically configured mixed-base calculation method, system, chip and storage medium.

[0005] In a first aspect, an embodiment of the present invention provides a two-stage pipeline-based computing method, the method comprising:

[0006] Obtaining the number of data bits, flag bit settings, and performance requirement parameters of a target computing task, wherein the target computing task includes a basic computing task and an advanced computing task, and the flag bit settings include a first-level pipeline setting and a second-level pipeline setting;

[0007] Determine the configuration mode of the target register according to the number of data bits, and load the operands participating in the calculation from the memory into the target register, where the target register is used to store the operands participating in the calculation and the corresponding calculation results, and the configuration mode is used to determine the dynamic combination mode of multiple native registers;

[0008] If the performance requirement parameter is a high real-time task, call the corresponding calculation unit according to the first-level pipeline setting in the flag bit setting to execute the basic calculation task, and obtain the first-level calculation result; and execute the advanced calculation task according to the second-level pipeline setting and the first-level calculation result in the flag bit setting to obtain the second-level calculation result;

[0009] If the performance requirement parameter is a low real-time task, according to the second-level pipeline setting in the flag bit setting, sequentially execute the basic calculation task and the advanced calculation task according to the operands in the target register to obtain the second-level calculation result.

[0010] Optionally, before the method, it further includes:

[0011] Receive a system interrupt signal, and write the number of data bits, flag bit setting, and performance requirement parameter of the target calculation task into the message register;

[0012] According to the interrupt signal, interrupt vector table, and interrupt program address, jump to the interrupt program execution address to start executing the target calculation task.

[0013] Optionally, the flag bit setting includes the calculation unit type and the accuracy of the actuarial unit;

[0014] Correspondingly, the calling of the corresponding calculation unit according to the first-level pipeline setting in the flag bit setting specifically includes:

[0015] Call the corresponding calculation unit according to the calculation unit type and the accuracy of the actuarial unit in the first-level pipeline setting of the flag bit setting.

[0016] Optionally, the flag bit setting further includes a data processing order parameter for controlling the calculation order of the operands participating in the calculation.

[0017] Optionally, after the method, it further includes:

[0018] Encrypt the second-level calculation result and upload it to the cloud server or the control system.

[0019] Optionally, the basic calculation tasks include addition, subtraction, multiplication, logical AND, and logical OR.

[0020] Optionally, the advanced computing tasks include aggregation computing, statistical analysis, pattern recognition, prediction models, and optimization algorithms.

[0021] In a second aspect, an embodiment of the present invention provides a computing system based on a two-level pipeline. The system includes:

[0022] A data acquisition module, configured to obtain the number of data bits, flag bit settings, and performance requirement parameters of a target computing task. The target computing task includes a basic computing task and an advanced computing task, and the flag bit settings include a first-level pipeline setting and a second-level pipeline setting;

[0023] A register dynamic configuration module, configured to determine the configuration method of a target register according to the number of data bits and load the operands participating in the calculation from the memory into the target register. The target register is used to store the operands participating in the calculation and the corresponding calculation results, and the configuration method is used to determine the dynamic combination method of multiple native registers;

[0024] A first task calculation module, configured to, if the performance requirement parameter is a high real-time task, call a corresponding calculation unit according to the first-level pipeline setting in the flag bit settings to execute the basic computing task and obtain a first-level calculation result; and execute the advanced computing task according to the second-level pipeline setting in the flag bit settings and the first-level calculation result to obtain a second-level calculation result;

[0025] A second task calculation module, configured to, if the performance requirement parameter is a low real-time task, execute the basic computing task and the advanced computing task in sequence according to the operands in the target register according to the second-level pipeline setting in the flag bit settings to obtain a second-level calculation result.

[0026] In a third aspect, an embodiment of the present invention provides a chip, characterized in that the chip includes:

[0027] One or more processors;

[0028] A memory, configured to store one or more programs;

[0029] Wherein, when the one or more programs are executed by the one or more processors, the one or more processors are caused to execute the method described in the first aspect.

[0030] In a fourth aspect, an embodiment of the present invention provides a storage medium, on which computer program instructions are stored, characterized in that when the computer program instructions are executed, the instruction processing method described in the first aspect is implemented.

[0031] The calculation method, system, chip, and storage medium based on a two-stage pipeline provided by the embodiments of the present invention propose a two-stage pipeline design that can adapt to complex calculation tasks with different data bits and different performance requirements, avoiding resource tension caused by processing a large amount of data at one time, ensuring the reasonable allocation of calculation resources at the first stage and the smooth execution of high-level calculation tasks at the second stage, and avoiding the resource bottleneck of the system; further, combined with the dynamic configuration register mechanism of the HEX4 instruction set system, different complexity calculation tasks can efficiently read calculation operands in the two-stage pipeline according to performance requirements, making it more advantageous in resource-constrained scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application.

[0033] Figure 1 It is a schematic flowchart of the calculation method based on a two-stage pipeline provided by the embodiments of the present invention;

[0034] Figure 2 It is a schematic structural diagram of the calculation system based on a two-stage pipeline provided by the embodiments of the present invention;

[0035] Figure 3 It is a schematic structural diagram of the chip provided by the embodiments of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] The following will describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application.

[0037] Similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, terms such as "first" and "second" are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0038] In modern computer systems, data calculation efficiency and calculation energy consumption management are two important challenges. The traditional single-stage pipeline architecture has resource waste and performance bottlenecks when processing multi-precision data. In addition, application scenarios with high real-time requirements and strict security requirements, such as power monitoring and industrial automation, pose higher requirements on the calculation system.

[0039] The computing pipeline of a computer is a technology that decomposes complex batch computing tasks into multiple simple subtasks and allows these subtasks to be executed overlapping in time, thereby improving the overall computing efficiency of the computer. When dealing with complex tasks, traditional single-stage pipelines suffer from resource waste and performance bottlenecks. Stages such as data prefetching, instruction decoding, execution, and storage lack optimization, resulting in low overall efficiency. Moreover, existing technologies often focus on a single data precision (such as 32-bit or 64-bit), making it difficult to meet the diverse data precision requirements in different scenarios. In addition, during data processing and storage, due to the lack of hardware optimization for specific tasks, there is a large amount of energy consumption waste, leading to a low energy efficiency ratio.

[0040] Some optimizations have also been made to traditional single-core pipelines in existing instruction sets. For example, the x86 architecture relies on memory, kernel timing tasks, and data interfaces to implement a multi-level computing pipeline, which has strong generality. However, due to its complex instruction set, multi-level pipeline design, backward compatibility requirements, complex memory model, and multi-core design, the x86 architecture has resource waste and performance bottlenecks. These problems mainly stem from its design goals of generality and compatibility, resulting in overuse of hardware resources and increased complexity. In addition, the x86 instruction set is huge and complex, containing thousands of instructions, supporting various functions from simple arithmetic to complex floating-point operations and string operations. The instruction length is not fixed, increasing the complexity of decoding and execution. The x86 processor uses a multi-level pipeline (such as 14 levels or more) to improve instruction throughput. However, the complex pipeline design is prone to pipeline conflicts, such as data dependencies and branch prediction errors. One of the core design goals of the x86 architecture is backward compatibility, ensuring that new processors can run old instruction sets (such as 16-bit, 32-bit, 64-bit). This requires the hardware design to support multiple instruction sets and modes. The x86 uses a complex memory model that supports virtual memory, paging, and segmentation mechanisms. In a multi-core system, cache coherence protocols (such as MESI) increase the performance overhead.

[0041] Other architectures such as ARM and RISC-V lack sufficient optimization when facing complex batch computing tasks, resulting in low computing efficiency and computing energy consumption, making it difficult for the computing pipelines in existing architectures to meet the needs of application scenarios with high real-time requirements and strict security requirements such as power monitoring and industrial automation.

[0042] Based on this, the embodiments of the present invention propose a computing method based on a two-stage pipeline, as shown in the appendix Figure 1 The method specifically includes the following steps.

[0043] Step S110: Obtain the data bit number, flag bit setting, and performance requirement parameters of the target computing task. The target computing task includes a basic computing task and an advanced computing task, and the flag bit setting includes a first-level pipeline setting and a second-level pipeline setting.

[0044] In a computer, a complete computing task is often complex and consists of multiple steps. The pipeline technology splits this complex computing task into multiple relatively independent and sequentially executed subtasks, and each subtask is completed by a specific stage in the pipeline. These subtasks are executed in parallel on different hardware units. That is to say, within one clock cycle, different stages of the pipeline can simultaneously process different subtasks of different computing tasks, thus achieving temporal overlap and greatly improving the computing efficiency.

[0045] The computing tasks in the embodiments of the present invention can be driven by system interrupt events. Taking the edge scenario applicable to the present invention as an example, such as the computing tasks related to parameters such as current and voltage in an electricity meter chip. In an embedded electricity meter chip, it is driven by an interrupt event. According to the interrupt signal, interrupt vector table, and interrupt program address, it jumps to the interrupt program execution address and starts to execute the target computing task. The triggering of the computing task is described in detail below.

[0046] The triggering and execution mechanism of the computing tasks in the embodiments of the present invention is the initial link. Different from some traditional ways of polling at fixed time intervals or actively polling to obtain and execute tasks, the embodiments of the present invention innovatively use system interrupt events to drive the execution of computing tasks. This interrupt-driven mechanism can bring higher real-time performance, more efficient resource utilization, and more flexible task scheduling capabilities to the system, especially suitable for specific scenarios with high requirements for real-time response and relatively limited resources.

[0047] To more clearly elaborate on this way of interrupt-driven computing tasks, the invention takes the edge scenario as an example for illustration. The edge scenario generally refers to the environment near the source of data generation and processing, with characteristics such as local data processing and low-latency response. Among many edge scenarios, the electricity meter chip is selected as a typical representative. As the core component of the power metering system, the electricity meter chip needs to calculate important parameters related to current, voltage, etc. in real time and accurately. The accurate calculation of these parameters is of crucial significance for the stable operation of the power system, electricity charge metering, power quality monitoring, etc. For example, accurate current and voltage data can help the power department detect line faults and electricity theft behaviors in a timely manner, and at the same time provide reasonable electricity usage suggestions for users.

[0048] In the specific environment of an embedded electricity meter chip, the process of interrupt event-driven computing tasks is as follows:

[0049] During the operation of the electricity meter chip, there are various events that may trigger interrupts. For example, when the current sensor detects that the current value reaches a preset threshold, it will send an interrupt signal to the chip; or the timer generates an interrupt signal at a predetermined time interval for periodically collecting and calculating parameters such as current and voltage. These interrupt signals are like an "alarm" of the system, informing the chip that there are events that need to be processed immediately.

[0050] When the chip receives an interrupt signal, it will determine the interrupt program to be executed based on the interrupt vector table. The interrupt vector table is a pre-defined data structure that contains the mapping relationship between various interrupt types and the corresponding interrupt program addresses. For example, the current overload interrupt corresponds to the interrupt program address for handling the current overload situation, and the voltage anomaly interrupt corresponds to the interrupt program address for handling the voltage anomaly. By querying the interrupt vector table, the chip can quickly and accurately find the interrupt program address that matches the current interrupt signal.

[0051] Once the chip determines the address of the interrupt program according to the interrupt vector table, it will jump to that address through the hardware mechanism. This process is similar to a function call in a computer program, but the interrupt jump has a higher priority. It will immediately interrupt the currently executing program flow and instead execute the interrupt program. This mechanism ensures that interrupt events can be processed in a timely manner, avoiding delays caused by waiting for the current program to finish execution.

[0052] After the chip jumps to the interrupt program execution address, it starts to execute the pre-written interrupt program code, which is the target calculation task. Taking the calculation of current and voltage parameters as an example, the interrupt program will contain corresponding algorithms and logics for processing and calculating the raw data of the collected current and voltage. For example, calculating the effective value and average value of the current, and the fluctuation range of the voltage, etc. These calculation tasks usually need to be completed within an extremely short time to ensure that the electricity meter chip can reflect the state of the power system in real time. After the calculation task is completed, the chip will resume the previously interrupted program flow according to the relevant mechanisms of interrupt handling and continue to run normally.

[0053] Before executing the target computing task, the system needs to obtain a series of key parameters in this step S110. These parameters will directly affect the execution efficiency, accuracy, and resource allocation of the computing task. The target computing task is mainly divided into basic computing tasks and advanced computing tasks. Basic computing tasks are usually some relatively simple and conventional arithmetic operations, such as simple addition, subtraction, multiplication, logical AND, logical OR, etc. They are common in various systems and are the basic support for the operation of the system. Advanced computing tasks are relatively complex and may involve complex algorithmic logic, a large amount of data processing, and high-precision arithmetic requirements, such as advanced aggregation calculations, statistical analysis, pattern recognition, prediction models, optimization algorithms, signal processing algorithms, complex model calculations, etc., which have higher requirements for the performance and configuration of the system.

[0054] Flag bit setting is an important part of this parameter acquisition. It includes primary pipeline setting and secondary pipeline setting. The core of the two-level pipeline lies in the data bit number (Nb) setting and register configuration. These two key factors cooperate with each other to jointly determine the way and efficiency of the pipeline to process data.

[0055] The data bit number Nb is an important indicator to measure data precision and processing method. Common Nb values include 4 bits, 8 bits, 12 bits, 16 bits, or 32 bits, etc. Different data bit numbers correspond to different data representation ranges and precisions. For example, the numerical range that can be represented by 4-bit data is relatively small, and the precision is also relatively low; while 32-bit data can represent a larger range of numerical values and has higher precision, which can more accurately describe the details of the data. The data bit number determines the arithmetic rules and storage methods adopted by the system when processing data. In terms of arithmetic rules, different data bit numbers may need to use different arithmetic logic units (ALUs) for operations to ensure the accuracy and efficiency of the operations. In terms of storage methods, the data bit number will affect the storage space occupied by the data in memory or registers, thereby indirectly affecting the memory management and data access speed of the system.

[0056] The flag bit setting in the embodiment of the present invention can also specify the number of bits for shifting, including left shift or right shift operations. Shifting operations play an important role in data processing. It can adjust the size of the data and achieve operations such as data scaling and alignment. For example, in signal processing, it may be necessary to perform shifting operations on the collected data to make it meet the processing requirements of subsequent algorithms; in the process of data encoding and decoding, shifting operations can also be used to adjust the format and position of the data. The speed and accuracy of the shifting operation directly affect the execution efficiency of the entire computing task. The system needs to quickly and accurately perform shifting operations on the data according to the shifting parameters set by the flag bit to ensure that the data can be correctly used in subsequent operations.

[0057] The flag bit setting includes the calculation unit type and the actuarial unit precision; correspondingly, calling the corresponding calculation unit according to the first-level pipeline setting in the flag bit setting specifically includes: calling the corresponding calculation unit according to the calculation unit type and the actuarial unit precision in the flag bit setting.

[0058] Taking the multiplication operation as an example, specifically, the calculation unit type is multiplication and the actuarial unit precision is 8 bits. The selection of the multiplication precision needs to comprehensively consider the precision requirements of the calculation task and the hardware performance of the system. To implement multiplication operations with different precisions, the system needs to have corresponding hardware support. For example, the CPU may be equipped with multipliers of different bit widths to meet the needs of multiplication operations with different precisions. At the same time, the system can also optimize the multiplication operation algorithm to improve the speed and efficiency of the multiplication operation and reduce the calculation time.

[0059] Step S120, determining the configuration method of the target register according to the data bit number and loading the operands participating in the calculation from the memory into the target register, where the target register is used to store the operands participating in the calculation and the corresponding calculation results, and the configuration method is used to determine the dynamic combination method of multiple native registers.

[0060] The system will dynamically configure the corresponding register size according to the setting of the data bit number Nb. Registers are high-speed storage units in the CPU used to temporarily store data and instructions, and their size directly affects the speed and ability of the CPU to process data. For example, when Nb is set to 8 bits, the system will configure 2 4-bit native registers. This configuration method is to adapt to the precision requirements of the data, ensure that the data can be accurately stored in the register, and can be efficiently read and written during subsequent operations.

[0061] Dynamically configuring registers is one of the features of the HEX4 instruction set used in the embodiments of the present invention. By dynamically configuring the register size according to the data bit number Nb, the system can make full use of hardware resources and avoid waste of resources. If the data bit number is small, using registers with a larger capacity will cause some register space to be idle, resulting in waste of resources; while if the data bit number is large, using registers with a smaller capacity cannot store the data completely and requires multiple read and write operations, reducing the operation efficiency. Therefore, dynamically configuring the register size can improve the overall operation efficiency of the system on the premise of meeting the data precision requirements.

[0062] In the second-level pipeline technology in the embodiments of the present invention, by decomposing the computing tasks into multiple stages for parallel execution, the instruction throughput rate and system performance of the CPU are significantly improved. As a key means for optimizing hardware resources, the dynamic configuration register mechanism can flexibly adjust the register resource allocation according to instruction characteristics, data features, and computing requirements. After deep cooperation with the second-level pipeline technology, it shows significant advantages in aspects such as resource utilization rate, performance optimization, and energy consumption control.

[0063] Under the traditional fixed register configuration, instructions with different data widths (such as 8-bit, 16-bit, 32-bit) need to use registers of the same size, resulting in small-width instructions occupying a large amount of register space and causing waste of hardware resources. The dynamic configuration register mechanism can dynamically allocate register resources according to the data width (Nb) of the instructions. For example, when executing 8-bit instructions, the system can allocate 2 4-bit native registers to form an 8-bit register group, avoiding occupying a complete 16-bit or 32-bit register; when executing 32-bit instructions, the system can dynamically combine 8 4-bit native registers or directly call 32-bit dedicated registers to ensure the complete storage of data. This on-demand allocation method eliminates the register fragmentation problem, increases the hardware resource utilization rate by 30%-50% (the specific increase ratio depends on the instruction width distribution), and significantly reduces the hardware redundancy cost.

[0064] In the second-level pipeline, there may be differences in data widths in different instruction stages. The dynamic configuration register mechanism allows adjacent pipeline stages to use different-sized register combinations. For example, when processing 8-bit instructions, a 4-bit register group is allocated, and when processing 32-bit instructions, a 32-bit register is allocated. Through this heterogeneous register configuration, each stage of the pipeline can independently adapt to the instruction requirements, avoiding pipeline stalls caused by register resource conflicts, and increasing the pipeline fill rate by 20%-40%, which is especially suitable for scenarios with mixed instruction sets.

[0065] Step S130, if the performance requirement parameter is a high-real-time task, then call the corresponding computing unit according to the first-level pipeline setting in the flag bit setting to execute the basic computing task, and obtain the first-level computing result; and execute the advanced computing task according to the second-level pipeline setting and the first-level computing result in the flag bit setting to obtain the second-level computing result.

[0066] Step S140, if the performance requirement parameter is a low-real-time task, then according to the second-level pipeline setting in the flag bit setting, sequentially execute the basic computing task and the advanced computing task according to the operands in the target register to obtain the second-level computing result.

[0067] Embodiments of the present invention can be executed in two ways according to step S130 and step S140 respectively according to the type of the computing task. For example, in a microgrid scenario, when the grid frequency deviation > 0.1 Hz, the output power of the photovoltaic inverter needs to be adjusted within 10 ms, which belongs to a scenario of high real-time / low latency tasks. Another example is the soil moisture prediction scenario, where sensor data is collected once an hour and combined with historical data to predict irrigation requirements, which belongs to a scenario of low real-time / high tolerance tasks. The type of the computing task in the embodiments of the present invention is determined according to the performance requirement parameters carried by the current computing task.

[0068] In the high real-time / low latency task of step S130, first, if the performance requirement parameter is a high real-time task, the corresponding computing unit is called according to the first-level pipeline setting in the flag bit setting to execute the basic computing task, and the first-level computing result is obtained. The data in the register is not used in this process. Taking the addition operation in the HEX4 instruction set as an example, refer to the following execution method of the basic computing task:

[0069] HEMOVE Nb = 000000, Rd = 000001, #11

[0070] HEMOVE Nb = 000000, Rd = 000100, #010

[0071] HEJIAFA Nb = 000000, Rd = 010000, Rs = 000001, Rs = 000100

[0072] If the performance requirement parameter is a high real-time task, the register data loading instruction HEMOVE directly executes the addition instruction HEJIAFA. This execution process belongs to the first-level computing pipeline of the system and is executed in the corresponding computing unit ALU. The data at the corresponding address can be directly read from the memory. If the performance requirement parameter is a low real-time task, the configuration method of determining the target register according to the data bit number in step S120 can be adopted, and the operands participating in the calculation (i.e., the operation of the HEMOVE instruction) loaded into the target register from the memory are used, and then it is completed in the second-level pipeline.

[0073] Even for the same computing task, when faced with different performance requirement parameters, one of steps S130 or S140 can be adopted to select and execute the basic computing task. Taking the calculation of power consumption data of an electricity meter chip as an example: Suppose voltage and current data are collected. When performing power calculation, the product of voltage and current can be calculated through multiplication to obtain the power. The power calculation can be carried out at the first level or the second level, specifically depending on the design requirements and performance requirements of the system. If high real-time performance and low latency are required, we can design to perform the power calculation at the first level; if more complex processing and batch analysis are needed, we can design to perform it at the second level. When performing energy calculation, the energy is obtained by integrating the accumulation of power over time. If the system requires high real-time performance and the power calculation task is relatively simple, it can be carried out at the first level; if the power calculation task is complex and the system has a higher tolerance for real-time performance, it is carried out at the second level. By reasonably allocating the power calculation task, the overall performance and efficiency of the system can be optimized. When performing data correction, if the system requires high real-time performance and the data correction task is relatively simple, it can be designed to be carried out at the first level; if the data correction task is complex and the system has a higher tolerance for real-time performance, it can be carried out at the second level.

[0074] In addition, the execution methods of advanced computing tasks are all carried out in the second-level pipeline, which requires the application of the calculation results of basic computing tasks. In actual application scenarios, common advanced computing tasks include:

[0075] (1) Aggregation calculation: Summarize and statistically analyze a large number of preliminary calculation results, such as summation, average, maximum value, minimum value, etc. This helps to understand the overall data distribution and trend.

[0076] (2) Statistical analysis: Conduct more in-depth statistical analysis, such as calculating variance, standard deviation, trend analysis, etc. These analyses can help identify anomalies and fluctuations in the data, providing support for the stability and reliability of the system.

[0077] (3) Pattern recognition: Identify patterns or anomalies in the data, such as detecting voltage fluctuations, current mutations, etc. Pattern recognition helps to timely discover potential problems in the system and prevent the occurrence of faults.

[0078] (4) Prediction model: Make predictions based on historical data, such as predicting future power demands, equipment status, etc. The prediction model can provide a scientific basis for system optimization and adjustment, improving the forward-looking and adaptability of the system.

[0079] (5) Optimization algorithm: Optimize the data, such as optimizing energy usage efficiency, adjusting equipment parameters, etc. The optimization algorithm can enhance the overall performance of the system, reduce energy consumption, and improve resource utilization.

[0080] (6) Data reading and preprocessing: Read the data after the first-level processing from the memory and perform necessary preprocessing, such as data cleaning, format conversion, etc.

[0081] (7) Data aggregation and statistical analysis: Perform aggregation calculations and statistical analysis on the data to extract key indicators and features.

[0082] (8) Pattern recognition and anomaly detection: Use pattern recognition algorithms to identify patterns and anomalies in the data to ensure the stable operation of the system.

[0083] (9) Prediction and optimization: Based on the results of statistical analysis and pattern recognition, perform prediction and optimization to generate decision support information.

[0084] After the calculations of the two-level pipeline are completed, it is necessary to store and upload the second-level calculation results. Specifically, the second-level calculation results can be encrypted and stored, and uploaded to the cloud or PLC devices to ensure the security and availability of the data.

[0085] The calculation method based on a two-level pipeline provided by the embodiments of the present invention proposes a two-level pipeline design that can adapt to complex calculation tasks with different data bit widths and different performance requirements, avoiding resource tension caused by processing a large amount of data at one time, ensuring the reasonable allocation of computing resources at the first level and the smooth execution of high-level calculation tasks at the second level, and avoiding the resource bottleneck of the system; further, combined with the dynamic configuration register mechanism of the HEX4 instruction set system, different complexity calculation tasks can efficiently read calculation operands in the two-level pipeline according to performance requirements, making it more advantageous in resource-constrained scenarios.

[0086] Based on any of the above embodiments, as Figure 2 shown, the embodiments of the present invention provide a calculation system based on a two-level pipeline, specifically including:

[0087] A data acquisition module 210, configured to obtain the data bit width, flag bit settings, and performance requirement parameters of the target calculation task, where the target calculation task includes basic calculation tasks and high-level calculation tasks, and the flag bit settings include first-level pipeline settings and second-level pipeline settings;

[0088] A register dynamic configuration module 220, configured to determine the configuration method of the target register according to the data bit width and load the operands participating in the calculation from the memory into the target register, where the target register is used to store the operands participating in the calculation and the corresponding calculation results, and the configuration method is used to determine the dynamic combination method of multiple native registers;

[0089] The first task calculation module 230 is configured to, if the performance requirement parameter is a high real-time task, call a corresponding calculation unit to execute the basic calculation task according to the first-level pipeline setting in the flag bit setting, and obtain a first-level calculation result; and execute the advanced calculation task according to the second-level pipeline setting and the first-level calculation result in the flag bit setting to obtain a second-level calculation result.

[0090] The second task calculation module 240 is configured to, if the performance requirement parameter is a low real-time task, execute the basic calculation task and the advanced calculation task in sequence according to the operand in the target register according to the second-level pipeline setting in the flag bit setting, and obtain a second-level calculation result.

[0091] The computing system based on a two-level pipeline provided by the embodiment of the present invention proposes a two-level pipeline design that can adapt to complex computing tasks with different data bits and different performance requirements, avoiding resource tension caused by processing a large amount of data at one time, ensuring reasonable allocation of computing resources at the first level and the smooth execution of the second-level advanced computing task, and avoiding resource bottlenecks in the system; further, combined with the dynamic configuration register mechanism of the HEX4 instruction set system, different complexity computing tasks can efficiently read computing operands in the two-level pipeline according to performance requirements, making it more advantageous in resource-constrained scenarios.

[0092] Based on any of the above embodiments, Figure 3 The schematic physical structure diagram of the chip provided by the embodiment of the present invention is shown. The electronic device may include: a processor 310, a communication interface 320, a memory 330, and a communication bus 340. Among them, the processor 310, the communication interface 320, and the memory 330 communicate with each other through the communication bus 340. The processor 310 can call the logical instructions in the memory 330 to execute the following method:

[0093] Obtain the data bit, flag bit setting, and performance requirement parameter of the target computing task. The target computing task includes a basic computing task and an advanced computing task, and the flag bit setting includes a first-level pipeline setting and a second-level pipeline setting;

[0094] Determine the configuration method of the target register according to the data bit and load the operands participating in the calculation from the memory into the target register. The target register is used to store the operands participating in the calculation and the corresponding calculation results, and the configuration method is used to determine the dynamic combination method of multiple native registers:

[0095] If the performance requirement parameter is a high real-time task, call the corresponding computing unit according to the first-level pipeline setting in the flag bit setting to execute the basic computing task, and obtain the first-level computing result; and execute the advanced computing task according to the second-level pipeline setting and the first-level computing result in the flag bit setting to obtain the second-level computing result;

[0096] If the performance requirement parameter is a low real-time task, according to the second-level pipeline setting in the flag bit setting, sequentially execute the basic computing task and the advanced computing task according to the operands in the target register to obtain the second-level computing result.

[0097] In addition, when the logical instructions in the memory 330 above can be implemented in the form of a software functional unit and sold or used as an independent product, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiment of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0098] On the other hand, the embodiment of the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it is implemented to execute the methods provided in the above embodiments, for example, including:

[0099] Obtain the data bit number, flag bit setting, and performance requirement parameter of the target computing task. The target computing task includes a basic computing task and an advanced computing task, and the flag bit setting includes a first-level pipeline setting and a second-level pipeline setting;

[0100] Determine the configuration method of the target register according to the data bit number and load the operands participating in the calculation from the memory into the target register. Among them, the target register is used to store the operands participating in the calculation and the corresponding calculation results, and the configuration method is used to determine the dynamic combination method of multiple native registers;

[0101] If the performance requirement parameter is a high real-time task, call the corresponding computing unit according to the first-level pipeline setting in the flag bit setting to execute the basic computing task, and obtain the first-level computing result; and execute the advanced computing task according to the second-level pipeline setting in the flag bit setting and the first-level computing result to obtain the second-level computing result.

[0102] If the performance requirement parameter is a low real-time task, according to the second-level pipeline setting in the flag bit setting, sequentially execute the basic computing task and the advanced computing task according to the operands in the target register to obtain the second-level computing result.

[0103] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative work.

[0104] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution, in essence, or the part that contributes to the prior art can be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A calculation method based on a two-stage pipeline, characterized in that The method includes: Obtaining the number of bits of data, flag bit settings, and performance requirement parameters of a target computing task, where the target computing task includes a basic computing task and an advanced computing task, and the flag bit settings include a first-level pipeline setting and a second-level pipeline setting; Determining the configuration mode of a target register according to the number of bits of data and loading the operands participating in the calculation from the memory into the target register, where the target register is used to store the operands participating in the calculation and the corresponding calculation results, and the configuration mode is used to determine the dynamic combination mode of multiple native registers; If the performance requirement parameter is a high real-time task, calling a corresponding computing unit according to the first-level pipeline setting in the flag bit settings to execute the basic computing task to obtain a first-level calculation result; and executing the advanced computing task according to the second-level pipeline setting in the flag bit settings and the first-level calculation result to obtain a second-level calculation result; If the performance requirement parameter is a low real-time task, according to the second-level pipeline setting in the flag bit settings, sequentially executing the basic computing task and the advanced computing task according to the operands in the target register to obtain a second-level calculation result.

2. The calculation method according to claim 1, characterized in that, Before the method, it further includes: Receiving a system interrupt signal, and writing the number of bits of data, flag bit settings, and performance requirement parameters of the target computing task into a message register; Jumping to the interrupt program execution address according to the interrupt signal, interrupt vector table, and interrupt program address, and starting to execute the target computing task.

3. The calculation method according to claim 1, characterized in that, The flag bit settings include the type of computing unit and the precision of the actuarial unit; Correspondingly, the calling of the corresponding computing unit according to the first-level pipeline setting in the flag bit settings specifically includes: Calling a corresponding computing unit according to the type of computing unit and the precision of the actuarial unit in the first-level pipeline setting of the flag bit settings.

4. The calculation method according to claim 1, characterized in that, The flag bit settings further include a data processing sequence parameter for controlling the calculation sequence of the operands participating in the calculation.

5. The calculation method according to claim 1, characterized in that After the method, it further includes: Encrypting the second-level calculation result and uploading it to a cloud server or a control system.

6. The calculation method according to any one of claims 1 to 5, characterized in that The basic computing tasks include addition, subtraction, multiplication, logical AND, and logical OR.

7. The calculation method according to any one of claims 1 to 5, characterized in that, The advanced computing tasks include aggregation calculation, statistical analysis, pattern recognition, prediction model, and optimization algorithm.

8. A computing system based on a two-stage pipeline, characterized in that, The system includes: A data acquisition module for obtaining the number of bits of data, flag bit settings, and performance requirement parameters of a target computing task, where the target computing task includes a basic computing task and an advanced computing task, and the flag bit settings include a first-level pipeline setting and a second-level pipeline setting; A register dynamic configuration module for determining the configuration mode of a target register according to the number of bits of data and loading the operands participating in the calculation from the memory into the target register, where the target register is used to store the operands participating in the calculation and the corresponding calculation results, and the configuration mode is used to determine the dynamic combination mode of multiple native registers; The first task calculation module is configured to, if the performance requirement parameter is a high real-time task, call a corresponding calculation unit according to the first-level pipeline setting in the flag bit setting to execute the basic calculation task, and obtain a first-level calculation result; and execute the advanced calculation task according to the second-level pipeline setting in the flag bit setting and the first-level calculation result to obtain a second-level calculation result. The second task calculation module is configured to, if the performance requirement parameter is a low real-time task, execute the basic calculation task and the advanced calculation task in sequence according to the second-level pipeline setting in the flag bit setting and the operands in the target register, and obtain a second-level calculation result.

9. A chip, characterized in that, The chip includes: One or more processors; A memory for storing one or more programs; Wherein, when the one or more programs are executed by the one or more processors, the one or more processors are caused to execute the method according to any one of claims 1 to 7.

10. A storage medium, on which computer program instructions are stored, characterized in that, When the computer program instructions are executed, the ternary calculation method according to any one of claims 1-7 is implemented.

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