Direct input redundancy scheme with adaptive syndrome decoder

Abstract

The invention relates to a direct input redundancy scheme with an adaptive syndrome decoder. A device that has read data from a data plane can replace data from one of the planes with redundant data from the data plane that stores the redundant data. The device may then provide the redundant data to an error correction circuit coupled with the data plane that stores the redundant data. The output of the error correction circuit may be used to generate syndrome bits that may be decoded by a syndrome decoder. The syndrome decoder may indicate whether a bit of data to be corrected should be corrected by selectively reacting to an input based on a type of the data. For example, the syndrome decoder may react to a first set of inputs if the data bits to be corrected are regular data bits, and to a second set of inputs if the data bits to be corrected are redundant data bits.

Description

[0001] Relevant information of the divisional application

[0002] This application is a divisional application of a Chinese patent application with an application date of November 26, 2019, an application number of "201980087284.3", and an invention title of "Direct-Input Redundancy Scheme Using an Adaptive Syndrome Decoder".

[0003] Cross-reference

[0004] This patent application claims the priority of PCT Application No. PCT / US2019 / 063393, titled "Direct-Input Redundancy Scheme with Adaptive Syndrome Decoder", filed by Nakai on November 26, 2019. The PCT application claims the priority of US Patent Application No. 16 / 212,017, titled "Direct-Input Redundancy Scheme with Adaptive Syndrome Decoder", filed by Nakai on December 6, 2018. Each of the above applications is assigned to the assignee hereof and is hereby incorporated by reference in its entirety into this application.

[0005] The technical field relates to a direct-input redundancy scheme using an adaptive syndrome decoder. Background Art

[0006] The following generally relates to operating a memory array, and more particularly, to a direct-input redundancy scheme using an adaptive syndrome decoder.

[0007] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming different states of the memory device. For example, a binary device has two states typically represented by logic "1" or logic "0". In other systems, more than two states can be stored. To access the stored information, components of an electronic device can perform a read operation to sense the stored state in the memory device. To store information, components of an electronic device can perform a write operation to program a state into the memory device.

[0008] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. The memory device can be volatile or non-volatile. Non-volatile memories (e.g., FeRAM, PCM, RRAM) can maintain the logical states they store for a long time, even in the absence of an external power supply. Volatile memory devices (e.g., DRAM) may lose their stored states over time unless periodically refreshed by an external power supply.

[0009] During a retrieval operation, the memory device can read the data bits stored in the memory and perform error correction on them. Before error correction, the device can replace some of the data bits with alternative data bits, which can be referred to as redundant data bits. However, the data path between the memory locations of the redundant bits and the error correction circuitry may add unnecessary and costly delays to the error correction operation, which may increase the latency of the retrieval operation, as well as other drawbacks. Summary of the Invention

[0010] A device is described. The device can include an error correction code (ECC) circuit coupled to a data plane and configured to receive data bits from the data plane; a redundant ECC circuit coupled to a redundant data plane and configured to receive redundant data corresponding to data stored by at least one of the data planes; and a syndrome decoder circuit for a first data plane of the data planes, the syndrome decoder circuit being coupled to the redundant ECC circuit and the ECC circuit and configured to adjust its output at least in part based on whether the redundant data received by the redundant ECC circuit corresponds to data stored by the first data plane.

[0011] A device is described. The device can include a bit flip circuit configured to invert data bits; and a syndrome decoder for a first data plane, the syndrome decoder being coupled to the bit flip circuit and including: a first decoder configured to receive a first set of bits, the first set of bits including syndrome bits generated at least in part based on a set of data, inverted syndrome bits, or a combination thereof; and a second decoder configured to receive a second set of bits including an inverted version of the first set of bits.

[0012] Describe a method. The method may include generating syndrome bits for data to be stored by a data plane; selecting data bits from the data for an error correction operation; transmitting a control signal indicating whether the data bits are an alternative to data bits stored by one of the data planes to a syndrome decoder configured for the error correction operation; and decoding the syndrome bits at the syndrome decoder based at least in part on the control signal.

[0013] Describe a method. The method may include performing a first bit-by-bit operation on a first set of redundant data for a first data plane using an ECC circuit, the first set of redundant data corresponding to data stored by the first data plane; transmitting the result of the first bit-by-bit operation to a combination of logic gates; performing a second bit-by-bit operation on a second set of redundant data for a second data plane using the ECC circuit, the second set of redundant data corresponding to data stored by the second data plane; and transmitting the result of the second bit-by-bit operation to the combination of logic gates. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Illustrate an example memory array supporting a direct input redundancy scheme that utilizes a dedicated ECC circuit in accordance with various embodiments of the present disclosure.

[0015] Figure 2 Illustrate an example of a memory architecture supporting a direct input redundancy scheme that utilizes a dedicated ECC circuit in accordance with various embodiments of the present disclosure.

[0016] Figure 3 Illustrate an example Hamming matrix supporting a direct input redundancy scheme that utilizes a dedicated ECC circuit in accordance with various embodiments of the present disclosure.

[0017] Figure 4 Illustrate an example ECC module supporting a direct input redundancy scheme that utilizes a dedicated ECC circuit in accordance with various embodiments of the present disclosure.

[0018] Figure 5 Illustrate an example ECC module supporting a direct input redundancy scheme that utilizes a dedicated ECC circuit in accordance with various embodiments of the present disclosure.

[0019] Figure 6 Illustrate an example redundant ECC circuit and enabling circuitry supporting a direct input redundancy scheme that utilizes a dedicated ECC circuit in accordance with various embodiments of the present disclosure.

[0020] Figure 7 Illustrate an example Hamming matrix supporting a direct input redundancy scheme that utilizes an adaptive syndrome decoder circuit in accordance with various embodiments of the present disclosure.

[0021] Figure 8Describe an example ECC module that supports a direct input redundancy scheme using an adaptive syndrome decoder circuit system in accordance with various embodiments of the present disclosure.

[0022] Figure 9 Describe an example redundant ECC circuit that supports a direct input redundancy scheme using an adaptive decoder circuit system in accordance with various embodiments of the present disclosure.

[0023] Figure 10 Describe an example error correction module that supports a direct input redundancy scheme using an adaptive decoder circuit system in accordance with various embodiments of the present disclosure.

[0024] Figure 11 Describe a block diagram of a memory array that supports a direct input redundancy scheme using an adaptive decoder circuit system in accordance with various embodiments of the present disclosure.

[0025] Figure 12 Describe a system that supports a direct input redundancy scheme using an adaptive decoder circuit system in accordance with various embodiments of the present disclosure.

[0026] Figure 13 And 14 Describe one or more methods for using a direct input redundancy scheme with an adaptive decoder circuit system in accordance with various embodiments of the present disclosure. Detailed Description

[0027] A memory device can increase the reliability of stored data bits by performing error correction (e.g., using an error correction code (ECC)) on the data bits during a retrieval operation. In some cases, the memory device can further increase reliability by replacing some of the data bits with replacement bits, which can be referred to as redundant data bits. For example, the device can replace a data bit from one of the data planes involved in a read operation with a redundant data bit stored in a redundant data plane. However, transmitting the redundant data to the error correction circuit system for replacement can increase the latency of the error correction operation, which can be proportional to the length of the data path along which the redundant data travels to the error correction circuit system.

[0028] According to a first technique described herein, a memory device can reduce the length of a data path, and thus reduce propagation delay, by directly inputting redundant data bits into an error correction circuit dedicated to a redundant data plane. The error correction circuit can be coupled to an adaptive enable circuitry that can selectively transmit the output of the error correction circuit to other error correction components based on the data plane replaced by the redundant data. For example, when redundant data is used for the x-th data plane, the enable circuitry can transmit the output of the error correction circuit to a combination of error correction components, but when redundant data is used for the y-th data plane, the enable circuitry can transmit the output of the error correction circuit to a different combination of error correction components. Thus, even though the redundant data is directly passed to the error correction circuit of the redundant data plane (instead of the error correction circuit of the replaced data plane), the error correction components can operate without interference.

[0029] The features of the first technique are further described herein in the context of a memory system. Specific examples of apparatus and methods for directly inputting redundant data into an error correction circuit dedicated to redundant data are described. These and other features of the present disclosure are further illustrated and described with reference to device diagrams, system diagrams, and flowcharts related to generating syndrome bits for a codeword containing redundant data.

[0030] According to a second technique described herein, a memory device can reduce the length of a data path, and thus reduce propagation delay, by directly inputting redundant data bits into an error correction circuitry dedicated to a redundant data plane. The error correction circuitry for redundant data can perform operations on the redundant data that contribute to generating syndrome bits for the read data bits. Once the syndrome bits are generated, the device can use an adaptive syndrome decoder to decode the syndrome bits. The syndrome decoder can be adaptive because it selectively responds to inputs based on the type of data being decoded (e.g., redundant data versus regular data). For example, when the data being decoded is redundant data, the syndrome decoder can respond to a first set of inputs but can substantially ignore a second set of inputs. The output of the syndrome decoder can indicate to a bit flip circuit whether a data bit (e.g., a regular data bit or a redundant data bit) is incorrect and should be flipped (e.g., inverted).

[0031] The features of the second technique are further described herein in the context of a memory system. Specific examples of apparatus and methods for directly inputting redundant data into an error correction circuitry are described. These and other features of the present disclosure are further illustrated and described with reference to device diagrams, system diagrams, and flowcharts related to an adaptive syndrome decoder.

[0032] Figure 1Illustrate an example memory array 100 that supports a direct input redundancy scheme utilizing a dedicated ECC circuit according to various embodiments of the present disclosure. The memory array 100 can be used to store digital information (e.g., binary information) and can also be referred to as an electronic memory device. The memory array 100 includes memory cells 105 that are programmable to store different states. Each memory cell 105 is programmable to store two states represented as logic 0 and logic 1. In some cases, the memory cells 105 are configured to store more than two logic states.

[0033] The memory cells 105 can include memory elements with programmable states. Memory cells 105 in a DRAM or FeRAM architecture can store charges representing programmable states in a capacitor; for example, a charged and an uncharged capacitor can represent two logic states respectively. The DRAM architecture typically can use such a design and can use a capacitor that includes a dielectric material and has linear polarization properties as the memory element. The FeRAM architecture can also use such a design, but the capacitor used as the memory element can include a ferroelectric material with non-linear polarization properties. Memory cells 105 in a PCM architecture can change the resistivity of a material (e.g., resistance or threshold voltage), where different resistivities can represent different logic states. The PCM architecture can use a chalcogenide material with electrically programmable resistance as the memory element.

[0034] Operations such as reading and writing can be performed on the memory cells 105 by activating or selecting appropriate access lines 110 and digit lines 115. The access lines 110 can also be referred to as word lines 110, and the digit lines 115 can also be referred to as bit lines 115. Activating or selecting a word line 110 or a digit line 115 can include applying a voltage to the corresponding line. The word lines 110 and digit lines 115 are made of a conductive material. For example, the word lines 110 and digit lines 115 can be made of a metal (e.g., copper, aluminum, gold, tungsten, etc.), a metal alloy, other conductive materials, etc. According to Figure 1 an example, each row of the memory cells 105 is connected to a single word line 110, and each column of the memory cells 105 is connected to a single digit line 115. By activating one word line 110 and one digit line 115 (e.g., applying a voltage to the word line 110 or the digit line 115), a single memory cell 105 can be accessed at their intersection. Accessing the memory cell 105 can include reading or writing to the memory cell 105. The intersection of the word line 110 and the digit line 115 can be referred to as the address of the memory cell.

[0035] In some architectures, the logic storage device of a cell (e.g., a capacitor) can be electrically isolated from the digital line by a select component. A word line 110 can be connected to the select component and can control the select component. For example, the select component can be a transistor, and the word line 110 can be connected to the gate of the transistor. Activating the word line 110 causes an electrical connection or a closed circuit between the capacitor of the memory cell 105 and its corresponding digital line 115. The digital line can then be accessed to read from or write to the memory cell 105.

[0036] Access to the memory cell 105 can be controlled by a row decoder 120 and a column decoder 130. In some instances, the row decoder 120 receives a row address from a memory controller 140 and activates an appropriate word line 110 based on the received row address. Similarly, the column decoder 130 receives a column address from the memory controller 140 and activates an appropriate digital line 115. For example, the memory array 100 can include a plurality of word lines 110 labeled WL_1 to WL_M, and a plurality of digital lines 115 labeled DL_1 to DL_N, where M and N depend on the array size. Thus, by activating the word line 110 and the digital line 115, e.g., WL_3 and DL_N, the memory cell 105 at their intersection can be accessed.

[0037] After access, the memory cell 105 can be read or sensed by a sensing component 125 to determine the stored state of the memory cell 105. For example, after accessing the memory cell 105, the capacitor of the memory cell 105 can be discharged onto its corresponding digital line 115. Discharging the capacitor can be based on biasing or applying a voltage to the capacitor. The discharge can induce a change in the voltage of the digital line 115, which the sensing component 125 can compare with a reference voltage (not shown) to determine the stored state of the memory cell 105. For example, if the digital line 115 has a higher voltage than the reference voltage, the sensing component 125 can determine that the stored state in the memory cell 105 is a logic 1, and vice versa.

[0038] The reliability of the sensing operation can depend on the sensing window generated by reading the memory cell 105. For example, a larger sensing window can be associated with fewer bit errors compared to a smaller sensing window. The sensing window can be determined as the difference between the voltage of the digital line 115 caused by reading the memory cell 105 when storing a logic 1 and the voltage of the digital line 115 caused by reading the memory cell when storing a logic 0. The sensing component 125 can include various transistors or amplifiers to detect and amplify the difference in the signals, which can be referred to as latching. The detected logical state of the memory cell 105 can then be output as an output 135 through the column decoder 130.

[0039] Memory cell 105 can be set or written by activating the associated word line 110 and digit line 115. As discussed herein, activating the word line 110 electrically connects the corresponding row of memory cells 105 to their respective digit lines 115. By controlling the associated digit line 115 when the word line 110 is activated, the memory cell 105 can be written, i.e., a logical value can be stored in the memory cell 105. In some cases, a memory array 100 that stores data bits corresponding to logical values at a first memory cell 105 can (e.g., for reliability purposes) store another data bit corresponding to a logical state at another memory cell 105. The data bit stored at the second memory cell 105 can be referred to as a redundant data bit. The column decoder 130 can receive data to be written to the memory cell 105, such as input 135.

[0040] The memory controller 140 can control the operation (e.g., read, write, rewrite, refresh, etc.) of the memory cell 105 through various components such as the row decoder 120, column decoder 130, and sense component 125. The memory controller 140 can generate row and column address signals to activate the desired word line 110 and digit line 115. The memory controller 140 can also generate and control various voltage potentials used during the operation of the memory array 100. Generally, the amplitude, shape, or duration of the applied voltage discussed herein can be adjusted or varied and can be different for the various operations used to operate the memory array 100. Additionally, one, multiple, or all of the memory cells 105 within the memory array 100 can be accessed simultaneously; for example, multiple or all of the cells of the memory array 100 can be accessed simultaneously during a reset operation, in which all of the memory cells 105 or a group of memory cells 105 are set to a single logical state.

[0041] In some cases, the memory array 100 can be divided into sets of memory cells. For example, the memory array 100 can be divided into memory sections called data planes, at least some of which can contain multiple memory cells 105. The data planes can be configured such that different groups of data planes can be accessed by different word lines 110. For example, a group of data planes can be accessed by the same word line 110, which can also be shared with a redundant data plane configured to store redundant data bits corresponding to the data bits stored by the data plane (e.g., the redundant data bits can be based on the same logical state as the data bits stored at the data plane). The digit lines 115 of the memory cells in each data plane can be coupled to a respective error correction circuitry (e.g., an error correction code (ECC) module).

[0042] Before storing data in a set of data planes, memory array 100 may generate a certain amount of parity bits for the data for error correction purposes. The parity bits may be based on the data to be stored (e.g., as defined by an error correction code such as Hamming code). Once one or more parity bits are generated, they may be appended to the original data bits and stored in the set of data planes together with the original data bits. The combination of the original data bits and the appended parity bits may be referred to herein as a codeword. In some cases, some of the original data bits expected to be stored at the corresponding data planes may also be stored at redundant data planes. For example, a device having x logical states for storage may store the data bits corresponding to those x logical states not only in the memory cells of a data plane but also in the memory cells of a redundant data plane.

[0043] When reading a codeword, but before error correction, the set of redundant data bits may replace a set of original bits in a process called redundant repair. Redundant repair may increase the reliability of the codeword but also increases the latency of the read operation, especially when the propagation path of the redundant data is long.

[0044] In some instances, the information stored in memory array 100 (e.g., one or more codewords) may be requested by another device (e.g., a memory component such as a buffer or an external processor). After receiving a request for the information, memory array 100 may identify the location of the information within memory array 100 (e.g., memory array 100 may identify the location of one or more codewords within one or more sets of data planes). For example, memory array 100 may determine that the information is located within a set of memory cells that are located within a set of specific data planes. Memory array 100 may access the set of data planes via associated word lines 110 such that the data bits stored by the memory cells and the corresponding parity bits are output on corresponding digit lines 115.

[0045] However, before providing the information to the requesting device, memory array 100 may first process the information, performing redundant repair and error correction on the information bits stored in the set of memory planes. For example, after replacing a portion of the original data bits with redundant bits, memory array 100 may determine whether any of the bits are in error (e.g., in an inverted state compared to the originally stored state) and flip the incorrect bits to return them to the stored state expected by the requesting device.

[0046] During error correction (e.g., during an error correction operation), the memory array 100 may generate syndrome bits that can be used to detect errors in the read data bits and identify the locations of those errors. For example, the syndrome bits for a codeword can be compared with the parity bits for the codeword to determine whether the codeword contains an error. If no error is detected (e.g., if the syndrome bits match the parity bits), the data bits can be passed to the requesting device without error correction (e.g., without inverting any of the bits). However, if an error is detected (e.g., if the syndrome bits do not match the parity bits), the memory array 100 can decode the syndrome bits to identify the location of the error within the codeword such that the error can be corrected (e.g., inverted) before the codeword is passed to the requesting device.

[0047] To perform error correction, the data bits from each data plane involved in a read operation can be input into a corresponding error correction circuit, which can be located near the data plane. When redundant repair is used for bits in a data plane, redundant data bits rather than the original data bits can be input into the error correction circuit for that data plane (or at least undergo operations equivalent to those performed by the error correction circuit for that data plane). However, delivering the redundant bits to the appropriate error correction circuit (e.g., the error correction circuit for the data plane to be replaced) can be associated with propagation delays, e.g., due to the propagation path from the redundant data plane to the error correction circuit. According to the techniques described herein, compared to other architectures, the propagation path of redundant data can be shortened by inputting the redundant data into additional error correction circuits placed near the redundant data plane. The additional error correction circuits can replicate the output of the error correction circuit for the data plane to be replaced, thereby ensuring that the error correction operation is not disrupted.

[0048] Figure 2 An example of a memory architecture 200 that supports a direct input redundancy scheme that utilizes a dedicated ECC circuit in accordance with various embodiments of the present disclosure is illustrated. The memory architecture 200 can support a column redundancy scheme, where redundant data for a data plane is stored at a separate data plane (or “column”) reserved for redundant data. For example, in a column redundancy scheme, redundant data corresponding to the data in data plane 0 can be stored at redundant data plane 205.

[0049] The redundant data plane 205 may include multiple memory cells and may have the ability to store redundant data for (e.g., corresponding to) multiple data planes. For example, the redundant data plane 205 may be part of a global column redundancy architecture, where the redundant data plane 205 is configured to store redundant data for any one or all of the data planes accessed by the same word line as the redundant data plane 205. A data plane that does not store redundant data may be referred to herein as a regular data plane or a non-redundant data plane. The redundant data may be data representing the logical states that serve as the basis for the data bits stored in the regular data plane. Thus, when the data bits in the regular data plane are not corrupted, the redundant data bits corresponding to those data bits may be the same as those data bits. However, if the data bits in the regular data plane are corrupted, the redundant data bits corresponding to those data bits may include one or more different data bits.

[0050] The memory architecture 200 may include multiple regular data planes (e.g., data plane 0 to data plane 15), each of which is configured to store data bits and each of which is coupled to a common word line (e.g., word line 210). Thus, non-redundant data planes can be accessed or selected by the same word line. The word line 210 may also be coupled to the redundant data plane 205 and the parity data plane 215. The parity data plane 215 may be configured to store parity bits of a codeword, the data bits of which are stored by the regular data planes. Alternatively, the parity bits may be stored in one or more of the regular data planes. Although shown as having sixteen regular data planes, any number of regular data planes may be used to implement the redundant repair and error correction techniques described herein.

[0051] At least some (if not every) of the regular data planes, the redundant data plane 205, and the parity data plane 215 may include one or more digital lines for outputting the stored logical states as signals. The signals may pass through one or more processing components, such as sense amplifiers, before being passed to a data selector as data bits. The data selector may select between regular data and redundant data for ECC operations. When the data selector selects the redundant data, the redundant data bits corresponding to the regular data bits may be used to replace those regular data bits for ECC operations.

[0052] In some instances, a data selector may select regular data for ECC operations by establishing a conductive path between the ECC circuit and a digital line from the regular data plane. Alternatively, the data selector may select redundant data for ECC operations by establishing a conductive path between the ECC circuit and a digital line from the redundant data plane 205. The data selector may establish the conductive path by activating and deactivating one or more switching components, such as transistors. Thus, the memory architecture 200 may include a number of digital lines, at least some of which may be coupled to respective data planes and respective ECC circuits. Additionally, the memory architecture 200 may include one or more digital lines coupled to the redundant data plane 205 and the redundant ECC circuit 235.

[0053] In some cases, each regular data plane may be associated with a corresponding ECC circuit. For example, there may be a one-to-one correspondence between the ECC circuit and the regular data plane. Thus, the memory architecture 200 may include multiple ECC circuits, each of which is configured to receive data from a respective regular data plane. For example, ECC circuit 0 may receive data from data plane 0 via data selector 0, ECC circuit 1 may receive data from data plane 1 via data selector 1, and so on. Each ECC circuit may be designed to operate on the data bits from its respective data plane, defined, for example, by a Hamming matrix. Thus, different ECC circuits may be used for different regular data planes.

[0054] As described above, the regular data planes may be used to store information, such as codewords (or data portions of codewords). In such cases, the parity data plane 215 may store the parity bits of the codewords (or the parity bits may be distributed among the memory cells of one or more regular data planes). For example, each of the regular data planes may store a portion (e.g., eight bits) of the requested data (e.g., a total of 128 bits), and the parity data plane 215 may store the corresponding parity bits (e.g., eight parity bits). In some cases, an undamaged version of the codeword data may be stored as redundant data in the redundant data plane 205. For example, the redundant data plane 205 may store eight redundant bits corresponding to eight logical values represented (or expected to be represented) by eight data bits stored in data plane 0. Thus, the redundant data plane 205 may be configured to store redundant data that is the same as (or expected to be the same as) the data stored at the regular data plane 0. When one or more bits of the regular data are damaged (e.g., during a corresponding write operation or between a write operation and a read operation), a deviation may occur between the regular data and the corresponding redundant data.

[0055] When the stored information is requested by another device or component, the memory architecture 200 can perform a retrieval operation that involves reading the memory cells storing the information, performing an ECC operation on the read data, correcting errors in the read data, and transferring the corrected data to the output bus 230 for transfer to the requesting device. To initiate the retrieval operation, the requested information can be transferred from the regular plane (e.g., as a quantity of data bits) to the data selector. However, if a redundancy repair is in play (e.g., if one of the regular data planes is selected for redundancy repair), then the redundant data from the redundant data plane 205 must be transferred to the data selector corresponding to that data plane so that the redundant data (instead of the replaced regular data) undergoes the ECC operation.

[0056] But transferring the redundant data from the redundant data plane 205 to the appropriate data selector (or ECC circuit) can increase the latency of the system because the travel time of the redundant data can be proportional to the length of the propagation path between the redundant data plane and the data selector. For example, when the redundant data replaces data from the regular data plane 0, the latency of the system can increase (compared to no redundancy repair) because the redundant data travels along the propagation path 225-a, which in some cases can be up to 1 mm or greater. In some cases, because error correction cannot occur until all relevant data has undergone the ECC operation, any delay in providing data to the ECC circuit can result in a delay in the retrieval operation.

[0057] According to the techniques described herein, the latency of the retrieval operation can be reduced by directly inputting the redundant data into the ECC circuit corresponding to the redundant data plane 205. The ECC circuit corresponding to the redundant data plane 205 can be referred to as the redundant ECC circuit 235, and the redundant ECC circuit 235 can be configured to receive the redundant data from the redundant data plane 205. Thus, each data plane, whether regular or not, can have a corresponding ECC circuit. When the redundant data is transferred to the ECC module 220, the redundant data can follow the propagation path 225-b, which can be shorter than the propagation path 225-a. Therefore, the latency associated with transferring the redundant data to the ECC module can be reduced.

[0058] In a first embodiment, the redundant ECC circuit 235 can be coupled to an enabling circuitry that selectively transfers the output of the redundant ECC circuit 235 to certain components of the ECC circuitry 245. The components to which the output is transferred can be based on the data plane replaced by the redundant data. Refer to Figure 6 , for additional details regarding the relationship between the redundant ECC circuit 235 and the enabling circuitry.

[0059] In a second embodiment, the redundant ECC circuit 235 may be coupled to an adaptive syndrome decoder. The syndrome decoder may be adaptive in that it may consider certain inputs (e.g., and ignore other inputs) when decoding the syndrome bits of a codeword. Refer to Figure 10 The adaptive syndrome decoder is described in additional detail, and refer to Figure 9 The ECC circuit coupled to the syndrome decoder is described in additional detail.

[0060] A retrieval operation using the redundant ECC circuit 235 is now described. For illustrative purposes, the retrieval operation is described with reference to a codeword including 128 data bits and eight parity bits. However, the techniques described herein may be implemented for codewords of any length.

[0061] During a write operation, the data of the codeword may have been distributed across the regular data planes. For example, each of the regular data planes may have been used to store eight bits of the codeword (resulting in 128 bits stored by sixteen regular data planes). The eight parity bits may have been stored at the parity data plane 215, and the eight bits stored in (or expected to be stored in) data plane 0 may have been stored as redundant data at the redundant data plane 205.

[0062] During the retrieval process, each of the data planes (e.g., data planes 0 to 15) may be selected (e.g., using wordlines 210) and read. Thus, eight data bits may be transferred (e.g., via eight digital lines) from data plane 0 to mux 0, eight bits may be transferred from data plane 1 to mux 1, and so on. Each of the muxes (except mux 0) may establish a conductive path between the digital lines and the corresponding ECC circuit such that the data from each plane is input into the respective ECC circuit. However, instead of transferring data bits from data plane 0, mux 0 may transfer empty data bits (e.g., all zeros) such that the operation of the ECC module 220 is not corrupted (since data plane 0 has been selected for redundant repair). A copy of the data bits input into the ECC module 220 (except for the empty data bits output by mux 0) may also be transferred to the error correction module 240.

[0063] For the eight redundant data bits stored by the redundant data plane 205, these bits may be transferred directly to the redundant ECC circuit 235 (e.g., in place of the eight bits of data plane 0). A copy of the redundant data bits may also be transferred to the error correction module 240 (e.g., via mux 0 or some other component). Thus, all of the data bits that make up the requested codeword may be available for correction at the error correction module 240.

[0064] The ECC circuit can perform an initial ECC operation on the data bits received from the data plane, as described in more detail with reference to Figure 4 and 7 More specifically. Moreover, the redundant ECC circuit 235 can perform an initial ECC operation on the redundant data received from the redundant data plane 205, as described in more detail with reference to Figure 5 and 8 More specifically. The result of the initial ECC operation can be passed to the ECC circuitry 245 for further processing (e.g., additional ECC operations). The output of the ECC module 220 can be a certain number of syndrome bits that can be used for error correction. In some cases, the syndrome bits are derived from a bit-by-bit operation (e.g., an exclusive OR operation) performed on the parity bits and the bits output from the ECC circuitry 245.

[0065] After the syndrome bits are generated by the ECC module 220, they can be compared with the parity bits to determine whether an error exists in the corresponding codeword. For example, if the syndrome bits do not match the parity bits, an error can be detected. If an error is detected, the syndrome bits can be decoded (e.g., by a syndrome decoder included in the error correction module 240) to determine the location of the error. Once the location of the error is determined, the bit in error can be inverted (e.g., by a bit flip circuit included in the error correction module 240) to correct the error. After error correction has been performed, the codeword can be transmitted to other components or devices via the output bus 230.

[0066] Figure 3 An example Hamming matrix 300 that supports a direct input redundancy scheme using a dedicated ECC circuit in accordance with various embodiments of the present disclosure is illustrated. The Hamming matrix 300 can represent a (136, 128) Hamming code corresponding to 128 data bits, eight parity bits, and 136 total bits. The Hamming matrix 300 can be used in conjunction with an ECC circuit of the ECC circuits described, for example, with reference to Figure 2 Although described with reference to a (136, 128) Hamming code, any type of error correction code can be used to implement the techniques described herein.

[0067] The Hamming matrix 300 can illustrate the relationship between the parity bits, syndrome bits, and data bits across multiple data planes (e.g., sixteen data planes spanning from data plane 0 to data plane 15). For example, the Hamming matrix 300 can show how the parity bits of a codeword cover data from different data planes and how the corresponding syndrome bits can be generated from the data in those data planes.

[0068] The Hamming matrix 300 can be used to detect errors in a codeword and indicate the location of the error. For example, if the syndrome bits generated for a codeword do not match the parity bits of the codeword, the mismatch can indicate that the codeword contains an error. However, to locate the error, the device must know the data plane and bit where the error is stored. To determine the location of the error at the bit level within a particular data plane, the syndrome bits can be effectively compared with the syndrome patterns that make up each column of the Hamming matrix 300. The syndrome pattern that matches the syndrome bits can indicate the data plane (via syndrome bits S3 to S7) and the bit position (via syndrome bits S0 to S2) where the error is stored. For example, if the generated syndrome bits match the syndrome pattern 320, the device can determine that the error is in data bit D1 (indicated by syndrome bits S0 to S2) in data plane 0 (indicated by syndrome bits S3 to S7).

[0069] The Hamming matrix 300 can include a common matrix pattern 305 and a different matrix pattern 310. The common matrix pattern 305 shows the data bits covered by parity bits P0, P1, and P2. For example, as shown in the Hamming matrix 300, parity bit P0 covers (e.g., is based on) data bits D1, D3, D5, and D7 of all data planes, parity bit P1 covers data bits D2, D3, D6, and D7 of all data planes, and parity bit P2 covers data bits D4, D5, D6, and D7 of all data planes.

[0070] The common matrix pattern 305 also shows the data bits used to generate syndrome bits S0, S1, and S2 (which together indicate the location of the error at the bit level). The common matrix pattern 305 is called "common" because it is the same for each data plane (since each data plane stores eight data bits, in this example, only three bits are needed to indicate which one of the eight bits is in error). According to the Hamming matrix 300, syndrome bit S0 can be generated by performing an XOR operation on data bits D1, D3, D5, and D7 from all data planes, syndrome bit S1 can be generated by performing an XOR operation on data bits D2, D3, D6, and D7 from all data planes, and syndrome bit S2 can be generated by performing an XOR operation on data bits D4, D5, D6, and D7 from all data planes.

[0071] The different matrix patterns 310 show the data bits covered by the parity bits P3, P4, P5, P6, and P7. For example, according to the Hamming matrix 300, the parity bit P3 covers all the data bits in data planes 0, 2, 5, 6, 8, 11, 12, and 15 (e.g., based on), the parity bit P4 covers all the data bits in data planes 0, 3, 4, 6, 9, 10, 12, and 15, the parity bit P5 covers all the data bits in data planes 1, 2, 4, 6, 9, 11, 13, and 14, the parity bit P6 covers all the data bits in data planes 1, 3, 5, 7, 8, 10, 12, and 14, and the parity bit P7 covers all the data bits in data planes 1, 3, 5, 7, 9, 11, 13, and 15.

[0072] The different matrix patterns also show the data bits used to generate the syndrome bits S3, S4, S5, S6, and S7. The different matrix patterns 310 are called "different" because the matrices for each data plane are different or unique. For example, the syndrome matrix for data plane 0 is different from the syndrome matrices of all other data planes. This is because the syndrome bits S3 to S7 indicate the data plane where a storage error occurred. For example, the syndrome pattern 11000 of S3 to S7 may indicate data plane 0 with a storage error, while the syndrome pattern 11001 of S3 to S7 may indicate data plane 15 with a storage error. According to the Hamming matrix 300, the syndrome bit S3 can be generated by performing an XOR operation on all the data bits from data planes 0, 2, 5, 6, 8, 11, 12, and 15, the syndrome bit S4 can be generated by performing an XOR operation on all the data bits from data planes 0, 3, 4, 6, 9, 10, 12, and 15, the syndrome bit S5 can be generated by performing an XOR operation on all the data bits from data planes 1, 3, 5, 7, 8, 10, 12, and 14, and the syndrome bit S7 can be generated by performing an XOR operation on all the data bits from data planes 1, 3, 5, 7, 9, 11, 13, and 15.

[0073] For ease of illustration, the Hamming matrix 300 is presented in a compressed form. However, it should be understood that the different syndrome matrices for each data plane can be expanded, as shown in the partial enlarged view 315-a of data plane 0. Similarly, the complete syndrome matrices for the data planes can be expanded, as shown in the complete enlarged view 315-b of data plane 0.

[0074] Figure 4 Illustrate an example ECC module 400 that supports a direct input redundancy scheme using a dedicated ECC circuit according to various embodiments of the present disclosure. The ECC module 400 can be a reference Figure 2An example of the described ECC module. The ECC module 400 can be configured to generate and output a set of syndrome bits for a codeword that includes data bits from multiple data planes (e.g., data planes 0 to 15). The ECC module 400 can perform operations described using any combination of logic gates (e.g., OR, XOR, NOR, NAND, AND, NOT, and XNOR logic gates).

[0075] The ECC module 400 can include multiple ECC circuits (e.g., one ECC for each data plane involved in a retrieval operation). For example, the ECC module 400 can include sixteen ECC circuits, such as ECC circuits 0 to 15. The ECC module 400 can also include: an ECC circuitry 405, which can be an example of the ECC circuitry 245 described in the reference Figure 2 and a redundant ECC circuit 420, which can be an example of the redundant ECC circuit 235 described in the reference Figure 2 described.

[0076] Each ECC circuit can be configured to perform one or more bitwise operations on a set of data. A bitwise operation can be an operation that operates on one or more bit patterns at the bit level to return a single-bit result. For example, each ECC circuit can include a certain amount of logic gates that receive one or more bits as inputs and output a single bit, such as an XOR logic gate.

[0077] Thus, each ECC circuit can be configured to perform bitwise operations on data from the corresponding data plane. For example, ECC circuit 0 can be configured to perform bitwise operations on data (e.g., eight data bits) from data plane 0. Thus, ECC circuit 0 can include a certain amount of logic gates (or "bitwise operators"). The logic gates can operate on the data bits to output the result of one or more XOR operations to a logic stage 410. For example, ECC circuit 0 can output the result of an XOR operation on the data bits D1, D3, D5, D7 of data plane 0. The result of an XOR operation on data bits Dx, Dy, Dt, and Dz can be represented and referred to herein as Dxytz. Thus, the result of the operation performed by ECC circuit on data bits D1, D3, D5, and D7 can be represented and referred to as D1357. Similarly, ECC circuit 0 can output D2367, D4567, and D_ALL (which refers to the result of an XOR operation on all data bits D0 to D8).

[0078] Other ECC circuits can also be configured to output results similar to the XOR operations of ECC circuit 0. For example, all ECC circuits can be configured to output D1357, D2367, D4567, and D_ALL of their respective data bits. The ECC circuits can transmit D1357, D2367, D4567, and D_ALL to logic stage 410. Thus, as indicated by Hamming matrix 300, each ECC circuit can transmit its respective D1357 to the S0 circuit system ("S0 Cir."), D2367 to the S1 circuit system ("S1 Cir"), and D4567 to the S2 circuit system ("S2 Cir.").

[0079] The S0 circuit system can operate on its inputs to obtain the result of the XOR operation on those inputs. Thus, the S0 circuit system can effectively output the result of the XOR operation on data bits D1, D3, D5, D7 from each of those in the data plane (referred to as D1357_ALL). Similarly, the S1 circuit system can operate on its inputs to obtain the result of the XOR operation on those inputs. Thus, the S1 circuit system can effectively output the result of the XOR operation on data bits D2, D3, D6, D7 from each of those in the data plane (referred to as D1357_ALL). Similarly, the S2 circuit system can operate on its inputs to obtain the result of the XOR operation on those inputs. Thus, the S2 circuit system can effectively output the result of the XOR operation on data bits D4, D5, D6, D7 from each of those in the data plane (referred to as D4567_ALL). The outputs of the S0 circuit system, S1 circuit system, and S2 circuit system can be transmitted to logic stage 415 for additional operations.

[0080] Although each ECC circuit can output its corresponding D_ALL to logic stage 410, the D_ALL of each ECC circuit can be directed only to certain components of logic stage 410. For example, as indicated by Hamming matrix 300, only ECC circuits 0, 2, 5, 6, 8, 11, 12, and 15 can transmit their corresponding D_ALL to the S3 circuitry. This is because the syndrome bit S3 is based on all the data bits from data planes 0, 2, 5, 6, 8, 11, 12, and 15. Similarly, only ECC circuits 0, 3, 4, 6, 9, 10, 12, and 15 can transmit their corresponding D_ALL to the S4 circuitry, only ECC circuits 1, 2, 4, 6, 9, 11, 13, and 14 can transmit their corresponding D_ALL to the D5 circuitry, only ECC circuits 1, 3, 5, 7, 8, 10, 12, and 14 can transmit their corresponding D_ALL to the S6 circuitry, and only ECC circuits 1, 3, 5, 7, 9, 11, 13, and 15 can transmit their corresponding D_ALL to the S7 circuitry. Thus, logic stage 410 can transmit the result of an XOR operation on all the data from a selected data plane (referred to as D_ALL_Select) to logic stage 415.

[0081] The redundant ECC circuit 420 can receive redundant data (e.g., eight bits of redundant data) from a corresponding redundant data plane (e.g., the redundant data plane 205 described, for example, with reference to Figure 2 ). The redundant ECC circuit 420 can perform a bit-by-bit operation on the redundant data to effectively obtain the result of an XOR operation on the redundant data. For example, the redundant ECC circuit 420 can perform a bit-by-bit operation on the redundant data to obtain the result of an XOR operation on the redundant data bits RD1, RD3, RD5, and RD7 (denoted as RD1357). The redundant ECC circuit 420 can also obtain the result of an XOR operation on the redundant data bits RD2, RD3, RD6, and RD7 (denoted as RD2367), and the result of an XOR operation on the redundant data bits RD4, RD5, RD6, and RD7 (denoted as RD4567). Additionally, the redundant ECC circuit 420 can obtain the result of an XOR operation on all the redundant data bits (denoted as RD_ALL).

[0082] The redundant ECC circuit 420 can transmit RD1357, RD2367, and RD4567 to the corresponding circuitry in the logic stage 415 to generate syndrome bits S0, S1, and S2. For example, the redundant ECC circuit 420 can transmit RD1357 to the logic stage 415 through the conductive path 425-a, can transmit RD2367 to the logic stage 415 through the conductive path 425-b, and can transmit RD4567 to the logic stage 415 through the conductive path 425-c. The redundant ECC circuit 420 can transmit RD1357, RD2367, and RD4567 regardless of which data plane is selected for redundant repair (since S0, S1, and S2 are based on the selected data bits from all data planes).

[0083] However, the redundant ECC circuit 420 can selectively transmit RD_ALL to a subset of components (e.g., logic gates) in the logic stage 415 based on which data plane is selected for redundant repair. This is because only certain syndrome bits are based on the data of a given data plane. For example, as indicated by the Hamming matrix 300, the syndrome bit S3 is based on the data in data planes 0, 2, 5, 6, 8, 11, 12, and 15, but not on the data from data planes 1, 3, 4, 7, 9, 10, 13, and 14. Thus, if data plane 1 is selected for redundant repair, the redundant ECC circuit 420 may not transmit RD_ALL to the component responsible for generating S3 because S3 does not depend on the data from data plane 1 (which has been replaced by redundant data). Accordingly, the redundant ECC circuit 420 can selectively transmit RD_ALL (e.g., the result of a bit-by-bit operation on the redundant data) to the logic stage 415 through the conductive path 425-d, which can be a conductive path between the output of the redundant ECC circuit 420 and the logic stage 415.

[0084] The logic stage 415 can receive the outputs from the logic stage 410 and the redundant ECC circuit 420 and generate the syndrome bits of the codeword. The syndrome bits can be generated according to the Hamming matrix 300. The syndrome bits can be used in subsequent error correction operations to correct errors in the codeword.

[0085] Figure 5 An example ECC module 500 that supports a direct input redundancy scheme using a dedicated ECC circuit according to various embodiments of the present disclosure is described. The ECC module 500 can be an example of the ECC module referred to Figure 2 and 4 described. The ECC module 500 can be configured to generate and output a set of syndrome bits for a codeword that includes data bits from multiple data planes (e.g., data planes 0 to 15).

[0086] The ECC module 500 can include, as a reference Figure 2 and4 A certain amount of ECC circuits of the described ECC circuit examples. Each ECC circuit can be coupled to a corresponding data plane (e.g., ECC circuit 0 can be coupled to data plane 0, ECC circuit 1 can be coupled to data plane 1, etc.). The ECC module 500 can also include an ECC circuitry 505 and redundant ECC circuits 520, which can be examples of the ECC circuitry and redundant ECC circuits as described in reference Figure 2 and 4 Examples of the described ECC circuitry and redundant ECC circuits. Although described with reference to XOR gates, the functions of the ECC circuits and the ECC circuitry 505 can be implemented using any type and combination of logic gates.

[0087] In this example, each ECC circuit can receive a certain amount of data bits from its corresponding data plane and perform a bit-by-bit operation on the amount of data bits before outputting a single resulting bit to the ECC circuitry 505. Since the syndrome bits for the (136, 128) Hamming code are derived from XOR operations on various combinations of the data bits in the codeword, the ECC circuit can perform XOR operations on its corresponding data bits. For example, ECC circuit n can include a certain amount of XOR logic gates configured to perform XOR operations on the data bits received from data plane n. The XOR operations can include performing an XOR operation on data bits D1, D3, D5, and D7 (from data plane n) using a first logic gate, performing an XOR operation on data bits D2, D3, D6, and D7 (from data plane n) using a second logic gate, performing an XOR operation on data bits D4, D5, D6, and D7 (from data plane n) on Venus XOR operation, and performing an XOR operation on data bits D0, D1, D2, and D3 (from data plane n) using a fourth logic gate. ECC circuit n can also include an additional (e.g., fifth) logic gate configured to perform an XOR operation on the results of the XOR operations performed by the third and fourth logic gates.

[0088] Thus, as an example, the ECC circuit 0 for data plane 0 may perform an XOR operation on data bits D1, D3, D5, and D7 (from data plane 0) using logic gate 515-a, perform an XOR operation on data bits D2, D3, D6, and D7 (from data plane 0) using logic gate 515-b, perform an XOR operation on data bits D4, D5, D6, and D7 (from data plane 0) using logic gate 515-c, and perform an XOR operation on data bits D0, D1, D2, and D3 (from data plane 0) using logic gate 515-d. The ECC circuit 0 may also perform an XOR operation on the results of the XOR operations of logic gates 515-c and 515-d using logic gate 515-e to effectively obtain the result of a single XOR operation on all data bits from data plane 0. Thus, the output of logic gate 515-a may be D1357, the output of logic gate 515-b may be D2367, the output of logic gate 515-c may be D4567, the output of logic gate 515-d may be D0123, and the output of logic gate 515-e may be D_ALL.

[0089] The results of the XOR operations performed by different ECC circuits may be input into additional logic gates (e.g., included in logic state 510) to effectively obtain the result of a single XOR operation on those data bits. For example, according to Hamming matrix 300, an XOR operation may be effectively performed on data bits D1, D3, D5, and D7 from each data plane by logic gate 515-f. This is because the result of each XOR operation on the selected data bits (D1, D3, D5, D7) for each data plane may be input into logic gate 515-f. For example, D1357 for each data plane 0 to 15 may be input into logic gate 515-f.

[0090] Regardless of the exact input, the output of logic gate 515-f may be the result of an XOR operation on data bits D1, D3, D5, and D7 from all data planes involved in a read operation. Similarly, the output of logic gate 515-g may be the result of an XOR operation on data bits D2, D3, D6, and D7 from all data planes involved in a read operation. And the output of logic gate 515-h may be the result of an XOR operation on data bits D4, D5, D6, and D7 from all data planes involved in a read operation. However, the data bits from the data plane may be invalidated (e.g., set to zero) before being inserted into the corresponding ECC circuit for selecting the data plane for redundancy repair. For example, when data plane 0 is selected for redundancy repair, the data bits D0 to D7 inserted into ECC circuit 0 may be all zeros. This technique prevents the replaced data bits from interfering with the syndrome generation process.

[0091] Unlike logic gates 515-f through 515-h, logic gates 515-i through 515-u may not output the result of an XOR operation performed on the selected data bits from all data planes. Instead, logic gates 515-i through 515-u may output the result of an XOR operation performed on all data bits from the selected data plane. For example, logic gate 515-i may actually perform an XOR operation on all data from data planes 0, 2, 5, 6, 8, 11, 12, and 15 (as specified by Hamming matrix 300). The result of this XOR operation may be represented as and referred to as D_ALL S3, as it represents the XOR of all relevant non-redundant data bits used to generate S3. However, as described above, the data from the replaced data plane (e.g., data plane 0 in this case) may be invalid (e.g., set to zero) before being inserted into ECC module 500.

[0092] As referenced Figure 4 as described, redundant ECC circuit 520 may also transmit signals to ECC circuitry 505 (e.g., to logic stage 525). For example, redundant ECC circuit 520 may transmit RD1357 to logic gate 515-n, RD2367 to logic gate 515-o, and RD4567 to logic gate 515-p. Thus, the result of an XOR operation on redundant data bits D1, D3, D5, and D7 may be passed to logic gate 515-n, the result of an XOR operation on redundant data bits D2, D3, D6, and D7 may be passed to logic gate 515-o, and the result of an XOR operation on redundant data bits D4, D5, D6, and D7 may be passed to logic gate 515-p.

[0093] Redundant ECC circuit 520 may also selectively transmit the XOR result of all redundant data bits to certain components of logic stage 525. For example, when the selected data plane for redundant repair is one of the data planes upon which the generation of syndrome bit S3 is based, redundant ECC circuit 520 may transmit RD_ALL to logic gate 515-q. When RD_ALL is transmitted to logic gate 515-q, it may be represented as and referred to as RD_ALL_S3. Thus, when data plane 0 is selected for redundant repair, RD_ALL_S3 may be transmitted to logic gate 515-q (since S3 is generated based on all data bits from data planes 0, 2, 5, 6, 8, 11, 12, and 15 and the redundant data represents data from data plane 0). However, if data plane 1 is selected for redundant repair, RD_ALL may not be transmitted to logic gate 515-q (since S3 is generated based on all data bits from data planes 0, 2, 5, 6, 8, 11, 12, and 15 and the redundant data represents data from data plane 1).

[0094] In a similar manner, when the data plane selected for redundancy repair is one of the data planes on which the generation of the syndrome bit S4 is based, RD_ALL can be passed to logic gate 515-r. When RD_ALL is passed to logic gate 515-r, it can be represented as and referred to as RD_ALL_S4. Thus, when data plane 0 is selected for redundancy repair, RD_ALL_S4 can be passed to logic gate 515-r (because S4 is generated based on all the data bits from data planes 0, 3, 4, 5, 8, 9, 12, and 15, and the redundant data represents the data from data plane 0). However, if data plane 1 is selected for redundancy repair, RD_ALL may not be passed to the logic gate (because S4 is generated based on all the data bits from data planes 0, 3, 4, 5, 8, 9, 12, and 15, and the redundant data represents the data from data plane 1). Thus, the result of the XOR operation on all the redundant data bits can be passed from the redundant ECC circuit 520 to the ECC circuit system 505 based on the data plane selected for redundancy repair. To complete the example of data plane 0, none of RD_ALL_S5, RD_ALL_S6, or RD_ALL_S7 can be passed to the ECC circuit system 505 because none of these data planes are used to generate the syndrome bits S5, S6, or S7 when data plane 0 is selected for redundancy repair.

[0095] Thus, logic gates 515-q through 515-u can each be described as logic gates coupled to the ECC circuit and configured to receive the result of a bit-by-bit operation on the data bits from the selected data plane of the data planes. For a given logic gate, the result of the bit-by-bit operation can be transmitted on the conductive path between the output of the redundant ECC circuit 520 and the input of the logic gate. For example, as described with reference to Figure 4 the result of the bit-by-bit operation can be transmitted through conductive path 425-d. In some cases, another logic gate can be coupled to the ECC circuit 520 and can form part of the conductive path. For example, the logic gate 620 described with reference to Figure 6 can form part of the conductive path.

[0096] The logic gates in logic stage 525 can receive the result of the XOR operation on the regular data and the result of the XOR operation on the redundant data. Each logic gate in logic stage 525 can perform an XOR operation on its inputs to output a syndrome bit (or a bit that serves as the basis for a syndrome bit). For example, logic gate 515-n can perform an XOR operation on D1357_ALL and RD1357 to obtain S0. Similarly, logic gate 515-o can perform an XOR operation on D2367_ALL and RD2367 to obtain S1. And logic gate 515-p can perform an XOR operation on D4567_ALL and RD4567 to obtain S2.

[0097] Other logic gates in the logic stage 525 can also perform XOR operations on their corresponding inputs, and one of the inputs can be invalidated by the redundant ECC circuit 520 (as described in reference Figure 6 ). For example, when data plane 0 is selected for redundant repair, the logic gate 515-q can perform an XOR operation on D_ALL_S3 and RD_ALL_S3 to obtain the syndrome bit S3. And the logic gate 515-r can perform an XOR operation on D_ALL_S4 and RD_ALL_S4 to obtain the syndrome bit S4. However, instead of operating on RD_ALL_S5, RD_ALL_S6, and RD_ALL_S7, the logic gates 515-s, 515-t, and 515-u can operate on empty data bits (e.g., logical zeros). This is because the syndrome bits S5, S6, and S7 are not based on the data from data plane 0. Therefore, the logic gate 515-s can perform an XOR operation on D_ALL_S5 and logical zero to obtain the syndrome bit S5. Similarly, the logic gate 515-t can perform an XOR operation on D_ALL_S6 and logical zero to obtain the syndrome bit S6. And the logic gate 515-u can perform an XOR operation on D_ALL_S6 and logical zero to obtain the syndrome bit S7.

[0098] Figure 6 Illustrate an example redundant ECC circuit 600 and an enabling circuitry 605 that support a direct input redundancy scheme using a dedicated ECC circuit according to various embodiments of the present disclosure. The redundant ECC circuit 600 can be an example of the redundant ECC circuits described in reference Figure 2 , 4 and 5. Therefore, the redundant ECC circuit 600 can be coupled to the redundant data plane via digital lines and can be configured to perform an XOR operation on the redundant data received from the redundant data plane. In combination with the enabling circuitry 605, the redundant ECC circuit 600 can selectively transfer the result of the XOR operation on the redundant data to other components (e.g., to the ECC circuitry 505 as described in reference Figure 5 ).

[0099] The redundant ECC circuit 600 can include a certain amount of logic gates configured to output RD1357, RD2367, RD4567, and RD_ALL. However, RD_ALL can be appropriately transferred to certain selected components of the ECC circuitry 505. For example, when data plane 0 is selected for redundancy, RD_ALL can be appropriately transferred to the logic gate 515-q and the logic gate 515-r, but not to the logic gates 515-s to 515-u (because in some cases, only the syndrome bits S3 and S4 are based on the data from data plane 0).

[0100] According to the techniques described herein, enable circuitry 605 may be used to selectively convey RD_ALL or invalidate it. The enable circuitry 605 may include enable circuitry for each of the sub-bits S3 through S7. For example, the enable circuitry 605 may include an S3 enable circuitry for correcting sub-bit S3, an S4 enable circuitry for correcting sub-bit S4, an S5 enable circuitry for correcting sub-bit S5, an S6 enable circuitry for correcting sub-bit S6, and an S7 enable circuitry for correcting sub-bit S7. Each enable circuitry may be correspondingly coupled. For example, the output of the S3 enable circuitry may be coupled to logic gate 515-q, the output of the S4 enable circuitry may be coupled to logic gate 515-r, the output of the S5 enable circuitry may be coupled to logic gate 515-s, the output of the S6 enable circuitry may be coupled to logic gate 515-t, and the output of the S7 enable circuitry may be coupled to logic gate 515-u.

[0101] Each enable circuitry may be configured to convey the output of the redundant ECC circuitry 600 or invalidate it. For example, the S3 enable circuitry may be configured to convey RD_ALL (e.g., as RD_ALL_S3) or a logic zero based on the data plane selected for redundant repair. Each enable circuitry may include a certain amount of OR logic gates 615 coupled to an AND gate 620.

[0102] Each enable circuitry may receive RD_ALL and a corresponding control signal as inputs. The control signal may be the control bit CredEn <x>a combination where each indicates whether the corresponding data plane x has been selected for redundant repair. For example, CredEn<0> can indicate that data plane 0 has been selected for redundant repair when being logic one, and can indicate that data plane 0 has not been selected for redundant repair when being logic zero. Thus, in some cases, the control signal can indicate that the redundant data is related to (or its substitute for) the data stored by the data plane corresponding to the enabling circuit that receives the control signal.

[0103] Each control bit of the control signal can represent the redundant repair status of the data plane, and the bits of the data plane serve as the basis for the corresponding syndrome bits. Thus, the control bits for the S3 enabling circuit can be CredEn<0>, CredEn<2>, CredEn<5>, CredEn<6>, CredEn<8>, CredEn<11>, CredEn<12>, and CredEn<15> (because, as defined by the Hamming matrix 300, XOR based on the data bits in data planes 0, 2, 5, 6, 8, 11, 12, and 15 generates S3). As another example, the control bits for the S4 enabling circuit can be CredEn<0>, CredEn<3>, CredEn<4>, CredEn<6>, CredEn<9>, CredEn<10>, CredEn<12>, and CredEn<15> (because, as defined by the Hamming matrix 300, XOR based on the data bits in data planes 0, 3, 4, 6, 9, 10, 12, and 15 generates S4).

[0104] Taking the example where data plane 0 has been selected for redundant repair, the control bits for the S3 enabling circuit can be 10000000 (starting from CredEn<0> and ending with CredEn<15>). Thus, OR logic gate 615-a can output logic one, and OR logic gate 615-b can output logic zero. The outputs of logic gates 615-a and 615-b can drive OR logic gate 615-c. Thus, in this example, OR logic gate 615-c can output logic one. The output of OR logic gate 615-c can in turn (and together with RD_ALL) drive AND logic gate 620 (e.g., in response to the control signal). Thus, AND logic gate 620 can output RD_ALL (e.g., as RD_ALL_S3 output to logic gate 515-q) when the output of OR logic gate 615-c is one (as in this case), or output logic zero when the output of OR logic gate 615-c is zero (e.g., this would be the case if instead of data plane 0, data plane 3 were selected for redundant repair).

[0105] Accordingly, the AND logic gate 620 will be described as an AND logic gate that is coupled to the output of the redundant ECC circuit and configured to output a signal based at least in part on a control signal (e.g., a control signal consisting of the control bits CredEn<*>), the signal representing the result of an XOR operation on redundant data (e.g., RD_ALL). The signal can be transmitted to a logic gate that is coupled to both the output of the AND logic gate 620 and a set of regular data planes. For example, the signal can be transmitted to one or more of the logic gates 515-q to 515-u as described with reference to Figure 5 as described.

[0106] In some cases, the redundant ECC circuit 600 and the enable circuitry 605 can be operated as follows. The redundant ECC circuit 600 can perform a first bit-by-bit operation (e.g., an XOR operation) on a first set of redundant data (e.g., redundant data bits 0 to 7 for a first codeword). The first set of redundant data can be the same as the data stored (or expected to be stored) at a first data plane (e.g., data plane 0). The result of the first bit-by-bit operation can be transmitted to a first set of logic gates (e.g., logic gates 515-q and 515-r for syndrome bits S3 and S4) based on the redundant data being for the first data plane (e.g., data plane 0). In some cases, a first control signal can indicate that the redundant data is for the first data plane. A first set of syndrome bits for the first codeword can be generated based on the result of the first bit-by-bit operation.

[0107] The redundant ECC circuit 600 can also perform a second bit-by-bit operation (e.g., an XOR operation) on a second set of redundant data (e.g., redundant data bits 0 to 7 for a second codeword). The second set of redundant data can be the same as the data stored (or expected to be stored) at a second data plane (e.g., data plane 1). The redundant ECC circuit 600 can transmit the result of the second bit-by-bit operation to a second set of logic gates (e.g., logic gates 515-s, 515-t, and 515-u corresponding to syndrome bits S5, S6, and S7) that are different from the first set of logic gates (e.g., logic gates 515-q and 515-r corresponding to S3 and S4). The result of the second bit-by-bit operation can be transmitted to the second set of logic gates based on the redundant data being for the second data plane (e.g., data plane 1). In some cases, a second control signal can indicate that the redundant data is for the second data plane. A second set of syndrome bits for the second codeword can be generated based on the result of the second bit-by-bit operation.

[0108] Figure 7 An example Hamming matrix 700 that supports a direct input redundancy scheme that utilizes an adaptive syndrome decoder circuit in accordance with various embodiments of the present disclosure is illustrated. The Hamming matrix 700 can represent a (144, 136) Hamming code corresponding to 136 data bits, eight parity bits, and 144 total bits. The Hamming matrix 700 can be associated with an ECC circuit (e.g., as referenced Figure 8 the ECC circuits described) and redundant ECC circuits (e.g., as referenced Figure 9 to the redundant ECC circuits described). Although described with reference to (144, 136) Hamming codes, any type of error correction code may be used to implement the techniques described herein.

[0109] The Hamming matrix 700 may be different from the Hamming matrix 300 in that it includes an additional matrix for redundant data. This additional matrix may be referred to as the redundant data matrix 705. Adding the redundant data matrix 705 may affect the generation of syndrome bits. For example, by adding the redundant data matrix 705, S3 is calculated by performing an XOR operation on the data bits from data planes 0, 2, 5, 6, 8, 11, 12, 15 and the redundant data plane (as compared to performing an XOR operation only on the data bits from data planes 0, 2, 5, 6, 8, 11, 12, 15). If an error occurs in the redundant data, the fact that an error has occurred in the redundant data plane will be indicated by the last four syndrome bits S3 to S7 that match the pattern 01110. As previously described, the position of the erroneous data bit is indicated by the first three syndrome bits. Thus, when the syndrome bits generated by the ECC module are 11001110 (and do not match the parity bits), the position of the error in data bit 3 from the redundant data plane can be detected.

[0110] For ease of illustration, the Hamming matrix 700 is presented in a compressed form. However, it should be understood that different matrices may be expanded for each data plane (and redundant data plane), as discussed Figure 3 previously.

[0111] Figure 8 An example ECC module 800 is illustrated that supports a direct input redundancy scheme utilizing an adaptive syndrome decoder circuitry in accordance with various embodiments of the present disclosure. The ECC module 800 may be an example of the ECC module described Figure 2 previously. The ECC module 800 may be configured to generate and output a set of syndrome bits for a codeword that includes data bits from a plurality of data planes (e.g., data planes 0 to 15).

[0112] In the configuration of the circuitry for generating syndrome bits S3 to S7, the ECC module 800 may be different from the ECC module 500. Moreover, the redundant ECC circuit 810 may be different from (as referenced Figure 9 The redundant ECC circuit 520 described above. For example, the redundant ECC circuit 810 can transmit RD_ALL to logic gates 815-a, 815-b, and 815-c regardless of which data plane is selected for redundant repair in some cases. Moreover, no redundant data can be involved in generating syndrome bits S3 and S7 because, as shown in the Hamming matrix 700, in some cases, only syndrome bits S4, S5, and S6 are based on redundant data.

[0113] Figure 9 An example redundant ECC circuit 900 that supports a direct input redundancy scheme using an adaptive decoder circuit system according to various embodiments of the present disclosure is described. The redundant ECC circuit 900 can be an example of the redundant ECC circuit described in the reference Figure 2 The redundant ECC circuit 900 can transmit the result of the XOR operation on the redundant data to other components regardless of which data plane is selected for redundant repair. This scheme can be different from the scheme for the redundant ECC circuit 600. In the scheme for the redundant ECC circuit 600, the result of the XOR operation on the redundant data can be selectively transmitted to certain components based on the data plane that has been selected for redundant repair.

[0114] For example, the redundant ECC circuit 900 can transmit the result of the XOR operation for error correction of two different codewords (e.g., the first codeword and the second codeword) as follows. To perform error correction on the first codeword, the redundant ECC circuit 900 can perform a first bit-by-bit operation (e.g., an XOR operation) on a first set of redundant data for the first data plane. The first set of redundant data can be the data included in the first codeword and corresponding to the data stored by the first data plane. The redundant ECC circuit 900 can then transmit the result of the first bit-by-bit operation (e.g., RD_ALL) to a combination of logic gates (e.g., logic gates 815-a, 815-b, and 815-c corresponding to syndrome bits S4, S5, and S6). The result of the first bit-by-bit operation can be transmitted to the combination of logic gates independently of the use of the first set of redundant data for the first data plane. Next, a first set of syndrome bits for the first codeword can be generated based on the result of the first bit-by-bit operation. In some cases, at least one of the first set of syndrome bits can be generated by performing an XOR operation on the result of the first bit-by-bit operation (e.g., syndrome bit S4 can be generated by logic gate 815-a that performs an XOR operation on RD_ALL).

[0115] To perform error correction on the second codeword, the redundant ECC circuit 900 may perform a second bit-by-bit operation (e.g., an XOR operation) on a second set of redundant data for a second data plane different from the first data plane. The second set of redundant data may be data included in the second codeword and corresponding to the data stored by the second data plane. The redundant ECC circuit 900 may then transmit the result of the second bit-by-bit operation (e.g., RD_ALL) to the same combination of logic gates (e.g., logic gates 815-a, 815-b, and 815-c corresponding to syndrome bits S4, S5, and S6). The result of the second bit-by-bit operation may be transmitted to the combination of logic gates independently of the use of the second set of redundant data for the first data plane. Thus, a second set of syndrome bits for the second codeword may be generated based on the result of the second bit-by-bit operation. In some cases, at least one of the second set of syndrome bits may be generated by performing an XOR operation on the result of the first bit-by-bit operation (e.g., syndrome bit S4 may be generated by logic gate 815-a that performs an XOR operation on RD_ALL).

[0116] Figure 10 Illustrate an example error correction module 1000 that supports a direct input redundancy scheme that utilizes an adaptive decoder circuitry system in accordance with various embodiments of the present disclosure. The error correction module 1000 may be an example of the error correction module 240 described in reference [[ID=5 The error correction module 1000 may include a syndrome decoder circuit 1005, a data selector 1010, a bit flip circuit 1015, and an inverter 1020. Although shown as including a single syndrome decoder circuit, the error correction module 1000 may include multiple syndrome decoders (e.g., one for each data plane). In this example, the syndrome decoder circuit 1005 may be used for the first data plane (e.g., data plane 0). The error correction module 1000 may perform error correction on data bits that make up, for example, a codeword.

[0117] The syndrome decoder circuit 1005 may include multiple decoders, and each decoder may be composed of one or more logic gates. In this example, the decoder circuit includes NAND logic gates. However, other types of logic gates may be used to implement the techniques described herein.

[0118] During an error correction operation, the data selector 1010 may receive data bits (e.g., from one of the conventional data planes discussed in reference ​ or from the redundant data plane 205). During the same error correction operation, the inverter 1020 may receive a control signal (e.g., CredEn) indicating whether the data plane x corresponding to the syndrome decoder circuit 1005 has been selected for redundancy repair. <x>)。For example, when the syndrome decoder circuit 1005 corresponds to data plane 0, the inverter 1020 may receive a control signal CredEn<0> indicating whether data plane 0 has undergone redundant repair.

[0119] The data selector 1010 may also receive a control signal (e.g., CredEn <x>) and uses the control signal as a basis for selecting redundant data or standard data for error correction. After selecting the data, the data selector 1010 can transfer the selected data to the bit flip circuit 1015. However, if the syndrome decoder circuit 1005 indicates to do so, the bit flip circuit 1015 can invert the data bits. Otherwise, the data bits can be transferred to the output bus 1025 without inversion, and the output bus can be an example of the output bus 230 described in reference ​ described output bus 230.

[0120] Upon receiving the control signal CredEn <x>Afterwards, the inverter 1020 may invert the control signal to produce an inverted (or "complemented") version of the control signal, which may be referred to as CredEn <x>'. In an instance of data plane 0, inverter 1020 may output CredEn<0>'. In general, the inverted version of a bit or control signal n may be denoted as n'.

[0121] Syndrome decoder circuit 1005 may receive a control signal and the inverted version of the control signal as inputs. For example, redundancy decoder 1035 may receive the control signal, and standard decoder 1030 may receive the inverted version of the control signal. In an instance of data plane 0, redundancy decoder 1035 (e.g., logic gate 1045-b) may receive CredEn<0> and standard decoder 1030 (e.g., logic gate 1045-a) may receive CredEn<0>'. Given the relationships between redundancy decoder 1035, standard decoder 1030, and logic gate 1050, using the control signal and the inverted control signal as inputs to redundancy decoder 1035 and standard decoder 1030 respectively ensures that the output of either redundancy decoder 1035 or standard decoder 1030 is effectively disabled.

[0122] Each of the decoders in syndrome decoder circuit 1005 may receive a certain amount of syndrome-based bits (e.g., syndrome bits or inverted syndrome bits) as inputs. These inputs may change based on the position of the bits that have undergone error correction. For example, depending on whether the bit is the first bit (e.g., data bit 0) or the last bit (e.g., data bit 7) stored in the data plane that has undergone an error correction operation, different inputs may be used. Thus, in addition to receiving the control signal, redundancy decoder 1035 may also receive a certain amount of syndrome-based inputs. And, in addition to receiving the inverted control signal, standard decoder 1030 may receive a set of syndrome-based inputs. According to the techniques described herein, the syndrome-based bits received by standard decoder 1030 may be the inverted version (or "complement") of the syndrome-based bits received by redundancy decoder 1035. The reason for this is explained below.

[0123] In an instance of data plane 0, the common decoder 1040 may receive S0', S1', and S2' at logic gate 1045-c-1, and S4 and S7' at logic gate 1045-c-2. The common decoder 1040 may be referred to as "common" because it receives syndrome bits that are common (according to the Hamming matrix 700) to data plane 0 and the redundant data plane as inputs. This can be easily seen by placing the two matrices adjacent to each other in the comparison matrix 1055, which shows that for both data plane 0 and the redundant data plane, the syndrome bit S4 (equal to 1) and the parity bit S7 (equal to 0) are the same. Since they are part of the common matrix, S0, S1, and S2 are also the same for data plane 0 and the redundant data plane. Thus, in an instance where data plane 0 has undergone redundant repair, the common decoder 1040 may receive versions of the syndrome bits S0, S1, S2, S4, and S7.

[0124] Determine whether the syndrome bits are inverted before being inserted into the error correction module 1000 based on the expected values of the syndrome bits given by the Hamming matrix 700. For example, the syndrome bits may be processed (e.g., inverted) such that only a logical one is input to the syndrome decoder circuit 1005 if they are true for the Hamming matrix 700. For example, when performing an operation to detect an error in data bit 0 of data plane 0, the syndrome bits S0, S1, S2, S5, S6, and S7 may be inverted such that they appear as a logical one to the syndrome decoder circuit 1005. Similarly, when performing an operation to detect an error in data bit 0 of the redundant data plane, the syndrome bits S3 and S7 may be inverted such that they appear as a logical one to the syndrome decoder circuit 1005.

[0125] Since the syndrome bits S3, S5, and S6 are different between the matrices used for data plane 0 and the redundant data plane (e.g., 100 for data plane 0 compared to 011 for the redundant data plane), the syndrome bits must be processed differently and input to different decoders. In an instance of data plane 0, the syndrome bits S5 and S6 may be inverted such that S3, S5', and S6' (e.g., 111) may be input to the standard decoder 1030. And the syndrome bit S3 may be inverted such that S3', S5, and S6 (111) may be input to the redundant decoder 1035. Thus, the redundant decoder 1035 may receive as input the complement (S3', S5, S6) of the syndrome-based input (S3, S5', S6') received by the standard decoder 1030 (and vice versa).

[0126] After receiving their respective inputs, standard decoder 1030, redundant decoder 1035, and common decoder 1040 may convey the result of the NAND operation on those inputs to other components of syndrome decoder circuit 1005. In an example of data plane 0, standard decoder 1030 may convey the result of the NAND operation on S3, S5', and S6'. If all inputs of standard decoder 1030 are logic one, standard decoder 1030 may output logic zero. Otherwise, standard decoder 1030 may output logic one. Similarly, if all inputs of redundant decoder 1035 are logic one, redundant decoder 1035 may output logic zero. Otherwise, redundant decoder 1035 may output logic zero.

[0127] Logic gate 1050 may be an AND logic gate (or perform the operation of an AND logic gate). Logic gate 1050 may receive the outputs of standard decoder 1030 and redundant decoder 1035 as inputs. Logic gate 1050 may perform an AND operation on its inputs and output the result of the AND operation (e.g., to logic gate 1060). Thus, logic gate 1050 may be configured to effectively pass the output of either standard decoder 1030 or redundant decoder 1035 to the next stage (e.g., to logic gate 1060).

[0128] Since logic gate 1050 is driven by the output of either standard decoder 1030 or redundant decoder 1035, and since the driving output is determined based on a control signal, syndrome decoder circuit 1005 is configured to adjust its output at least in part based on whether the redundant data received by the redundant ECC circuit corresponds to the data stored by the first data plane.

[0129] In other words, the output of syndrome decoder circuit 1005 may be based on a first set of inputs (e.g., the inputs of standard decoder 103) and a second set of inputs (e.g., the inputs of redundant decoder 1035). According to the techniques described herein, syndrome decoder circuit 1005 may control its output by invalidating the first set of inputs when the redundant data is for (e.g., corresponds to) the first data plane, and invalidating the second set of inputs when the redundant data is for (e.g., corresponds to) a data plane other than the first data plane. If a set of inputs does not change the output of syndrome decoder circuit 1005, it may be referred to as invalid.

[0130] Logic gate 1060 can be a NOR logic gate (or perform the function of a NOR logic gate). Logic gate 1060 can receive the output of common decoder 1040 and the output of logic gate 1050 as inputs. In an example of data plane 0, the output of common decoder 1040 can be 1) the result of a NAND operation on S0', S1', and S2, and 2) the result of a NAND operation on S4 and S7'. Logic gate 1060 can perform a NOR operation on its inputs and output the result of the NOR operation to, for example, inverter 1065 and / or bit flip circuit 1015. Inverter 1065 can invert the output of logic gate 1060 and transmit the inverted version of the output of logic gate 1060 to bit flip circuit 1015. Thus, the syndrome decoder circuit 1005 can be configured to output a control signal indicating whether to invert a selected data bit.

[0131] Bit flip circuit 1015 can also receive selected data from data selector 1010. For example, bit flip circuit 1015 can receive regular data bits from data plane 0 (e.g., when data plane 0 is not selected for redundancy repair), or redundant data bits from a redundant data plane (e.g., when data plane 0 is selected for redundancy repair). Based on the output of syndrome decoder circuit 1005 (e.g., the control signal and the control signal'), bit flip circuit 1015 can invert the data bit. After inverting the data bit, or after preventing the inversion of the data bit, bit flip circuit 1015 can output the data bit (or the inverted data bit) to output bus 1025 to communicate with other components. Thus, error correction module 1000 can perform error correction on data bits from a regular data plane or a redundant data plane.

[0132] ​ Block diagram 1100 illustrating a memory array supporting a direct input redundancy scheme utilizing an adaptive decoder circuit system in accordance with various embodiments of the present disclosure. Block diagram 1100 can include memory array 100-a, which can be an example of memory array 100 as discussed ​ above. Memory array 100-a can be referred to as an electronic memory device, and can include memory controller 140-a, word lines 110-a, bit lines 115-a, and sense components 125-a, which can be examples of memory controller 140, word lines 110, bit lines 115, and sense components 125 described ​ above. Memory array 100-a can include data plane 1125, which can include a regular data plane, a redundant data plane, and a parity data plane.

[0133] Memory array 100-a can also include reference component 1120, ECC module 220-a, and error correction module 240-a. The components of memory array 100-a can communicate electronically with each other and can perform the functions described ​ The described functions.

[0134] Memory controller 140-a can combine with other components to apply voltages across memory array 100-a, write data to memory cells 105-a, read data from data plane 1125, and generally operate memory array 100-a, as ​ described. Memory controller 140-a can include bias component 1110 and timing component 1115. Memory controller 140-a can communicate electronically with data plane 1125, sense component 125-a, and reference component 1120.

[0135] Bias component 1110 can be configured (e.g., by memory controller 140-a) to activate word lines 110-a or digit lines 115-a by applying voltages to those various nodes. For example, bias component 1110 can be configured to apply voltages to read or write memory cells as described herein. In some cases, memory controller 140-a can include a row decoder, column decoder, or both as referenced ​ described. This can enable memory controller 140-a to access one or more memory cells within data plane 1125. Bias component 1110 can also provide a voltage potential to reference component 1120 in order to generate a reference signal for sense component 125-a. Additionally, bias component 1110 can provide a voltage potential for the operation of sense component 125-a.

[0136] Timing component 1115 can be configured to control the timing of various word line selections, board biasing, or component activation / deactivation. For example, timing component 1115 can control the timing of voltage application to perform the memory functions discussed herein, such as reading and writing, and error correction. In some cases, timing component 1115 can control the operation of bias component 1110.

[0137] Reference component 1120 can include various components for generating a reference signal for sense component 125-a. Reference component 1120 can include circuitry configured to generate the reference signal.

[0138] Sense component 125-a can compare the signal from the memory cell with the reference signal from reference component 1120. After determining the logical state stored by the memory cell, sense component 125-a can transmit a signal representing the logical state to other components of memory array 100-a. In some cases, the signal representing the logical state can be transmitted to a data selector, as referenced ​ As described, it can also transmit signals to the ECC module 220-a and / or the error correction module 240-a. In some cases, the reference component 1120 and the sensing component 125-a can be components of the memory controller 140-a.

[0139] In some cases, in combination with the ECC module 220-a and the error correction module 240-a, the memory controller 140-a can perform error correction on the codewords retrieved from the data plane 1125. As part of the error correction operation, the memory array 100-a can generate (e.g., via the ECC module 220-a) syndrome bits for the data stored in the data plane 1125. The memory array 100-a can then select data bits from the data for the error correction operation. The memory array 100-a can transmit a control signal indicating whether the data bit is an alternative to a data bit stored in one of the data planes to a syndrome decoder configured for the error correction operation. Based on the control signal, the memory array 100-a can decode the syndrome bits to determine whether the data bit should be corrected (e.g., inverted).

[0140] ​ Illustrate a system 1200 that supports a direct input redundancy scheme that utilizes an adaptive decoder circuit system in accordance with various embodiments of the present disclosure. The system 1200 includes a device 1205, which can be or include a printed circuit board to connect or physically support various components. The device 1205 includes a memory array 100-b, which can be an example of the memory array 100 as described in the reference ​ and 11 The memory array 100-b can include a memory controller 140-b and a data plane 1125-a, which can be examples of the memory controller 140 and the data plane 1125 as described in the reference ​ and 11 The device 1205 can also include a processor 1210, a BIOS component 1215, peripheral components 1220, and an input / output control component 1225. The components of the device 1205 can communicate electronically with each other via a bus 1230.

[0141] The processor 1210 can be configured to operate the memory array 100-b through the memory controller 140-b. In some cases, the processor 1210 can execute the reference ​ and 11 The functions of the described memory controller 140. In other cases, the memory controller 140-b may be integrated into the processor 1210. The processor 1210 may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components, and the processor 1210 may perform various functions described herein. The processor 1210 may be configured, for example, to execute computer-readable instructions stored in the memory array 100-b to cause the device 1205 to perform various functions or tasks.

[0142] The BIOS component 1215 may be a software component that includes a basic input / output system (BIOS) operating as firmware, which may initialize and run various hardware components of the system 1200. The BIOS component 1215 may also manage the data flow between the processor 1210 and various components such as the peripheral components 1220, the input / output control component 1225, etc. The BIOS component 1215 may include a program or software stored in a read-only memory (ROM), flash memory, or any other non-volatile memory.

[0143] The peripheral components 1220 may be any input or output device, or an interface to such a device, that may be integrated into the device 1205. Examples may include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a universal serial bus (USB) controller, a serial or parallel port, or a peripheral card slot such as a peripheral component interconnect (PCI) or accelerated graphics port (AGP) slot.

[0144] The input / output control component 1225 may manage data communication between the processor 1210 and the peripheral components 1220, the input device 1235, or the output device 1240. The input / output control component 1225 may also manage peripheral devices not integrated into the device 1205. In some cases, the input / output control component 1225 may represent a physical connection or port to an external peripheral device.

[0145] The input 1235 may represent a device or signal external to the device 1205 that provides an input to the device 1205 or its components. This may include a user interface or an interface with or between other devices. In some cases, the input 1235 may be a peripheral device interfacing with the device 1205 via the peripheral components 1220, or may be managed by the input / output control component 1225.

[0146] Output 1240 may represent a device or signal external to device 1205 that is configured to receive an output from any of device 1205 or its components. Examples of output 1240 may include a display, an audio speaker, a printing device, another processor, or a printed circuit board, etc. In some cases, output 1240 may be a peripheral device interfaced with device 1205 via peripheral component 1220 or may be managed by input / output control component 1225.

[0147] The components of memory controller 140-b, device 1205, and memory array 100-b may be constituted by circuitry designed to perform their functions. This may include various circuit elements configured to perform the functions described herein, such as wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements.

[0148] ​ Method 1300 for a direct input redundancy scheme using an adaptive decoder circuitry in accordance with various embodiments of the present disclosure is illustrated. Method 1300 may illustrate a portion of a retrieval operation including error correction.

[0149] At block 1305, the method may include generating a syndrome bit for data stored by a data plane. The operation of 1305 may be performed according to the method ​ described herein. In certain instances, the operation of 1305 may be performed by an ECC module as described in reference ​ , 8 and 10.

[0150] At block 1310, the method may include selecting data bits from the data for an error correction operation. The operation of 1310 may be performed according to the method ​ described herein. In certain instances, the operation of 1310 may be performed by a memory controller as described in reference ​ and 11 .

[0151] At block 1315, the method may include transmitting a control signal indicating whether the data bit is a replacement for a data bit stored by one of the data planes to a syndrome decoder configured for an error correction operation. In some cases, transmitting the control signal includes transmitting the control signal to a first decoder of the syndrome decoder. In some cases, the method may further include transmitting an inverted version of the control signal to a second decoder of the syndrome decoder. The operation of 1315 may be performed according to the method ​ described herein. In certain instances, the operation of 1315 may be performed by a memory controller as described in reference ​ and 11 .

[0152] At block 1320, the method may include decoding syndrome bits at least in part based on a control signal. The operation of 1320 may be performed according to the method described in reference ​ The operation of 1320 may be performed by a syndrome decoder circuit as described in reference ​ In some instances, the operation of 1320 may be performed by a syndrome decoder circuit as described in reference

[0153] In some cases, the method may include transmitting data bits to a bit flip circuit configured for error correction operations. In such cases, the method may include activating the bit flip circuit at least in part based on the result of decoding the syndrome bits.

[0154] In some cases, the method may include decoding the syndrome bits at least in part based on an input for a first decoder when the data bits are alternate data bits; and decoding the syndrome bits at least in part based on an input for a second decoder when the data bits are not alternate data bits.

[0155] In some cases, the method may include: determining that the data bits are stored by a data plane configured to store data, the data representing a logical state underlying the data stored by one or more in the data plane; and detecting that the data bits are alternate data bits at least in part based on the determination.

[0156] In some cases, portions of method 1300 may be performed by a device. The device may include an ECC circuit coupled to the data plane and configured to receive data bits from the data plane. Each of the ECC circuits may include a set of logic gates configured to perform bitwise operations on data from a corresponding data plane. The device may also include a redundant ECC circuit coupled to a redundant data plane and configured to receive redundant data corresponding to data stored by at least one in the data plane. The redundant ECC circuit may include a set of logic gates configured to perform bitwise operations on the redundant data. The device may also include a syndrome decoder circuit for a first data plane in the data plane, the syndrome decoder circuit being coupled to the redundant ECC circuit and the ECC circuit and configured to adjust its output at least in part based on whether the redundant data received by the redundant ECC circuit corresponds to data stored at the first data plane.

[0157] In some cases, the output of the syndrome decoder circuit is at least partially based on a first set of inputs (e.g., the inputs to the standard decoder 1030) and a second set of inputs (e.g., the inputs to the redundant decoder 1035). In such cases, the syndrome decoder circuit may be configured to adjust its output by configuring to invalidate the first set of inputs when the redundant data corresponds to data stored at the first data plane, and to invalidate the second set of inputs when the redundant data corresponds to data stored at a data plane other than the first data plane.

[0158] In some cases, the syndrome decoder circuit includes a first logic gate (e.g., logic gate 1045-b) and a second logic gate (e.g., logic gate 1045-a), each configured to receive a syndrome-based input including syndrome bits and / or inverted syndrome bits or combinations thereof. In such cases, the device may further include an inverter having an input coupled to the first logic gate and an output coupled to the second logic gate of the syndrome decoder circuit. The inverter may be configured to receive a signal indicating whether the redundant data corresponds to data stored at the first data plane. When the redundant data corresponds to data stored at the first data plane, the syndrome decoder circuit may be configured to output an indication of whether to invert a bit based at least in part on the syndrome-based input for the first logic gate and independent of the syndrome-based input for the second logic gate. When the redundant data corresponds to data stored at a data plane other than the first data plane, the syndrome decoder circuit may be configured to output an indication of whether to invert a bit based at least in part on the syndrome-based input for the second logic gate and independent of the syndrome-based input for the first logic gate.

[0159] In some cases, the device further includes a bit flip circuit coupled to the syndrome decoder circuit. The bit flip circuit may be configured to invert bits from the first data plane or the redundant data plane at least in part based on the output of the syndrome decoder circuit.

[0160] In some cases, the device may include a bit flip circuit configured to invert data bits and a syndrome decoder for the first data plane. The syndrome decoder may be coupled to the bit flip circuit and may include a first decoder (e.g., the redundant decoder 1035) and a second decoder (e.g., the standard decoder 1030). The first decoder may be configured to receive a first set of bits including syndrome bits and / or inverted syndrome bits generated at least in part based on a set of data. The second decoder may be configured to receive a second set of bits including an inverted version of the first set of bits. The first and second decoders may be configured to receive the first and second sets of bits, respectively, as part of the same decoding operation (e.g., the decoding operation of the same bit).

[0161] In some cases, the syndrome decoder further includes a third decoder configured to receive a third set of bits, the third set of bits including the syndrome bits and / or the inversion syndrome bits. The third set of bits can be different from the first and second sets of bits and can be generated based at least in part on the set of data.

[0162] In some cases, the apparatus may include an inverter coupled to the first decoder and the second decoder. The inverter may be configured to receive a control signal indicating whether the set of data includes redundant data corresponding to data stored at the first data plane. In such cases, the first decoder may be configured to receive the control signal from the memory controller, and the second decoder may be configured to receive an inverted version of the control signal from the inverter.

[0163] In some cases, the apparatus includes a data selector circuit configured to select a data bit based at least in part on a control signal. In such cases, the bit flipping circuit can be configured to invert the selected data bit based at least in part on an output of the syndrome decoder.

[0164] ​ A method 1400 is illustrated for utilizing a direct-input redundancy scheme for adaptive decoder circuitry according to various embodiments of the present disclosure. The method 1400 may illustrate portions of two retrieval operations including error correction.

[0165] At block 1405, the method may include performing a first bitwise operation (e.g., an XOR operation) on a first set of redundant data for a first data plane using an ECC circuit, the first set of redundant data corresponding to data stored by the first data plane. ​ The method described performs the operation of 1405. In some examples, the operation of 1405 can be performed by referring to ​ 、 6 , 8 and 9 described redundant ECC circuit execution.

[0166] At block 1410, the method may include transferring the result of the first bitwise operation (e.g., RD_ALL) to a combination of logic gates (e.g., logic gates 815-a, 815-b, and 815-c). Transferring the result of the first bitwise operation to the combination of logic gates may be independent of the first set of redundant data for the first data plane. ​ The described method performs the operation of 1410. In some examples, the operation of 1410 can be performed by referring to ​ 、 6 , 8 and 9 described redundant ECC circuit execution.

[0167] At block 1415, the method may include performing a second bitwise operation (e.g., an XOR operation) on a second set of redundant data for a second data plane using an ECC circuit, the second set of redundant data corresponding to data stored by the second data plane. The operation of 1415 may be performed according to the method described in reference ​ In some instances, the operation of 1415 may be performed by a redundant ECC circuit as described in references ​ , 6 , 8, and 9.

[0168] At block 1420, the method may include transmitting the result of the second bitwise operation to a combination of logic gates. Transmitting the result of the second bitwise operation to the combination of logic gates may be independent of the second set of redundant data for the second data plane. The operation of 1420 may be performed according to the method described in reference ​ In some instances, the operation of 1420 may be performed by a redundant ECC circuit as described in references ​ , 6 , 8, and 9.

[0169] In some instances, the method may further include generating a first set of syndrome bits for a codeword that includes a first set of redundant data. The first set of syndrome bits may be at least partially based on the result of the first bitwise operation. In some instances, the method may further include generating a second set of syndrome bits for a second codeword that includes a second set of redundant data. The second set of syndrome bits may be at least partially based on the result of the second bitwise operation.

[0170] In some cases, the method includes performing an XOR operation on the result of the first bitwise operation (e.g., by one of logic gates 815-a, 815-b, or 815-c), and performing an XOR operation on the result of the second bitwise operation (e.g., by one of logic gates 815-a, 815-b, or 815-c).

[0171] Describes a method. The method may include: generating syndrome bits for data stored by a data plane; selecting data bits for an error correction operation from the data; transmitting a control signal indicating whether the data bits are alternatives for data bits stored by one of the data planes to a syndrome decoder configured for the error correction operation; and decoding the syndrome bits at the syndrome decoder based on the control signal.

[0172] Describe a device. The device may include a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be executed by the processor to cause the device to: generate syndrome bits for data stored by a data plane; select data bits from the data for error correction operations; transmit a control signal indicating whether the data bits are an alternative to data bits stored by one of the data planes to a syndrome decoder configured for error correction operations; and decode the syndrome bits at the syndrome decoder based on the control signal.

[0173] Describe another device. The device may include: means for generating syndrome bits for data stored by a data plane; means for selecting data bits from the data for error correction operations; means for transmitting a control signal indicating whether the data bits are an alternative to data bits stored by one of the data planes to a syndrome decoder configured for error correction operations; and means for decoding the syndrome bits at the syndrome decoder based on the control signal.

[0174] Describe a non-transitory computer-readable medium storing code. The code may include instructions that may be executed by a processor to generate syndrome bits for data stored by a data plane; select data bits from the data for error correction operations; transmit a control signal indicating whether the data bits are an alternative to data bits stored by one of the data planes to a syndrome decoder configured for error correction operations; and decode the syndrome bits at the syndrome decoder based on the control signal.

[0175] Some examples of the methods, devices, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for: transmitting the data bits to a bit flip circuit configured for error correction operations; and activating the bit flip circuit based on the result of decoding the syndrome bits.

[0176] In some examples of the methods, devices, and non-transitory computer-readable media described herein, transmitting the control signal may include operations, features, means, or instructions for transmitting the control signal to a first decoder of the syndrome decoder; and wherein the method further includes transmitting an inverted version of the control signal to a second decoder of the syndrome decoder.

[0177] Some examples of the methods, devices, and non-transitory computer-readable media described herein may further include operations, features, means, or instructions for: decoding the syndrome bits based on an input for the first decoder when the data bits may be alternative data bits; and decoding the syndrome bits based on an input for the second decoder when the data bits may not be alternative data bits.

[0178] Some examples of the methods, apparatuses, and non-transitory computer-readable media described herein may further include operations, features, devices, or instructions for: determining that a data bit is stored by a data plane configured to store data, the data representing a logical state that may be a basis for data stored by one or more of the data in the data plane; and detecting, based on the determination, that the data bit may be an alternative data bit.

[0179] Describe a method. The method may include: performing a first bit-by-bit operation on a first set of redundant data for a first data plane using an error correction code (ECC) circuit, the first set of redundant data corresponding to data stored by the first data plane; transmitting the result of the first bit-by-bit operation to a combination of logic gates; performing a second bit-by-bit operation on a second set of redundant data for a second data plane using the ECC circuit, the second set of redundant data corresponding to data stored by the second data plane; and transmitting the result of the second bit-by-bit operation to a combination of logic gates.

[0180] Describe an apparatus. The apparatus may include a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be executed by the processor to cause the apparatus to: perform a first bit-by-bit operation on a first set of redundant data for a first data plane using an error correction code (ECC) circuit, the first set of redundant data corresponding to data stored by the first data plane; transmit the result of the first bit-by-bit operation to a combination of logic gates; perform a second bit-by-bit operation on a second set of redundant data for a second data plane using the ECC circuit, the second set of redundant data corresponding to data stored by the second data plane; and transmit the result of the second bit-by-bit operation to a combination of logic gates.

[0181] Describe another apparatus. The apparatus may include: means for performing a first bit-by-bit operation on a first set of redundant data for a first data plane using an error correction code (ECC) circuit, the first set of redundant data corresponding to data stored by the first data plane; means for transmitting the result of the first bit-by-bit operation to a combination of logic gates; means for performing a second bit-by-bit operation on a second set of redundant data for a second data plane using the ECC circuit, the second set of redundant data corresponding to data stored by the second data plane; and means for transmitting the result of the second bit-by-bit operation to a combination of logic gates.

[0182] Describe a non-transitory computer-readable medium storing code. The code may include instructions that may be executed by a processor to: perform a first bitwise operation on a first set of redundant data for a first data plane, the first set of redundant data corresponding to data stored by the first data plane; transmit the result of the first bitwise operation to a combination of logic gates; perform a second bitwise operation on a second set of redundant data for a second data plane, the second set of redundant data corresponding to data stored by the second data plane; and transmit the result of the second bitwise operation to a combination of logic gates.

[0183] Some examples of the methods, apparatuses, and non-transitory computer-readable media described herein may further include operations, features, apparatuses, or instructions for: generating a first set of syndrome bits for a codeword including the first set of redundant data, the first set of syndrome bits being based on the result of the first bitwise operation; and generating a second set of syndrome bits for a second codeword including the second set of redundant data, the second set of syndrome bits being based on the result of the second bitwise operation.

[0184] Some examples of the methods, apparatuses, and non-transitory computer-readable media described herein may further include operations, features, apparatuses, or instructions for: performing an exclusive OR (XOR) operation on the result of the first bitwise operation; and performing an XOR operation on the result of the second bitwise operation.

[0185] Some examples of the methods, apparatuses, and non-transitory computer-readable media described herein may further include operations, features, apparatuses, or instructions for: transmitting the result of the first bitwise operation to a combination of logic gates independently of the first set of redundant data for the first data plane; and transmitting the result of the second bitwise operation to a combination of logic gates independently of the second set of redundant data for the second data plane.

[0186] Describe an apparatus. The apparatus may include: an error correction code (ECC) circuit coupled to a data plane and configured to receive data bits from the data plane; a redundant ECC circuit coupled to a redundant data plane and configured to receive redundant data corresponding to data stored by at least one of the data planes; and a syndrome decoder circuit for a first data plane of the data planes, coupled to the redundant ECC circuit and the ECC circuit and configured to adjust its output based on whether the redundant data received by the redundant ECC circuit corresponds to data received by the first data plane.

[0187] In some instances, the output may be based on a first set of inputs and a second set of inputs, and wherein the syndrome decoder circuit may be configured to adjust its output by being configured to invalidate the first set of inputs when the redundant data corresponds to data stored by the first data plane, and to invalidate the second set of inputs when the redundant data corresponds to data stored by a data plane other than the first data plane.

[0188] In some instances, the syndrome decoder circuit includes a first logic gate and a second logic gate, each of which may be configured to receive a syndrome-based input, the syndrome-based input including syndrome bits or inverted syndrome bits, or a combination thereof.

[0189] Some instances of the device may include an inverter that includes an input coupled to the first logic gate of the syndrome decoder circuit and an output coupled to the second logic gate of the syndrome decoder circuit, the inverter being configured to receive a signal indicating whether the redundant data may correspond to data stored by the first data plane.

[0190] In some instances, when the redundant data is available for the first data plane, the syndrome decoder circuit may be configured to output an indication of whether a bit may be inverted based on the syndrome-based input for the first logic gate and independent of the syndrome-based input for the second logic gate.

[0191] In some instances, when the redundant data is available for a data plane other than the first data plane, the syndrome decoder circuit may be configured to output an indication of whether a bit may be inverted based on the syndrome-based input for the second logic gate and independent of the syndrome-based input for the first logic gate.

[0192] Some instances of the device may include a bit flip circuit that is coupled to the syndrome decoder circuit and is configured to invert bits from the first data plane or the redundant data plane based on the output of the syndrome decoder circuit.

[0193] In some instances, the redundant ECC circuit includes a set of logic gates configured to perform a bit-by-bit operation on the redundant data, and wherein each of the ECC circuits includes a set of logic gates configured to perform a bit-by-bit operation on data from the data plane.

[0194] A device is described. The device may include a bit flip circuit configured to invert data bits, and a syndrome decoder for a first data plane, the syndrome decoder being coupled to the bit flip circuit and including a first decoder configured to receive a first set of bits, the first set of bits including syndrome bits, inverted syndrome bits, or a combination thereof, generated based on a set of data; and a second decoder configured to receive a second set of bits, the second set of bits including an inverted version of the first set of bits.

[0195] In some instances, the first and second decoders may be configured to receive first and second sets of bits, respectively, as part of the same decoding operation.

[0196] In some instances, the syndrome decoder may further include operations, features, apparatuses, or instructions for a third decoder configured to receive a third set of bits that includes syndrome bits, inverted syndrome bits, or a combination thereof that are different from the first and second sets of bits and are generated based on the set of data.

[0197] Some instances of the device may include an inverter coupled to the first decoder and the second decoder, the inverter configured to receive a control signal indicating whether the set of data includes redundant data corresponding to a first data plane.

[0198] In some instances, the first decoder may be configured to receive a control signal from a memory controller, and the second decoder may be configured to receive an inverted version of the control signal from the inverter.

[0199] Some instances of the device may include a data selector circuit configured to select data bits based on the control signal, wherein a bit flip circuit may be configured to invert the selected data bits based on the output of the syndrome decoder.

[0200] As used herein, the term "virtual ground" refers to a circuit node that is held at a voltage of approximately zero volts (0V) but is not directly grounded. Thus, the voltage of the virtual ground may fluctuate temporarily and return to approximately 0V in a steady state. A virtual ground may be implemented using various electronic circuit elements such as a voltage divider consisting of an operational amplifier and resistors. Other implementations are possible. "Virtual ground" or "virtual earth ground" means connected to approximately 0V.

[0201] The terms "electronically communicate" and "coupled" refer to a relationship between components that supports an electronic flow between the components. This may include a direct connection between the components or may include intermediate components. Components that electronically communicate or are coupled to each other may actively exchange electrons or signals (e.g., in a powered-on circuit) or may not actively exchange electrons or signals (e.g., in a powered-off circuit), but may be configured and operable to exchange electrons or signals immediately after the circuit is powered on. For example, two components physically connected via a switch (e.g., a transistor) electronically communicate or are coupled regardless of the state of the switch (i.e., open or closed).

[0202] The term "isolated" or "electrically isolated" refers to a relationship between components where electrons cannot currently flow between them; components are isolated from each other if there is an open circuit between the components. For example, two components physically connected via a switch may be isolated from each other when the switch is open.

[0203] As used herein, the term "substantially" means that the modified feature (e.g., a verb or adjective modified by the term substantially) need not be absolute but should be close enough to achieve the advantage of the characteristic.

[0204] The devices discussed herein, including the memory array 100, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate can be controlled by doping with various chemicals including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation or by any other doping method during the initial formation or growth of the substrate.

[0205] One or more transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals can be connected to other electronic components by conductive materials such as metal. The source and drain can be conductive and can include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "turned off" or "deactivated".

[0206] The specific embodiments described above in conjunction with the accompanying drawings describe examples and do not represent the only examples that can be implemented or that are within the scope of the claims. When used in this specification, the terms "example" and "exemplary" mean "serving as an example, instance, or illustration" and not "preferred" or "superior to other examples". The specific embodiments include specific details for the purpose of providing an understanding of the described technology. However, the technology can be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0207] Any of a variety of different techniques and technologies can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0208] The various illustrative blocks and components described in connection with the disclosure herein can be implemented or performed using a general purpose processor, a digital signal processor (DSP), an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0209] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted through a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope and spirit of the disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination of these. The features implementing the functions can also be physically located at various positions, including being distributed such that portions of the functions are implemented at different physical locations. As used herein, including in the claims, when used in a list of two or more items, the term "and / or" means that any one of the listed items can be taken alone, or any combination of two or more of the listed items can be taken. For example, if a composition is described as containing components A, B, and / or C, the composition can contain: only A; only B; only C; a combination of A and B; a combination of A and C; a combination of B and C; or a combination of A, B, and C. Also, as used herein, including in the claims, the "or" used in a list of items (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list such that a list such as "at least one of A, B, or C" represents A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C).

[0210] Computer-readable media includes both computer storage media and communication media, and communication media includes any media that facilitates transfer of a computer program from one place to another. Storage media can be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, computer-readable media may include RAM, ROM, EEPROM, flash memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store the desired program code in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer or a general purpose or special purpose processor. Also, any connection is properly termed a computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0211] The foregoing description of the disclosure has been provided to enable a person skilled in the art to make or use the disclosure. It will be readily apparent to those skilled in the art that various modifications to the disclosure can be made, and the general principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.< / x> < / x> < / x> < / x> < / x>

Claims

1. An apparatus, comprising: a bit flip circuit configured to invert data bits; and a syndrome decoder for a data plane, the syndrome decoder being coupled to the bit flip circuit and comprising: a first decoder configured to receive a first set of bits, the first set of bits being generated at least in part based on a set of data, the first set of bits including syndrome bits, inverted syndrome bits, or a combination thereof; and a second decoder configured to receive a second set of bits, the second set of bits including an inverted version of the first set of bits.

2. The apparatus of claim 1, wherein the first decoder and the second decoder are configured to receive the first set of bits and the second set of bits, respectively, as part of the same decoding operation.

3. The apparatus of claim 1, wherein the syndrome decoder further comprises: a third decoder configured to receive a third set of bits, the third set of bits including syndrome bits, inverted syndrome bits, or a combination thereof that are different from the first set of bits and the second set of bits and are generated at least in part based on the set of data.

4. The apparatus of claim 3, wherein the third set of bits includes bits common to the data plane and a redundant data plane associated with the data plane.

5. The apparatus of claim 1, further comprising: an inverter coupled to the first decoder and the second decoder, the inverter being configured to receive a control signal indicating whether the set of data includes redundant data corresponding to the data plane.

6. The apparatus of claim 5, wherein the first decoder is configured to receive the control signal from a memory controller, and the second decoder is configured to receive an inverted version of the control signal from the inverter.

7. The apparatus of claim 5, further comprising: a data selector circuit configured to select data bits at least in part based on the control signal, wherein the bit flip circuit is configured to invert the selected data bits at least in part based on an output of the syndrome decoder.

8. The apparatus according to claim 1, wherein the syndrome decoder further comprises: A third decoder configured to receive a third set of bits, an AND logic gate coupled to the first decoder and the second decoder, a NOR logic gate coupled to the AND logic gate and the third decoder, an inverter coupled to the NOR logic gate and configured to invert an output of the NOR logic gate, or a combination thereof.

9. A method, comprising: receiving, at a first decoder of a syndrome decoder for a data plane, a first set of bits, the first set of bits being generated at least in part based on a set of data and including syndrome bits, inverted syndrome bits, or a combination thereof; receiving, at a second decoder of the syndrome decoder, a second set of bits, the second set of bits including an inverted version of the first set of bits; and inverting, by a bit flip circuit, one or more bits of the set of data at least in part based on an output of the syndrome decoder, the output of the syndrome decoder being at least in part based on the first set of bits or the second set of bits.

10. The method according to claim 9, wherein the first set of bits and the second set of bits are received as part of the same decoding operation.

11. The method according to claim 9, further comprising: receiving, at a third decoder of the syndrome decoder, a third set of bits, the third set of bits including syndrome bits, inverted syndrome bits, or a combination thereof that are different from the first set of bits and the second set of bits and are at least partially generated based on the set of data, wherein the output of the syndrome decoder is at least partially based on the third set of bits.

12. The method according to claim 11, wherein the third set of bits includes bits common to the data plane and a redundant data plane associated with the data plane.

13. The method according to claim 9, further comprising: receiving, at the first decoder, a control signal from a memory controller indicating whether the set of data includes redundant data corresponding to the data plane; receiving, at an inverter coupled to the first decoder and the second decoder, the control signal; and outputting, by the inverter, an inverted version of the control signal to the second decoder.

14. The method according to claim 13, further comprising: selecting data bits at least partially based on the control signal by a data selector circuit, wherein the one or more bits include the selected data bits.

15. An apparatus, comprising: a bit flip circuit configured to invert data bits; a syndrome decoder for a data plane and coupled to the bit flip circuit, the syndrome decoder including a first decoder and a second decoder; and a controller coupled to the bit flip circuit and the syndrome decoder, the controller operative to cause the apparatus to: receive, at the first decoder, a first set of bits that are at least partially generated based on a set of data and that include syndrome bits, inverted syndrome bits, or a combination thereof; receive, at the second decoder, a second set of bits that includes an inverted version of the first set of bits; and invert, by the bit flip circuit, one or more bits of the set of data at least partially based on the output of the syndrome decoder, the output of the syndrome decoder being at least partially based on the first set of bits or the second set of bits.

16. The apparatus according to claim 15, wherein the first set of bits and the second set of bits are received as part of the same decoding operation.

17. The apparatus according to claim 15, wherein the controller is further operative to cause the apparatus to: receive, at a third decoder of the syndrome decoder, a third set of bits, the third set of bits including syndrome bits, inverted syndrome bits, or a combination thereof that are different from the first set of bits and the second set of bits and are at least partially generated based on the set of data, wherein the output of the syndrome decoder is at least partially based on the third set of bits.

18. The apparatus according to claim 17, wherein the third set of bits includes bits common to the data plane and a redundant data plane associated with the data plane.

19. The apparatus according to claim 15, wherein the controller is further operative to cause the apparatus to: at the first decoder, receive a control signal from a memory controller indicating whether the set of data includes redundant data corresponding to the data plane; at an inverter coupled to the first decoder and the second decoder, receive the control signal; and output an inverted version of the control signal to the second decoder through the inverter.

20. The apparatus according to claim 19, wherein the controller is further operative to cause the apparatus to: select data bits through a data selector circuit based at least in part on the control signal, wherein the one or more bits include the selected data bits.

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