Mass production acceleration method and device, equipment and storage medium

Abstract

The invention provides a mass production acceleration method and device, equipment and a storage medium. The method comprises the following steps: executing full-disk scanning on Flash; reading chip selection ports contained in the Flash, and creating an independent power-on index table and a mass production information table for the LUN of each chip selection port according to the LUN of each chip selection port; and storing the power-on index table and the mass production information table corresponding to the LUN of each chip selection port by adopting a first preset address allocation rule, and creating link mapping between the power-on index table and the mass production information table. According to the method, the chip selection ports of the Flash are read, the independent power-on index table and the mass production information table are created for the LUN of each chip selection port according to the chip selection ports, the power-on index table and the mass production information table are directly read and loaded for mass production of the multi-patch Flash into the single-patch Flash in the later period, and therefore low-lattice scanning of the Flash can be achieved, and the mass production of the Flash can be improved.

Description

Technical Field

[0001] The present invention relates to the field of flash memory technology, and in particular to a mass production speed-up method, device, equipment and storage medium. Background Art

[0002] In the field of storage technology, NAND Flash (hereinafter referred to as Flash) is a non-volatile storage medium. Due to its high density, low cost, and excellent rewritable performance, it is widely used in various storage products such as USB flash drives, SD cards, and solid-state drives (SSDs). The physical properties of Flash dictate that it must work in conjunction with a storage controller chip to write, read, and manage data.

[0003] Flash memory can be mounted in two ways: single-mount and multi-mount. Single-mount refers to mounting a single Flash chip in a storage product, while multi-mount refers to mounting at least two Flash chips in a storage product. The most significant advantage of multi-mount over single-mount is that it can significantly increase the capacity of storage products.

[0004] Due to the limitations of the firmware code design, converting a multi-chip Flash to a single-chip Flash for mass production requires a low-level format re-scan. Low-level formatting involves a full scan and initialization of the Flash, which is time-consuming and can affect mass production efficiency. Summary of the Invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a mass production speed-up method, device, equipment and storage medium that can convert multiple Flash memory sticks into single Flash memory sticks for card opening and mass production without the need for low-format scanning. The first aspect of the present application provides a mass production speed-up method, comprising:

[0006] Perform a full scan of Flash;

[0007] Read the chip select ports contained in the Flash, and create an independent power-on index table and the mass production information table for the LUN of each chip select port according to the LUN of each chip select port;

[0008] The first preset address allocation rule is adopted to store the power-on index table and the mass production information table corresponding to the LUN of each chip select port, and a link mapping is created between the power-on index table and the mass production information table.

[0009] Furthermore, in one preferred embodiment, performing a full disk scan on the Flash includes:

[0010] Write data to Flash;

[0011] Read the data written to the Flash;

[0012] Parse and compare the data written to the Flash with the read data, and obtain the attribute characteristics of the Flash according to the result of the parsing and comparison.

[0013] Further, in one preferred embodiment, the first preset address allocation rule includes:

[0014] Read the page template corresponding to the LUN of the current chip select port, and obtain the total number of pages of the LUN of the current chip select port according to the page template;

[0015] Segment the total number of pages according to a preset address length;

[0016] Allocate the page address corresponding to one of the segmented nodes to store the power-on index table and the mass production information table.

[0017] Further, in one preferred embodiment, after storing the power-on index table and the mass production information table corresponding to the LUN of each chip select port by using the first preset address allocation rule and creating a link mapping between the power-on index table and the mass production information table, it further includes:

[0018] Integrate and process the power-on index table corresponding to the LUN of each chip select port to obtain a power-on main index table;

[0019] Obtain the total number of chip select ports according to the chip select ports included in the read Flash;

[0020] Allocate an address to store the power-on main index table according to the total number of chip select ports in combination with the first preset address allocation rule.

[0021] The second aspect of the present application provides a mass production speed-up device, including:

[0022] A scanning module for performing a full scan of the Flash;

[0023] A creation module for reading the chip select ports included in the Flash and creating an independent power-on index table and the mass production information table for the LUN of each chip select port;

[0024] A first allocation and storage module for storing the power-on index table and the mass production information table corresponding to the LUN of each chip select port by using the first preset address allocation rule and creating a link mapping between the power-on index table and the mass production information table.

[0025] Further, in one preferred embodiment, the scanning module includes:

[0026] A writing unit for writing data into the Flash;

[0027] A reading unit for reading the data written in the Flash;

[0028] A parsing and comparison unit for parsing and comparing the data written in the Flash with the read data, and obtaining the attribute characteristics of the Flash according to the result of the parsing and comparison.

[0029] Further, in one preferred embodiment, the first preset address allocation rule includes:

[0030] Read the page template corresponding to the LUN of the current chip select port, and obtain the total number of pages of the LUN of the current chip select port according to the page template;

[0031] Segment the total number of pages according to a preset address length;

[0032] Allocate the page address corresponding to one of the segmented nodes to store the power-on index table and the mass production information table.

[0033] Further, in one preferred embodiment, it further includes:

[0034] An integration module for integrating the power-on index tables corresponding to the LUNs of each chip select port to obtain a power-on main index table;

[0035] A reading module for obtaining the total number of chip selects according to the chip select port included in the read Flash;

[0036] A second allocation and storage module for allocating an address to the power-on main index table for storage according to the total number of chip selects in combination with a second preset address allocation rule.

[0037] The third aspect of the present application provides an electronic device, including:

[0038] A processor; and

[0039] A memory having executable code stored thereon, characterized in that when the executable code is executed by the processor, the processor executes the mass production speed-up method as described above.

[0040] The fourth aspect of the present application provides a computer-readable storage medium, characterized in that it stores executable code, and when the executable code is executed by a processor of an electronic device, the processor executes the mass production speed-up method as described above.

[0041] The technical solution of this application includes: performing a full - disk scan on the Flash; reading the chip - select ports included in the Flash, and creating independent power - on index tables and mass - production information tables for the LUNs of each chip - select port according to the LUN of each chip - select port; using the first preset address allocation rule to store the power - on index tables and mass - production information tables corresponding to the LUNs of each chip - select port, and creating a link mapping between the power - on index table and the mass - production information table. By reading the chip - select ports of the Flash and creating independent power - on index tables and mass - production information tables for the LUNs of each chip - select port according to the chip - select ports, it is equivalent that each LUN has its own independent power - on index table and mass - production information table. Even if the customer later changes from multi - stick Flash to single - stick Flash for mass production, directly reading and loading the power - on index table and mass - production information table can achieve low - level formatting and scanning of the Flash, complete the initialization of the Flash, and improve the mass production of the Flash. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, so they should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0043] Figure 1 is a schematic flowchart of a mass - production speed - up method shown in an embodiment of this application;

[0044] Figure 2 is a schematic flowchart of a mass - production speed - up method shown in another embodiment of this application;

[0045] Figure 3 shows a schematic structural diagram of a mass - production speed - up device in an embodiment of this application;

[0046] Figure 4 shows a schematic structural diagram of a mass - production speed - up device in another embodiment of this application;

[0047] Figure 5 shows a schematic structural diagram of an electronic device in an embodiment of this application;

[0048] Figure 6 shows a schematic structural diagram of a Flash in an embodiment of this application;

[0049] Figure 7 shows a schematic diagram of the relationship among the power - on index table, the bad list, and the mass - production information table in an embodiment of this application;

[0050] Figure 8 shows a schematic structural diagram of a dual - stick Flash in an embodiment of this application. Detailed implementation manners

[0051] For ease of understanding the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present invention can be understood more thoroughly and comprehensively.

[0052] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or there can also be a middle element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be a middle element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are only for the purpose of illustration and do not represent the only embodiments.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the description of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0054] In the related art, due to the limitations of the firmware code design, if it is necessary to convert multi-chip Flash into single-chip Flash for mass production, it is necessary to perform a re-low-level format scan on the multi-chip Flash. The low-level format scan is a process of performing a full-disk scan and initialization on the Flash, and the process takes a long time, which will affect the mass production efficiency.

[0055] Therefore, in order to solve the above technical problems, the present application provides a method for accelerating mass production, which can convert multi-chip Flash into single-chip Flash for card opening and mass production without low-level format scanning.

[0056] The technical solution of the present application will be described in detail below with reference to the drawings.

[0057] Figure 1 The flowchart of the method for accelerating mass production in an embodiment of the present application is shown.

[0058] Please refer to Figure 1 , a method for accelerating mass production, includes the following steps:

[0059] Step 110: Perform a full-disk scan on the Flash.

[0060] As Figure 6The following shows the storage organizational structure inside Flash. Flash has several LUNs (which can also be called DIEs). Each LUN has several planes. Each plane has several blocks. Each block has several pages. Each page corresponds to a word line, and the word line is composed of thousands of storage units. A LUN is the basic unit for receiving and executing Flash commands, and Flash is controlled to be selected by the chip select port CE.

[0061] It should be noted that if Flash is to be able to stably store data, the storage control chip needs to understand what the internal "structure" of Flash looks like. This involves a full scan of Flash, which is commonly known as low-level formatting in the industry. A bad column refers to the storage units in a certain column of the Flash storage array that cannot read and write data normally due to physical defects or electrical stress interference. A bad block refers to a block in Flash that contains too many bad pages and cannot read and write data normally. A bad page refers to a page in Flash that is damaged and cannot read and write data normally. The purpose of the full scan is basically to identify bad columns, bad pages, and bad blocks, and it is necessary to clarify the distribution positions of bad columns, bad pages, and bad blocks. In the case of clarifying the distribution positions of bad columns, bad pages, and bad blocks, the remaining positions are the positions of good columns, good pages, and good blocks.

[0062] In this embodiment, the full scan of Flash can be carried out in the following manner: write data to Flash; read the data written to Flash; parse and compare the data written to Flash with the read data, and obtain the attribute characteristics of Flash according to the result of the parsing and comparison. In this way, by comparing the written data with the read data, the distribution positions of bad columns, bad pages, and bad blocks inside Flash can be parsed according to the comparison result, and these position information will form complete bad list, bad page table, and bad block table, and be stored inside Flash. In addition, when performing the full scan of Flash, corresponding management data will also be generated, and these management data will also form complete management tables. These management tables are equivalent to recording how to operate Flash. Through these management tables, combined with the bad list, bad page table, and bad block table, the storage control chip can operate Flash to achieve data reading and writing work.

[0063] As mentioned in the background art, compared with single-chip mass production, the core advantage of multi-chip mass production is that the storage products produced in mass production have a larger capacity, and a larger capacity means a higher price. In the past, for the low-level formatting information of multiple Flashs, the soft firmware code design was stored in a summary manner. For example, assume that a storage product is mass-produced in a dual-chip manner, that is, the storage product includes 2 Flashs, each Flash has 2 chip select ports CE, and each chip select port CE corresponds to 1 LUN, which is equivalent to having 4 pieces of low-level formatting mass production information (respectively, the low-level formatting mass production information of LUN0 to 4). These 4 pieces of low-level formatting mass production information are centrally stored in the LUN corresponding to the chip select port CE of a certain Flash, and the address allocation logic is allocated according to the 4CE allocation logic. This results in that when changing from dual-chip to single-chip mass production, searching for these 4 pieces of mass production information according to the original address logic allocation cannot find them by the storage control chip, resulting in mass production failure. The customer can only run a low-level scan again to generate new low-level formatting mass production information, which is very time-consuming. This is also the defect of the original soft firmware design.

[0064] Step S120: Read the chip select ports included in the Flash, and create an independent power-on index table and a mass production information table for the LUN of each chip select port according to the LUN of each chip select port.

[0065] The power-on index table (Bootindex) is the first table that needs to be loaded when the Flash is powered on, which is equivalent to the process of the Flash completing initialization. And through the power-on index table, the remaining mass production information tables can be searched and matched.

[0066] The mass production information table (MPInfo) is a table that records the basic data of the Flash, and this table is generated when performing a low-level scan on the Flash. The mass production information table includes: BCM (bad list), Retry table (re-read voltage table), etc. These information tables are all information tables recording the characteristics of the current Flash. Through the mass production information table, the storage control chip can "understand" the characteristics of the current Flash and complete data writing, reading, erasing, etc. of the Flash.

[0067] How to match the mass production information table through the power-on index table? For example Figure 7As shown in the figure, in the design of the firmware code, the address of the bad list is recorded at the head of the power-on index table. When the Flash is successfully powered on, after the Flash loads the power-on index table, the bad list can be found through the address recorded at the head of the power-on index table. Since the length of the bad list is long, in addition to recording the bad column information of the Flash, the bad list also serves to record the addresses of other tables. That is, the head of the bad list records the addresses of tables such as the Retry table. When the Flash finds the bad list, the remaining tables can be found through the bad list. Since the addresses of the remaining tables can be recorded at the head of the bad list, why not choose to directly record the addresses of all the remaining tables at the head of the power-on index table to achieve direct matching mapping? This is because the length of the power-on index table is limited and cannot record the addresses of too many tables. Because the Flash needs to be powered on quickly, the power-on index table should not record too much information content and needs to rely on this table to complete the initialization power-on of the Flash as soon as possible.

[0068] To address the technical problems described in the above steps, the storage control chip scans the hardware topology of the Flash through the chip select port CE to determine the current chip select port of the Flash. If the Flash has 4 chip select ports CE, independent power-on index tables and mass production information tables are created for the LUNs of each chip select port. Considering that the previous firmware code stored multiple low-level formatting mass production information centrally, when the subsequent customer changed to single-chip mass production and searched for these 4 mass productions according to the original address logic allocation, one Flash would fail in mass production because it found its corresponding low-level formatting mass production information. In this embodiment, independent power-on index tables and mass production information tables are directly created for the LUNs corresponding to each Flash chip select port CE, which is equivalent to storing their respective low-level formatting mass production information after low-level formatting. Even if it is modified to single-chip mass production later, the low-level formatting mass production information of the Flash can still be found.

[0069] The advantage of this embodiment is that the independent storage design allows the management tables of each LUN to independently allocate storage space, avoiding address logic conflicts caused by the centralized storage of multi-chip Flash mass production information. For example, the 4 LUNs (CE0~CE3) of the dual-chip Flash each reserve a fixed area in the corresponding Flash physical block (such as the reserved area of LUN0 stores the index table and mass production information of CE0). The single-chip Flash only needs to read the management table corresponding to the currently existing CE port and does not need to rely on the logical addresses of other CEs.

[0070] Step S130: Adopt the first preset address allocation rule to store the power-on index tables and mass production information tables corresponding to the LUNs of each chip select port, and create a link mapping between the power-on index table and the mass production information table.

[0071] After confirming to adopt the method of using a single chip select port CE to manage the power-on index table and the mass production information table, it is necessary to allocate actual storage addresses for these two tables for storage. In this embodiment, the first preset address allocation rule can be carried out in the following manner: read the page template corresponding to the LUN of the current chip select port, and obtain the total number of pages of the LUN of the current chip select port according to the page template; segment the total number of pages according to the preset address length; allocate the page address corresponding to one of the segmented nodes to store the power-on index table and the mass production information table.

[0072] To better understand the principle of the technical solution of this application, the following will be described with a specific case.

[0073] Suppose a customer needs to mass produce 1 storage product, including a storage control chip, a PCB, and 2 Flash memories. The Flash memories have 2 chip select ports CE, and each chip select port CE can control 1 LUN, as Figure 8 shown. At the start of mass production, the customer chooses to directly use the double-sided pasting method to mass produce the storage product, that is, 1 PCB is pasted with 2 Flash memories.

[0074] The customer uses a mass production tool (MPTool) to perform low-level formatting and card opening mass production. First, perform a full scan of the 2 Flash memories, write full data to the 2 Flash memories and then read them, and analyze according to the results of the written data and the read data to obtain the attribute characteristics of the 2 Flash memories.

[0075] Then, read the chip select ports included in the Flash memories, and create independent power-on index tables and mass production information tables for the LUNs of each created chip select port according to the LUNs of each chip select port. In this embodiment, each Flash memory has 2 chip select ports CE, and each chip select port CE controls 1 LUN. It is equivalent to that 2 Flash memories have 4 copies of low-level formatting mass production information, namely LUN0 to LUN4. Create independent power-on index tables and mass production information tables for the LUNs of each chip select port.

[0076] Subsequently, read the page template corresponding to the LUN of the current chip select port, obtain the total number of pages of the LUN of the current chip select port according to the page template, segment the total number of pages according to the preset address length, and allocate the page address corresponding to one of the segmented nodes to store the power-on index table and the mass production information table. Taking LUN0 as an example, the page template of LUN0 read, and the total number of pages of the LUN of the current chip select port obtained according to the page template is 51,200 Pages (Page0 to Page51,199 respectively). Segment the total number of pages according to the preset address length of 512 (this preset address length of 512 is an empirical value obtained from debugging various types of Flash, and such segmentation can ensure the uniformity of the address), and obtain 1,000 segmentation points, which is equivalent to 1,000 page addresses. Allocate the page address corresponding to one of the segmented nodes to store the power-on index table and the mass production information table. In addition, when allocating the page address corresponding to one of the segmented nodes to store the power-on index table and the mass production information table, the status flag bit of the page template can be used to determine whether the current page is a good page or a bad page. If it is a bad page, then allocate the page address corresponding to another segmented node to store it.

[0077] Finally, create a link mapping between the power-on index table and the mass production information table according to the relationship as Figure 7 shown, and complete the entire mass production process. However, the customer changes the double-sided paste to single-sided paste according to actual needs, that is, 1 storage product, including a storage control chip, a PCB, and 1 Flash. Since each LUN of each chip select port CE has an independent power-on index table and mass production information table, the customer only needs to perform a high-level format scan on the Flash to achieve the mass production of the Flash, which can save most of the customer's time.

[0078] In this embodiment, by reading the chip select port of the Flash and creating independent power-on index tables and mass production information tables for the LUNs of each chip select port according to the chip select port, it is equivalent that each LUN has its own separate power-on index table and mass production information table. Even if the customer later changes the multi-sided Flash to single-sided Flash for mass production, directly reading and loading the power-on index table and the mass production information table can achieve the low-level format scan of the Flash, complete the initialization of the Flash, and improve the mass production of the Flash.

[0079] Figure 2 The figure shows a schematic flow chart of a mass production speed-up method shown in another embodiment of the present application.

[0080] Please refer to Figure 2 , a mass production speed-up method, including the following steps:

[0081] Step 210, perform a full disk scan on the Flash.

[0082] For the description of step S210, please refer to step S110, which will not be elaborated here.

[0083] Step S220: Read the chip select ports included in the Flash, and create independent power-on index tables and mass production information tables for the LUNs of each chip select port according to the LUNs of each chip select port.

[0084] For the description of step S220, please refer to step S120, which will not be elaborated here.

[0085] Step S230: Adopt the first preset address allocation rule to store the power-on index tables and mass production information tables corresponding to the LUNs of each chip select port, and create a link mapping between the power-on index tables and the mass production information tables.

[0086] For the description of step S230, please refer to step S130, which will not be elaborated here.

[0087] Furthermore, in this embodiment, in order to prevent the power-on index tables and mass production information tables from "disappearing", backup tables will be created for the power-on index tables and mass production information tables corresponding to the LUNs of each chip select port, and the addresses of these backup tables are the page addresses of the original power-on index tables and original mass production information tables plus 1. For example, if the page address where the original power-on index table of the current LUN0 is stored is Page100, then its backup table is stored in Page101. The advantage of this design is that it is convenient for addressing and can improve the addressing efficiency. When the original power-on index table cannot be found, the storage control chip directly starts to search the backup table and finds the power-on index table corresponding to the LUN of the current chip select port according to the addressing logic of the backup table. The same applies to the original mass production information table, which will not be repeated here.

[0088] Even further, in this embodiment, the power-on index tables and mass production information tables are the core tables for Flash initialization. In order to prevent interference from other data, the blocks storing the power-on index tables and mass production information tables will be marked as special blocks, such as non-writable blocks and only-readable blocks, to prevent the Flash from storing other data in the blocks storing the power-on index tables and mass production information tables later. The method adopted can be to specially process the blocks by adding non-writable marks to the blocks.

[0089] Step S240: Integrate the power-on index tables corresponding to the LUNs of each chip select port to obtain the main power-on index table.

[0090] In order to be compatible with mass production of multi-chip and single-chip, in this embodiment, the power-on index tables corresponding to the LUNs of each chip select port can be integrated to obtain a power-on master index table. The power-on master index table is a summary table of all LUN power-on index tables. When mass-producing Flash in a multi-chip manner, the storage control chip only needs to read and load the power-on master index table to complete the power-on initialization of Flash.

[0091] Step S250: Obtain the total number of chip select bits according to the chip select ports included in the read Flash.

[0092] After obtaining the power-on master index table, it is necessary to allocate an address to store the power-on master index table. Since the power-on master index table is a summary of all LUN power-on index tables, it is necessary to store the power-on index table according to the address allocation logic of multiple chip select ports CE. In this embodiment, the total number of chip select bits (i.e., the total number of chip select ports) is obtained by reading the chip select ports included in the Flash again.

[0093] Step S260: Allocate an address to store the power-on master index table according to the total number of chip select bits and in combination with the second preset address allocation rule.

[0094] In this embodiment, an address is allocated to store the power-on master index table according to the total number of chip select bits and in combination with the second preset address allocation rule. The second preset address allocation rule is the same as the first preset address allocation rule. The difference is that the second preset address allocation rule reads the page templates corresponding to the LUNs of all chip select ports, obtains the total number of pages of all LUNs of all chip select ports according to the page templates, segments the total number of pages according to the preset address length, and allocates the page address corresponding to one of the segmented nodes to store the power-on master index table. For example, assuming that the total number of pages of each LUN is 51200 pages, then the total number of pages of all LUNs is 51200 * 4 = 204800, and then the total number of pages is segmented according to the preset address length of 512, and the page address corresponding to one of the segmented nodes is allocated to store the power-on master index table.

[0095] Similar to the foregoing method embodiment, the present application also provides a mass production speed-up device and a corresponding embodiment.

[0096] Figure 3 The structural schematic diagram of the mass production speed-up device in an embodiment of the present application is shown.

[0097] Please refer to Figure 3 , a mass production speed-up device 300 includes: a scanning module 310, a creation module 320, and a first allocation and storage module 330. Among them:

[0098] The scanning module 310 is used to perform a full disk scan on the Flash.

[0099] Further, the scanning module 310 includes: a writing unit 311 for writing data to the Flash; a reading unit 312 for reading the data written to the Flash; and a parsing and comparing unit 313 for parsing and comparing the data written to the Flash with the read data, and obtaining the attribute characteristics of the Flash according to the result of the parsing and comparing.

[0100] The creating module 320 is used to read the chip select ports included in the Flash, and according to the LUN of each chip select port, give each LUN of the created chip select port an independent power-on index table and a mass production information table.

[0101] The first allocation storage module 330 is used to store the power-on index table and the mass production information table corresponding to the LUN of each chip select port by adopting a first preset address allocation rule, and create a link mapping between the power-on index table and the mass production information table.

[0102] Further, in this embodiment, read the page template corresponding to the LUN of the current chip select port, obtain the total number of pages of the LUN of the current chip select port according to the page template; segment the total number of pages according to a preset address length; allocate the page addresses corresponding to the pages of the current segmented node to store the power-on index table and the mass production information table.

[0103] It should be noted that the mass production speed-up method implemented by the mass production speed-up device disclosed in this embodiment is as described in the above embodiment, so it will not be elaborated here. Optionally, each module in this embodiment and the above other operations or functions are respectively for implementing the method in the foregoing embodiment.

[0104] Figure 4 The structural schematic diagram of a mass production speed-up device in an embodiment of the present application is shown.

[0105] Please refer to Figure 4 , a mass production speed-up device 300 includes: a scanning module 310, a creating module 320, a first allocation storage module 330, an integration module 340, a reading module 350, and a first allocation storage module 360. Among them, for the functions of the scanning module 310, the creating module 320, and the first allocation storage module 330, please refer to Figure 3 , which will not be elaborated here.

[0106] The integration module 340 is used to perform integration processing on the power-on index tables corresponding to the LUNs of each chip select port to obtain a power-on main index table;

[0107] The reading module 360 is used to obtain the total number of chip select bits according to the chip select ports included in the read Flash;

[0108] The second allocation storage module 370 is used to allocate addresses to the power-on main index table for storage according to the total number of chip select bits and in combination with a second preset address allocation rule.

[0109] Further, in this embodiment, a backup module 380 and a backup address allocation module 390 are further included. The backup module 380 is used to create backups for the power-on index table and the mass production information table corresponding to the LUN of each chip select port. The backup address allocation module 390 is used to allocate addresses for the backups of the power-on index table and the mass production information table.

[0110] It should be noted that, in order to prevent the power-on index table and the mass production information table from "disappearing", backup tables will be created for the power-on index table and the mass production information table corresponding to the LUN of each chip select port, and the addresses of these backup tables are the page addresses of the original power-on index table and the original mass production information table plus 1. For example, if the page address where the original power-on index table of the current LUN0 is stored is Page100, then its backup table is stored in Page101. The advantage of this design is that it is convenient for addressing and can improve the addressing efficiency. When the original power-on index table cannot be found, the storage control chip directly starts to search for the backup table and finds the power-on index table corresponding to the LUN of the current chip select port according to the addressing logic of the backup table. The same applies to the original mass production information table, which will not be repeated here.

[0111] Further, in this embodiment, a special processing module 391 is further included. The special processing module 391 is used to mark the blocks storing the power-on index table and the mass production information table as non-writable blocks.

[0112] It should also be noted that, as the core tables for Flash initialization, in order to prevent interference from other data, the blocks storing the power-on index table and the mass production information table will be marked as special blocks, such as non-writable blocks and blocks that can only be read, to prevent the Flash from storing other data in the blocks storing the power-on index table and the mass production information table in the future. The method adopted can be to specially process the blocks by adding non-writable marks to the blocks.

[0113] Refer to Figure 5 , another embodiment of the present application shows that a computing electronic device 500 includes: a processor 510 and a memory 520.

[0114] The processor 510 may be a central processing unit (CPU), or may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0115] The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The memory 510 can include various types of storage units, such as system memory, read-only memory (ROM), and permanent storage devices.

[0116] Among them, the ROM can store static data or instructions required by the processor 520 or other modules of the computer. The permanent storage device can be a read-write storage device. The permanent storage device can be a non-volatile storage device that does not lose the stored instructions and data even when the computer is powered off. In some embodiments, the permanent storage device uses a mass storage device (such as a magnetic or optical disk, flash memory) as the permanent storage device.

[0117] In some other embodiments, the permanent storage device can be a removable storage device (such as a floppy disk, optical drive). The system memory can be a read-write storage device or a volatile read-write storage device, such as dynamic random access memory. The system memory can store some or all of the instructions and data required by the processor during operation.

[0118] In addition, the memory 520 can include any combination of computer-readable storage media, including various types of semiconductor memory chips (such as DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), and magnetic disks and / or optical disks can also be used.

[0119] In some embodiments, the memory 520 can include a removable storage device that is readable and / or writable, such as a compact disc (CD), a read-only digital versatile disc (such as DVD-ROM, dual-layer DVD-ROM), a read-only Blu-ray disc, a high-density optical disc, a flash memory card (such as SD card, min SD card, and Micro-SD card, etc.), a magnetic floppy disk, etc. The computer-readable storage medium does not include carrier waves and instantaneous electronic signals transmitted wirelessly or by wire. Executable code is stored on the memory 520, and when the executable code is processed by the processor 510, it can cause the processor 510 to execute some or all of the methods described above.

[0120] In addition, the method according to the present application can also be implemented as a computer program or a computer program product, which includes computer program code instructions for executing some or all of the steps of the above method of the present application.

[0121] Alternatively, the present application can also be implemented as a computer-readable storage medium (or a non-transitory machine-readable storage medium or a machine-readable storage medium) storing executable code (or a computer program or computer instruction code), which, when executed by a processor of an electronic device (or a server, etc.), causes the processor to execute some or all of the steps of the above-described method according to the present application.

[0122] The embodiments of the present application have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles of the embodiments, the practical application, or the improvement of the technology in the market, or to enable other ordinary skill in the art in the technical field to understand the embodiments disclosed herein.

Claims

1. A method for accelerating mass production, characterized in that, Including: Perform a full - disk scan on the Flash; Read the chip - select ports included in the Flash, and create an independent power - on index table and the mass - production information table for the LUN of each chip - select port according to the LUN of each chip - select port; Adopt the first preset address - allocation rule to store the power - on index table and the mass - production information table corresponding to the LUN of each chip - select port, and create a link mapping between the power - on index table and the mass - production information table.

2. The mass production speed-up method according to claim 1, wherein The performing a full - disk scan on the Flash includes: Write data to the Flash; Read the data written to the Flash; Parse and compare the data written to the Flash with the read data, and obtain the attribute characteristics of the Flash according to the result of the parsing and comparison.

3. The mass production speed-up method according to any one of claims 1, characterized in that The first preset address - allocation rule includes: Read the page template corresponding to the LUN of the current chip - select port, and obtain the total number of pages of the LUN of the current chip - select port according to the page template; Segment the total number of pages according to the preset address length; Allocate the page address of the page corresponding to one of the segmented nodes to store the power - on index table and the mass - production information table.

4. The mass production speed-up method according to claim 3, wherein After adopting the first preset address - allocation rule to store the power - on index table and the mass - production information table corresponding to the LUN of each chip - select port, and create a link mapping between the power - on index table and the mass - production information table, it further includes: Integrate the power - on index tables corresponding to the LUN of each chip - select port to obtain a power - on main index table; Obtain the total number of chip - select ports according to the chip - select ports included in the read Flash; According to the total number of chip - select ports, combined with the first preset address - allocation rule, allocate an address to store the power - on main index table.

5. A mass production speed-up device, characterized in that, Including: A scanning module for performing a full - disk scan on the Flash; A creating module for reading the chip - select ports included in the Flash, and creating an independent power - on index table and the mass - production information table for the LUN of each chip - select port according to the LUN of each chip - select port; A first allocation and storage module for adopting the first preset address - allocation rule to store the power - on index table and the mass - production information table corresponding to the LUN of each chip - select port, and create a link mapping between the power - on index table and the mass - production information table.

6. The mass production speed-up device according to claim 5, characterized in that, The scanning module includes: A writing unit for writing data to the Flash; A reading unit for reading the data written to the Flash; A parsing and comparing unit for parsing and comparing the data written to the Flash with the read data, and obtaining the attribute characteristics of the Flash according to the result of the parsing and comparison.

7. The mass production speed-up device according to claim 5, wherein The first preset address - allocation rule includes: Read the page template corresponding to the LUN of the current chip - select port, and obtain the total number of pages of the LUN of the current chip - select port according to the page template; Segment the total number of pages according to the preset address length; Allocate the page address of the page corresponding to one of the segmented nodes to store the power - on index table and the mass - production information table.

8. The mass production speed-up device according to claim 7, wherein, It further includes: An integration module, configured to integrate the power-on index tables corresponding to the LUNs of each of the chip select ports to obtain a power-on master index table; A reading module, configured to obtain the total number of chip selects according to the chip select ports included in the read Flash; A second allocation and storage module, configured to allocate addresses to the power-on master index table for storage according to the total number of chip selects and in combination with a second preset address allocation rule.

9. An electronic device, comprising: A processor; And A memory, on which executable code is stored, characterized in that when the executable code is executed by the processor, the processor is caused to execute the mass production speed-up method according to any one of claims 1 to 4.

10. A computer-readable storage medium, characterized in that, Stored with executable code, when the executable code is executed by the processor of the electronic device, the processor is caused to execute the mass production speed-up method according to any one of claims 1 to 4.

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