Shared storage circuit for multi-channel data caching

Abstract

The invention discloses a shared storage circuit for multi-channel data caching, which is characterized in that a data channel selector selects input data of a plurality of channels, numbers the channels, and transmits the channel numbers and the data of the selected channels to a shared storage through an output end; the channel priority arbiter performs priority ranking on data effective enable signals from a plurality of channels at the same moment and controls channel selection of the data channel selector; the storage address manager generates a write-in address, a write-in enabling signal, a read-out address signal and a read-out enabling signal according to a designed write-in and read-out rule, and transmits the signals to the shared memory; and the shared memory is used for writing or reading data according to the requirements of the memory address manager. The circuit distributes the storage space in a targeted manner according to the distribution characteristics of channel data in practical application, so that the storage overhead of the storage circuit is saved, and the storage efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular, to a shared storage circuit for multi-channel data caching. Background Art

[0002] The efficient caching and reading technology of multi-channel data has important application values in modern communication systems, high-performance computing, signal processing, high-data-rate sensing and other fields. During the multi-channel data transmission process, the arrival of data within a channel usually shows a random distribution, which makes the data volume have large fluctuations in time - that is, it may increase suddenly in a short time or may significantly decrease during certain periods. If the data transmission bandwidth is directly designed according to the highest data rate, it will not only increase the system complexity but also cause waste of bandwidth resources. Therefore, the design of the caching circuit is particularly important. The caching circuit can temporarily store the channel data when the data rate is high and read out these data when the data rate is low, so as to balance the data flow and reduce the demand for the transmission bandwidth.

[0003] The traditional multi-channel data caching method usually allocates independent storage resources for each channel. This design was relatively simple and effective in early applications. However, with the continuous improvement of the complexity of multi-channel data distribution in modern electronic systems, the independent storage resource allocation method begins to show obvious limitations. First, the uneven distribution and randomness between channels lead to over-allocation of storage resources on some channels, while on other channels, they may be idle for a long time, resulting in waste of storage space. Especially in scenarios such as high-energy particle physics experiments that need to process complex multi-channel data, the particle hits within each channel have random distribution characteristics, and there is also a certain distribution correlation between different channels. This correlation often requires additional redundant space to be reserved when allocating storage resources to cope with possible peak data loads. However, in actual work, the utilization rate of these redundant storage resources is often very low, further exacerbating the problem of waste of storage space.

[0004] In view of the above difficulties in multi-channel data caching, the concept of shared storage is proposed and, to a certain extent, improves the utilization rate of storage space. Through the shared memory, multiple channels can flexibly and dynamically allocate storage resources, thus reducing the waste of storage space. However, the current design schemes of shared storage need to solve the following problems: how to efficiently group multiple-channel data to reduce the storage space, how to coordinate the access order of multiple channels to the shared storage to avoid data conflicts, and how to manage the storage addresses to ensure the correct reading and writing of data, etc. Summary of the Invention

[0005] The object of the present invention is to provide a shared storage circuit for multi-channel data caching. According to the distribution characteristics of channel data in practical applications, the circuit allocates storage space specifically, saves the storage overhead of the storage circuit, and improves the storage efficiency.

[0006] The object of the present invention is achieved by the following technical solutions:

[0007] A shared storage circuit for multi-channel data caching, the circuit includes a data channel selector, a channel priority arbiter, a shared memory, and a storage address manager, where:

[0008] The data channel selector includes two input terminals and one output terminal: one input terminal receives data from multiple channels within the corresponding group; the other input terminal receives the channel selection signal from the channel priority arbiter, and one output terminal outputs the channel data to be transmitted to the shared memory;

[0009] The data channel selector selects the data of multiple input channels by receiving the channel selection signal from the channel priority arbiter, adds the channel number at the same time, and transmits the channel number and the data together to the shared memory through the output terminal;

[0010] The channel priority arbiter includes one input terminal and two output terminals: one input terminal receives the data valid enable signals from multiple channels within the corresponding group; one output terminal outputs the arbitration result of the channel selection to the data channel selector; the other output terminal outputs the enable signal for the data validity in all channels to the storage address manager;

[0011] The channel priority arbiter performs priority sorting on the data valid enable signals from multiple channels at the same time, and controls the channel selection of the data channel selector; among them, the channel priority rule is designed according to application requirements and circuit design requirements;

[0012] The storage address manager includes three input terminals and one output terminal: the first input terminal receives the data valid enable signal transmitted from the channel priority arbiter; the second input terminal receives the read signal from outside the system; the third input terminal is connected to the shared memory; one output terminal outputs the write or read address and enable for controlling the shared memory;

[0013] The storage address manager records the storage status of each storage unit in the shared memory in real time, and generates write addresses, write enables, read addresses, and read enable signals according to the write requirements of the channel data and the read requirements from outside the system according to the designed write and read rules, and transmits the corresponding addresses and enable signals to the shared memory;

[0014] The shared memory comprises two input terminals and two output terminals: one input terminal receives the channel number and the data of the corresponding channel from the data channel selector; the other input terminal receives the write or read address and enable from the storage address manager; one output terminal outputs the read data to the outside of the system; and the other output terminal is connected to the storage address manager;

[0015] The shared memory is used to write or read data according to the requirements of the storage address manager.

[0016] It can be seen from the technical solution provided by the present invention that the circuit allocates storage space in a targeted manner according to the distribution characteristics of channel data in actual applications, thereby saving storage overhead of the storage circuit and improving storage efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A schematic structural diagram of a shared memory circuit for multi-channel data caching provided by an embodiment of the present invention;

[0019] Figure 2 Schematic diagram of the relationship between the shared memory size (number of words) and the number of shared channels in an embodiment of the present invention;

[0020] Figure 3 Schematic diagram of the shared grouping shape of the channel array in an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, and do not constitute a limitation of the present invention. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0022] like Figure 1The figure shows a schematic structural diagram of a shared storage circuit for multi-channel data caching provided by an embodiment of the present invention. The circuit includes a data channel selector (abbreviated as DS), a channel priority arbitrator (abbreviated as PA), a shared memory (abbreviated as S-Mem), and a memory address manager (abbreviated as AM), where:

[0023] The data channel selector includes two input terminals and one output terminal: one input terminal receives data from multiple channels within the corresponding group; the other input terminal receives a channel selection signal from the channel priority arbitrator, and one output terminal outputs channel data to be transmitted to the shared memory;

[0024] The data channel selector selects the data of multiple input channels by receiving the channel selection signal from the channel priority arbitrator, adds a channel number at the same time, and transmits the channel number and data together to the shared memory through the output terminal;

[0025] The channel priority arbitrator includes one input terminal and two output terminals: one input terminal receives data valid enables from multiple channels within the corresponding group; one output terminal outputs the arbitration result of the channel selection to the data channel selector; the other output terminal outputs the enable signal for data validity in all channels to the memory address manager;

[0026] The channel priority arbitrator performs priority sorting on the data valid enable signals from multiple channels at the same time to control the channel selection of the data channel selector; among them, the channel priority rule is designed according to application requirements and circuit design requirements;

[0027] The memory address manager includes three input terminals and one output terminal: the first input terminal receives the data valid enable signal transmitted from the channel priority arbitrator; the second input terminal receives a read signal from outside the system; the third input terminal is connected to the shared memory; one output terminal outputs to control the write or read address and enable of the shared memory;

[0028] The memory address manager records the storage status of each storage unit in the shared memory in real time, and generates a write address, a write enable, a read address, and a read enable signal according to the write requirements of the channel data and the read requirements from outside the system according to the designed write / read rules, and transmits the corresponding address and enable signal to the shared memory;

[0029] The shared memory includes two input terminals and two output terminals: one input terminal receives the channel number and the corresponding channel data from the data channel selector; the other input terminal receives the write or read address and the enable signal from the storage address manager; one output terminal outputs the read data to the outside of the system; the other output terminal is connected to the storage address manager;

[0030] The shared memory is used to write or read data according to the requirements of the storage address manager.

[0031] In specific implementation, the data channel selector should add a channel number to the stored data to distinguish the data source. If the channel data already contains it, there is no need to add it.

[0032] During the process of writing or reading data in the shared memory, if there is no correlation in the data distribution among channels, then according to the read frequency of the shared memory, the distribution function in the time dimension, and the requirements for channel data caching, calculate the functional relationship between the number of storage units (number of words) required by the shared memory and the number of shared channels, and accordingly select the appropriate number of shared channels and the number of storage units (number of words) of the shared memory. Specifically:

[0033] First, determine the maximum time T that the data stays in the memory according to the read frequency f of the shared memory:

[0034]

[0035] Then, according to the arrival frequency λ of the channel data and the distribution of the data arrival within the channel, obtain the probability formula P(M) that M data arrive in a single channel within the maximum residence time T, and accordingly obtain the joint probability formula P(N,M) of a total of M data arrivals in N channels. Specifically:

[0036] P(M) = p(M,T,λ) (2)

[0037]

[0038] In formula (3), the subscript i represents the channel number; M i represents that the i-th channel has arrived at M i data within time T, and its value is a natural number from 0 to M; all possible cases of {M i} need to satisfy that their sum is M;

[0039] In formula (3), for the condition M iSumming with N means summing over all possible combinations that cover all possible cases where a total of M data arrive in N channels. All combinations are independent events from each other, so the total probability is the sum of the probabilities of each of these combinations occurring.

[0040] Then, according to the probability formula P(N,M), the probabilities of the data arriving from 0 times to M times are added together to obtain the probability formula P(N, m ≤ M) for the number of data arrivals in N channels being less than or equal to M, which is expressed as:

[0041]

[0042] Then, using the probability formula P(N, m ≤ M), all the numbers k that satisfy the maximum loss rate μ are obtained, that is, the probability of the number of data arrivals being greater than k does not exceed μ. Among all the values of k, a minimum K is found such that the probability that the total number of data arrivals in N channels exceeds K times is just lower than the maximum loss rate μ, which is expressed as:

[0043] K = Y(N) = min k≥0 {k | P(N, m ≤ k) ≥ 1 - μ} (5)

[0044] Then K is the minimum number of storage units required when satisfying the maximum loss rate μ;

[0045] In the process of determining the minimum number of storage units K, the only variable parameter is the number of channels N. By changing the number of channels N and repeating the above process, the functional relationship K = Y(N) between the minimum number of storage units K and the shared number of channels N is obtained. When only considering the circuit area, the minimum value of the function K = Y(N) is found, and the point with a smaller number of storage units K is found to determine the shared number of channels N.

[0046] On the other hand, if there is a correlation in the data distribution between some channels, then these channels are divided into different groups to eliminate the influence of the correlation.

[0047] In addition, to ensure that the data stored in the shared memory can be traced back to the channel source, the bit width of the storage unit of the shared memory should be the sum of the bit width of the channel data and the bit width of the channel numbers within the group. If the data does not need to distinguish the source, the memory bit width is only the data bit width.

[0048] The write and read rules designed by the storage address manager include:

[0049] The storage address manager records the idle state of each storage unit in real time. When new data arrives, it will allocate an idle storage unit for storage according to the priority; each time an address is allocated for new data, the one with the highest priority will be selected from all the idle storage units for allocation;

[0050] When reading out data, the data in the non-idle state is read out according to the readout requirements outside the system. Specifically, it is read out after screening and matching according to the requirements or all the stored data is directly read out.

[0051] In addition, the channel priority arbiter should select an appropriate priority rule according to the requirements in the actual application. For example, static priority, dynamic priority, etc. can be adopted. Whenever the data of the channel with a higher priority is valid, the data channel selector will give priority to selecting and numbering it.

[0052] The working process of the circuit described in the embodiment of the present invention is described below with a specific example. This example is based on the 130nm CMOS process in the application scenario of the cache and readout circuit for the measurement data of the front-end pixel detector in high-energy particle physics experiments, as Figure 1 shown. There is a measurement circuit in each channel to measure the arrival time and energy of the particles hit by the front-end detector in the channel, and then the measurement data is transmitted to the circuit described in this embodiment. In this embodiment, each group will cache and read out the data of 8 channels.

[0053] In this embodiment, the particle hit rate in each channel is 75kHz, that is, on average, there will be 75,000 particle hits and corresponding test data per second that need to be cached and read out. The hit distribution in each channel is approximately a Poisson distribution. In a single hit, the time information of the particle hit is 8 bits, and the energy information of the particle hit is 4 bits. There is generally a correlation between the hits in adjacent channels, which is determined by the particle hit rule in high-energy particle physics experiments. This correlation is specifically manifested in this embodiment that after a particle hits the channel array, there is a certain probability that it directly hits all adjacent channels in a region, and the maximum size of this region is a 2×2 channel matrix. The maximum residence time of the cached data in this embodiment is 13.8 microseconds, and the maximum loss rate of the data cached in the channel allowed by the application is 1%.

[0054] Assuming that there is no correlation between the distributions of each channel, then according to the requirements for the maximum residence time of the cached data, the distribution function of the single-channel data in the time dimension, and the maximum loss rate requirement for the channel data cache, the functional relationship between the number of storage units (words) required by the shared memory and the number of shared channels when meeting the maximum loss rate requirement is calculated, and accordingly, an appropriate number of shared channels is selected.

[0055] For example, in this embodiment, it is considered that the maximum residence time of the data is 13.8 microseconds, and the particle hit rate of a single channel is 75kHz. Therefore, the parameter λ of the Poisson distribution of a single channel in this embodiment is obtained as:

[0056] λ = 75kHz × 13.8μs = 1.035 (1)

[0057] That is, the average number of hits is 1.035 within the maximum residence time. Therefore, for each channel, the probability distribution formula of the number of particle hits N within the maximum residence time of its data is as follows:

[0058]

[0059] Since the joint distribution of multiple independent and identically distributed Poisson distributions is still a Poisson distribution, and the parameter λ is the sum of the λs of each independent distribution, the probability distribution formula of the number of particle hits N within the maximum residence time of its data for n independent channels can be obtained as follows:

[0060]

[0061] Then, according to the probability distribution formula (3), and the maximum allowable data loss rate is 1%, we list the cumulative probability of the number of hits for a single channel as shown in Table 1:

[0062] Table 1 Probability statistics of the number of particle hits when different numbers of channels are shared

[0063]

[0064] The probabilities in Table 1 represent the probabilities not greater than a specific number of hits. The bold part of the font is the case of the minimum number of storage units that satisfies the maximum loss rate of 1%. Thus, it can be obtained that with a 99% probability, the number of hits of a single particle does not exceed 4. Furthermore, it can be determined that if one channel is selected as a shared group, the number of storage units in the memory should be set to 4. Similarly, when two channels are grouped together, the probabilities of different numbers of hits can be obtained as shown in Table 1. Correspondingly, with a 99% probability, the total number of hits within the two-channel group does not exceed 6 times, that is, the number of storage units in the memory should be 6. At the same time, it can be calculated that the average number of storage units occupied by a single channel in this grouping is 3. By analogy, the relationship change diagram between the number of channels shared in the memory and the average number of storage units occupied by a single channel can be obtained, as shown in Figure 2 Shown is a schematic diagram of the relationship between the size (number of words) of the shared memory and the number of shared channels in the embodiment of the present invention.

[0065] The requirement of this embodiment is to save storage space as much as possible. The channel number part is encoded using the most space-saving 8421 binary code. In order to make full use of all the code values of the above encoding, it is advisable to select 2 m channels to share, corresponding to channel numbers of 1, 4, 8, 16, etc. From Figure 2It can be seen that as the number of shared channels increases, the demand for storage space decreases, and the rate of decrease gradually slows down. In this embodiment, considering the difficulty of physical implementation in the circuit backend, it is considered that 8 channels as the number of shared storage channels is an optimal choice that can both save a large amount of storage space and meet the requirements of backend layout and wiring. Accordingly, the number of storage units shared by 8 channels in the same group is determined to be 16.

[0066] If there is a correlation in some channels, the adjacent channels with correlation are grouped into different groups to eliminate the influence of correlation.

[0067] For example, as Figure 3 shown in the schematic diagram of the shared grouping shape of the channel array in the embodiment of the present invention. Considering that there is a certain probability that particles hit a 2×2 channel array simultaneously, which will cause a correlation in the data distribution between adjacent channels. Therefore, a grouping shape such as Figure 3 is used, that is, there is a spacing of one channel between the shared channels, and the adjacent channels with correlation are grouped into different groups to reduce the influence of correlation. This grouping shape not only makes the distance between the grouped channels not too far to affect the physical implementation of the circuit, but also can isolate the influence of the correlation of particle hits between adjacent channels. This is because in most cases, the channel matrix simultaneously hit by particles does not exceed 2×2. Therefore, it can be considered that the particle hits between the channels in the same group are independent, meeting the independence assumption used in the above calculation.

[0068] In this embodiment, the encoder in the data channel selector will distinguish 8 channels and number the 8 channels using 3-bit binary 8421 code. Finally, the number of bits of each storage unit is 15 bits, including 3 bits for channel number, 8 bits for time information of particle hits, and 4 bits for energy information of particle hits.

[0069] The channel priority rule adopted by the channel priority arbiter in this embodiment is static priority, that is, the priority decreases sequentially from channel 0 to channel 7. Whenever the data of the channel with higher priority is valid, the data channel selector will select and number it first.

[0070] In this embodiment, the address allocation rule of the storage address manager is as follows: The storage address manager records the free status of each storage unit in real time. When new data arrives, it will allocate a free storage unit for storage according to the priority. The priority here still uses the static priority. Each storage unit is numbered from 0 to 15, and the priority decreases in turn. Each time an address is allocated for new data, the storage unit with the highest priority among all free units will be selected for allocation. When reading out, the data in the non-free state will be read out according to the reading requirements outside the system. It can be read out after screening and matching according to the requirements, or all the stored data can be read out directly.

[0071] In this embodiment, the number of bits occupied by the single-channel independent storage is 48 bits, while in the case of 8-channel sharing, the average number of bits occupied by a single channel is 30 bits, which is about 37% less than the storage space. In this embodiment, the historical statistical data of the above particle detector is used as the input excitation for simulation, and the results show that this design effectively caches the channel data while saving a large amount of storage space.

[0072] It should be noted that the content not described in detail in the embodiments of the present invention belongs to the prior art well-known to those skilled in the art.

[0073] In summary, the circuit described in the embodiments of the present invention has the following advantages:

[0074] 1. By analyzing and calculating the distribution characteristics of channel data in the application of multi-channel data caching, the grouping of shared channels and the number of words and bit widths of the shared memory are designed specifically, thereby saving the memory size required for caching and reducing the circuit area;

[0075] 2. The priority rule, address allocation rule, and channel coding rule adopted by the present invention can be designed according to the actual application, with flexibility and easy hardware integration;

[0076] [[ID=ID=18]]3. The present invention can realize efficient caching and reading of multi-channel data while saving a large amount of storage space. It is not affected by the correlation of data distribution between channels, has good universality and practicability, and is easy to be integrated into a chip. Especially when dealing with a multi-channel system with a high data rate, the storage space saving is obvious.

[0077] As described above, it is only the preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims. The information disclosed in the background art part of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or imply in any form that this information constitutes the prior art known to those skilled in the art.

Claims

1. A shared storage circuit for multi-channel data caching, characterized in that, The circuit includes a data channel selector, a channel priority arbiter, a shared memory, and a storage address manager, where: The data channel selector includes two input terminals and one output terminal: one input terminal receives data from multiple channels within the corresponding group; the other input terminal receives the channel selection signal from the channel priority arbiter, and one output terminal outputs the channel data to be transmitted to the shared memory; The data channel selector selects the data of multiple input channels by receiving the channel selection signal from the channel priority arbiter, adds the channel number at the same time, and transmits the channel number and the data together to the shared memory through the output terminal; The channel priority arbiter includes one input terminal and two output terminals: one input terminal receives the data valid enable signals from multiple channels within the corresponding group; one output terminal outputs the arbitration result of the channel selection to the data channel selector; the other output terminal outputs the enable signal for the data validity in all channels to the storage address manager; The channel priority arbiter performs priority sorting on the data valid enable signals from multiple channels at the same time, and controls the channel selection of the data channel selector; among them, the channel priority rule is designed according to application requirements and circuit design requirements; The storage address manager includes three input terminals and one output terminal: the first input terminal receives the data valid enable signal transmitted from the channel priority arbiter; the second input terminal receives the read signal from outside the system; the third input terminal is connected to the shared memory; one output terminal outputs to control the write or read address and enable of the shared memory; The storage address manager records the storage state of each storage unit in the shared memory in real time, and generates write addresses, write enables, read addresses, and read enable signals according to the write requirements of the channel data and the read requirements outside the system according to the designed write and read rules, and transmits the corresponding addresses and enable signals to the shared memory; The shared memory includes two input terminals and two output terminals: one input terminal receives the channel number and the data of the corresponding channel from the data channel selector; the other input terminal receives the write or read address and enable from the storage address manager; one output terminal outputs the read data to outside the system; the other output terminal is connected to the storage address manager; The shared memory is used to write or read data according to the requirements of the storage address manager.

2. The shared storage circuit for multi-channel data caching according to claim 1, wherein The data channel selector should add a channel number to the stored data to distinguish the data source. If the channel data already contains it, there is no need to add it.

3. The shared storage circuit for multi-channel data caching according to claim 1, wherein During the process of writing or reading data in the shared memory, if there is no correlation between the data distributions of each channel, then according to the read frequency of the shared memory, the distribution function in the time dimension, and the requirements for channel data caching, calculate the functional relationship between the number of storage units required by the shared memory and the number of shared channels, and select the appropriate number of shared channels and the number of storage units of the shared memory accordingly; If there is a correlation in the data distribution among certain channels, these channels are grouped into different groups to eliminate the influence of the correlation.

4. The shared storage circuit for multi-channel data caching according to claim 3, wherein The calculation process of the number of the shared channels and the number of storage units of the shared memory is specifically as follows: First, the maximum time T that the data stays in the memory is determined according to the read frequency f of the shared memory: Then, according to the arrival frequency λ of the channel data and the distribution of the data arrival within the channel, the probability formula P(M) for the data to arrive M times in a single channel within the maximum residence time T is obtained, and based on this, the probability formula P(N,M) for a total of M times of data arrival under N channels is obtained, specifically as follows: P(M) = p(M, T, λ) (2) In formula (3), the subscript i represents the channel number; M i indicates that the i-th channel has received M i data within time T, and its value is a natural number from 0 to M; In formula (3), the summation over conditions M i and N means summing over all possible combinations that cover all possible cases where data arrives M times in total among N channels. All these combinations are mutually independent events. Therefore, the total probability is the sum of the probabilities of each of these combinations occurring; According to the probability formula P(N,M), the probabilities of the arrival data from 0 times to M times are added to obtain the probability formula P(N, m≤M) for the number of data arrivals less than or equal to M under N channels, expressed as: Then, using the probability formula P(N, m≤M), the number k that satisfies all the maximum loss rates μ is obtained, that is, the probability that the number of data arrivals is greater than k does not exceed μ. Among all the k values, a minimum K is found such that the probability that the total number of data arrivals in N channels exceeds K times is just lower than the maximum loss rate μ, expressed as: K = Y(N) = min k≥0 {k | P(N, m ≤ k) ≥ 1 - μ} (5) Then K is the minimum number of storage units required when satisfying the maximum loss rate μ; In the process of determining the minimum number of storage units K, by changing the number of channels N and repeating the above process, the functional relationship K = Y(N) between the minimum number of storage units K and the number of shared channels N is obtained, and the minimum value of the function K = Y(N) is found to determine the number of shared channels N.

5. The shared storage circuit for multi-channel data caching according to claim 1, wherein The bit width of the storage unit of the shared memory is the sum of the bit width of the channel data and the bit width of the channel number within the group.

6. The shared storage circuit for multi-channel data caching according to claim 1, wherein The channel priority arbiter selects a suitable priority rule according to the requirements in the actual application, including static priority or dynamic priority. Whenever the data of the channel with a higher priority is valid, the data channel selector will preferentially select and number it.

7. The shared storage circuit for multi-channel data caching according to claim 1, characterized in that, The write and read rules designed by the storage address manager include: The storage address manager records the idle state of each storage unit in real time. When new data arrives, it will allocate an idle storage unit for storage according to the priority; each time an address is allocated for new data, the one with the highest priority will be selected from all the idle storage units for allocation; When reading out data, the data in the non-idle state is read out according to the read requirements outside the system, specifically, it is read out after screening and matching according to the requirements or all the stored data is directly read out.

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