Data prefetching method and related device

Abstract

The invention provides a data prefetching method, which comprises the following steps of: after a processor accesses target data based on a target instruction, determining a prefetching step length from a plurality of address differences recorded by a target item corresponding to the target instruction in an access instruction list according to a current value of an out-of-order flag bit, and executing data prefetching operation based on the predicted step length; wherein the current value of the out-of-order flag bit is determined according to the number of prediction errors of the branch predictor in multiple data access operations recently executed by the processor, so that the current value of the out-of-order flag bit can represent the out-of-order degree of data currently accessed by the processor; the prefetch step length is determined from the address differences recorded by the target item based on the out-of-order flag bit, so that the determined prefetch step length better fits the out-of-order degree of data access of the processor, the accuracy of data prefetch operation is improved, and the probability of cache miss when the processor processes data is reduced.

Description

Technical Field

[0001] This specification relates to the field of computer application technologies. Specifically, it relates to data prefetching technologies in the field of computer application technologies, and more specifically, to a data prefetching method and related devices. Background Art

[0002] Data prefetching is a technology used to improve the performance of computer systems. Data prefetching can predict the data that the processor may need during future execution and load this data from storage devices (such as memory, disks, etc.) into the cache or a storage area closer to the processor in advance. In this way, when the processor actually needs to use this data, it can obtain and use this data faster, thereby reducing the waiting time of the processor and improving the operating efficiency of the entire system.

[0003] However, currently, the accuracy of data prefetching technologies needs to be improved. It is necessary to improve the accuracy of data prefetching technologies to reduce the number of cache misses and improve the execution efficiency of the processor. Summary of the Invention

[0004] Embodiments of this specification provide a data prefetching method and related devices to achieve the purpose of improving the accuracy of data prefetching technologies and enhancing the execution efficiency of the processor.

[0005] To achieve the above technical objectives, embodiments of this specification provide the following technical solutions:

[0006] In a first aspect, a data prefetching method is provided, which is applied to a processor. The data prefetching method includes:

[0007] In response to the processor accessing target data based on a target instruction, determine a prefetch step size from multiple address differences in a target item record corresponding to the target instruction in the memory access instruction table according to the current value of the out-of-order flag bit;

[0008] Execute a data prefetching operation based on the prefetch step size and the address of the target data;

[0009] The target item includes multiple address differences. The address difference includes the difference between the addresses of data accessed in adjacent access operations among multiple access operations performed based on the target instruction. The current value of the out-of-order flag bit is determined according to the number of prediction errors of the branch predictor in multiple recent data access operations performed by the processor.

[0010] In a second aspect, a data prefetching device is provided, which is applied to a processor. The data prefetching device includes:

[0011] A step size determination module, configured to, in response to the processor accessing target data based on a target instruction, determine a prefetch step size from multiple address differences recorded in a target item corresponding to the target instruction in a memory access instruction table according to a current value of an out-of-order flag bit;

[0012] A data prefetch module, configured to perform a data prefetch operation based on the prefetch step size and an address of the target data;

[0013] The target item includes multiple address differences, and the address difference includes a difference between addresses of data accessed in adjacent access operations among multiple access operations performed based on the target instruction; the current value of the out-of-order flag bit is determined according to the number of times of prediction errors of a branch predictor in multiple recent data access operations performed by the processor.

[0014] In a third aspect, a processor is provided, and the processor is configured to:

[0015] In response to a first target event occurring, perform a data prefetch operation based on a target address and a prefetch offset;

[0016] The first target event includes: the target data accessed by the processor based on a target instruction is not in a cache, or the target data is obtained by a prefetch operation; the target address includes an address of the target data;

[0017] The prefetch offset is determined based on offsets recorded in multiple offset items in an offset list, and the offset in the offset item is determined based on a target item and a virtual address of the target data, and the target item includes virtual addresses of multiple data accessed by the processor based on the target instruction.

[0018] In a fourth aspect, a system-on-chip is provided, including: a memory and a processor; wherein,

[0019] The memory is configured to store data;

[0020] The processor is configured to: in response to the processor accessing target data based on a target instruction, determine a prefetch step size from multiple address differences recorded in a target item corresponding to the target instruction in a memory access instruction table according to a current value of an out-of-order flag bit;

[0021] Based on the prefetch step size and an address of the target data, perform a data prefetch operation on data stored in the memory;

[0022] The target item includes a plurality of the address differences, where the address difference includes the difference between the addresses of the data accessed by adjacent access operations in multiple access operations performed based on the target instruction; the current value of the out-of-order flag is determined according to the number of prediction errors of the branch predictor in multiple recent data access operations performed by the processor.

[0023] In a fifth aspect, a computing device is provided, including: the system-on-chip as described in any one of the above.

[0024] As can be seen from the above technical solutions, in the data prefetching method provided by the embodiments of this specification, after the processor accesses the target data based on the target instruction, the prefetching step size can be determined from the multiple address differences recorded in the target item corresponding to the target instruction in the access instruction table according to the current value of the out-of-order flag, and the data prefetching operation is performed based on the predicted step size; among them, the current value of the out-of-order flag is determined according to the number of prediction errors of the branch predictor in multiple recent data access operations performed by the processor. In this way, the current value of the out-of-order flag can represent the out-of-order degree of the data currently accessed by the processor. Determining the prefetching step size from the multiple address differences recorded in the target item based on this out-of-order flag can make the determined prefetching step size more in line with the out-of-order degree of the data accessed by the processor, which is beneficial to improving the accuracy of the data prefetching operation, and thus beneficial to reducing the probability of cache misses when the processor processes data. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of this specification. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0026] Figure 1 It is a schematic structural diagram of a memory access instruction table provided by the embodiments of this specification;

[0027] Figure 2 It is a schematic flowchart of a data prefetching method provided by the embodiments of this specification;

[0028] Figure 3 It is a schematic flowchart of the processing when it is detected that the branch predictor makes a prediction error provided by the embodiments of this specification;

[0029] Figure 4 It is a schematic flowchart of the processing when it is detected that an access operation is performed provided by the embodiments of this specification;

[0030] Figure 5A schematic structural diagram of a computing device provided by an embodiment of this specification. Specific embodiments

[0031] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this specification should have the ordinary meanings understood by those of ordinary skill in the field to which this specification belongs. The "first", "second" and similar terms used in the embodiments of this specification do not indicate any order, quantity or importance, but are only used to avoid confusion of components.

[0032] Unless otherwise required by the context, throughout this specification, "a plurality of" means "at least two", and "including" is interpreted as an open and inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples" etc. are intended to indicate that specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of this specification. The schematic representations of the above terms do not necessarily refer to the same embodiment or example.

[0033] Next, the technical solutions in the embodiments of this specification will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this specification. Obviously, the described embodiments are only a part of the embodiments of this specification, rather than all the embodiments. Based on the embodiments in this specification, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this specification.

[0034] Overview

[0035] With the rapid development of processor technology, the operating speed of the processor is getting faster and faster, while the speed of the matching memory (such as DRAM (Dynamic Random Access Memory)) has not been correspondingly improved. This speed difference limits the processing performance of the processor. Each time the processor accesses off-chip memory (such as DRAM), the processor may need to pause for hundreds of clock cycles, significantly affecting the performance of the processor.

[0036] The cache hierarchy can improve the performance of data reference programs with good temporal and spatial locality. However, in some types of application programs such as big data, due to the high cache miss rate, it is still difficult to reduce the data reference latency.

[0037] For this reason, the data prefetching technology came into being. The data prefetching technology can be implemented based on the principle of program locality. Program locality includes temporal locality and spatial locality. Among them, temporal locality means that if a data item is being accessed, then it is very likely to be accessed again in the near future. For example, in a loop, the loop variable and the data used in the loop body are accessed in each loop iteration. Spatial locality means that if a data item is accessed, then the data items adjacent to its address are also very likely to be accessed in the near future. For example, when accessing an array element, it is very likely that the adjacent elements in the array will be accessed next. Based on the above program locality, the data prefetching technology can preload the data that the processor may use from the storage device into the cache through a certain algorithm to reduce the time required for the processor to obtain data. In the related technology, the data prefetching is based on the assumption that the program is executed in order. When the branch predictor in the processor makes a wrong prediction, the processor may execute along the wrong path, thus interfering with the training of the data prefetching and affecting the performance of data prefetching. For example, the traditional stride prefetching is usually triggered by instructions with a constant memory access address interval and issues prefetch requests based on these intervals. However, when the branch predictor makes a wrong prediction and causes the processor to execute the wrong path, even if the instructions on the true path have a constant memory access interval, the data prefetching cannot correctly capture this feature, thus affecting the accuracy of its judgment and prediction.

[0038] To solve this problem, the inventor designed a memory access instruction table as shown in Figure 1 The memory access instruction table may include multiple items. Each item may include fields such as instruction PC (instruction program counter value) and multiple address differences. The instruction PC is used to indicate the virtual address of the instruction, and the instruction PC can be used to uniquely identify which instruction this item corresponds to. The multiple address differences may include the differences between the addresses of the data accessed by adjacent access operations among multiple access operations executed based on the target instruction. In addition, in some embodiments, the memory access instruction table may further include a cache line address (the data address of the instruction's most recent access, and this data address may be a virtual address), a valid bit, and a write pointer. Among them, the valid bit can be used to identify the valid state of this item, and the write pointer can be used to indicate the field where the new address difference is written when the address difference in this item needs to be updated. For example, in the initial state, the address differences 0 to 5 may all be 0. At this time, the write pointer can be 0 to point to address difference 0. When a new address difference needs to be written into this item, it can be written into address difference 0, and then the write pointer is incremented by 1 to point to address difference 1. At this time, when a new address difference needs to be written into this item, it can be correctly written into address difference 1.

[0039] In addition to the above memory access instruction table, the current value of the out-of-order flag can also be determined by counting the number of times the branch predictor makes incorrect predictions in multiple recent data access operations performed by the processor. In this way, the current value of the out-of-order flag can be used to characterize the degree of out-of-order data access by the processor. For example, when the degree of out-of-order data access by the processor is low, the out-of-order flag can be 0. At this time, based on this out-of-order flag, a prefetch step size can be determined from multiple address differences according to a certain strategy, and the next data prefetch operation can be performed based on this prefetch step size. When the degree of out-of-order data access by the processor is high and the branch predictor frequently makes incorrect predictions, the out-of-order flag can be 1. At this time, based on this out-of-order flag, a prefetch step size can be determined from multiple address differences according to another strategy, and the next data prefetch operation can be performed based on this prefetch step size. In this way, determining the prefetch step size from the multiple address differences recorded in the target item based on this out-of-order flag can make the determined prefetch step size more in line with the degree of out-of-order data access by the processor, which is beneficial to improving the accuracy of data prefetch operations and thus reducing the probability of cache misses when the processor processes data.

[0040] Based on the above concept, an embodiment of this specification provides a data prefetch method. Next, the data prefetch method provided by the embodiment of this specification will be described exemplarily with reference to the accompanying drawings.

[0041] Exemplary Method

[0042] Taking the application to a processor as an example, an embodiment of this specification provides a data prefetch method, as Figure 2 shown, including:

[0043] S201: In response to the processor accessing target data based on a target instruction, determine a prefetch step size from multiple address differences recorded in a target item corresponding to the target instruction in the memory access instruction table according to the current value of the out-of-order flag;

[0044] S202: Perform a data prefetch operation based on the prefetch step size and the address of the target data;

[0045] When using a target instruction, the processor can read the instruction based on the virtual address of the target instruction, and read and execute the data according to the address of the target data that the instruction needs to operate on. The processor can use the Program Counter (PC) to track the address of the instruction that needs to be executed currently.

[0046] The target item includes a plurality of the address differences, where the address difference includes the difference between the addresses of the data accessed by adjacent access operations in multiple access operations executed based on the target instruction. For example, if the processor executes 7 access operations based on the target instruction, and the addresses of the data accessed by the 7 access operations are A, A + 1, A + 2, A + 3, A + 4, A + 5, and A + 6 respectively, then six address differences can be obtained according to the differences between the addresses of the data accessed by adjacent access operations, and these six address differences are all 1. The current value of the out-of-order flag bit is determined according to the number of prediction errors of the branch predictor in multiple recent data access operations executed by the processor.

[0047] As described above, the current value of the out-of-order flag bit can be used to characterize the out-of-order degree of data access by the processor. In some embodiments, the value of the out-of-order flag bit can include 0 or 1, indicating a low out-of-order degree and a high out-of-order degree respectively. When the current values of the out-of-order flag bits are different, different strategies can be used to determine the prefetch step size from the multiple address differences recorded in the target item, so as to improve the data prefetch accuracy under different out-of-order degrees. Of course, in addition to dividing the out-of-order degree into two levels of low and high as described above, the number of bits of the out-of-order flag bit can also be set to multiple bits to characterize a more detailed out-of-order degree. This specification does not limit this, and it depends on the actual situation specifically.

[0048] When performing a data prefetch operation based on the prefetch step size and the address of the target data, at least one data can be prefetched in units of the prefetch step size on the basis of the address of the target data. Assuming that the address of the target data is A and the prefetch step size is 2, then the data with the address A + 2 can be prefetched, or multiple data with the addresses A + 2, A + 4, A + 6... etc. can be prefetched.

[0049] Generally speaking, in this embodiment, after the processor accesses the target data based on the target instruction, the data prefetch method can determine the prefetch step size from the multiple address differences recorded in the target item corresponding to the target instruction in the access instruction table according to the current value of the out-of-order flag bit, and perform a data prefetch operation based on this prediction step size. Among them, the current value of the out-of-order flag bit is determined according to the number of prediction errors of the branch predictor in multiple recent data access operations executed by the processor. In this way, the current value of the out-of-order flag bit can characterize the out-of-order degree of the data currently accessed by the processor. Determining the prefetch step size from the multiple address differences recorded in the target item based on this out-of-order flag bit can make the determined prefetch step size more suitable for the out-of-order degree of data access by the processor, which is beneficial to improving the accuracy of the data prefetch operation, and thus is beneficial to reducing the probability of cache misses when the processor processes data.

[0050] In one embodiment, determining the prefetch step size from multiple address differences of a target entry record corresponding to the target instruction in the memory access instruction table according to the current value of the out-of-order flag bit includes:

[0051] If the current value of the out-of-order flag bit includes a first target value, then determine the first address difference among the multiple address differences of the target entry as the prefetch step size, where the first address difference includes: multiple address differences with the same value in the memory access instruction table;

[0052] If the current value of the out-of-order flag bit includes a second target value, then determine the second address difference among the multiple address differences recorded in the target entry as the prefetch step size, where the second address difference includes the address difference in the memory access instruction table that can divide evenly into multiple other address differences;

[0053] The first target value is different from the second target value.

[0054] In this embodiment, a method for determining the prefetch step size from multiple address differences of a target entry record when the out-of-order flag bit is different is given. Specifically, when the current value of the out-of-order flag bit includes a first target value (for example, it can be 0), it is considered at this time that the degree of out-of-order data access of the processor is relatively low, and the first address difference among the multiple address differences of the target entry can be determined as the prefetch step size. Suppose the multiple address differences in the target entry include: 2, 3, ......

[0055] When the current value of the out-of-order flag bit includes a second target value (for example, it can be 1), it is considered at this time that the degree of out-of-order data access of the processor is relatively high, and the second address difference among the multiple address differences of the target entry can be determined as the prefetch step size. Suppose the multiple address differences in the target entry include: -2, +4, +2, +4, -2, etc. When the degree of out-of-order is relatively high, through multiple relationship detection, it can be found that +2 can be divided evenly into multiple other address differences, thereby identifying the address difference pattern of +2 for subsequent data prefetching and access.

[0056] For example, assume that when the out-of-order degree is low, the processor accesses cache lines (data) A, A+2, A+4, A+6, A+8, A+10... on demand. There is a rule of +2 between the accessed cache line addresses. Here, it is only necessary to identify whether the difference between the continuously accessed cache line addresses is the same. Predict that cache lines A+12, A+14... will be accessed subsequently, and then perform prefetch operations on data such as A+12 and A+14.

[0057] However, when the out-of-order degree is high, for example, when a branch misprediction occurs, it may cause the normal execution order to be disrupted. The order of accessing cache lines may become A+2, A, A+4, A+6, A+10, A+8... At this time, the difference between adjacent accessed cache line addresses can no longer identify the rule of +2. At this time, the address differences in the target items are -2, +4, +2, +4, -2 respectively. Through multiple-relationship detection, it can be detected that +2 can just be divided evenly by several other address differences, so as to identify the address difference rule of +2. Based on the address difference rule of +2, the normal execution order can be correctly predicted and data prefetch can be performed, so as to facilitate the prediction of subsequent data access.

[0058] Generally speaking, in this embodiment, corresponding determination strategies for prefetch step sizes are set respectively for low and high out-of-order degrees, which is beneficial to improving the prefetch accuracy at different out-of-order degrees.

[0059] In an optional embodiment, a feasible way to determine the current value of the out-of-order flag bit is given. Specifically, if the number of prediction errors of the branch predictor is greater than or equal to the error threshold in multiple recent data access operations executed by the processor, then determine the current value of the out-of-order flag bit as the second target value;

[0060] If the number of prediction errors of the branch predictor is less than the error threshold in multiple recent data access operations executed by the processor, then determine the current value of the out-of-order flag bit as the first target value.

[0061] The branch predictor can be a hardware unit in the pipeline of the processor. The branch predictor can use a specific algorithm to predict which direction the program flow will be caused by branch instructions (such as jumps, loops, etc.). Branch instructions change the execution order of the program according to certain conditions, and the branch predictor tries to predict the results of these conditions so that the processor can continue to execute subsequent instructions without waiting for the evaluation of branch conditions. However, when the branch predictor makes a wrong prediction due to reasons such as branch target address changes and insufficient instruction stream information, the processor needs to perform a flush operation, discard the already predicted instructions, empty the pipeline and restart execution along the correct branch.

[0062] In this embodiment, multiple data access operations continuously executed by the processor can be grouped as a set for evaluating the degree of out-of-order execution. Specifically, assuming that in the most recent 8 data access operations executed by the processor, the branch predictor has made 4 or more prediction errors, it can be considered that the degree of out-of-order data access by the processor is relatively high at this time, and the current value of the out-of-order flag can be determined as the second target value. Conversely, if in the most recent 8 data access operations executed by the processor, the branch predictor has made less than 4 prediction errors, it can be considered that the degree of out-of-order data access by the processor is relatively low at this time, and the current value of the out-of-order flag can be determined as the first target value. By evaluating the degree of out-of-order execution with every 8 data access operations as a set, the degree of out-of-order data processing by the processor can be evaluated more accurately, and complex calculations are not required, which helps to simplify the complexity of the method.

[0063] In one embodiment, a specific way of counting the number of access operations and the number of prediction errors of the branch predictor is given. Specifically, the processor further includes: a first counter and a second counter. The first counter is used to record the number of access operations most recently executed by the processor, and the second counter is used to record the number of prediction errors of the branch predictor. After the processor accesses the target data based on the target instruction, the following steps are further included:

[0064] Increment the count value of the first counter by 1. When the count value of the first counter is less than the memory access times threshold and the count value of the second counter is greater than or equal to the error times threshold, determine the current value of the out-of-order flag as the second target value;

[0065] When the count value of the first counter is less than the memory access times threshold and the count value of the second counter is less than the error times threshold, determine the current value of the out-of-order flag as the first target value.

[0066] In this embodiment, the first counter and the second counter are respectively used to count the number of access operations most recently executed by the processor and the number of prediction errors of the branch predictor. The first counter can be called the load_counter counter (record counter), and the second counter can be called the mis_pre_counter counter (mis-prediction counter). These two counters can be initialized to 0 before use. When the corresponding events occur, the counters are incremented by 1 for counting. When the count value of the first counter exceeds the memory access times threshold, the first counter and the second counter can be cleared for re-counting. In this way, it is convenient to count the number of access operations most recently executed by the processor and the number of prediction errors of the branch predictor.

[0067] In a feasible implementation, a feasible method for counting times based on a first counter and a second counter is provided. Specifically, the data prefetching method further includes:

[0068] In response to a prediction error occurring in the branch predictor, determine whether the count value of the first counter is greater than or equal to the memory access times threshold. If so, clear the count values of the first counter and the second counter; if not, increment the count value of the second counter by one.

[0069] Among them, the response to the prediction error occurring in the branch predictor includes:

[0070] In response to a notification message from the branch predictor, or the processor performs a line flushing operation; the notification message is sent when the branch predictor has a prediction error.

[0071] In this implementation, a feasible notification method for the branch predictor to have a prediction error is provided. For example, when the branch predictor has a prediction error, a notification message can be sent to other components of the processor to notify that a prediction error has occurred. Also for example, it can be monitored whether the processor has performed a line flushing operation due to a prediction error in the branch predictor. If so, it indicates that the branch predictor has a prediction error. Determining whether the branch predictor has a prediction error flexibly through various optional methods is beneficial to improving the applicability of the method.

[0072] In an implementation, a feasible maintenance method for the memory access instruction table is provided. Specifically, the memory access instruction table includes multiple items. The item includes the data address last accessed by the instruction, multiple address differences, a write pointer, and the program counter value of the instruction. The program counter value of the instruction is used to indicate the virtual address of the instruction, and the write pointer is used to indicate the field where the new address difference is written; before determining the prefetch step size from the multiple address differences recorded in the memory access instruction table corresponding to the target instruction according to the current value of the out-of-order flag bit after the processor accesses the target data based on the target instruction, it further includes:

[0073] Query the memory access instruction table according to the target instruction. If the target item corresponding to the target instruction does not exist in the memory access instruction table, allocate an item in the memory access instruction table as the target item for the target instruction.

[0074] If the target entry exists in the memory access instruction table, a new address difference is obtained by subtracting the data address recorded in the target entry during the target instruction's most recent access from the virtual address of the cache line currently accessed by the target instruction. The new address difference is written into the target entry according to the write pointer, the write pointer is incremented by one, and the data address recorded in the target entry during the target instruction's most recent access is updated according to the virtual address of the cache line currently accessed by the target instruction.

[0075] In this embodiment, before performing the prefetch operation, the memory access instruction table is first maintained according to the operation of the processor accessing the target data based on the target instruction, which is beneficial to ensuring the timeliness of the data in the memory access instruction table, so that the data such as the address difference recorded in the memory access instruction table can reflect the current data access behavior of the processor.

[0076] In one embodiment, a feasible way to allocate an entry for the target instruction as the target entry in the memory access instruction table is provided. Specifically, allocating an entry for the target instruction as the target entry in the memory access instruction table includes:

[0077] Determine a replacement candidate entry among multiple entries in the memory access instruction table according to the target replacement algorithm;

[0078] Update the program counter value of the instruction in the replacement candidate entry to the program counter value of the target instruction;

[0079] Update the data address of the instruction in the replacement candidate entry during its most recent access to the virtual address of the data accessed by the target instruction during its most recent access;

[0080] Update the multiple address differences in the replacement candidate entry to 0 and update the write pointer to 0.

[0081] Optionally, the target replacement algorithm includes but is not limited to at least one of the Second Chance replacement algorithm, the Least Recently Used (LRU) replacement algorithm, and the Least Frequently Used (LFU) replacement algorithm. By determining the replacement candidate entry through the above target replacement algorithm, relatively active entries in the memory access instruction table can be retained, avoiding frequent replacement of frequently used entries, which is beneficial to reducing the replacement operation for the entries in the memory access instruction table and reducing the algorithm overhead.

[0082] The data prefetch method provided in this specification will be introduced below in a specific embodiment, referring to Figure 3 、 Figure 4 and in combination with reference to Figure 1 , Figure 1Shows the field names included in each item in the memory access instruction table. In the memory access instruction table, the instruction PC can be used as an index to record information such as the virtual address of the data (or cache line) accessed by the instruction in the recent period and the address difference. In one embodiment, the memory access instruction table may include 64 items, and the entire memory access instruction table can adopt a fully associative structure to facilitate the search operation when an item needs to be replaced. When an item in the memory access instruction table needs to be replaced and maintained, the second-chance replacement algorithm can be used for item replacement. Each item may include the following fields: instruction PC, cache line address, valid bit, write pointer, and multiple address differences; among them, the instruction PC is used to indicate the address of the instruction, that is, the location of the instruction in the memory, the cache line address represents the data address accessed by the instruction most recently (for example, it can be the virtual address of the cache line accessed by the instruction most recently), the value of the valid bit represents whether this item is valid, the write pointer is used to point to the field where the new address difference can be written, and in Figure 1 Among them, the number of multiple address differences is 6, which records the address differences between adjacent access operations in the most recent 7 access operations of the instruction.

[0083] Figure 3 Shows the processing flow when it is detected that the branch predictor has a prediction error:

[0084] S1. When it is detected that the branch prediction unit in the processor has a prediction error (i.e., misprediction), judge whether the value of the first counter is greater than or equal to the memory access times threshold (for example, it can be 8, 9, 10, etc., taking 8 as an example in Figure 3 Among them), this first counter can be pre-initialized to 0 during the initialization process. If not, then go to step S2; if so, then go to step S3;

[0085] S2. Increment the value of the second counter by 1.

[0086] S3. Clear the count values of the first counter and the second counter.

[0087] Figure 4 Shows the processing flow when an access operation is detected. When an access operation for accessing target data based on a target instruction is detected, the following process starts to be executed:

[0088] S10. Increment the value of the first counter by 1;

[0089] S11. Judge whether the value of the first counter is greater than or equal to 8. If so, then go to step S12; if not, then end the setting process of the current value of the out-of-order flag bit and wait for the next access operation;

[0090] S12. Judge whether the value of the second counter is greater than or equal to 4. If so, then go to step S13; if not, then go to step S14;

[0091] S13. Set the current value of the out-of-order flag to the second target value, and at the same time clear the count values of the first counter and the second counter;

[0092] S14. Set the current value of the out-of-order flag to the first target value, and at the same time clear the count values of the first counter and the second counter;

[0093] S15. Use the PC value of the target instruction to search the memory access instruction table. If there is a matching entry that matches the PC of the target instruction, go to step S16; if there is no matching entry that matches the PC of the target instruction, go to step S22;

[0094] S16. Subtract the data address last accessed by the target instruction recorded in the target entry from the virtual address of the cache line currently accessed by the target instruction to obtain a new address difference;

[0095] S17. Write the new address difference to the address difference field pointed to by the write pointer to update the address difference in the target entry;

[0096] S18. Update the target entry cache line address (i.e., the data address last accessed by the target instruction recorded in the target entry) to the virtual address of the cache line currently accessed by the target instruction;

[0097] S19. Determine whether the current value of the out-of-order flag is the first target value. If so, go to step S20; if not, go to step 21;

[0098] S20. Check whether there is an address difference among the multiple address differences of the target entry that is the same as one or more (e.g., 2, 3, 4, etc.) other address differences. If so, determine this address difference as the first address difference and perform a data prefetch operation with the first address difference as the prefetch step size;

[0099] S21. Detect whether there is an address difference among the multiple address differences of the target entry that can be divided by one or more (e.g., 2, 3, 4, etc.) other address differences. If so, determine this address difference as the second address difference and perform a data prefetch operation with the second address difference as the prefetch step size;

[0100] S22. Use the target replacement algorithm to allocate an entry in the memory access instruction table to the target instruction, update the PC value of this entry to the PC value of the target instruction, update the cache line address field of this entry to the virtual address of the cache line currently accessed by the target instruction (i.e., the virtual address of the target data), update the address difference field of this entry to 0, and update the write pointer end to 0.

[0101] Exemplary device

[0102] In an exemplary embodiment of the present specification, a data prefetching device is further provided, which is applied to a processor. The data prefetching device includes:

[0103] A step size determination module, configured to, in response to the processor accessing target data based on a target instruction, determine a prefetch step size from multiple address differences recorded in a target item corresponding to the target instruction in a memory access instruction table according to a current value of an out-of-order flag bit;

[0104] A data prefetch module, configured to perform a data prefetch operation based on the prefetch step size and an address of the target data;

[0105] The target item includes multiple address differences, and the address difference includes a difference between addresses of data accessed in adjacent access operations among multiple access operations performed based on the target instruction; the current value of the out-of-order flag bit is determined according to the number of prediction errors of a branch predictor in multiple recent data access operations performed by the processor.

[0106] For specific limitations on the data prefetching device, reference can be made to the limitations on the data prefetching method in the foregoing text, which will not be elaborated here. Each module in the foregoing data prefetching device can be implemented in whole or in part by software, hardware, and their combination. The foregoing modules can be embedded in a processor in a computer device in a hardware form or be independent of the processor, or can be stored in a memory in the computer device in a software form, so as to facilitate the processor to call and execute operations corresponding to the foregoing modules.

[0107] Exemplary Device

[0108] An embodiment of the present specification provides a processor, which is configured to:

[0109] In response to a first target event occurring, perform a data prefetch operation based on a target address and a prefetch offset;

[0110] The first target event includes: the target data accessed by the processor based on a target instruction is not in a cache, or the target data is obtained through a prefetch operation; the target address includes an address of the target data;

[0111] The prefetch offset is determined based on offsets recorded in multiple offset items in an offset list, and the offset in the offset item is determined based on a target item and a virtual address of the target data, and the target item includes virtual addresses of multiple data accessed by the processor based on the target instruction.

[0112] An embodiment of the present specification further provides a system-on-chip, including: a memory and a processor; wherein,

[0113] The memory is configured to store data;

[0114] The processor is configured to: in response to the processor accessing target data based on a target instruction, determine a prefetch step size from multiple address differences recorded in a target entry corresponding to the target instruction in a memory access instruction table according to a current value of an out-of-order flag bit;

[0115] Perform a data prefetch operation on the data stored in the memory based on the prefetch step size and the address of the target data;

[0116] The target entry includes multiple of the address differences, and the address difference includes a difference between addresses of data accessed in adjacent access operations among multiple access operations performed based on the target instruction; the current value of the out-of-order flag bit is determined according to the number of prediction errors of a branch predictor in multiple recent data access operations performed by the processor.

[0117] Another embodiment of this specification also proposes a computing device. Refer to Figure 5 As shown, an exemplary embodiment of this specification also provides a computing device, including: a system-on-chip as described in any of the above embodiments, and the system-on-chip includes a processor.

[0118] The internal structure of the computing device may be as Figure 5 As shown, the computing device includes a processor, a memory, a network interface, and an input device connected through a system bus. Among them, the processor of the computing device is used to provide computing and control capabilities. The memory of the computing device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computing device is used to communicate with an external terminal through a network connection. The computer program provides corresponding functions when executed by the processor.

[0119] The processor may include a main processor, and may also include a baseband chip, a modem, etc.

[0120] The memory stores a program for implementing the technical solution of the present invention, and may also store an operating system and other key services. Specifically, the program may include program code, and the program code includes computer operation instructions. More specifically, the memory may include a read-only memory (ROM), other types of static storage devices that can store static information and instructions, a random access memory (RAM), other types of dynamic storage devices that can store information and instructions, a disk memory, a flash memory, etc.

[0121] The processor can be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the solution of the present invention. It can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0122] The input device can include devices for receiving data and information input by the user, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer or a gravity sensor, etc.

[0123] The output device can include devices for allowing information to be output to the user, such as a display screen, a printer, a speaker, etc.

[0124] The communication interface can include devices of any transceiver type for communicating with other devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area network (WLAN), etc.

[0125] The processor executes the program stored in the memory and calls other devices, which can be used to implement each step of any data prefetching method provided in the above embodiments of the present specification.

[0126] The computing device may further include a display component and a voice component. The display component may be a liquid crystal display screen or an electronic ink display screen. The input device of the computing device may be a touch layer covering the display component, or a button, a trackball or a touchpad provided on the housing of the computing device, or an external keyboard, a touchpad or a mouse, etc.

[0127] Those skilled in the art can understand that Figure 5 the structure shown in

[0128] Those of ordinary skill in the art can understand that all or part of the processes in the above-described implementation methods can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the implementation methods of the above various methods. Among them, any reference to a memory, storage, database, or other medium used in the various embodiments provided in this specification can include non-volatile and / or volatile memories. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0129] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.

[0130] The above-described embodiments only represent several embodiments of this specification. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the solutions provided by the embodiments of this specification. It should be noted that for those of ordinary skill in the art, without departing from the concept of this specification, several modifications and improvements can still be made, and these all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification should be subject to the appended claims.

Claims

1. A data prefetching method, characterized in that, Applied to a processor, the data prefetching method includes: In response to the processor accessing target data based on a target instruction, determining a prefetch step size from multiple address differences recorded in a target entry corresponding to the target instruction in a memory access instruction table according to a current value of an out-of-order flag bit; Performing a data prefetch operation based on the prefetch step size and an address of the target data; The target entry includes multiple address differences, and the address difference includes a difference between addresses of data accessed by adjacent access operations in multiple access operations performed based on the target instruction; the current value of the out-of-order flag bit is determined according to the number of prediction errors of a branch predictor in multiple recent data access operations performed by the processor.

2. The method according to claim 1, wherein The determining the prefetch step size from multiple address differences recorded in the target entry corresponding to the target instruction in the memory access instruction table according to the current value of the out-of-order flag bit includes: If the current value of the out-of-order flag bit includes a first target value, determining a first address difference among the multiple address differences of the target entry as the prefetch step size, where the first address difference includes multiple address differences with the same value in the memory access instruction table; If the current value of the out-of-order flag bit includes a second target value, determining a second address difference among the multiple address differences recorded in the target entry as the prefetch step size, where the second address difference includes an address difference in the memory access instruction table that can divide other multiple address differences; The first target value is different from the second target value.

3. The method according to claim 2, wherein If the number of prediction errors of the branch predictor in multiple recent data access operations performed by the processor is greater than or equal to an error threshold, determining the current value of the out-of-order flag bit as the second target value; If the number of prediction errors of the branch predictor in multiple recent data access operations performed by the processor is less than the error threshold, determining the current value of the out-of-order flag bit as the first target value.

4. The method according to claim 2, wherein The processor further includes: a first counter and a second counter, where the first counter is used to record the number of recent access operations performed by the processor, and the second counter is used to record the number of prediction errors of the branch predictor; after the step of responding to the processor accessing target data based on the target instruction, it further includes: Incrementing the count value of the first counter, and when the count value of the first counter is less than a memory access count threshold and the count value of the second counter is greater than or equal to an error count threshold, determining the current value of the out-of-order flag bit as the second target value; When the count value of the first counter is less than the memory access count threshold and the count value of the second counter is less than the error count threshold, determining the current value of the out-of-order flag bit as the first target value.

5. The method according to claim 1, wherein The processor further includes: a first counter and a second counter, where the first counter is used to record the number of recent access operations performed by the processor, and the second counter is used to record the number of prediction errors of the branch predictor; the data prefetching method further includes: In response to a prediction error occurring in the branch predictor, determine whether the count value of the first counter is greater than or equal to the memory access count threshold. If so, clear the count values of the first counter and the second counter; if not, increment the count value of the second counter by one.

6. The method according to claim 5, characterized in that, The "responding to a prediction error occurring in the branch predictor" includes: responding to a notification message from the branch predictor, or the processor performing a wire brushing operation; the notification message is sent when the branch predictor has a prediction error.

7. The method according to claim 1, wherein The memory access instruction table includes multiple entries. Each entry includes the data address last accessed by the instruction, multiple address differences, a write pointer, and the program counter value of the instruction. The program counter value of the instruction is used to indicate the virtual address of the instruction, and the write pointer is used to indicate the field where the new address difference is written; before determining the prefetch step size from the multiple address differences recorded in the memory access instruction table corresponding to the target instruction according to the current value of the out-of-order flag bit after the processor accesses the target data based on the target instruction, further includes: Query the memory access instruction table according to the target instruction. If there is no target entry corresponding to the target instruction in the memory access instruction table, allocate an entry in the memory access instruction table as the target entry for the target instruction; If there is a target entry in the memory access instruction table, subtract the data address last accessed by the target instruction recorded in the target entry from the virtual address of the cache line currently accessed by the target instruction to obtain a new address difference. Write the new address difference into the target entry according to the write pointer, increment the write pointer by one, and update the data address last accessed by the target instruction recorded in the target entry according to the virtual address of the cache line currently accessed by the target instruction.

8. The method according to claim 7, wherein The "allocating an entry in the memory access instruction table as the target entry for the target instruction" includes: Determine a replacement candidate entry among the multiple entries in the memory access instruction table according to a target replacement algorithm; Update the program counter value of the instruction in the replacement candidate entry to the program counter value of the target instruction; Update the data address last accessed by the instruction in the replacement candidate entry to the virtual address of the data last accessed by the target instruction; Update the multiple address differences in the replacement candidate entry to 0 and update the write pointer to 0.

9. A processor, characterized in that, The processor is configured to: In response to the processor accessing target data based on a target instruction, determine a prefetch step size from the multiple address differences recorded in the target entry corresponding to the target instruction in the memory access instruction table according to the current value of the out-of-order flag bit; Perform a data prefetch operation based on the prefetch step size and the address of the target data; The target entry includes multiple of the address differences, and the address difference includes the difference between the addresses of the data accessed in adjacent access operations among multiple access operations performed based on the target instruction; The current value of the out-of-order flag bit is determined according to the number of prediction errors that occur in the branch predictor during multiple data access operations recently performed by the processor.

10. A system on a chip, characterized in that, including: a memory and a processor; wherein, the memory is configured to store data; The processor is configured to: in response to the processor accessing target data based on a target instruction, determine a prefetch step size from among a plurality of address differences recorded in a target entry corresponding to the target instruction in a memory access instruction table according to a current value of an out-of-order flag bit; perform a data prefetch operation on data stored in the memory based on the prefetch step size and an address of the target data; the target entry includes a plurality of the address differences, and the address difference includes a difference between addresses of data accessed in adjacent access operations among multiple access operations performed based on the target instruction; the current value of the out-of-order flag bit is determined according to the number of times of prediction errors of a branch predictor in multiple recent data access operations performed by the processor.

11. A computing device, characterized in that, Comprising: The system-on-chip according to claim 9.

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