Data prefetching method, processor, electronic equipment and computer equipment

Abstract

The invention provides a data prefetching method, a processor, electronic equipment and computer equipment, the method is applied to the processor, and the method comprises the following steps: when a memory access instruction triggers a data prefetching operation, determining a cache hit rate; when the cache hit rate is lower than a set threshold value, a matched table item is retrieved from a mode history table according to the first index information and the second index information; or, when the cache hit rate is not lower than the set threshold value, a matched table item is retrieved from the mode history table according to first index information; wherein the retrieval precision of retrieving the matching table item from the mode history table according to the first index information is higher than the retrieval precision of retrieving the matching table item from the mode history table according to the second index information; and determining a data prefetching address based on the retrieved table item, and reading the data from the memory based on the data prefetching address. According to the scheme, the data prefetching requirements of the processor in different working states can be dynamically met, and the data prefetching performance of the processor is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular, to a data prefetching method, a processor, an electronic device, and a computer device. Background Art

[0002] Prefetching technology reduces memory access latency and improves the overall system performance by predicting the data that the processor is about to access and loading the data into the cache in advance. Among them, footprint prefetching is a relatively common prefetching technology. Footprint prefetching is a prefetching method based on footprint regions. By dividing the memory into fixed-size footprint regions (Regions) and recording the accessed memory blocks in each Region, the access pattern of the Region is represented by a bit vector (i.e., footprint). When accessing an adjacent or new Region, the footprint prefetcher predicts the memory blocks that may be accessed according to the previously recorded footprint and preloads this data in advance to reduce the cache miss and memory access latency of the processor.

[0003] During the execution of footprint prefetching, the footprint prefetcher in the processor retrieves the matching historical access pattern from the pre-constructed pattern history table according to information such as the instruction PC (Program Counter), access address offset Offset, and address Address of the current memory access instruction, and determines the data prefetch address based on the retrieval result. Since the load and memory access requirements of the processor are different at different times, the above footprint prefetching method is difficult to adapt to the change of the data prefetching requirements of the processor in different states. Summary of the Invention

[0004] In view of the above technical problems, this application proposes a data prefetching method, a processor, an electronic device, and a computer device, which can dynamically match the range and accuracy of data prefetching of the processor with the working state of the processor, can dynamically meet the data prefetching requirements of the processor in different working states, and avoid the influence of a single fixed data prefetching mode on the data prefetching performance of the processor in a dynamically changing working state.

[0005] A first aspect of this application proposes a data prefetching method, which is applied to a processor, and the method includes:

[0006] Determine the cache hit rate when a memory access instruction triggers a data prefetch operation;

[0007] When the cache hit rate is lower than a set threshold, retrieve the table entries that match the first index information and the table entries that match the second index information from the pattern history table according to the first index information and the second index information; or, when the cache hit rate is not lower than the set threshold, retrieve the table entries that match the first index information from the pattern history table according to the first index information;

[0008] Among them, the table entries in the pattern history table are used to record the historical access records of the memory area; the first index information and the second index information include the information of the memory access instruction, and the retrieval accuracy of retrieving the matching table entries from the pattern history table according to the first index information is higher than the retrieval accuracy of retrieving the matching table entries from the pattern history table according to the second index information;

[0009] Determine the data prefetch address based on the retrieved table entries, and read data from the memory based on the data prefetch address.

[0010] In some implementation manners, the first index information includes the program counter value PC and the address Address of the memory access instruction;

[0011] The second index information includes the program counter value PC and the address offset Offset of the memory access instruction.

[0012] In some implementation manners, when the cache hit rate is lower than the set threshold, the determining the data prefetch address based on the retrieved table entries includes:

[0013] When the cache hit rate is lower than the first threshold, select a first number of first table entries and a second number of second table entries from the retrieved table entries as the target table entries; or, when the cache hit rate is not lower than the first threshold and lower than the set threshold, select a third number of first table entries and a fourth number of second table entries from the retrieved table entries as the target table entries;

[0014] Among them, the first threshold is less than the set threshold; the value of dividing the second number by the first number is greater than the value of dividing the fourth number by the third number; the first table entries include the table entries that match the first index information, and the second table entries include the table entries that match the second index information;

[0015] Determine the data prefetch address based on the target table entries.

[0016] In some implementation manners, the determining the data prefetch address based on the retrieved table entries includes:

[0017] Determine the target memory area accessed by the memory access instruction from the retrieved table entry based on the virtual address of the memory access instruction;

[0018] Based on the historical access record of the target memory area, determine the memory blocks that have been historically accessed in the target memory area as prefetch memory blocks;

[0019] Determine the data prefetch address based on the base address of the memory access instruction and the position of the prefetch memory block in the target memory area.

[0020] In some implementations, the historical access records of each memory area are represented by vectors in the retrieved table entry;

[0021] Determine the target memory area accessed by the memory access instruction from the retrieved table entry based on the virtual address of the memory access instruction, including:

[0022] Based on the Offset information in the virtual address of the memory access instruction, locate the target memory area accessed by the memory access instruction from the vector.

[0023] In some implementations, the pattern history table is constructed through the following processing:

[0024] During the memory access process of the processor, record the memory access footprint of the processor in the form of vectors through a training table to obtain training table entries; where one instruction corresponds to one training table entry, and in this training table entry, the memory access footprint vector corresponding to this instruction is recorded;

[0025] When any table entry in the training table is replaced out of the training table, store this replacement entry in the pattern history table.

[0026] In some implementations, before storing this replacement entry in the pattern history table, the method further includes:

[0027] Judge whether the number of vector bits representing the accessed ones in the memory access footprint vector in this replacement entry is greater than 1;

[0028] In the case where the number of vector bits representing the accessed ones in the memory access footprint vector in this replacement entry is greater than 1, store this replacement entry in the pattern history table.

[0029] In some implementations, storing this replacement entry in the pattern history table includes:

[0030] Use the instruction PC corresponding to this replacement entry to retrieve the pattern history table entry corresponding to this instruction PC from the pattern history table;

[0031] If a pattern history table entry corresponding to the instruction PC is retrieved from the pattern history table, the transformed memory access footprint vector is stored in the target sub-entry in the pattern history table entry corresponding to the instruction PC, and the instruction address Address corresponding to the replacement entry is stored as a label in the target sub-entry; wherein, the target sub-entry is the sub-entry corresponding to the address offset Offset corresponding to the replacement entry in the pattern history table entry corresponding to the instruction PC.

[0032] If a pattern history table entry corresponding to the instruction PC is not retrieved from the pattern history table, a pattern history table entry is allocated for the replacement entry in the pattern history table, and the replacement entry is written into the allocated pattern history table entry.

[0033] In some implementation manners, storing the transformed memory access footprint vector in the target sub-entry in the pattern history table entry corresponding to the instruction PC includes:

[0034] When a memory access footprint vector has already been stored in the target sub-entry in the pattern history table entry corresponding to the instruction PC, the transformed memory access footprint vector is superimposed with the memory access footprint vector in the target sub-entry.

[0035] In some implementation manners, allocating a pattern history table entry for the replacement entry in the pattern history table includes:

[0036] Determine whether there is an invalid pattern history table entry in the pattern history table;

[0037] If there is an invalid pattern history table entry, the invalid pattern history table entry is allocated to the replacement entry;

[0038] If there is no invalid pattern history table entry, the pattern history table entry with the lowest access frequency is allocated to the replacement entry.

[0039] A second aspect of this application proposes a processor, which is configured to execute the above data prefetch method.

[0040] A third aspect of this application proposes an electronic device, including a processor and a memory;

[0041] The memory is connected to the processor and is used for storing programs;

[0042] The processor is used to implement the above data prefetch method by running the programs in the memory.

[0043] A fourth aspect of this application proposes a computer device, including the above processor.

[0044] The data prefetching method proposed in this application selects index information with different retrieval precisions from the pattern history table according to the cache hit rate of the processor to retrieve pattern history table entries, and then performs data prefetching based on the retrieved pattern history table. The above solution realizes different-precision pattern history table retrievals through different index information when the processor is in different memory access working states, so that the range and precision of data prefetching can be dynamically matched with the working state of the processor, and can dynamically meet the data prefetching requirements of the processor in different working states, overcoming the disadvantages of fuzzy prefetching and exact prefetching themselves, and avoiding the impact of a single fixed data prefetching mode on the data prefetching performance of the processor in a dynamically changing working state. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0046] Figure 1 It is a schematic diagram of a partial structure inside a processor provided by an embodiment of the present application.

[0047] Figure 2 It is a schematic flowchart of a data prefetching method provided by an embodiment of the present application.

[0048] Figure 3 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0049] The technical solution of the embodiment of the present application is applicable to the application scenario where the processor prefetches data from the memory, especially applicable to the processor footprint prefetching application scenario. By adopting the technical solution of the embodiment of the present application, the processor can flexibly adjust the data prefetching method in different working states, so that the data prefetching operation can adapt to the change of the data prefetching requirements of the processor in different working states, and improve the data prefetching efficiency.

[0050] With the development of computer architecture, the speed and performance of processors have been continuously improved, but the memory access speed is relatively slow, becoming a bottleneck of system performance. To solve this problem, hardware prefetching technology has been widely applied. The prefetching technology reduces the memory access latency and improves the overall system performance by predicting the data that the processor is about to access and loading the data into the cache in advance.

[0051] Current hardware prefetching techniques are mainly divided into two categories: temporal prefetching and spatial prefetching.

[0052] Temporal prefetching takes advantage of the temporal locality of data access. It assumes that data accessed within a certain time period is likely to be accessed again in the next time period. By preloading this data that is about to be accessed again, temporal prefetching reduces memory access latency.

[0053] Spatial prefetching is based on the spatial locality of data access. It assumes that after accessing a certain memory address, its adjacent addresses are also likely to be accessed. Therefore, it preloads the data blocks of these adjacent addresses. Spatial prefetching assumes that the memory access pattern is repetitive in space. For example, if a series of addresses are accessed near X during a certain access, a similar sequence of addresses may be accessed near Y. This kind of prefetching utilizes the repeatability of data structures, that is, so-called pattern locality.

[0054] In practical applications, spatial prefetching techniques are widely adopted. The most common ones are sequential prefetching, stride prefetching, and footprint prefetching.

[0055] Sequential prefetching: Assume that memory access is sequential, so adjacent memory blocks are prefetched.

[0056] Stride prefetching: Assume that memory access is in a fixed stride, so the next memory block calculated by the fixed stride is prefetched.

[0057] Footprint prefetching: It is a Region-based prefetching method. By dividing the memory into fixed-size footprint regions (Regions) and recording the memory blocks accessed within each Region, a bit vector (i.e., footprint) is used to represent the access pattern of the Region. When accessing an adjacent or new Region, the footprint prefetcher will predict the memory blocks that may be accessed based on the previously recorded footprint and preload this data in advance to reduce the cache miss and memory access latency of the processor.

[0058] The Bingo prefetcher is a commonly used footprint prefetcher, and its working process is as follows:

[0059] A) Memory access monitoring: When the processor performs a memory access operation, the Bingo prefetcher monitors these memory accesses in real time. It records the PC (Program Counter) of each access and the accessed memory address through a Filter table (FT). Each time a new memory region is accessed, this region is stored in the FT.

[0060] B) Accumulation table recording: If subsequent accesses reach other unaccessed data blocks in this region, the Bingo prefetcher transfers the information of this region from the FT to the Accumulation table (AT). The access information of this region is recorded in the AT and represented in the form of a bit-vector: 1 indicates accessed, and 0 indicates not accessed.

[0061] C) Training completion: The training process is completed when one of the following two situations occurs: the entry corresponding to a region in the AT is replaced, or the data block of this region is replaced from the cache. The spatial access vector (i.e., footprint) after training completion is associated with the trigger event of this spatial region and stored in the Pattern History Table (PHT) in the form of <trigger event, access footprint>.

[0062] D) Trigger prefetch: When a specific condition is met (such as accessing a new Region or cache miss), the Bingo prefetcher uses the PC and Offset of the current memory access instruction, or the PC and Address of the current memory access instruction as an index to search for the previously recorded similar access patterns in the PHT. When the PC and Address index is successful, it is considered an exact prefetch, and the prefetch address is generated using the PHT entry indexed; when the PC and Address index fails, but the PC and Offset index is successful, it is considered a fuzzy prefetch, and the prefetch address is generated using the PHT entry indexed.

[0063] Although fuzzy prefetch and exact prefetch have their own advantages in different scenarios, they both have obvious deficiencies:

[0064] A) Deficiencies of fuzzy prefetch:

[0065] Cache pollution: Fuzzy prefetch tends to perform extensive prefetching under uncertain access patterns, which easily leads to a large number of invalid prefetch requests, increasing the cache burden, and then polluting the cache and affecting system performance.

[0066] Bandwidth waste: Due to the wide coverage of fuzzy prefetch but insufficient accuracy, it may prefetch a large amount of unnecessary data, consuming the limited memory bandwidth and reducing system efficiency.

[0067] B) Deficiencies of exact prefetch:

[0068] Limited coverage: Precise prefetching depends on accurate recording of past access patterns and is applicable to scenarios with stable and regular patterns. However, in cases where memory access patterns are complex, variable, or irregular, precise prefetching is difficult to work effectively.

[0069] Poor flexibility: Precise prefetching has poor adaptability to changing memory access patterns and cannot respond quickly to new access patterns, resulting in reduced prefetching efficiency.

[0070] It can be seen that the loads and memory access requirements of the processor are different at different times, and the existing footprint prefetching methods are difficult to adapt to the changes in data prefetching requirements of the processor in different states.

[0071] To address the above technical problems, the present application proposes a new data prefetching scheme that enables the processor to flexibly adjust the data prefetching method in different working states, so that the data prefetching operation can adapt to the changes in data prefetching requirements of the processor in different working states and improve the data prefetching efficiency.

[0072] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0073] The embodiment of the present application proposes a data prefetching method, which can be executed by a prefetcher in a processor.

[0074] Figure 1 A partial structural schematic diagram inside the processor is shown. Refer to Figure 1 It can be seen that the prefetcher (PF) is arranged between the load store unit (LSU) and the memory management unit (MMU). The LSU can prefetch data from the MMU through the prefetcher PF, or the LSU can also directly send a data request to the MMU.

[0075] The MMU may include a cache, and the MMU can perform access to the memory. Thus, when the MMU receives a data request from the LSU or PF, it can obtain data from the cache and feedback it to the LSU or PF (the PF then feeds the data back to the LSU), or the MMU can also directly load data from the memory into the cache or read data from the memory and feedback it to the PF or LSU.

[0076] The data prefetching method proposed in the embodiments of this application is mainly applied between the processor and the memory system to improve the cache hit rate of the processor and reduce the memory access latency. The data prefetching method proposed in the embodiments of this application can be applied to the following several typical application scenarios:

[0077] High-performance computing: In application scenarios that require a large amount of memory access, such as scientific computing, image processing, and big data analysis, the data prefetching method in the embodiments of this application can significantly improve the efficiency of memory access and reduce the performance bottleneck caused by cache misses during the computing process.

[0078] Embedded systems: In embedded systems with limited resources, applying the data prefetching method in the embodiments of this application can optimize the utilization rate of the cache, reduce the system power consumption, and improve the overall performance.

[0079] Servers and data centers: In the high-load environment of servers and data centers, applying the data prefetching method in the embodiments of this application can reduce the memory access latency and improve the system response speed and throughput.

[0080] As the basis for prefetching memory data, in the embodiments of this application, the prefetcher monitors the memory access process of the processor in real time, records and summarizes the memory access footprint, and obtains the pattern history table.

[0081] During the memory access process of the processor, the prefetcher records the memory access footprint of the processor in the form of a vector through the training table to obtain a training table entry; among them, one memory area corresponds to one training table entry, and in this training table entry, the memory access footprint vector of the processor for this memory area is recorded.

[0082] Specifically, when the prefetcher detects that the processor performs a memory access, the training table (Traintable) in the prefetcher will detect the current memory access pattern in real time, that is, detect the PC, Offset, and Address of the current memory access instruction, determine the 1K memory area accessed and the specific memory block accessed, and record to obtain the memory access pattern corresponding to this 1K memory area.

[0083] Then, the prefetcher retrieves a matching table entry from the training table based on the address of the 1K memory area recorded in this memory access pattern. If the memory access pattern matches an entry in the training table, the footprint of the 1k space corresponding to this memory access pattern is marked in this table entry and recorded in the form of a bit-vector. In the embodiment of the present application, the 1k memory space is divided into 16 cachelines of 64B, and each cacheline corresponds to one bit of the bit-vector. If the value of a bit in the bit-vector is 1, it means that the cacheline corresponding to this bit has been accessed. If the value of a bit in the bit-vector is 0, it means that the cacheline corresponding to this bit has not been accessed.

[0084] If the memory access pattern does not match an entry in the training table, the 1K memory space and the specific memory block being accessed are determined according to the PC, Offset, and Address of the current memory access instruction, and a new training table entry is allocated. The PC and Offset of this training table entry are the PC and Offset of this memory access pattern, the Address of this training table entry is the base address of this 1K memory space, and the memory access footprint vector in this training table entry is the vector of the access footprint to this 1K memory space recorded in this memory access pattern. That is to say, for a 1K memory space, the PC and Offset of the instruction that first accesses this memory space are used as the PC and Offset of the training table entry for this 1K memory space. On this basis, the access footprint of the subsequent accesses to this 1K memory space is updated, but only the access footprint of the subsequent access instructions to this 1K space to this 1K space is updated to the memory access footprint vector of the training table entry for this 1K memory space, and the PC and Offset of this training table entry are not updated.

[0085] When any entry in the above training table is replaced out of the training table, this replacement entry is stored in the Pattern History Table (PHT) for further summarization and training.

[0086] It can be seen that in the above training table and pattern history table, a combination of PC + Offset corresponds to a memory access footprint vector bit-vector, which is used to record the memory access footprint to a certain memory space.

[0087] In some other embodiments, before storing this replacement entry in the pattern history table PHT, the prefetcher will determine whether to store it in the PHT for further training according to the information in this replacement entry.

[0088] First, the prefetcher determines whether the number of vector bits representing the accessed vector bits in the memory access footprint vector bit-vector in the replacement entry is greater than 1, that is, it determines whether the number of bits set to 1 in the bit-vector of the replacement entry is greater than 1.

[0089] When the number of vector bits representing the accessed vector bits in the memory access footprint vector in the replacement entry is greater than 1, store the replacement entry in the pattern history table. If the number of vector bits representing the accessed vector bits in the memory access footprint vector in the replacement entry is not greater than 1, discard the replacement entry.

[0090] If the number of access times of the accessed area recorded in the replacement entry is greater than 1, it indicates that the accessed area has a certain spatial locality and its access pattern is worthy of further training. Therefore, store the replacement entry in the PHT. If the number of access times of the accessed area recorded in the replacement entry is not greater than 1, it indicates that the accessed area does not have spatial locality and is not suitable for further training the footprint prefetching strategy. Therefore, it can be discarded.

[0091] In some other embodiments, it is also disclosed that before storing the above replacement table in the PHT, the memory access footprint vector bit-vector in the replacement table is further extended.

[0092] As introduced in the above embodiments, the length of the memory access footprint vector bit-vector is 16 bits, and each bit corresponds to a memory block in a memory area. This bit-vector is used to record the access history of each memory block in the memory area by the processor.

[0093] To reduce the storage overhead, the embodiments of the present application expand the memory access footprint vector bit-vector and store the expanded memory access footprint vector bit-vector in a stacked manner in the PHT, so as to achieve the purpose of saving storage space.

[0094] Specifically, the prefetcher uses the access address offset Offset of the training entry as the central position corresponding to the memory access footprint vector stored in the training entry, and expands the number of vector bits on both sides of the central position in the memory access footprint vector to N - 1 bits respectively, where N is the number of memory blocks included in the specific-sized memory area.

[0095] In the embodiments of the present application, a 1K memory area is divided into 16 cachelines, and the above N is 16.

[0096] That is to say, the prefetcher determines the value of the access address offset Offset in the training entry, and then determines the position corresponding to the Offset in the memory access footprint vector of the training entry according to the value of the Offset as the central position.

[0097] Then, starting from this central position, the number of vector bits on both the left and right sides of the memory access footprint vector is expanded to 15 bits (vector bits are supplemented in the high or low positions, and the values of the supplemented vector bits are set to 0), and the expanded 15-bit vectors are concatenated. Further, the value of each vector bit in the expanded memory access footprint vector is expanded to 2 bits.

[0098] For example, assuming that the Offset of the training entry is 9, the ninth vector position in the memory access footprint vector of the training entry is used as the central position, then the number of vector bits on the left side of the central position is expanded to 15 bits, the number of vector bits on the right side of the central position is expanded to 15 bits, the two expanded 15-bit vectors are concatenated, and the value of each vector bit is expanded to 2 bits.

[0099] After the above processing, the memory access footprint vectors corresponding to different Offsets of the same PC can be stored in a superimposed manner, instead of storing the memory access footprint vectors corresponding to each Offset of the same PC separately, thus saving storage space.

[0100] Moreover, the above method of recording the memory access footprint corresponding to an Offset records the access footprints of each memory block at the relative position with respect to the Offset, rather than the access footprints of the memory blocks at the absolute position. In this way, when superimposing and storing the memory access footprints of different Offsets, the relative positions can be guaranteed to be unified, facilitating the execution of the superimposing operation.

[0101] Based on the above bit-vector storage method of the memory access footprint vector, when storing the above replacement item into the PHT, first, according to the above vector expansion method, the memory access footprint vector in the replacement item is expanded into a vector with a length of 30 bits (each bit is 2 bits) to obtain the transformed memory access footprint vector. Then, the transformed memory access footprint vector can be stored in the PHT. For example, the transformed memory access footprint vector can be superimposed with the memory access footprint vector corresponding to the same PC stored in the PHT, or a table entry can be allocated separately for the transformed memory access footprint vector to store the transformed memory access footprint vector.

[0102] In some other embodiments, before storing the transformed memory access footprint vector into the PHT, first use the instruction PC corresponding to the replacement item to retrieve the existing entry corresponding to this instruction PC from the PHT, that is, retrieve the pattern history entry with the same PC as the replacement item from the PHT.

[0103] If an existing entry corresponding to this instruction PC is retrieved from the PHT, that is, a pattern history entry with the same PC as the replacement item is retrieved, then store the bit-vector of the transformed memory access footprint vector of the replacement item into the target sub-entry in this existing entry, and store the instruction address Address corresponding to the replacement item as a label into the target sub-entry; wherein, the target sub-entry is the sub-entry corresponding to the address offset Offset of the replacement item in the existing entry.

[0104] In the embodiments of the present application, one PC in the PHT corresponds to one pattern history entry. In the pattern history entry corresponding to each PC, there are at most 16 sub-entries (one PC corresponds to at most 16 Offsets, and each sub-entry corresponds to one Offset).

[0105] Using the PC of the above replacement item as the retrieval condition, retrieve the pattern history entry corresponding to the PC of the above replacement item from the PHT. In the case where the pattern history entry corresponding to the PC of the above replacement item is retrieved, further retrieve the sub-entry corresponding to the Offset of the above replacement item from this pattern history entry corresponding to the PC of the above replacement item. If the sub-entry corresponding to the Offset of the above replacement item is retrieved, then store the bit-vector of the transformed memory access footprint vector of the replacement item into this sub-entry, and store the instruction address Address corresponding to the replacement item as a label into this sub-entry.

[0106] If the sub-entry corresponding to the Offset of the above replacement item is not retrieved from this pattern history entry corresponding to the PC of the above replacement item, then a sub-entry corresponding to the Offset of the above replacement item can be added to this pattern history entry corresponding to the PC of the above replacement item, and then store the bit-vector of the transformed memory access footprint vector of the replacement item into this added sub-entry, and store the instruction address Address corresponding to the replacement item as a label into this added sub-entry.

[0107] When storing the transformed memory access footprint vector (bit-vector) of the above replacement item into the above target sub-item, if there is already a memory access footprint vector stored in the above target sub-item, the transformed memory access footprint vector of the above replacement item is superimposed on the memory access footprint vector already stored in the target sub-item (each vector bit consists of 2 bits, and 1 is added for repeated access). If the above target sub-item is empty, the transformed memory access footprint vector of the above replacement item is directly stored in the target sub-item.

[0108] If the existing entry corresponding to the instruction PC of the replacement item is not retrieved from the PHT, that is, the pattern history entry with the same PC as the replacement item is not retrieved, a pattern history entry is allocated for the replacement item in the PHT, and the replacement item is written into the pattern history entry.

[0109] In some embodiments, when allocating a pattern history entry for the replacement item in the PHT, first determine whether there is an invalid pattern history entry in the PHT, that is, search for an invalid pattern history entry in the PHT. If there is an invalid pattern history entry in the PHT, the first found invalid pattern history entry is allocated to the replacement item.

[0110] If there is no invalid pattern history entry, according to the Least Recently Used (LRU) algorithm, the pattern history entry with the lowest access frequency, that is, the least recently used, is allocated to the replacement item.

[0111] After allocating a pattern history entry for the replacement item, the replacement item is written into the allocated pattern history entry. In this pattern history entry, the information of the replacement item is stored in the form of <trigger event, access footprint>, specifically <PC|Offset|Address, Region>, where Region is the memory access footprint vector corresponding to the trigger event represented by PC|Offset|Address.

[0112] Through the above processing, the prefetcher establishes and accumulates a series of footprint prefetch training data in the PHT. Based on these training data, data prefetch operations can be performed during subsequent processor memory accesses.

[0113] Based on the above pattern history table, an embodiment of the present application proposes a data prefetch method. Refer to Figure 2 As shown, the method includes:

[0114] S101. Determine the cache hit rate when a memory access instruction triggers a data prefetch operation.

[0115] Specifically, the above-mentioned memory access instruction refers to the current memory access instruction of the processor, which includes the PC, Offset, and Address information of the instruction.

[0116] The current memory access instruction triggers a data prefetch operation. It can be that the memory access address of the current memory access instruction falls into a memory area that has not been accessed before. The system regards this as a new memory access pattern, which usually means that the processor is accessing a new data area, and the previous access pattern may no longer be applicable. Therefore, the system needs to adjust and predict according to the new access pattern.

[0117] Alternatively, the current memory access instruction triggers a data prefetch operation. It can also be when the processor tries to access data that does not exist in the cache through the current memory access instruction, that is, when the current memory access instruction causes a cache miss. At this time, the system will trigger a prefetch operation to preload data blocks that may be needed in the future.

[0118] When the current memory access instruction of the processor triggers a data prefetch operation, the prefetcher calculates the current cache hit rate of the processor, that is, calculates the probability that the processor hits the required data from the cache within a certain period of time before the current moment. Suppose the processor requests data from the cache 100 times, and 60 of them hit the required data from the cache, then the cache hit rate is 60%.

[0119] S102. In the case where the cache hit rate is lower than the set threshold, retrieve the table entry that matches the first index information and the table entry that matches the second index information from the pattern history table according to the first index information and the second index information; or, in the case where the cache hit rate is not lower than the set threshold, retrieve the table entry that matches the first index information from the pattern history table according to the first index information.

[0120] Among them, the above-mentioned pattern history table is the pattern history table constructed through the above embodiments, and the table entries in this pattern history table are used to record the historical access records of memory areas.

[0121] The above-mentioned first index information and second index information are composed of the information of the above-mentioned memory access instruction. For example, the PC, Offset, and Address of the memory access instruction can be combined into index information. The first index information and the second index information are used to retrieve the pattern history table entries that match the instruction information contained in the first index information and the second index information from the above-mentioned pattern history table.

[0122] In an embodiment of the present application, information based on a memory access instruction forms first index information and second index information with different retrieval precisions. Among them, the retrieval precision of retrieving a matching entry from the pattern history table according to the first index information is higher than that of retrieving a matching entry from the pattern history table according to the second index information.

[0123] In some embodiments, the above-mentioned first index information may be composed of PC + Address of the memory access instruction; the above-mentioned second index information may be composed of PC + Offset of the memory access instruction, or in other embodiments, the above-mentioned second index information may also only include the PC of the memory access instruction.

[0124] When the cache hit rate of the processor is lower than a set threshold, the prefetcher retrieves an entry matching the first index information and an entry matching the second index information from the pattern history table according to the first index information and the second index information respectively. In this case, since the cache hit rate of the processor is low, the prefetcher needs to prefetch more data to improve the cache hit rate of the processor. Therefore, the prefetcher uses the first index information and the second index information simultaneously to perform pattern history table retrieval. Since the retrieval precision of the first index information is high, a pattern history table entry that more precisely matches the current memory access instruction can be retrieved. And since the retrieval precision of the second index information is low, more pattern history table entries that match the current memory access instruction can be retrieved, improving the cache hit rate of the processor.

[0125] When the cache hit rate of the processor is not lower than the set threshold, the prefetcher retrieves a pattern history table entry matching the first index information from the pattern history table according to the first index information. In this case, since the cache hit rate of the processor is high, there is no need to prefetch too much data, and only the data that the processor may need needs to be precisely prefetched. Therefore, the prefetcher retrieves the pattern history table entry from the pattern history table through the first index information, and a pattern history table entry that more precisely matches the current memory access instruction can be retrieved, thereby reducing the memory access bandwidth pressure and avoiding cache pollution, which is beneficial to improving the processor performance.

[0126] S103. Determine a data prefetch address based on the retrieved entry, and read data from the memory based on the data prefetch address.

[0127] Specifically, after the prefetcher retrieves a pattern history table entry from the pattern history table, it determines a data prefetch address based on the retrieved pattern history table entry. This data prefetch address is the address of the accessed memory block recorded in the retrieved pattern history table entry.

[0128] For example, the prefetcher determines the location of the memory block accessed in a certain memory space through the retrieved table entry, and then, by adding the base address of the memory space accessed by the current memory access instruction to the location of the above-mentioned accessed memory block, the data prefetch address in the memory space accessed by the current memory access instruction can be obtained.

[0129] Then, the prefetcher reads data from the memory according to the determined data prefetch address, that is, prefetches the data in the memory block of the memory space accessed by the current memory access instruction.

[0130] As can be seen from the above introduction, the data prefetch method proposed in the embodiment of the present application retrieves the pattern history table entry from the pattern history table according to the cache hit rate of the processor to select index information with different retrieval precisions, and then performs data prefetch according to the retrieved pattern history table. The above solution realizes different-precision pattern history table retrievals through different index information when the processor is in different memory access working states, so that the range and precision of data prefetch can be dynamically matched with the working state of the processor, can dynamically meet the data prefetch requirements of the processor in different working states, overcomes the disadvantages of fuzzy prefetch and exact prefetch itself, and avoids the influence of a single fixed data prefetch mode on the data prefetch performance of the processor in a dynamically changing working state.

[0131] In another embodiment, the ratio of retrieving the pattern history table entry from the pattern history table through the first index information and through the second index information can also be flexibly adjusted according to the cache hit rate of the processor.

[0132] For example, on the basis of setting a threshold for the cache hit rate, a first threshold is also set, and the first threshold is less than the above-mentioned set threshold.

[0133] When the cache hit rate of the processor is lower than the first threshold, retrieve the table entries matching the first index information and the table entries matching the second index information from the pattern history table according to the first index information and the second index information, and select, from the retrieved table entries, a first number of first table entries and a second number of second table entries as the target table entries. Among them, the first table entry is the pattern history table entry retrieved from the pattern history table with the first index information as the retrieval condition, that is, the table entry obtained by exact retrieval, and the second table entry is the pattern history table entry retrieved from the pattern history table with the second index information as the retrieval condition, that is, the table entry obtained by fuzzy retrieval.

[0134] When the cache hit rate of the processor is not lower than the above-mentioned first threshold and lower than the above-mentioned set threshold, retrieve the table entries matching the first index information and the table entries matching the second index information from the pattern history table according to the first index information and the second index information, and select a third number of first table entries and a fourth number of second table entries from the retrieved table entries as the target table entries.

[0135] Finally, determine the data prefetch address based on the target table entries retrieved above.

[0136] Moreover, in this embodiment, the value of the second number divided by the first number is greater than the value of the fourth number divided by the third number, that is, the proportion of the table entries obtained by fuzzy retrieval among the target table entries for determining the data prefetch address increases as the cache hit rate of the processor decreases and decreases as the cache hit rate of the processor increases. In this way, the proportion of fuzzy prefetching and exact prefetching can be flexibly adjusted according to the change of the memory access working state of the processor, and the memory access performance of the processor can be improved more dynamically and in detail.

[0137] In another embodiment, when the prefetcher determines the data prefetch address based on the table entries retrieved from the pattern history table, it is determined through the following processing steps A1 - A3:

[0138] A1. Based on the virtual address of the memory access instruction, determine the target memory area accessed by the memory access instruction from the retrieved table entries.

[0139] Specifically, according to bit[9:6] of the virtual address of the memory access instruction, the Offset of the memory access instruction can be determined, and based on this Offset, the memory area corresponding to the corresponding pattern history table entry is determined as the target memory area. That is, the memory area recorded in the pattern history table entry corresponding to this Offset is the target memory area accessed by the memory access instruction.

[0140] In another embodiment, the historical access records corresponding to each memory area corresponding to the same PC in the PHT are stored after being extended and superimposed, so that the historical access records of each memory area are represented by a 30-bit vector (each bit is 2 bits).

[0141] In this case, based on the Offset information in the virtual address of the memory access instruction, the target memory area accessed by the memory access instruction is located from this vector.

[0142] Specifically, after retrieving the pattern history table entry corresponding to the PC of the memory access instruction from the PHT, the 30-bit memory access footprint vector in the pattern history table entry is taken out.

[0143] Then, the position where the Offset of the memory access instruction is located is mapped to the 30-bit memory access footprint vector. For example, if the current offset is 9, then with the 9th bit of the 30-bit memory access footprint vector as the center, 6 bits are taken to the left (reaching the boundary bit15 after taking 6 bits to the left from the 9th bit, a total of 16 bits from bit15-bit0, bit-vector) and 9 bits are taken to the right to form a prefetch region, and this prefetch region is the target memory region.

[0144] In the embodiment of the present application, for different values of the Offset, rules for extracting the prefetch region in the 30-bit memory access footprint vector are respectively specified. Therefore, for any Offset, the range of the prefetch region can be extracted from the corresponding 30-bit memory access footprint vector according to the preset memory region selection rule corresponding to that Offset.

[0145] In addition, based on the memory region selection rules set for each Offset, multiple prefetch regions can be determined from the 30-bit memory access footprint vector. For each prefetch region, it can be used as a target memory region. For example, for Offset = 0, vector bit ranges of 0 to 15, 9 to 24, and 16 to 30 can be selected from the 30-bit memory access footprint vector to form 3 different prefetch regions, and these 3 prefetch regions can all be used as target memory regions for subsequent determination of data prefetch addresses. This can make data prefetch not limited to the footprint of a certain memory region, but can perform data prefetch based on the access footprints of adjacent multiple memory regions.

[0146] A2. Based on the historical access records of the target memory region, determine the memory blocks in the target memory region that have been historically accessed as prefetch memory blocks.

[0147] Specifically, from the pattern history table entry corresponding to the target memory region, determine the memory access footprint vector bit-vector of the processor for the target memory region. The memory blocks corresponding to the bits with a value of "1" in this vector are the memory blocks in the target memory region that have been historically accessed, and these memory blocks are determined as prefetch memory blocks.

[0148] A3. Based on the base address of the memory access instruction and the position of the prefetch memory block in the target memory region, determine the data prefetch address.

[0149] Specifically, bit[xx:10] of the virtual address of the above memory access instruction is the base address of the memory access instruction. Using this base address and adding the position of the prefetch memory block in the target memory area, the data prefetch address can be calculated.

[0150] For example, assume that the vector bit values corresponding to the 1st, 5th, 6th, and 7th memory blocks in the above target memory area are 1. Then the data prefetch addresses are the four addresses: {va[xx:10] (base address), 4'b0001}, {va[xx:10], 4'b0101}, {va[xx:10], 4'b0110}, and {va[xx:10], 4'b0111}.

[0151] When there are multiple target memory areas determined through the above processing, for each target memory area, the corresponding data prefetch address can be determined respectively based on the base address of the memory area accessed by the memory access instruction and the memory access footprint vector of this target memory area.

[0152] Corresponding to the above data prefetch method, an embodiment of the present application also proposes a processor, which is configured to execute the data prefetch method introduced in any of the above embodiments. Specifically, the structure of this processor can be seen in Figure 1 As shown, when this processor executes the data prefetch method introduced in any of the above embodiments, it can be specifically executed by the prefetcher in this processor.

[0153] Based on the above processor, an embodiment of the present application also proposes a computer device, which includes the above processor.

[0154] Exemplarily, this computer device can specifically be a personal computer, a server, a work computer, a workstation, a smart terminal, a smart wearable device, etc.

[0155] In the embodiments of the present application, the processor is a circuit with signal processing capabilities. In one implementation, the processor can be a circuit with instruction reading and running capabilities, such as a CPU, a microprocessor, a GPU, or a DSP, etc.; in another implementation, the processor can implement certain functions through the logical relationship of hardware circuits, and the logical relationship of this hardware circuit is fixed or can be reconstructed. For example, the processor is a hardware circuit implemented by an ASIC or a PLD, such as an FPGA, etc. In addition, it can also be a hardware circuit designed for artificial intelligence, which can be understood as a type of ASIC, such as an NPU, a TPU, a DPU, etc.

[0156] Another embodiment of the present application also proposes an electronic device, see Figure 3 As shown, this device includes:

[0157] A memory 200 and a processor 210;

[0158] Among them, the memory 200 is connected to the processor 210 and is used for storing programs.

[0159] The processor 210 is used to implement the data prefetching method disclosed in any of the above embodiments by running the programs stored in the memory 200.

[0160] Specifically, the above electronic device may further include: a bus, a communication interface 220, an input device 230, and an output device 240.

[0161] The processor 210, the memory 200, the communication interface 220, the input device 230, and the output device 240 are interconnected through the bus. Among them:

[0162] The bus may include a path for transmitting information between various components of the computer system.

[0163] The processor 210 may be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present invention. It may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0164] The processor 210 may include a main processor and may also include a baseband chip, a modem, etc.

[0165] The memory 200 stores programs for implementing the technical solution of the present invention and may also store an operating system and other critical services. Specifically, the program may include program code, and the program code includes computer operation instructions. More specifically, the memory 200 may include a read-only memory (ROM), other types of static storage devices that can store static information and instructions, a random access memory (RAM), other types of dynamic storage devices that can store information and instructions, a disk memory, a flash memory, etc.

[0166] The input device 230 may include a device for receiving data and information input by a user, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer, or a gravity sensor, etc.

[0167] The output device 240 may include a device for allowing information to be output to the user, such as a display screen, a printer, a speaker, etc.

[0168] The communication interface 220 may include a device such as any transceiver for communicating with other devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area network (WLAN), etc.

[0169] The processor 210 executes the program stored in the memory 200 and calls other devices, which can be used to implement each step of any one of the data prefetching methods provided in the foregoing embodiments of the present application.

[0170] An embodiment of the present application also proposes a chip, which includes a processor and a data interface. The processor reads and runs the program stored on the memory through the data interface to execute the data prefetching method introduced in any of the foregoing embodiments. The specific processing process and its beneficial effects can be referred to the embodiment introduction of the data prefetching method above.

[0171] In addition to the foregoing methods and devices, an embodiment of the present application may also be a computer program product, which includes computer program instructions. When the computer program instructions are run by a processor, the processor is caused to execute the steps in the data prefetching method described in any of the foregoing embodiments of this specification.

[0172] The computer program product may be written in any combination of one or more programming languages for programming code to perform the operations of the embodiments of the present application. The programming languages include object-oriented programming languages, such as Java, C++, etc., and also include conventional procedural programming languages, such as the "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, executed as an independent software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0173] In addition, an embodiment of the present application may also be a storage medium, on which a computer program is stored, and the computer program is executed by a processor to perform the steps in the data prefetching method described in any of the foregoing embodiments of this specification.

[0174] For the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the present application is not limited by the described action sequence, because according to the present application, certain steps may be in other sequences or performed simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the present application.

[0175] It should be noted that the various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the similarities between the various embodiments, reference can be made to each other. For the device embodiments, since they are basically similar to the method embodiments, they are described relatively simply. For the relevant parts, reference can be made to the corresponding descriptions in the method embodiments.

[0176] The steps in the methods of the various embodiments of the present application can be adjusted, combined, and deleted according to actual needs. The technical features recorded in the various embodiments can be replaced or combined.

[0177] The modules and sub-modules in the devices and terminals in the various embodiments of the present application can be combined, divided, and deleted according to actual needs.

[0178] In the several embodiments provided by the present application, it should be understood that the disclosed terminals, devices, and methods can be implemented in other ways. For example, the terminal embodiments described above are merely illustrative. For example, the division of modules or sub-modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple sub-modules or modules can be combined or integrated into another module, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of devices or modules can be in electrical, mechanical, or other forms.

[0179] The modules or sub-modules described as separate components may or may not be physically separated. The components serving as modules or sub-modules may or may not be physical modules or sub-modules. That is, they can be located in one place or distributed to multiple network modules or sub-modules. Some or all of the modules or sub-modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0180] In addition, the various functional modules or sub-modules in the various embodiments of the present application can be integrated in a processing module, or each module or sub-module can exist physically alone, or two or more modules or sub-modules can be integrated in one module. The above-mentioned integrated modules or sub-modules can be implemented in the form of hardware or in the form of software functional modules or sub-modules.

[0181] Those skilled in the art may further realize that the units and algorithm steps of each example described in connection with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this application.

[0182] The steps of the methods or algorithms described in connection with the embodiments disclosed herein can be directly implemented by hardware, software units executed by a processor, or a combination of the two. The software units can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0183] Finally, it should also be noted that in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the said element.

[0184] The above description of the disclosed embodiments enables those skilled in the art to implement or use this application. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application will not be limited to the embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data prefetching method, characterized in that, Applied to a processor, the method includes: Determining a cache hit rate when a memory access instruction triggers a data prefetch operation; When the cache hit rate is lower than a set threshold, retrieving an entry matching the first index information and an entry matching the second index information from a pattern history table according to the first index information and the second index information; or, when the cache hit rate is not lower than the set threshold, retrieving an entry matching the first index information from the pattern history table according to the first index information; Wherein, the entries in the pattern history table are used to record the historical access records of memory regions; the first index information and the second index information include information of the memory access instruction, and the retrieval accuracy of retrieving a matching entry from the pattern history table according to the first index information is higher than that of retrieving a matching entry from the pattern history table according to the second index information; Determining a data prefetch address based on the retrieved entry, and reading data from the memory based on the data prefetch address.

2. The method according to claim 1, wherein The first index information includes the program counter value PC and the address Address of the memory access instruction; The second index information includes the program counter value PC and the address offset Offset of the memory access instruction.

3. The method according to claim 1, wherein When the cache hit rate is lower than the set threshold, the determining the data prefetch address based on the retrieved entry includes: When the cache hit rate is lower than a first threshold, selecting a first number of first entries and a second number of second entries from the retrieved entries as target entries; or, when the cache hit rate is not lower than the first threshold and lower than the set threshold, selecting a third number of first entries and a fourth number of second entries from the retrieved entries as target entries; Wherein, the first threshold is less than the set threshold; the value of dividing the second number by the first number is greater than the value of dividing the fourth number by the third number; the first entries include the entries matching the first index information, and the second entries include the entries matching the second index information; Determining the data prefetch address based on the target entries.

4. The method according to claim 1, wherein The determining the data prefetch address based on the retrieved entry includes: Determining a target memory region accessed by the memory access instruction from the retrieved entry based on the virtual address of the memory access instruction; Determining a prefetch memory block in the target memory region that has been historically accessed based on the historical access record of the target memory region; Determining the data prefetch address based on the base address of the memory access instruction and the position of the prefetch memory block in the target memory region.

5. The method according to claim 4, characterized in that Representing the historical access records of each memory region by a vector in the retrieved entry; Determining a target memory region accessed by the memory access instruction from the retrieved entry based on the virtual address of the memory access instruction, including: Locating the target memory region accessed by the memory access instruction from the vector based on the Offset information in the virtual address of the memory access instruction.

6. The method according to any one of claims 1 to 5, characterized in that The pattern history table is constructed through the following processing: During the memory access process of the processor, the memory access footprint of the processor is recorded in the form of a vector by the training table to obtain a training table entry; wherein, one instruction corresponds to one training table entry, and in this training table entry, the memory access footprint vector corresponding to this instruction is recorded; When any entry in the training table is replaced out of the training table, the replaced entry is stored in the pattern history table.

7. The method according to claim 6, characterized in that, Before storing the replaced entry in the pattern history table, the method further includes: Determining whether the number of vector bits representing accessed in the memory access footprint vector in the replaced entry is greater than 1; In the case where the number of vector bits representing accessed in the memory access footprint vector in the replaced entry is greater than 1, storing the replaced entry in the pattern history table.

8. The method according to claim 6, characterized in that, Storing the replaced entry in the pattern history table includes: Using the instruction PC corresponding to the replaced entry to retrieve the pattern history table entry corresponding to this instruction PC from the pattern history table; If the pattern history table entry corresponding to this instruction PC is retrieved from the pattern history table, storing the transformed memory access footprint vector in the target sub-item in the pattern history table entry corresponding to this instruction PC, and storing the instruction address Address corresponding to the replaced entry as a label in the target sub-item; wherein, the target sub-item is the sub-item corresponding to the address offset Offset corresponding to the replaced entry in the pattern history table entry corresponding to this instruction PC; If the pattern history table entry corresponding to this instruction PC is not retrieved from the pattern history table, allocating a pattern history table entry for the replaced entry in the pattern history table, and writing the replaced entry into the allocated pattern history table entry.

9. The method according to claim 8, wherein Storing the transformed memory access footprint vector in the target sub-item in the pattern history table entry corresponding to this instruction PC includes: In the case where a memory access footprint vector has already been stored in the target sub-item in the pattern history table entry corresponding to this instruction PC, superimposing the transformed memory access footprint vector and the memory access footprint vector in the target sub-item.

10. The method according to claim 8, wherein Allocating a pattern history table entry for the replaced entry in the pattern history table includes: Determining whether there is an invalid pattern history table entry in the pattern history table; If there is an invalid pattern history table entry, allocating this invalid pattern history table entry to the replaced entry; If there is no invalid pattern history table entry, allocating the pattern history table entry with the lowest access frequency to the replaced entry.

11. A processor, characterized in that, The processor is configured to execute the data prefetching method according to any one of claims 1 to 10.

12. An electronic device, characterized in that, Including a processor and a memory; The memory is connected to the processor and is used to store programs; The processor is used to implement the data prefetching method according to any one of claims 1 to 10 by running the program in the memory.

13. A computer device, characterized in that, Including the processor according to claim 11.

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